Resistive switching memory cell, resistive switching memory array, resistive switching memory and method of operation

Abstract

The application provides a resistive switching memory cell, a resistive switching memory array, a resistive switching memory and an operating method, and relates to the technical field of memory. The resistive switching memory cell comprises: a plurality of resistive switching devices, the plurality of resistive switching devices forming a plurality of resistive switching device rows and a plurality of resistive switching device columns; a plurality of gating devices, each of the gating devices being connected to a first electrode of each of the resistive switching devices in one of the resistive switching device rows, the gating devices being adapted to be connected to a word line and a global source line respectively, and to electrically connect or electrically disconnect the global source line connected to the gating devices and the first electrode of the resistive switching devices; and a plurality of isolating devices, each of the isolating devices being connected to a second electrode of each of the resistive switching devices in one of the resistive switching device columns, the isolating devices being adapted to be connected to a control word line and a global bit line respectively, and to electrically connect or electrically disconnect the global bit line connected to the isolating devices and the second electrode of the resistive switching devices.

Description

Technical Field

[0001] This application relates primarily to the field of memory technology, and in particular to a resistive switching memory cell, a resistive switching memory array, a resistive switching memory, and an operating method thereof. Background Technology

[0002] Resistive Random Access Memory (RRAM) is considered a promising next-generation non-volatile memory technology due to its high read / write speeds and good compatibility with CMOS processes. In existing RRAM array architectures, the 1T1R (single transistor-single resistive device) structure is a classic solution to the sneak path current problem in RRAM cross-arrays. The 1T1R architecture solves the array interference problem by connecting each resistive device in series with a switch. In this structure, when a resistive device is not selected, the switch is turned off, blocking the current path and eliminating leakage current interference from non-target resistive devices in the array, ensuring the accuracy of read / write operations. However, the density of this structure is limited by the switch size. Since each resistive device must be equipped with a switch, its cell area is often determined by the size of the resistive device, resulting in an actual effective size much larger than the ideal size, i.e., low storage density.

[0003] Therefore, there is an urgent need for a resistive switching memory cell that can improve storage density and has good read / write accuracy. Summary of the Invention

[0004] The technical problem to be solved by this application is to provide a resistive switching memory cell, a resistive switching memory array, a resistive switching memory, and an operating method that can improve storage density while having good read and write accuracy.

[0005] To address the aforementioned technical problems, this application provides a resistive switching memory cell, comprising: multiple resistive switching devices, arranged in a first direction as multiple rows of resistive switching devices and in a second direction as multiple columns of resistive switching devices, each resistive switching device including a first electrode and a second electrode, the first direction intersecting the second direction; multiple gating devices, each gating device connected to the first electrode of each resistive switching device in a row of resistive switching devices, the gating devices being adapted to be connected to a word line and a global source line respectively, and electrically connected or electrically disconnected between the global source line connected to the gating device and the first electrode of the resistive switching device according to the input voltage of the connected word line; and multiple isolation devices, each isolation device connected to the second electrode of each resistive switching device in a column of resistive switching devices, the isolation devices being adapted to be connected to a control word line and a global bit line respectively, and electrically connected or electrically disconnected between the global bit line connected to the isolation device and the second electrode of the resistive switching device according to the input voltage of the connected control word line.

[0006] Optionally, the resistive switching memory cell further includes: multiple local source lines, each local source line extending along a second direction, each local source line being connected to a gating device and the first electrode of each resistive switching device corresponding to the gating device; and multiple local bit lines, each local bit line extending along a first direction, each local bit line being connected to an isolation device and the second electrode of each resistive switching device corresponding to the isolation device.

[0007] Optionally, the number of resistive switching devices is ,in, The number of rows and columns for resistive switching devices are both [number]. .

[0008] Optionally, the gating device includes a first transistor, the gate of which is adapted to be connected to a word line, wherein the source of the first transistor is adapted to be connected to a global source line, and the drain of the first transistor is connected to the first electrode of a corresponding resistive switching device; or the drain of the first transistor is adapted to be connected to a global source line, and the source of the first transistor is connected to the first electrode of a corresponding resistive switching device.

[0009] Optionally, the isolation device includes a second transistor, the gate of which is adapted to be connected to a control word line, wherein the source of the second transistor is connected to the second electrode of a corresponding resistive switching device, and the drain of the second transistor is adapted to be connected to a global bit line; or the drain of the second transistor is connected to the second electrode of a corresponding resistive switching device, and the source of the second transistor is adapted to be connected to a global bit line.

[0010] Optionally, each pair of gating devices is adapted to be connected to the same word line, and the resistive switching memory cell is adapted to correspond to two global source lines, wherein each gating device is adapted to correspond to a different combination of word line and global source line.

[0011] Optionally, each pair of adjacent gating devices is adapted to be connected to the same word line, and each gating device arranged along the first direction is adapted to be alternately connected to two global source lines in sequence.

[0012] To address the aforementioned technical problems, this application provides a resistive variable memory array, comprising: a plurality of the aforementioned resistive variable memory cells, wherein the plurality of resistive variable memory cells are arranged along a first direction to form a plurality of resistive variable memory cell rows, and arranged along a second direction to form a plurality of resistive variable memory cell columns, wherein each resistive variable memory cell in a resistive variable memory cell row is adapted to be connected through the same global source line and control word line, and each resistive variable memory cell in a resistive variable memory cell column is adapted to be connected through the same word line and global bit line.

[0013] To address the aforementioned technical problems, this application provides a resistive random access memory (RRAM), comprising: the aforementioned RRAM array; peripheral circuitry; multiple word lines, each word line being connected to at least one gating device of each RRAM cell in a row of RRAM cells within the peripheral circuitry; multiple global source lines, each global source line being connected to at least one gating device of each RRAM cell in a row of RRAM cells within the peripheral circuitry; multiple global bit lines, each global bit line being connected to an isolation device of each RRAM cell in a column of RRAM cells within the peripheral circuitry; and multiple control word lines, each control word line being connected to each isolation device of each RRAM cell in a row of RRAM cells within the peripheral circuitry, wherein each resistive device corresponds to a different combination of global source lines, word lines, and global bit lines, and the peripheral circuitry is adapted to perform read and write operations on the RRAM array through the word lines, global source lines, global bit lines, and control word lines.

[0014] To solve the above-mentioned technical problems, this application provides an operation method applied to the above-mentioned resistive random access memory. The operation method includes: inputting corresponding control voltages to the word line, global source line, global bit line and control word line corresponding to the resistive random access memory cell through peripheral circuits, so as to perform read or write operations on the target resistive random access device row in the resistive random access memory cell.

[0015] Optionally, the step of inputting corresponding control voltages to the word line, global source line, global bit line, and control word line of the resistive switching memory cell via external circuitry to perform read or write operations on the target resistive switching device row in the resistive switching memory cell further includes: inputting a first on-state voltage to the word line corresponding to the target resistive switching device row via external circuitry, so as to electrically connect the global source line corresponding to the target resistive switching device row with the first electrode of each resistive switching device in the target resistive switching device row; inputting a second on-state voltage to the control word line corresponding to the resistive switching device cell via external circuitry, so as to electrically connect each global bit line corresponding to the resistive switching device cell with the second electrode of each resistive switching device in the resistive switching device row; and inputting a first read voltage and a second read voltage to the global source line and each global bit line corresponding to the target resistive switching device row via external circuitry, so as to make the voltage difference between the first electrode and the second electrode of each resistive switching device in the target resistive switching device row exceed the read voltage threshold.

[0016] Optionally, the step of inputting corresponding control voltages to the word line, global source line, global bit line, and control word line corresponding to the resistive switching memory cell via external circuitry to perform read or write operations on the target resistive switching device row in the resistive switching memory cell further includes: inputting a first conduction voltage to the word line corresponding to the target resistive switching device row via external circuitry to electrically connect the global source line corresponding to the target resistive switching device row with the first electrode of each resistive switching device in the target resistive switching device row; inputting a second conduction voltage to the control word line corresponding to the resistive switching device cell via external circuitry to electrically connect the global bit line corresponding to the resistive switching device cell with the second electrode of each resistive switching device in the resistive switching device row; and inputting corresponding Set operation voltages to the global source line corresponding to the target resistive switching device row and the global bit line corresponding to each resistive switching device in the target resistive switching device row via external circuitry to make the voltage difference between the first and second electrodes of each resistive switching device performing the Set operation in the target resistive switching device row exceed the Set voltage threshold.

[0017] Optionally, the step of inputting corresponding control voltages to the word line, global source line, global bit line, and control word line corresponding to the resistive switching memory cell via external circuitry to perform read or write operations on the target resistive switching device row in the resistive switching memory cell further includes: inputting a first conduction voltage to the word line corresponding to the target resistive switching device row via external circuitry to electrically connect the global source line corresponding to the target resistive switching device row with the first electrode of each resistive switching device in the target resistive switching device row; inputting a second conduction voltage to the control word line corresponding to the resistive switching device cell via external circuitry to electrically connect the global bit line corresponding to the resistive switching device cell with the second electrode of each resistive switching device in the resistive switching device row; and inputting corresponding Set operation voltages to the global source line corresponding to the target resistive switching device row and the global bit line corresponding to each resistive switching device in the target resistive switching device row via external circuitry to make the voltage difference between the first and second electrodes of each resistive switching device performing the Reset operation in the target resistive switching device row exceed the Reset voltage threshold.

[0018] Compared with existing technologies, this application has the following advantages: By assigning each gating device to a row of resistive switching devices containing multiple resistive switching devices, and assigning each isolation device to a column of resistive switching devices containing multiple resistive switching devices, it is not necessary to set a corresponding switching device for each resistive switching device, thereby increasing the proportion of resistive switching devices in the resistive switching memory cell, i.e., increasing the storage density. Furthermore, by controlling whether each resistive switching device in the corresponding row is electrically connected or disconnected from the corresponding global source line through the gating device, and by controlling whether each resistive switching device in the corresponding column is electrically connected or disconnected from the corresponding global bit line through the isolation device, leakage current of non-target resistive switching devices can be reduced when performing read / write operations on the target resistive switching device row, thus suppressing leakage current problems of the entire resistive switching memory cell and improving read / write accuracy. Attached Figure Description

[0019] The accompanying drawings are included to provide a further understanding of this application; they are incorporated into and constitute a part of this application. The drawings illustrate embodiments of this application and, together with this specification, serve to explain the principles of this application. In the drawings: Figure 1 This is a schematic diagram of the structure of a resistive switching memory cell according to an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a resistive switching memory array according to an embodiment of this application; Figure 3 This is a flowchart illustrating an operation method according to an embodiment of this application; Figure 4 yes Figure 3 A flowchart illustrating the sub-step of the read operation performed in step S1. Figure 5 yes Figure 1 A schematic diagram of a medium-resistance variable-speed memory cell performing a read operation; Figure 6 yes Figure 3 A flowchart illustrating the sub-step of executing the Set operation in step S1; Figure 7 yes Figure 1 A schematic diagram of a medium-resistance variable-voltage memory cell performing a Set operation; Figure 8 yes Figure 3 A flowchart illustrating the sub-step of the Reset operation in step S1; and Figure 9 yes Figure 1 A schematic diagram of a medium-resistance variable memory cell performing a Reset operation. Detailed Implementation

[0020] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some examples or embodiments of this application. For those skilled in the art, these drawings can be applied to other similar scenarios without creative effort. Unless obvious from the context or otherwise specified, the same reference numerals in the drawings represent the same structures or operations.

[0021] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include plural forms. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0022] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of this application. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following drawings denote similar items; therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0023] In the description of this application, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0024] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0025] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, these terms have no special meaning and therefore should not be construed as limiting the scope of protection of this application. In addition, although the terminology used in this application is selected from commonly known and used terms, some terms mentioned in this application's specification may have been chosen by the applicant according to his or her judgment, and their detailed meanings are explained in the relevant sections of this description. Moreover, this application should be understood not only through the actual terms used, but also through the meaning implied by each term.

[0026] It should be understood that when a component is referred to as "on another component," "connected to another component," "coupled to another component," or "in contact with another component," it can be directly on, connected to, coupled to, or in contact with that other component, or there may be an intervening component. In contrast, when a component is referred to as "directly on another component," "directly connected to," "directly coupled to," or "directly in contact with" another component, there is no intervening component. Similarly, when a first component is referred to as "electrically contacting" or "electrically coupled to" a second component, there is an electrical path between the first and second components that allows current to flow. This electrical path may include capacitors, coupled inductors, and / or other components that allow current to flow, even if there is no direct contact between the conductive components.

[0027] Reference Figure 1 One embodiment of this application proposes a resistive switching memory cell 10. For example... Figure 1 As shown, the resistive switching memory cell 10 includes 16 resistive switching devices 11, multiple gating devices (M0, M1, M2, and M3), multiple isolation devices (M4, M5, M6, and M7), multiple local source lines (SL0, SL1, SL2, and SL3), and multiple local bit lines (BL0, BL1, BL2, and BL3). Specifically, the 16 resistive switching devices 11 are arranged in multiple rows along the first direction y and in multiple columns along the second direction x. In this embodiment, each row includes four resistive switching devices 11 arranged along the second direction x, and each column includes four resistive switching devices 11 arranged along the first direction y. Furthermore, in this embodiment, the first direction y is perpendicular to the second direction x. It should be noted that in this application, the first direction y and the second direction x intersect, but are not limited to being perpendicular to each other. In some embodiments, in order to match the design of the resistive switching memory including the resistive switching memory unit 10, the included angle between the first direction and the second direction is an acute angle.

[0028] It should be noted that this application does not limit the number of resistive switching devices 11 included in the resistive switching memory cell 10. In some embodiments, the resistive switching memory cell 10 includes four resistive switching devices 11, forming two rows and two columns, wherein each row includes two resistive switching devices 11 and each column includes two resistive switching devices 11. In some embodiments, the resistive switching memory cell 10 includes twelve resistive switching devices 11, forming three rows and four columns, wherein each row includes four resistive switching devices 11 and each column includes three resistive switching devices 11. Preferably, the number of resistive switching devices 11 in the resistive switching memory cell 10 is... ,in, Furthermore, the number of rows and columns of the resistive switching device are both [missing information]. .

[0029] Continue to refer to Figure 1 In this embodiment, the resistive switching device 11 includes a first electrode 111 and a second electrode 112. Specifically, in this embodiment, the first electrode 111 is the bottom electrode (BE) of the resistive switching device 11, and the second electrode 112 is the top electrode (TE) of the resistive switching device 11. It should be noted that this application does not limit the electrode arrangement of the first electrode 111 and the second electrode 112. In some embodiments, the first electrode 111 is the top electrode of the resistive switching device 11, and the second electrode 112 is the bottom electrode of the resistive switching device 11.

[0030] Continue to refer to Figure 1 In this embodiment, gating devices M0, M1, M2, and M3 are respectively connected to the first electrode 111 of each resistive switching device 11 in a row of resistive switching devices. Further, each local source line extends along the second direction x, and each local source line is respectively connected to a gating device and the first electrode 111 of each resistive switching device 11 corresponding to the gating device. For example, local source line SL0 is respectively connected to... Figure 1 The first electrodes 111 of the four uppermost resistive switching devices 11 are connected, thus forming Figure 1 The top row of resistive switching devices, and the local source line SL0 is also connected to the gating device M0, thus enabling the gating device M0 to... Figure 1 In the top row of resistive switching devices, the first electrodes 111 of each resistive switching device 11 are connected. It should be noted that... Figure 1 The local source line is extended to illustrate that the resistive switching device unit 10 can contain more resistive switching devices 11. Understandably, in a resistive switching device row containing only 4 resistive switching devices 11, the two ends of the local source line are connected to the corresponding gating device and the resistive switching device 11 furthest from that gating device, respectively.

[0031] Correspondingly, in this embodiment, isolation devices M4, M5, M6, and M7 are respectively connected to the second electrode 112 of each resistive switching device 11 in a resistive switching device array. Further, each local bit line extends along the first direction y, and each local bit line is respectively connected to an isolation device and the second electrode 112 of each resistive switching device 11 corresponding to the isolation device. For example, the local bit line BL0 is respectively connected to... Figure 1 The second electrodes 112 of the four leftmost resistive switching devices 11 are connected, thus forming Figure 1 The leftmost row of resistive switching devices, and the local bit line BL0 is also connected to the isolator M4, thus making the isolator M4 and Figure 1 In the leftmost row of resistive switching devices, the second electrodes 112 of each resistive switching device 11 are connected. It should be noted that... Figure 1 The local bit line is extended to indicate that the resistive switching device unit 10 can contain more resistive switching devices 11. Understandably, in a resistive switching device column containing only 4 resistive switching devices 11, the two ends of the local bit line are connected to the corresponding isolation device and the resistive switching device 11 furthest from that isolation device, respectively.

[0032] Continue to refer to Figure 1 In this embodiment, the gating device is adapted to be connected to the word line and the global source line respectively, and to electrically connect or disconnect the global source line connected to the gating device and the first electrode 111 of the resistive switching device 11 according to the input voltage of the connected word line. Furthermore, in this embodiment, the isolation device is adapted to be connected to the control word line and the global bit line respectively, and to electrically connect or disconnect the global bit line connected to the isolation device and the second electrode 112 of the resistive switching device 11 according to the input voltage of the connected control word line. Further, every two gating devices are adapted to be connected to the same word line, and the resistive switching memory cell 10 is adapted to correspond to two global source lines. Each gating device is adapted to correspond to a different combination of word line and global source line. For example, when two gating devices correspond to the same global source line, these two gating devices correspond to different word lines. Even further, every two adjacent gating devices are adapted to be connected to the same word line, and each gating device arranged along the first direction is adapted to be alternately connected to two global source lines in sequence.

[0033] Specifically, in this embodiment, the resistive switching unit 10 corresponds to two word lines, namely word lines WL0 and WL1, two global source lines, namely global source lines GSL0 and GSL1, four global bit lines, namely global bit lines GBL0, GBL1, GBL2, and GBL3, and one control word line CWL. Word line WL0 is connected to adjacent gating devices M0 and M1, and word line WL1 is connected to adjacent gating devices M2 and M3. Global source line GSL0 is connected to gating devices M0 and M2, and global source line GSL1 is connected to gating devices M1 and M3. Global bit line GBL0 is connected to isolation device M4, global bit line GBL1 is connected to isolation device M5, global bit line GBL2 is connected to isolation device M6, and global bit line GBL3 is connected to isolation device M7. The control word line CWL is connected to isolators M4, M5, M6, and M7, respectively. It should be noted that this application does not limit the connection configuration of word lines and global source lines with gating devices. In some embodiments, each word line is connected to one gating device, and each global source line is connected to one gating device; in some embodiments, one word line is connected to two gating devices, and these two gating devices are connected to different global source lines; in some embodiments, one global source line is connected to two gating devices, and these two gating devices are connected to different word lines.

[0034] Continue to refer to Figure 1 In this embodiment, each gating device includes a first transistor. The gate of each first transistor is adapted to be connected to a corresponding word line, the source of each first transistor is adapted to be connected to a corresponding global source line, and the drain of each first transistor is connected to the first electrode 111 of the corresponding resistive switching device 11. For example, the gate of the first transistor corresponding to gating device M0 is adapted to be connected to word line WL0, the source is adapted to be connected to global source line SL0, and the drain is connected to... Figure 1 In the top row of resistive switching devices, the first electrodes 111 of each resistive switching device 11 are connected. It should be noted that this application does not limit the correspondence between the source and drain of the first transistor and the global source line and the first electrode. In some embodiments, the drain of the first transistor is adapted to be connected to the corresponding global source line, and the source of the first transistor is connected to the first electrode of the corresponding resistive switching device. In this embodiment, the first transistor is preferably a CMOS transistor, thereby maintaining the corresponding performance while having better miniaturization compared to other switching devices, thus reducing the proportion of non-resistive switching devices 11 in the resistive switching memory cell 10, and improving the storage density.

[0035] Continue to refer to Figure 1In this embodiment, each isolation device includes a second transistor. The gate of each second transistor is adapted to be connected to a control word line, the source of each second transistor is connected to the second electrode 112 of the corresponding resistive switching device 11, and the drain of each second transistor is adapted to be connected to the corresponding global bit line. For example, the gate of the second transistor corresponding to isolation device M4 is adapted to be connected to the control word line CWL, and the source is adapted to be connected to... Figure 1 In the leftmost row of resistive switching devices, the second electrodes 112 of each resistive switching device 11 are connected, and the drain is adapted to be connected to the global bit line BL0. It should be noted that this application does not limit the correspondence between the source and drain of the second transistor and the global bit line and the second electrode. In some embodiments, the drain of the second transistor is connected to the second electrode of the corresponding resistive switching device, and the source of the second transistor is connected to the corresponding global bit line. In this embodiment, the second transistor is preferably a CMOS transistor, thereby maintaining the corresponding performance while having better miniaturization compared to other switching devices, thus reducing the proportion of non-resistive switching devices 11 in the resistive switching memory cell 10 to improve storage density. Furthermore, it is understood that read and write operations are performed in the resistive switching memory cell 10 on a row-by-row basis, and during read and write operations, the upper limit of the current flowing through the gating device is much greater than the upper limit of the current flowing through the isolation device. Therefore, in this embodiment, based on the upper limit of the current that the isolation device needs to withstand and the manufacturing process limits of the isolation device, the size of the isolation device can be made smaller than that of the gate device, thereby further reducing the proportion of non-resistive switching devices 11 in the resistive switching memory cell 10, and thus further improving the storage density.

[0036] Understandably, through the above settings, this embodiment, by changing the gate input voltage of the first transistor via the global bit line, enables the source and drain of the first transistor to be mutually connected or disconnected, thereby achieving an electrical connection or disconnection between the global source line connected to the source and the first electrode connected to the drain. Correspondingly, this embodiment, by changing the gate input voltage of the second transistor via the control word line CWL, enables the source and drain of the second transistor to be mutually connected or disconnected, thereby achieving an electrical connection or disconnection between the second electrode connected to the source and the global bit line connected to the drain. It should be noted that this application does not limit the specific components required for the isolation device and the gating device to achieve electrical connection and disconnection; in some embodiments, both the isolation device and the gating device include thyristors.

[0037] In this embodiment, each row of resistive switching devices is provided with a corresponding gating device, and each column of component devices is provided with a corresponding isolation device. Each row and column of resistive switching devices includes multiple resistive switching devices 11. Therefore, in this embodiment, each gating device and isolation device can correspond to multiple resistive switching devices 11. Specifically, compared to the 1T1R configuration where one resistive switching device 11 corresponds to one transistor, in this embodiment, the 16 resistive switching devices 11 correspond to a total of 4 gating devices and 4 isolation devices, meaning each gating device or isolation device corresponds to 2 resistive switching devices. Clearly, compared to the 1T1R configuration, this embodiment reduces the number of related devices other than the resistive switching devices 11 by half, thereby allowing more resistive switching devices 11 to be placed in a unit space, thus increasing storage density. Furthermore, in this embodiment, by corresponding each global source line and each global bit line to multiple gating devices and multiple isolation devices respectively, the total number of global source lines and global bit lines is reduced, thereby simplifying the layout of the peripheral circuits connected to the global source lines and global bit lines and the layout routing of the resistive switching memory cell 10. This reduces the design complexity while further reducing the total area of ​​the peripheral circuits and the area of ​​the resistive switching memory cell 10, thus further improving the storage density.

[0038] Furthermore, in this embodiment, each selection device corresponds to a row of resistive switching devices, and the row of resistive switching devices includes multiple resistive switching devices 11. Therefore, compared to the leakage current problem caused by one switching device corresponding to one resistive switching device in the 1T1R, this embodiment can reduce the impact of leakage current by a factor of two. For example, for an existing resistive switching memory cell composed of 16 resistive switching devices in a 1T1R design, the total leakage current generated when performing read and write operations on four resistive switching devices in some scenarios is approximately a. However, due to the reduction of transistors, when performing the same read and write operations in the same scenario, the total leakage current of the selected global source line of the resistive switching memory cell 10 in this embodiment is approximately a / 2, and the total leakage current of the selected global bit line is approximately a / 4. This reduces the voltage drop across the external voltage path to the global source line and global bit line during read and write operations, allowing the external voltage to be applied more accurately to the resistive switching device performing the read and write operation, making the read and write operation on the target resistive switching device more accurate.

[0039] It should also be noted that, more preferably, the number of resistive switching devices 11 in the resistive switching memory cell 10 of this embodiment is 16 or 64. This allows for the reduction of the maximum current limit that the switching devices need to withstand while configuring fewer switching devices, thereby reducing the size of the switching devices. Configuring fewer switching devices reduces programming complexity and difficulty, resulting in a simpler and more reliable resistive switching memory cell design. Furthermore, the aforementioned number of resistive switching devices 11 reduces the number of switching and isolation devices, thereby reducing leakage current. Therefore, when the total number of resistive switching devices 11 is 16 or 64, a better overall effect can be achieved between increasing storage density, reducing leakage current, reducing programming complexity, and reducing design difficulty.

[0040] Continue to refer to Figure 2 An embodiment of this application also proposes a resistive switching memory array 20, which includes a plurality of resistive switching memory cells 10. The plurality of resistive switching memory cells 10 are arranged along a first direction y to form a plurality of resistive switching memory cell rows, and along a second direction x to form a plurality of resistive switching memory cell columns. In this embodiment, each resistive switching memory cell 10 in a row is adapted to be connected via the same global source line and control word line, and each resistive switching memory cell 10 in a column is adapted to be connected via the same word line and global bit line. Specifically, as shown... Figure 2 As shown, the resistive switching memory array 20 includes four resistive switching memory cells according to any of the above embodiments, namely resistive switching memory cell 21, resistive switching memory cell 22, resistive switching memory cell 23, and resistive switching memory cell 24. Resistive switching memory cells 21 and 22 form a row of resistive switching memory cells, resistive switching memory cells 23 and 24 form a row of resistive switching memory cells, resistive switching memory cells 21 and 23 form a column of resistive switching memory cells, and resistive switching memory cells 22 and 24 form a column of resistive switching memory cells. Among them, resistive switching memory cell 21 and resistive switching cell 22 are adapted to be connected through control word line CWL0, global source line SL0 and global source line SL1, resistive switching memory cell 23 and resistive switching cell 24 are adapted to be connected through control word line CWL1, global source line SL2 and global source line SL3, resistive switching memory cell 21 and resistive switching cell 23 are adapted to be connected through word line WL0, word line WL1, global bit line BL0, global bit line BL1, global bit line BL1 and global bit line BL3, and resistive switching memory cell 22 and resistive switching cell 24 are adapted to be connected through word line WL2, word line WL3, global bit line BL4, global bit line BL5, global bit line BL6 and global bit line BL7.

[0041] The resistive switching memory array 20 of this embodiment is adapted to perform read and write operations on the target resistive switching memory cell through global word lines and control word lines, so as to effectively suppress crosstalk between non-target resistive switching memory cells and the target resistive switching memory cell. For example, refer to... Figure 2When the rows of resistive devices corresponding to the global word line WL0 and the global source line GSL0 in the resistive memory cell 21 are read or written, the isolation devices corresponding to each resistive device 11 in the rows of resistive devices in the resistive memory cell 23 that are also controlled and turned on by the global word line WL0 are kept in the off state by controlling the word line RWL1. This avoids the current flowing in the resistive memory cell 23 to reduce unnecessary path current and thus does not increase unnecessary power consumption. In other words, it can effectively suppress the crosstalk effect when the resistive memory cell 23 performs read and write operations on the resistive memory cell 21.

[0042] One embodiment of this application also proposes a resistive random access memory (RRAM). The RRAM includes a RRAM array 20 according to any of the above embodiments, peripheral circuitry, multiple word lines, multiple global source lines, multiple global bit lines, and multiple control word lines. Each word line is connected to at least one gating device of each RRAM cell 10 in a row of RRAM cells within the peripheral circuitry. Each global source line is connected to at least one gating device of each RRAM cell 10 in a row of RRAM cells within the peripheral circuitry. Each global bit line is connected to an isolation device of each RRAM cell 10 in a column of RRAM cells within the peripheral circuitry. Each control word line is connected to each isolation device of each RRAM cell 10 in a row of RRAM cells within the peripheral circuitry. In this embodiment, each resistive device corresponds to a different combination of global source lines, word lines, and global bit lines; that is, the global source lines, word lines, and all bit lines corresponding to each resistive device are not completely identical. Furthermore, the peripheral circuitry is adapted to perform read and write operations on the RRAM array 20 through the word lines, global source lines, global bit lines, and control word lines. As is understandable, the settings of word lines, global source lines, global bit lines, and control word lines in specific resistive switching memory cells 10 and resistive switching memory arrays 20 have already been explained in the preceding text, and will not be repeated here.

[0043] Continue to refer to Figure 3 An embodiment of this application also proposes an operation method 200, which is applied to the resistive random access memory (RRAM) of any embodiment of this application. Specifically, the operation method 200 includes the following steps. Step S1 involves inputting corresponding control voltages to the word line, global source line, global bit line, and control word line corresponding to the RRAM cell via peripheral circuitry to perform read or write operations on the target RRAM cell 10. It is understood that the target RRAM cell is a row of RRAM cells within the RRAM cell 10.

[0044] Continue to refer to Figure 3 and Figure 4For the read operation, step S1 further includes the following sub-steps. Step S111: Input a first on-state voltage to the word line corresponding to the target resistive switching device row through the peripheral circuit, so as to electrically connect the global source line corresponding to the target resistive switching device row with the first electrode 111 of each resistive switching device 11 in the target resistive switching device row. Step S112: Input a second on-state voltage to the control word line corresponding to the resistive switching device unit through the peripheral circuit, so as to electrically connect each global bit line corresponding to the resistive switching device unit 10 with the second electrode 112 of each resistive switching device 11 in the resistive switching device row. Step S113: Input a first read voltage and a second read voltage to the global source line and each global bit line corresponding to the target resistive switching device row, respectively, through the peripheral circuit, so as to make the voltage difference between the first electrode 111 and the second electrode 112 of each resistive switching device 11 in the target resistive switching device row exceed the read voltage threshold.

[0045] For example, refer to Figure 1 and Figure 5When the peripheral circuit performs a read operation on the row of resistive switching devices corresponding to the selection device M0, the peripheral circuit inputs a first on-state voltage VDD1 to the word line WL0 to turn on selection devices M0 and M2, a first off-state voltage VSS to the word line WL1 to turn off selection devices M1 and M3, a second on-state voltage VDD2 to the control word line CWL to turn on isolation devices M4, M5, M6, and M7, a first read voltage V11 to the global source line GSL0, a non-read voltage V13 to the global source line GSL1, and a second read voltage V12 to the global bit lines GBL0, GBL1, GBL2, and GBL3, respectively. Based on the above, in the resistive switching memory cell 10, only the resistive switching devices 11 in the rows of resistive switching devices corresponding to the on-state devices M0 and M2 are in the on-state. Furthermore, the peripheral circuit controls the magnitudes of the first read voltage V11, the second read voltage V12, and the non-read voltage V13 to ensure that the voltage difference between the first electrode 111 and the second electrode 112 of each resistive switching device 11 (i.e., resistive switching device A1, A2, A3, and A4) in the row of resistive switching devices corresponding to the conducting device M0 exceeds the read voltage threshold, and the voltage difference between the first electrode 111 and the second electrode 112 of each resistive switching device 11 in the row of resistive switching devices corresponding to the conducting device M2 does not exceed the read voltage threshold, thereby ensuring that only the row of resistive switching devices corresponding to the selecting device M0 is read. Preferably, the non-read voltage is the same as the second read voltage, so that even when the gating device M1 is turned on, there is no voltage difference between the first electrode 111 and the second electrode 112 of each resistive device 11 in the row of resistive devices that does not perform a read operation. This suppresses the generation of interference current in the row of resistive devices that could affect the accurate reading of the current of each resistive device 11 in the row of resistive devices corresponding to the gating device M1, thereby improving the accuracy of the read operation. It should be noted that this application does not limit the setting of the first read voltage V11, the second read voltage V12, and the non-read voltage V13. In some embodiments, at least one of the first read voltage V11, the second read voltage V12, and the non-read voltage V13 is a positive voltage, and in some embodiments, at least one of the first read voltage V11, the second read voltage V12, and the non-read voltage V13 is a negative voltage.

[0046] Continue to refer to Figure 3 and Figure 6For the Set operation in the write operation, step S1 further includes the following sub-steps. Step S121: Input a first on-state voltage to the word line corresponding to the target resistive switching device row through the external circuit, so as to electrically connect the global source line corresponding to the target resistive switching device row with the first electrode 111 of each resistive switching device 11 in the target resistive switching device row. Step S122: Input a second on-state voltage to the control word line corresponding to the resistive switching device unit through the external circuit, so as to electrically connect the global bit line corresponding to the resistive switching device unit with the second electrode 112 of each resistive switching device 11 in the resistive switching device row. Step S123: Input the corresponding Set operation voltage to the global source line corresponding to the target resistive switching device row and the global bit line corresponding to each resistive switching device 11 in the target resistive switching device row through the external circuit, so as to make the voltage difference between the first electrode 111 and the second electrode 112 of each resistive switching device 11 performing the Set operation in the target resistive switching device row exceed the Set voltage threshold.

[0047] For example, refer to Figure 1 and Figure 7When the peripheral circuit performs a Set operation on resistive switching devices A1 and A3 in the row of resistive switching devices corresponding to gating device M0, but does not perform a Set operation on resistive switching devices A2 and A4, the peripheral circuit inputs a first turn-on voltage VDD1 to word line WL0 to turn on gating devices M0 and M2, inputs a first non-turn-on voltage VSS to word line WL1 to turn off gating devices M1 and M3, inputs a second turn-on voltage VDD2 to control word line CWL to turn on isolation devices M4, M5, M6, and M7, inputs a first Set operation voltage V21 to global source line GSL0, inputs a first non-Set operation voltage V23 to global source line GSL1, inputs a second Set operation voltage V22 to global bit lines GBL0 and GBL2 respectively, and inputs a second non-Set operation voltage V24 to global bit lines GBL1 and GBL3 respectively. Based on the above, resistive switching devices A1, A2, A3, A4, B1, B2, B3, and B4 in the resistive switching memory cell 10 are in a conducting state. Furthermore, the peripheral circuit controls the magnitudes of the first Set operation voltage V21, the second Set operation voltage V22, the first Non-Set operation voltage V23, and the second Non-Set operation voltage V24 to ensure that the voltage difference between the first electrode 111 and the second electrode 112 of resistive switching devices A1 and A3 exceeds the Set voltage threshold, and the voltage difference between the first electrode 111 and the second electrode 112 of resistive switching devices A2, A4, B1, B2, B3, and B4 does not exceed the Set voltage threshold. This ensures that the Set operation is performed only on resistive switching devices A1 and A3 in the resistive switching memory cell 10.

[0048] It should be noted that this application does not limit the specific voltages of the first Set operating voltage V21, the second Set operating voltage V22, the first non-Set operating voltage V23, and the second non-Set operating voltage V24. In some cases, the first Set operating voltage V21 is a, the second Set operating voltage V22 is 0, the first non-Set operating voltage V23 is a / 2, and the second non-Set operating voltage V24 is a / 2; in some cases, the first Set operating voltage V21 is a, the second Set operating voltage V22 is 0, the first non-Set operating voltage V23 is a / 3, and the second non-Set operating voltage V24 is 2a / 3; in some cases, the first Set operating voltage V21 is 0, the second Set operating voltage V22 is 1, the first non-Set operating voltage V23 is 2a / 3, and the second non-Set operating voltage V24 is a / 3. Furthermore, this application does not limit the setting method of the first Set operating voltage V21, the second Set operating voltage V22, the first non-Set operating voltage V23, and the second non-Set operating voltage V24. In some embodiments, at least one of the first Set operating voltage V21, the second Set operating voltage V22, the first non-Set operating voltage V23, and the second non-Set operating voltage V24 is a positive voltage, and in some embodiments, at least one of the first Set operating voltage V21, the second Set operating voltage V22, the first non-Set operating voltage V23, and the second non-Set operating voltage V24 is a negative voltage.

[0049] Continue to refer to Figure 3 and Figure 8 For the Reset operation in the write operation, step S1 further includes the following sub-steps: Step S131: Input a first on-state voltage to the word line corresponding to the target resistive switching device row through the external circuit, so as to electrically connect the global source line corresponding to the target resistive switching device row with the first electrode 111 of each resistive switching device 11 in the target resistive switching device row. Step S132: Input a second on-state voltage to the control word line corresponding to the resistive switching device unit through the external circuit, so as to electrically connect the global bit line corresponding to the resistive switching device unit with the second electrode 112 of each resistive switching device 11 in the resistive switching device row. Step S133: Input the corresponding Set operation voltage to the global source line corresponding to the target resistive switching device row and the global bit line corresponding to each resistive switching device 11 in the target resistive switching device row through the external circuit, so as to make the voltage difference between the first electrode 111 and the second electrode 112 of each resistive switching device 11 performing the Reset operation in the target resistive switching device row exceed the Reset voltage threshold.

[0050] For example, refer to Figure 1 and Figure 9When the peripheral circuit performs a reset operation on resistive switching devices A1 and A3 in the row of resistive switching devices corresponding to gating device M0, but does not perform a reset operation on resistive switching devices A2 and A4, the peripheral circuit inputs a first on-state voltage VDD1 to word line WL0 to turn on gating devices M0 and M2, inputs a first off-state voltage VSS to word line WL1 to turn off gating devices M1 and M3, inputs a second on-state voltage VDD2 to control word line CWL to turn on isolation devices M4, M5, M6, and M7, inputs a first reset operation voltage V31 to global source line GSL0, inputs a first off-state operation voltage V33 to global source line GSL1, inputs a second reset operation voltage V32 to global bit line GBL0 and global bit line GBL2 respectively, and inputs a second off-state operation voltage V34 to global bit line GBL1 and global bit line GBL3 respectively. Based on the above, resistive switching devices A1, A2, A3, A4, B1, B2, B3, and B4 in the resistive switching memory cell 10 are in a conducting state. Furthermore, the peripheral circuit controls the magnitudes of the first Reset operating voltage V31, the second Reset operating voltage V32, the first non-Reset operating voltage V33, and the second non-Reset operating voltage V34 to ensure that the voltage difference between the first electrode 111 and the second electrode 112 of resistive switching devices A1 and A3 exceeds the Reset voltage threshold, and the voltage difference between the first electrode 111 and the second electrode 112 of resistive switching devices A2, A4, B1, B2, B3, and B4 does not exceed the Reset voltage threshold. This ensures that only resistive switching devices A1 and A3 in the resistive switching memory cell 10 are reset.

[0051] It should be noted that this application does not limit the specific voltages of the first Reset operation voltage V31, the second Reset operation voltage V32, the first non-Reset operation voltage V33, and the second non-Reset operation voltage V34. The specific setting methods can be referred to the relevant voltage setting methods in the Set operation section above, and will not be repeated here. Furthermore, this application does not limit the setting methods of the first Reset operation voltage V31, the second Reset operation voltage V32, the first non-Reset operation voltage V33, and the second non-Reset operation voltage V34. In some embodiments, at least one of the first Reset operation voltage V31, the second Reset operation voltage V32, the first non-Reset operation voltage V33, and the second non-Reset operation voltage V34 is a positive voltage; in some embodiments, at least one of the first Reset operation voltage V31, the second Reset operation voltage V32, the first non-Reset operation voltage V33, and the second non-Reset operation voltage V34 is a negative voltage.

[0052] It should be noted that for bipolar resistive random access memory (BRAM), one of the Reset voltage threshold and the other is negative; for unipolar BRAM, both the Reset and Set voltage thresholds are positive, but their magnitudes differ. It should also be noted that write operations include Forming operations, which follow the same pattern as Reset and Set operations and will not be elaborated upon here.

[0053] In this embodiment, the above-described operation method 200 enables accurate read and write operations on the resistive random access memory (RRAM) composed of resistive random access memory (RRAM) cells 10. This ensures that the RRAM is capable of read and write operations while increasing storage density and reducing leakage current and crosstalk through the RRAM cells 10.

[0054] The basic concepts have been described above. Obviously, for those skilled in the art, the above disclosure is merely illustrative and does not constitute a limitation of this application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this application, and therefore remain within the spirit and scope of the exemplary embodiments of this application.

[0055] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic related to at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0056] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the present application requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0057] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used in the description of embodiments are modified in some examples with the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may be changed depending on the characteristics required by individual embodiments. In some embodiments, numerical parameters should take into account specified significant digits and employ a general method of digit reservation. Although the numerical ranges and parameters used to confirm their breadth of scope in some embodiments of this application are approximate values, in specific embodiments, such values ​​are set as precisely as feasible.

[0058] Although this application has been described with reference to specific embodiments, those skilled in the art should recognize that the above embodiments are only used to illustrate this application, and various equivalent changes or substitutions can be made without departing from the spirit of this application. Therefore, any changes or modifications to the above embodiments within the essential spirit of this application will fall within the scope of the claims of this application.

Claims

1. A resistive switching memory cell, characterized in that, include: Multiple resistive switching devices are arranged in multiple rows along a first direction and in multiple columns along a second direction. Each resistive switching device includes a first electrode and a second electrode. The first direction intersects the second direction. Multiple gating devices, each of the gating devices being connected to the first electrode of each of the resistive switching devices in a row of resistive switching devices, the gating devices being adapted to be connected to a word line and a global source line respectively, and to electrically connect or disconnect the global source line connected to the gating device and the first electrode of the resistive switching device according to the input voltage of the connected word line. A plurality of isolation devices, each of the isolation devices being connected to the second electrode of each of the resistive switching devices in a row of resistive switching devices, the isolation devices being adapted to be connected to a control word line and a global bit line respectively, and to electrically connect or disconnect the global bit line connected to the isolation device and the second electrode of the resistive switching device according to the input voltage of the connected control word line.

2. The resistive switching memory cell as described in claim 1, characterized in that, The resistive switching memory unit further includes: Multiple local source lines, each of which extends along the second direction, and each of which is connected to the first electrode of a gating device and each of the resistive switching devices corresponding to the gating device; Multiple local bit lines, each of which extends along the first direction, and each of which is connected to the second electrode of an isolation device and the corresponding resistive switching device.

3. The resistive switching memory cell as described in claim 1, characterized in that, The number of resistive switching devices is ,in, , The number of rows and columns of the resistive switching devices are both [number of rows and number of columns]. .

4. The resistive switching memory cell as described in claim 1, characterized in that, The gating device includes a first transistor, the gate of which is adapted to be connected to the word line. Wherein, the source of the first transistor is adapted to be connected to the global source line, and the drain of the first transistor is connected to the first electrode of the corresponding resistive switching device; or The drain of the first transistor is adapted to be connected to the global source line, and the source of the first transistor is connected to the first electrode of the corresponding resistive switching device.

5. The resistive switching memory cell as described in claim 1, characterized in that, The isolation device includes a second transistor, the gate of which is adapted to be connected to the control word line. Wherein, the source of the second transistor is connected to the second electrode of the corresponding resistive switching device, and the drain of the second transistor is adapted to be connected to the global bit line; or The drain of the second transistor is connected to the second electrode of the corresponding resistive switching device, and the source of the second transistor is adapted to be connected to the global bit line.

6. The resistive switching memory cell as described in claim 1, characterized in that, Each pair of the aforementioned gating devices is adapted to be connected to the same word line, and the resistive switching memory cell is adapted to correspond to two of the aforementioned global source lines. Each of the gating devices is adapted to correspond to different combinations of the word lines and the global source lines.

7. The resistive switching memory cell as described in claim 6, characterized in that, Each pair of adjacent gating devices is adapted to be connected to the same word line, and each of the gating devices arranged along the first direction is adapted to be alternately connected to the two global source lines in sequence.

8. A resistive switching memory array, characterized in that, include: Multiple resistive switching memory cells as described in any one of claims 1 to 7, The plurality of resistive switching memory cells are arranged in multiple rows along the first direction and in multiple columns along the second direction. Each resistive switching memory cell in the row is adapted to be connected via the same global source line and the same control word line. Each of the resistive switching memory cells in the column is adapted to be connected via the same word line and the global bit line.

9. A resistive random access memory, characterized in that, include: The resistive switching memory array as described in claim 8; Peripheral circuits; Multiple word lines, each of the word lines being connected to the peripheral circuitry and at least one of the gating devices of each of the resistive switching memory cells in the row of the resistive switching memory cells; Multiple global source lines, each of which is connected to the peripheral circuit and at least one of the gating devices of each of the resistive switching memory cells in the row of the resistive switching memory cells; Multiple global bit lines, each of which is connected to the peripheral circuit and an isolation device of each of the resistive switching memory cells in the column of resistive switching memory cells; Multiple control word lines are provided, each of which is connected to the peripheral circuitry and to each isolation device of each resistive switching memory cell in a row of resistive switching memory cells. Each of the resistive switching devices corresponds to a different combination of the global source line, the word line, the global bit line, and the control word line. The peripheral circuitry is adapted to perform read and write operations on the resistive variable memory array via the word lines, the global source lines, the global bit lines, and the control word lines.

10. An operating method, characterized in that, Applied to the resistive random access memory as described in claim 9, the operation method includes: The peripheral circuit inputs corresponding control voltages to the word line, global source line, global bit line, and control word line of the resistive switching memory cell to perform read or write operations on the target resistive switching device row in the resistive switching memory cell.

11. The operating method as described in claim 10, characterized in that, The step of inputting corresponding control voltages to the word line, global source line, global bit line, and control word line corresponding to the resistive switching memory cell through the peripheral circuit to perform read or write operations on the target resistive switching device row in the resistive switching memory cell further includes: The peripheral circuit inputs a first conduction voltage to the word line corresponding to the row of target resistive switching devices, so that the global source line corresponding to the row of target resistive switching devices is electrically connected to the first electrode of each resistive switching device in the row of target resistive switching devices. The peripheral circuit inputs a second on-state voltage to the control word line corresponding to the resistive switching device unit, so that each global bit line corresponding to the resistive switching device unit is electrically connected to the second electrode of each resistive switching device in the resistive switching device row. The peripheral circuit inputs a first read voltage and a second read voltage to the global source line and each of the global bit lines corresponding to the row of target resistive switching devices, so that the voltage difference between the first electrode and the second electrode of each resistive switching device in the row of target resistive switching devices exceeds the read voltage threshold.

12. The operating method as described in claim 10, characterized in that, The step of inputting corresponding control voltages to the word line, global source line, global bit line, and control word line corresponding to the resistive switching memory cell through the peripheral circuit to perform read or write operations on the target resistive switching device row in the resistive switching memory cell further includes: The peripheral circuit inputs a first conduction voltage to the word line corresponding to the row of target resistive switching devices, so that the global source line corresponding to the row of target resistive switching devices is electrically connected to the first electrode of each resistive switching device in the row of target resistive switching devices. The peripheral circuit inputs a second on-state voltage to the control word line corresponding to the resistive switching device unit, so that each global bit line corresponding to the resistive switching device unit is electrically connected to the second electrode of each resistive switching device in the resistive switching device row. The peripheral circuit inputs the corresponding Set operation voltage to the global source line corresponding to the target resistive switching device row and the global bit line corresponding to each resistive switching device in the target resistive switching device row, so that the voltage difference between the first electrode and the second electrode of each resistive switching device performing the Set operation in the target resistive switching device row exceeds the Set voltage threshold.

13. The operating method as described in claim 10, characterized in that, The step of inputting corresponding control voltages to the word line, global source line, global bit line, and control word line corresponding to the resistive switching memory cell through the peripheral circuit to perform read or write operations on the target resistive switching device row in the resistive switching memory cell further includes: The peripheral circuit inputs a first conduction voltage to the word line corresponding to the row of target resistive switching devices, so that the global source line corresponding to the row of target resistive switching devices is electrically connected to the first electrode of each resistive switching device in the row of target resistive switching devices. The peripheral circuit inputs a second on-state voltage to the control word line corresponding to the resistive switching device unit, so that each global bit line corresponding to the resistive switching device unit is electrically connected to the second electrode of each resistive switching device in the resistive switching device row. The peripheral circuit inputs the corresponding Set operation voltage to the global source line corresponding to the target resistive switching device row and the global bit line corresponding to each resistive switching device in the target resistive switching device row, so that the voltage difference between the first electrode and the second electrode of each resistive switching device performing the Reset operation in the target resistive switching device row exceeds the Reset voltage threshold.

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