Semiconductor devices and methods of manufacture, operation, semiconductor structures, packaging structures, in-memory computing devices

Abstract

Embodiments of the present disclosure provide a semiconductor device and a manufacturing method, an operating method, a semiconductor structure, a packaging structure and a computing and storage device. The semiconductor device includes a first semiconductor structure and a second semiconductor structure bonded together. The first semiconductor structure includes a memory array, a peripheral circuit coupled to the memory array, a first bonding contact, a second bonding contact and a third bonding contact each coupled to the peripheral circuit. The second semiconductor structure includes a control circuit, an analog-to-digital conversion circuit coupled to the control circuit, a fourth bonding contact and a fifth bonding contact each coupled to the control circuit, and a sixth bonding contact coupled to the analog-to-digital conversion circuit. A first signal channel is formed between the first bonding contact and the fourth bonding contact. A second signal channel is formed between the second bonding contact and the fifth bonding contact. A third signal channel is formed between the third bonding contact and the sixth bonding contact. The first, second and third signal channels are configured to transmit different information.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, a semiconductor device and its manufacturing, operation method, semiconductor structure, packaging structure, and memory computing device. Background Technology

[0002] In the classic von Neumann computing architecture, memory and processor are separate, with data transfer between them via a data bus. When executing commands, the processor first reads data from memory, processes it, and then writes the updated data back to memory. This frequent data movement incurs significant power consumption and time overhead. Furthermore, due to limited memory bandwidth, the processor's processing speed is constrained by the memory access speed, greatly impacting computational performance. With the rise of big data and artificial intelligence applications, the processing of massive amounts of data has made the bottlenecks of the von Neumann computing architecture increasingly prominent. Summary of the Invention

[0003] In view of the above, embodiments of the present disclosure provide a semiconductor device and its manufacturing, operation method, semiconductor structure, packaging structure, and memory computing device.

[0004] In a first aspect, embodiments of this disclosure provide a semiconductor device, including a first semiconductor structure and a second semiconductor structure bonded together; the first semiconductor structure includes a memory array, peripheral circuitry coupled to the memory array, and a first bonding contact, a second bonding contact, and a third bonding contact respectively coupled to the peripheral circuitry; the second semiconductor structure includes a control circuit, an analog-to-digital converter circuit coupled to the control circuit, a fourth bonding contact and a fifth bonding contact respectively coupled to the control circuit, and a sixth bonding contact coupled to the analog-to-digital converter circuit; wherein the first bonding contact and the fourth bonding contact form a first signal channel; the second bonding contact and the fifth bonding contact form a second signal channel; and the third bonding contact and the sixth bonding contact form a third signal channel; the first signal channel, the second signal channel, and the third signal channel are configured to transmit different information.

[0005] In some implementations, the first signal channel is configured to transmit system information adapted to the ONFI protocol and system information between the control circuit and the peripheral circuit during the execution of in-memory computation; the second signal channel is configured to transmit synchronization control information between the peripheral circuit and the control circuit during the execution of in-memory computation; and the third signal channel is configured to transmit system information between the memory array and the analog-to-digital converter circuit during the execution of in-memory computation.

[0006] In some implementations, when performing a first read operation, the control circuit is configured to: send a first command through the first signal channel; the peripheral circuit is configured to: in response to the first command, send first synchronization control information through the second signal channel; the first synchronization control information includes a first read operation start sensing trigger signal; the control circuit is configured to: send a first control signal to the analog-to-digital converter circuit; the analog-to-digital converter circuit is configured to: in response to the first control signal, acquire a first memory current signal output by the memory array through the third signal channel; and convert the first memory current signal into first read data; the control circuit is configured to: send second synchronization control information through the second signal channel; the second synchronization control information includes a trigger signal indicating completion of the first read operation sensing; the peripheral circuit is configured to: send third synchronization control information through the second signal channel; the third synchronization control information includes a first read operation end signal.

[0007] In some implementations, during a first time period, the first command is transmitted through the first signal channel; during a second time period, the first synchronization control information is transmitted through the second signal channel; and during a third time period, the first storage current signal is transmitted through the third signal channel; the first time period is earlier than the second time period; during a third time period, second synchronization control information is transmitted through the second signal channel; the second time period is earlier than the third time period; and during a fourth time period, third synchronization control information is transmitted through the second signal channel; the third time period is earlier than the fourth time period.

[0008] In some implementations, when performing a write operation, the control circuit is configured to send a second command through the first signal channel; the second command includes write data; and the peripheral circuit is configured to store the write data to the storage array in response to the second command.

[0009] In some implementations, when performing a write verification operation, the peripheral circuit is configured to: send fourth synchronization control information through the second signal channel; the fourth synchronization control information includes the status information of the storage array; the control circuit is configured to: send a second control signal to the analog-to-digital converter circuit; the analog-to-digital converter circuit is configured to: in response to the second control signal, acquire a second computing current signal output by the storage array through the third signal channel; and convert the second computing current signal into verification data; the control circuit is configured to: verify the write data with the verification data, and send fifth synchronization control information through the second signal channel; the fifth synchronization control information includes the verification operation... The operation is completed; the peripheral circuit is configured to send a sixth synchronization control message through the second signal channel; the sixth synchronization control message includes a signal that the verification data can be stored in the storage array; the control circuit is configured to send a third control signal to the analog-to-digital converter circuit; the analog-to-digital converter circuit is configured to, in response to the third control signal, store the verification data in the storage array through the third signal channel; or, the control circuit is configured to store the verification data in the storage array through the first signal channel; the peripheral circuit is configured to send a seventh synchronization control message through the second signal channel; the seventh synchronization control message includes an end signal for the write operation.

[0010] In some implementations, during the fifth time period, the second command is transmitted through the first signal channel; during the sixth time period, the fourth synchronization control information is transmitted through the second signal channel; the second storage current signal is transmitted through the third signal channel; the fifth synchronization control information and the sixth synchronization control information are transmitted through the second signal channel respectively; the verification data is transmitted through the third signal channel or the first signal channel; the fifth time period is earlier than the sixth time period; during the seventh time period, the seventh synchronization control information is transmitted through the second signal channel; the sixth time period is earlier than the seventh time period.

[0011] In some implementations, when performing the second read operation, the control circuit is configured to send a third command through the first signal channel; and the peripheral circuit is configured to, in response to the third command, send the second read data stored in the memory array to the control circuit through the first signal channel.

[0012] In some embodiments, the first semiconductor structure further includes a bit line located between the peripheral circuit and the memory array; the memory array is coupled to the peripheral circuit via the bit line.

[0013] In some embodiments, the first semiconductor structure includes a first sub-semiconductor structure on which the memory array is formed and a second sub-semiconductor structure on which the peripheral circuitry is formed; the first sub-semiconductor structure further includes a first bonding layer and a second bonding layer located on opposite sides of the memory array; the second sub-semiconductor structure further includes a third bonding layer on which the first bonding contact, the second bonding contact, and the third bonding contact are formed; the second semiconductor structure includes a fourth bonding layer on which the fourth bonding contact, the fifth bonding contact, and the sixth bonding contact are formed; the fourth bonding layer is bonded to the first bonding layer; and the second bonding layer is bonded to the third bonding layer.

[0014] In some embodiments, the semiconductor device further includes: a first connection structure that extends through the memory array and is respectively connected to the first bonding contact and the fourth bonding contact; a second connection structure that extends through the memory array and is respectively connected to the second bonding contact and the fifth bonding contact; and a third connection structure that extends through the memory array and is respectively connected to the third bonding contact and the sixth bonding contact.

[0015] In some embodiments, the second semiconductor structure includes a three-dimensional NAND-type memory.

[0016] Secondly, embodiments of this disclosure provide a packaging structure, including: a packaging substrate, a semiconductor device as described in the above embodiments, and a molding compound; the semiconductor device is disposed on the packaging substrate; and the molding compound encapsulates the semiconductor device.

[0017] Thirdly, embodiments of this disclosure provide a memory computing device, including the semiconductor device described in the above embodiments.

[0018] Fourthly, embodiments of this disclosure provide a semiconductor structure, the semiconductor structure including a memory array, peripheral circuits coupled to the memory array, and a first bonding contact, a second bonding contact, and a third bonding contact respectively coupled to the peripheral circuits; wherein, the first bonding contact is configured to transmit a first signal; the second bonding contact is configured to transmit a second signal; and the third bonding contact is configured to transmit a third signal; the information contents of the first signal, the second signal, and the third signal are different.

[0019] In some implementations, the information content of the first signal includes system information adapted to the ONFI protocol and system information interacting with the peripheral circuit during the execution of in-memory computation; the information content of the second signal includes synchronization control information interacting with the peripheral circuit during the execution of in-memory computation; and the information content of the third signal includes system information interacting with the memory array during the execution of in-memory computation.

[0020] In some embodiments, the semiconductor structure includes a first sub-semiconductor structure on which the memory array is formed and a second sub-semiconductor structure on which the peripheral circuitry is formed; the first sub-semiconductor structure further includes a first bonding layer and a second bonding layer located on opposite sides of the memory array; the second sub-semiconductor structure further includes a third bonding layer on which the first bonding contact, the second bonding contact and the third bonding contact are formed; the second bonding layer and the third bonding layer are bonded together.

[0021] In some embodiments, the semiconductor structure further includes: a first connection structure extending through the memory array and connected to the first bonding contact; a second connection structure extending through the memory array and connected to the second bonding contact; and a third connection structure extending through the memory array and connected to the third bonding contact.

[0022] In some embodiments, the semiconductor structure further includes: a bit line located between the peripheral circuit and the memory array; the memory array is coupled to the peripheral circuit via the bit line.

[0023] Fifthly, embodiments of this disclosure provide a method for manufacturing a semiconductor device, the method comprising: forming a first semiconductor structure and a second semiconductor structure bonded together; the first semiconductor structure comprising a memory array, a peripheral circuit coupled to the memory array, and a first bonding contact, a second bonding contact, and a third bonding contact respectively coupled to the peripheral circuit; the second semiconductor structure comprising a control circuit, an analog-to-digital converter circuit coupled to the control circuit, a fourth bonding contact and a fifth bonding contact respectively coupled to the control circuit, and a sixth bonding contact coupled to the analog-to-digital converter circuit; wherein the first bonding contact and the fourth bonding contact are coupled to form a first signal channel; the second bonding contact and the fifth bonding contact are coupled to form a second signal channel; the third bonding contact and the sixth bonding contact are coupled to form a third signal channel; the first signal channel, the second signal channel, and the third signal channel transmit different information.

[0024] In some implementations, the first signal channel transmits system information adapted to the ONFI protocol and system information between the control circuit and the peripheral circuit during the execution of in-memory computation; the second signal channel transmits synchronization control information between the peripheral circuit and the control circuit during the execution of in-memory computation; and the third signal channel transmits system information between the memory array and the analog-to-digital converter circuit during the execution of in-memory computation.

[0025] In some embodiments, the method further includes forming a bit line between the peripheral circuit and the memory array, and coupling the memory array to the peripheral circuit via the bit line.

[0026] In some embodiments, the formation of the first and second semiconductor structures with bonding connections includes: forming the memory array and a first bonding layer and a second bonding layer located on opposite sides of the memory array to form a first sub-semiconductor structure; forming the peripheral circuit and a third bonding layer including the first bonding contact, the second bonding contact, and the third bonding contact to form a second sub-semiconductor structure; forming the control circuit, the analog-to-digital conversion circuit, and a fourth bonding layer including the fourth bonding contact, the fifth bonding contact, and the sixth bonding contact to form a second semiconductor structure; and bonding the fourth bonding layer to the first bonding layer and bonding the second bonding layer to the third bonding layer to form the first and second semiconductor structures with bonding connections.

[0027] In some embodiments, the method further includes: forming a first connection structure that extends through the memory array and is respectively connected to the first bonding contact and the fourth bonding contact; forming a second connection structure that extends through the memory array and is respectively connected to the second bonding contact and the fifth bonding contact; and forming a third connection structure that extends through the memory array and is respectively connected to the third bonding contact and the sixth bonding contact.

[0028] In a sixth aspect, embodiments of this disclosure provide an operation method for a semiconductor device, the semiconductor device including the semiconductor device described in the above embodiments of this disclosure; the operation method includes: when performing a first read operation, a control circuit transmits a first command to a peripheral circuit through a first signal channel; the first command includes a first read instruction, a first read address, and input vector data; in response to the first command, the peripheral circuit transmits first synchronization control information to the control circuit through a second signal channel; the first synchronization control information includes a trigger signal for the start of the first read operation; the control circuit instructs an analog-to-digital converter circuit to acquire a first storage current signal through a third signal channel and convert the first storage current signal into first read data; the control circuit transmits second synchronization control information to the peripheral circuit through the second signal channel; the second synchronization control information includes a trigger signal for the completion of the first read operation; and the peripheral circuit transmits third synchronization control information through the second signal channel; the third synchronization control information includes a signal for the end of the first read operation.

[0029] In some embodiments, the operation method further includes: when performing a write operation, the control circuit sends a second command to the peripheral circuit through the first signal channel; the second command includes write data; in response to the second command, the peripheral circuit stores the write data in the storage array.

[0030] In some embodiments, the operation method further includes: when performing a write verification operation, the peripheral circuit transmits fourth synchronization control information to the control circuit through the second signal channel; the fourth synchronization control information includes the status information of the storage array; the control circuit instructs the analog-to-digital conversion circuit to acquire a second storage current signal through the third signal channel and convert the second storage current signal into verification data; and, verifying the write data with the verification data; the control circuit sends fifth synchronization control information to the peripheral circuit through the second signal channel; the fifth synchronization control information includes a signal that the write verification operation has been completed; the peripheral circuit transmits sixth synchronization control information through the second signal channel; the sixth synchronization control information includes a signal that the verification data can be stored in the storage array; the control circuit transmits the verification data to the peripheral circuit through the third signal channel or the first signal channel; the peripheral circuit transmits seventh synchronization control information to the control circuit through the second signal channel; the seventh synchronization control information includes a signal that the write operation has ended.

[0031] In some embodiments, the operation method further includes: when performing a second read operation, the control circuit transmits a third command through the first signal channel; the third command includes a second read instruction and a second read address; in response to the third command, the peripheral circuit transmits the second read data stored in the memory array to the control circuit through the first signal channel.

[0032] In this embodiment, a memory array, peripheral circuits coupled to the memory array, and first, second, and third bonding contacts coupled to the peripheral circuits are arranged in a first semiconductor structure. A control circuit, an analog-to-digital converter (ADC) circuit, and fourth and fifth bonding contacts coupled to the control circuit, and a sixth bonding contact coupled to the ADC circuit are arranged in a second semiconductor structure. After the first and second semiconductor structures are bonded together, a first signal channel is formed between the first and fourth bonding contacts, a second signal channel is formed between the second and fifth bonding contacts, and a third signal channel is formed between the third and sixth bonding contacts. The first, second, and third signal channels are configured to transmit different information; that is, different signal channels are set in the semiconductor device to transmit different information. This effectively solves the interaction problem between the first and second semiconductor structures according to different protocol requirements, enabling the semiconductor device to perform read, write, and erase operations as specified by the ONFI protocol, as well as to achieve in-memory computing functionality, thereby expanding the application range of the semiconductor device. Attached Figure Description

[0033] Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Figure 1 ;

[0034] Figure 2 A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Figure 2 ;

[0035] Figure 3 A three-dimensional structural schematic diagram of a semiconductor device provided in an embodiment of this disclosure;

[0036] Figure 4 This is a schematic diagram showing the distribution of multiple storage cells in a storage array according to an embodiment of the present disclosure;

[0037] Figure 5 A schematic diagram of an exemplary first semiconductor structure including peripheral circuitry provided in an embodiment of this disclosure;

[0038] Figure 6 A schematic cross-sectional view of an exemplary storage array including storage strings, provided for an embodiment of this disclosure;

[0039] Figure 7 An exemplary peripheral circuit diagram provided for embodiments of this disclosure;

[0040] Figure 8 Schematic diagrams of three signal channels provided in embodiments of this disclosure;

[0041] Figure 9A flowchart illustrating the execution of a first read operation according to an embodiment of this disclosure;

[0042] Figure 10 This is a schematic diagram of the clock signal waveforms corresponding to each signal channel during the execution of the first read operation, provided in an embodiment of this disclosure.

[0043] Figure 11 A schematic flowchart illustrating the execution of a first write operation according to an embodiment of this disclosure;

[0044] Figure 12 A schematic diagram of clock signal waveforms for each signal channel during the execution of a first write operation and a write verification operation, provided in an embodiment of this disclosure;

[0045] Figure 13 A schematic diagram of a semiconductor structure provided in an embodiment of this disclosure;

[0046] Figure 14 A schematic diagram of a packaging structure provided in an embodiment of this disclosure;

[0047] Figure 15 This is a schematic diagram of an exemplary memory computing device having semiconductor devices according to an embodiment of the present disclosure;

[0048] Figure 16 This is a schematic diagram of an exemplary memory card having semiconductor devices according to an embodiment of the present disclosure;

[0049] Figure 17 This is a schematic diagram of an exemplary solid-state driver having a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0050] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0051] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0052] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0053] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0054] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0055] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0056] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0057] In the classic von Neumann computing architecture, memory and processor are separate, with data transfer between them via a data bus. When executing commands, the processor first reads data from memory, processes it, and then writes the updated data back to memory. This frequent data movement incurs significant power consumption and time overhead. Furthermore, due to limited memory bandwidth, processor speed is constrained by memory access speed, severely impacting computational performance. With the rise of big data and artificial intelligence applications, the processing of massive amounts of data has made the bottlenecks of the von Neumann computing architecture increasingly prominent. To address these bottlenecks, in-memory computing chip architecture has emerged. Its basic idea is to embed computing functions within memory and directly utilize memory for logical calculations, thereby reducing the amount and distance of data transfer between memory and processor, lowering power consumption while improving computational performance. This promises to build high-performance, high-bandwidth, and high-energy-efficiency computing systems.

[0058] In-memory computing (IMC) chips possess both storage and computational capabilities due to their inherent physical characteristics. Storage capability refers to the ability of different memory devices to store numerical values ​​by changing their electrical conductance, while computational capability refers to the ability to perform vector-matrix multiplication within a given time by constructing an array of storage devices and applying Ohm's law and Kirchhoff's laws. IMC chips include, but are not limited to, Static Random Access Memory (SRAM), NAND flash memory, and Dynamic Random Access Memory (DRAM). Among these, NAND flash memory, being a non-volatile memory with a large capacity, has become a widely studied and important component in IMC chips.

[0059] The in-memory computing chip architecture of NAND flash memory provided in the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Figure 1 Before illustrating the semiconductor device, we first define the various directions that may be used in the following description. The stacking direction of the first semiconductor structure and the second semiconductor structure in the semiconductor device is defined as the first direction (i.e., the Z-axis direction). In a plane perpendicular to the Z-axis direction, we define the intersecting second direction (i.e., the X-axis direction) and the third direction (i.e., the Y-axis direction). In some embodiments, the X-axis direction, the Y-axis direction, and the Z-axis direction can be mutually perpendicular.

[0060] refer to Figure 1 , Figure 1 This is a schematic diagram of a semiconductor device provided in an embodiment of the present disclosure. The semiconductor device includes a first semiconductor structure 100 and a second semiconductor structure 200. The first semiconductor structure 100 includes a memory array 101, a peripheral circuit 102 coupled to the memory array 101, and a first bonding contact 103, a second bonding contact 104, and a third bonding contact 105 respectively coupled to the peripheral circuit 102. The second semiconductor structure 200 includes a control circuit 201, an analog-to-digital converter (ADC) 202 coupled to the control circuit 201, a fourth bonding contact 203 and a fifth bonding contact 204 respectively coupled to the control circuit 201, and a sixth bonding contact 205 coupled to the ADC 202. Here, each structure can be coupled in any suitable manner.

[0061] In this configuration, the first bonding contact 103 and the fourth bonding contact 203 form a first signal channel ①; the second bonding contact 104 and the fifth bonding contact 204 form a second signal channel ②; and the third bonding contact 105 and the sixth bonding contact 205 form a third signal channel ③. The first signal channel ①, the second signal channel ②, and the third signal channel ③ are configured to transmit different information. In this way, the interaction problem between the first semiconductor structure 100 and the second semiconductor structure 200 can be effectively solved according to different protocol requirements, enabling the semiconductor device to perform read, write, and erase operations as specified by the ONFI protocol, as well as to achieve in-memory computing functionality, thus expanding the application range of the semiconductor device.

[0062] It should be noted that the accompanying drawings shown in the embodiments of this disclosure are merely illustrative and do not limit the specific locations and direct connections of the corresponding circuits and memory arrays shown in the drawings. For example, an interconnect layer may also be included between the bonding contacts and the corresponding circuits and memory arrays. The interconnect layer includes a multi-layered metal layer with wiring, through which the bonding contacts are connected to the corresponding circuits.

[0063] In some embodiments, the first semiconductor structure 100 and the second semiconductor structure 200 are stacked on top of each other along the Z-axis; and the memory array 101 and the peripheral circuit 102 in the first semiconductor structure 100 can also be stacked on top of each other along the Z-axis, thereby reducing the overall size of the semiconductor device.

[0064] For example, in conjunction with reference Figure 2 and Figure 3 , Figure 2 A schematic cross-sectional structure of another semiconductor device is shown as an example. Figure 3 An example is shown Figure 2The corresponding three-dimensional structure diagram of the semiconductor device shows that the first semiconductor structure 100 includes a first sub-semiconductor structure 110 on which a memory array 101 is formed, and a second sub-semiconductor structure 120 on which a peripheral circuit 102, a first bonding contact 103, a second bonding contact 104 and a third bonding contact 105 are formed; the first sub-semiconductor structure 110 and the second sub-semiconductor structure 120 are stacked on top of each other along the Z-axis direction.

[0065] In some specific embodiments, a first sub-semiconductor structure 110, a second sub-semiconductor structure 120, and a second semiconductor structure 200 can be formed in parallel on different substrates. For example, the first sub-semiconductor structure 110 can be formed on a first substrate, the second sub-semiconductor structure 120 on a second substrate, and the second semiconductor structure 200 on a third substrate. They are then stacked together using various suitable bonding techniques, such as hybrid bonding and transfer bonding. Here, the second semiconductor structure 200 and the first sub-semiconductor structure 110, as well as the first sub-semiconductor structure 110 and the second semiconductor structure 120, can be bonded together using methods such as hybrid bonding (also known as "metal / dielectric hybrid bonding connection"), transfer bonding, anodic bonding, fused bonding, adhesive bonding, and eutectic bonding.

[0066] In some embodiments, such as Figure 2 As shown, the first sub-semiconductor structure 110 is located between the second sub-semiconductor structure 120 and the second semiconductor structure 200. In other words, the second semiconductor structure 200 is coupled to the first sub-semiconductor structure 110, and the side of the first sub-semiconductor structure 110 away from the second semiconductor structure 200 along the Z-axis is coupled to the second sub-semiconductor structure 120. The second semiconductor structure 200 can be coupled to an external device (e.g., a host). In this embodiment of the present disclosure, by vertically integrating the first sub-semiconductor structure 110, the second sub-semiconductor structure 120, and the second semiconductor structure 200, the chip size can be reduced and the storage density can be increased. In addition, integrating the control circuit 201 into the second semiconductor structure 200 can shorten the distance between the control circuit 201 and the peripheral circuit 102, thereby reducing signal delay.

[0067] In some embodiments, reference Figure 2The first sub-semiconductor structure 110 includes a first bonding layer 210 and a second bonding layer 220, which are located on opposite sides of the memory array 101 along the Z-axis. The second sub-semiconductor structure 120 includes a third bonding layer 230 on which a first bonding contact 103, a second bonding contact 104 and a third bonding contact 105 are formed. The second semiconductor structure 200 includes a fourth bonding layer 240 having a fourth bonding contact 203, a fifth bonding contact 204, and a sixth bonding contact 205; wherein the first bonding layer 210 and the fourth bonding layer 240 are bonded, and the second bonding layer 220 and the third bonding layer 230 are bonded, so that the first bonding contact 103 and the fourth bonding contact 203 are coupled to form a first signal channel ①, the second bonding contact 104 and the fifth bonding contact 204 are coupled to form a second signal channel ②, and the third bonding contact 105 and the sixth bonding contact 205 are coupled to form a third signal channel ③.

[0068] In some embodiments, the bonding contacts may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. In a specific example, the bonding contacts of the bonding layer include Cu. The remaining area of ​​the bonding layer may be formed of a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts in the bonding layer and the surrounding dielectric can be used for hybrid bonding, simultaneously achieving metal-to-metal bonding and dielectric-to-dielectric bonding.

[0069] refer to Figure 2 The semiconductor device also includes a first connection structure 301 that runs through the memory array 101 and is connected to the first bonding contact 103 and the fourth bonding contact 203 respectively; thereby, the control circuit 201 in the first semiconductor structure can be connected to the peripheral circuit 102 through the fourth bonding contact 203, the first connection structure 301 and the first bonding contact 103, thus forming the first signal channel ①.

[0070] refer to Figure 2 The semiconductor device further includes a second connection structure 302 that runs through the memory array 101 and is connected to the second bonding contact 104 and the fifth bonding contact 204, respectively. Thus, the control circuit 201 in the first semiconductor structure can be connected to the peripheral circuit 102 via the fifth bonding contact 204, the second connection structure 302, and the second bonding contact 104, thereby forming the second signal channel ②.

[0071] refer to Figure 2The semiconductor device also includes a third connection structure 303 that penetrates the memory array 101 and is connected to the third bonding contact 105 and the sixth bonding contact 205, respectively. Thus, the analog-to-digital converter circuit 202 in the first semiconductor structure can be connected to the peripheral circuit 102 through the sixth bonding contact 205, the third connection structure 303, and the third bonding contact 105, thereby forming a third signal channel ③. In actual operation, the first connection structure 301, the second connection structure 302, and the third connection structure 303 can be through array contacts (TACs).

[0072] It should be noted that each bonding layer is provided with bonding contacts connecting to each circuit or memory array, and all bonding contacts are configured identically. The above embodiments of this disclosure only exemplarily describe some bonding contacts; in other embodiments, refer to... Figure 2 The first bonding layer 210 may also include A bonding contacts, B bonding contacts and C bonding contacts; the second bonding layer 220 may also include D bonding contacts, E bonding contacts, F bonding contacts, G bonding contacts and H bonding contacts; the third bonding layer 230 may also include I bonding contacts and J bonding contacts.

[0073] For example, the fourth bonding contact 203 is bonded to the A bonding contact, the fifth bonding contact 204 is bonded to the B bonding contact, the sixth bonding contact 205 is bonded to the C bonding contact, the first bonding contact 103 is bonded to the D bonding contact, the second bonding contact 104 is bonded to the E bonding contact, the third bonding contact 105 is bonded to the F bonding contact, the G bonding contact is bonded to the I bonding contact, and the H bonding contact is bonded to the J bonding contact.

[0074] In some embodiments, reference Figure 2 The first semiconductor structure 100 further includes bit lines (BLs) 106, which are located between the memory array 101 and the peripheral circuit 102, and are coupled to both the memory array 101 and the peripheral circuit 102. In practice, the first semiconductor structure 100 may include multiple bit lines 106. Each bit line 106 can be coupled to multiple memory cells in the memory array 101. In this embodiment, the memory array 101 can be coupled to the peripheral circuit 102 via bit lines 106, G-bonding contacts, and I-bonding contacts, or via H-bonding contacts and J-bonding contacts. In practice, different transmission paths between the memory array 101 and the peripheral circuit 102 can be selected according to different protocol requirements. A detailed description of the transmission paths is provided below and will not be repeated here.

[0075] In some embodiments, the first semiconductor structure includes a three-dimensional NAND-type memory, that is, the memory array is a NAND-type memory array, or the memory cell is a NAND memory cell.

[0076] In some specific embodiments, the storage array 101 may include multiple storage planes, each storage plane may include multiple storage banks, each storage bank may include multiple storage blocks, each storage block may include multiple sub-storage blocks, each sub-storage block may include multiple storage strings, and each storage string may include multiple storage cells connected in series. For example, refer to... Figure 4 , Figure 4 An exemplary schematic diagram of the distribution of multiple storage cells in a storage array 101 is provided. For example... Figure 4 As shown, the memory array consists of several rows of parallel, staggered memory cell rows parallel to the gate isolation structure (GLS). Each two rows of memory cell rows are separated by a gate isolation structure and a select gate isolation structure. Each memory cell row includes multiple memory strings arranged along the X-direction. Figure 4 The diagram illustrates one memory cell in each memory string, with the remaining memory cells stacked along the Z-axis. The select gate isolation structure can be a top select gate isolation structure (TSG CUT), which divides the top select gate (TSG) into multiple top select lines. Alternatively, it can be a bottom select gate isolation structure (BSG CUT), which divides the bottom select gate (BSG) into multiple bottom select lines. The gate isolation structure can include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory array into multiple memory blocks, and multiple second gate isolation structures can divide each memory block into multiple sub-memory blocks. Figure 4 Only one memory block is shown as an example, but the memory can include multiple such blocks. Figure 4 The memory blocks shown are separated by a first gate isolation structure, and multiple memory blocks can be arranged along the Y direction.

[0077] It should be noted that, Figure 4 The number of cell rows shown between the gate isolation structure and the selected gate isolation structure is merely an example and is not intended to limit the number of cell rows contained in a sub-block of the three-dimensional NAND memory in this disclosure. In practical applications, the number of cell rows contained in a sub-block can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0078] Figure 5This is a schematic diagram of an exemplary second semiconductor structure including peripheral circuitry provided for embodiments of the present disclosure. The second semiconductor structure may include a memory array 101 and peripheral circuitry 102 coupled to the memory array 101. Taking a three-dimensional NAND-type memory array as an example, the memory cells 305 are NAND memory cells, provided in the form of an array of memory strings 304, each memory string 304 extending vertically. In some embodiments, each memory string 304 includes a plurality of memory cells 305 coupled in series and stacked vertically. Each memory cell 305 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 305. Each memory cell 305 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0079] In some implementations, each memory cell 305 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 305 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, such as a multi-level cell (MLC) storing two bits per cell, a triple-level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0080] like Figure 5As shown, each memory string 304 may include a bottom select gate (BSG) 307 at its source end and a top select gate (TSG) 306 at its drain end. The bottom select gate 307 and top select gate 306 can be configured to activate the selected memory string 304 during read and program operations. In some embodiments, the source ends of memory strings 304 within the same memory block 313 can be coupled via a common source line (CSL) 310. In other words, all memory strings 304 within the same memory block 313 have a common source (ACS). According to some embodiments, the top select gate 306 of each memory string 304 is coupled to a corresponding bit line 106, allowing data to be read from or written to the bit line 106 via an output bus (not shown). In some implementations, each memory string 304 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the top select transistor 306) or a deselect voltage (e.g., 0V) to the corresponding top select transistor 306 via one or more top select lines (TSL) 308 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the bottom select transistor 307) or a deselect voltage (e.g., 0V) to the corresponding bottom select transistor 307 via one or more bottom select lines (BSL) 309.

[0081] like Figure 5 As shown, the memory string 304 can be organized into multiple memory blocks 313, each of which can have a common source line 310. In some embodiments, each memory block 313 is the basic data unit for an erase operation, i.e., all memory cells 305 on the same memory block 313 are erased simultaneously. To erase a memory cell 305 in a selected memory block, an erase voltage bias can be used to couple the common source line 310 to the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 305 in adjacent memory strings 304 can be coupled via word lines (WL) 312, which selects which row of memory cells 305 is affected by a read or program operation.

[0082] Figure 6 This is a schematic cross-sectional view of an exemplary storage array including storage strings, provided for embodiments of this disclosure. Figure 6As shown, the memory array 101 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 stacked alternately in sequence, and a channel structure perpendicularly penetrating the gate layers 411 and the insulating layers 412. The channel structure is coupled to each gate layer 411 to form a memory cell, and the channel structure is coupled to the plurality of gate layers in the stacked structure 410 to form a memory string 304. The gate layers 411 and the insulating layers 412 may be stacked alternately, and two adjacent gate layers 411 are separated by an insulating layer 412.

[0083] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as a top select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a bottom select gate line, and the gate layer 411 extending laterally between the top select gate line and the bottom select gate line may serve as a word line layer. The top select gate line is used to form a top select transistor 306, and the bottom select gate line is used to form a bottom select transistor 307.

[0084] In some embodiments, the stacked structure 410 may be disposed on the substrate 400. The substrate 400 may include silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. In other embodiments, the semiconductor device may not include a substrate.

[0085] In some embodiments, the memory string 304 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0086] In some embodiments, return to reference Figure 5 The peripheral circuitry 102 may include any suitable analog, digital, and mixed-signal circuitry for operating the memory array 101 by applying voltage and / or current signals to each target memory cell via bit line 106, word line 312, common-source line 310, bottom select line 309, and top select line 308, and sensing voltage and / or current signals from each target memory cell. The peripheral circuitry 102 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MODS) technology.

[0087] refer to Figure 7 , Figure 7 Some exemplary peripheral circuitry is shown, including a page buffer / sensor amplifier 401, a column decoder / bit line driver 402, a row decoder / word line driver 403, a voltage generator 404, control logic 405, a register 406, a flash memory interface I / F 407, and a data bus 408. It should be understood that in some examples, the peripheral circuitry may also include... Figure 7 Additional peripheral circuitry not shown.

[0088] Page buffer / sensor amplifier 401 can be configured to read data from memory array 101 and program (write) data to memory array 101 according to control signals from control logic 405. In one example, page buffer / sensor amplifier 401 can store a page of programming data (write data) to be programmed into memory array 101. In another example, page buffer / sensor amplifier 401 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, page buffer / sensor amplifier 401 can also sense a low-power signal from the bit line representing the data bits stored in the memory cell and amplify a small voltage swing to a recognizable logic level during a read operation. Column decoder / bit line driver 402 can be configured to be controlled by control logic 405 and select one or more memory cell strings by applying a bit line voltage generated from voltage generator 404.

[0089] The row decoder / word line driver 403 can be configured to be controlled by control logic 405 and to select / deselect memory blocks of memory array 101 and select / deselect word lines of memory blocks. The row decoder / word line driver 403 can also be configured to drive word lines using word line voltages generated from voltage generator 404. In some embodiments, the row decoder / word line driver 403 can also select / deselect and drive bottom select lines and top select lines. As described in detail below, the row decoder / word line driver 403 is configured to perform programming operations on memory cells coupled to one or more selected word lines. The voltage generator 404 can be configured to be controlled by control logic 405 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 101.

[0090] Control logic 405 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 406 can be coupled to control logic 405 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Flash interface 407 can be coupled to control logic 405 and acts as a control buffer to buffer control commands received from host devices (not shown) and relay them to control logic 405, as well as to buffer status information received from control logic 405 and relay it to the memory controller. Flash interface 407 can also be coupled to column decoder / bit line driver 402 via data bus 408 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 101.

[0091] In some embodiments, return to reference Figure 3 The second semiconductor structure 200 may further include a digital processing circuit 206 coupled to the control circuit 201 and an interface circuit 207. The digital processing circuit 206 may include a dedicated processor, including but not limited to a CPU, GPU, digital signal processor (DSP), tensor processing unit (TPU), vision processing unit (VPU), neural processing unit (NPU), collaborative processing unit (SPU), physical processing unit (PPU), and image signal processor (ISP). In a specific example, the NPU may perform operations such as arithmetic / logic operations, rotation and shift operations, compensation operations, activation operations, and pooling operations. The interface circuit 207 may be used to receive and send data between the semiconductor device and other external devices. Specifically, the interface circuit 207 is configured to output the result of the operations performed by the digital processing circuit 206 to the external device.

[0092] Here, the control circuit 201 can be configured to control the operation of the first semiconductor structure 100 and the second semiconductor structure 200. That is, the control circuit 201 can act as a memory controller managing data storage and transmission in the second semiconductor structure 200 and an arithmetic controller managing data processing and transmission in the first semiconductor structure 100. In some embodiments, the control circuit 201 is also configured to control data transmission between the first semiconductor structure 100 and the second semiconductor structure 200. In some embodiments, the control circuit 201 is also configured to receive input data sent by an external device and send the input data to the first semiconductor structure 100.

[0093] Here, the analog-to-digital converter 202 converts the current / voltage signal output from the storage array 101 into a digital signal. The control circuit 201 and the digital processing circuit 206 perform various operations on the digital signal. Then, the result of the operations performed by the control circuit 201 and the digital processing circuit 206 is output to an external device through the interface circuit 207.

[0094] As mentioned above, different transmission paths can be selected between various circuits and the memory array according to different protocol requirements. In this embodiment of the disclosure, the first signal channel ①, the second signal channel ②, and the third signal channel ③ can transmit different information in combination with different protocol requirements and different needs of the control circuit. For example, refer to... Figure 8The first signal channel ① is configured to transmit system information adapted to the ONFI protocol and system information between the control circuit and peripheral circuits during the execution of Computing In Memory (CIM). The second signal channel ② is configured to transmit synchronization control information between the peripheral circuit and the control circuit during the execution of CIM. The third signal channel ③ is configured to transmit system information between the storage array and the analog-to-digital conversion circuit during the execution of CIM.

[0095] Specifically, the first signal channel ① is mainly used to transmit command information, address information, data information (writing or reading data), and status / feature information during read / write operations conforming to the ONFI protocol. It also transmits some interaction information between the control circuit and peripheral circuits during in-memory CIM computation, such as command information and data information (weight matrix, input vector data). The second signal channel ② is mainly used to transmit synchronization control information between the peripheral circuit and control circuit during in-memory CIM computation, such as synchronization signals and trigger signals. For example, synchronization signals can be used to coordinate the timing of the entire system, and trigger signals can be used to trigger specific events or operations. The third signal channel ③ is mainly used to transmit data information during in-memory CIM computation, such as CIM read data and CIM verification data.

[0096] It should be noted that during the CIM write operation of in-memory CIM calculation, the storage array 101 can be configured to store the weight matrix. Specifically, multiple weights in the weight matrix can be written into the storage array 101 according to certain mapping rules.

[0097] During the CIM read operation of in-memory computation (CIM), the semiconductor device needs to perform operations on the input vector data and the weight matrix. The input vector data can be an input vector composed of multiple elements, and the weight matrix consists of multiple weights. Each element in the input vector data needs to be multiplied and accumulated with the multiple weights in the weight matrix to obtain the corresponding element in the output data. In the computation phase, the first semiconductor structure can receive input vector data from an external device. Each element in the input vector data can be converted into an input voltage by a digital-to-analog converter (DAC) and input to the storage array via bit lines or word lines. After the multiplication and accumulation operation of the input vector data and the weight matrix, the corresponding storage current signal is output through the bit lines. The storage current signal enters the analog-to-digital converter (ADC) via peripheral circuitry and undergoes analog-to-digital conversion. Then, the ADC transmits the conversion result to the control circuit to output the final read data.

[0098] The following description, in conjunction with the accompanying diagram, illustrates the transmission of the three signal channels during the read and write operations of the in-memory computing CIM.

[0099] In some embodiments, in conjunction with reference Figure 2 and Figure 9 When performing the first read operation, namely the in-memory computation read operation (CIM Read), the control circuit 201 is configured to send a first command CMD1 through the first signal channel ①. The first command CMD1 is used to indicate the CIM read operation, that is, to perform vector multiplication and addition operations with the weight array by input vector data and read the operation result. At this time, the first command CMD1 includes a first read instruction (CIM Read CMD), a first read address (CIMRead Add), and input vector data (CIM Read Input data).

[0100] The peripheral circuit 102 is configured to receive and respond to the first command CMD1, and send first synchronization control information through the second signal channel ②; the first synchronization control information includes a trigger signal indicating that a first read operation can be sensed. It should be noted that before sending the first synchronization control information, the peripheral circuit 102 is also configured to acquire the status information of the storage array 101, which characterizes whether the storage array 101 can currently perform an in-memory computation read operation (CIM Read). During this process, the storage array 101's running (array setting) duration is, for example, Ta1.

[0101] The control circuit 201 is configured to receive first synchronization control information and send a first control signal to the analog-to-digital converter circuit 202; the first control signal is used to indicate the acquisition of the first computing current signal output by the storage array 101. Here, the first computing current signal output by the storage array 101 is transmitted to the peripheral circuit 102 through the bit line 106, and the peripheral circuit 102 then transmits it to the analog-to-digital converter circuit 202 through the third signal channel ③.

[0102] The analog-to-digital converter circuit 202 is configured to: in response to a first control signal, acquire a first memory current signal through a third signal channel ③, and convert the first memory current signal into first read data. During this process, the duration for which the analog-to-digital converter circuit 202 senses and acquires the first memory current signal is, for example, Ts1, i.e., the sampling time of the analog-to-digital converter circuit 202 is Ts1.

[0103] The control circuit 201 is configured to: acquire the first read data and the trigger signal of the analog-to-digital conversion circuit 202 ending the sensing, and send the second synchronization control information to the peripheral circuit 102 through the second signal channel ②; the second synchronization control information includes the trigger signal of the first read operation sensing completion.

[0104] The peripheral circuit 102 is configured to receive second synchronization control information and send third synchronization control information to the control circuit 201 via the second signal channel ②. The third synchronization control information includes a first read operation end signal. Here, the time from the completion of sensing by the analog-to-digital conversion circuit 202 to the end of the first read operation is, for example, Tb1. Thus, one CIM read operation is completed.

[0105] In some embodiments, reference Figure 10 , Figure 10 This is a schematic diagram of the clock signal waveforms corresponding to each signal channel during a first read operation, as shown in an embodiment of this disclosure. (Refer to reference...) Figure 9 and Figure 10 In the first time period T1, the first command CMD1 is transmitted through the first signal channel ①; the first command CMD1 includes a first read instruction (CIM Read CMD), a first read address (CIM Read Add), and input vector data (CIM Read Input data). The first time period T1 includes the operating duration Ta1 of the memory array 101. In the second time period T2, the first semiconductor structure is driven ( Figure 10 The NAND Drive generates a signal indicating that a first read operation can begin (i.e., first synchronization control information), and transmits this first synchronization control information to the control circuit 201 via the second signal channel ②. Additionally, the analog-to-digital converter 202 acquires the first storage current signal via the third signal channel ③. Figure 10 (Marked as Current level). In the third time period T3, the third signal channel ③ completes sensing, and the second semiconductor structure is driven ( Figure 11 The circuit (marked as Logic Drive) generates a trigger signal indicating the completion of the first read operation (i.e., the second synchronization control information), and transmits this second synchronization control information to the peripheral circuit 102 via the second signal channel ②. In the fourth time period T4, the peripheral circuit 102 transmits the third synchronization control information via the second signal channel ②. It should be understood that the first time period T1 is earlier than the second time period T2; the second time period T2 is earlier than the third time period T3; and the third time period T3 is earlier than the fourth time period T4.

[0106] It should be noted that after the input vector data is multiplied and accumulated with multiple weights in the weight matrix of the storage array, the first storage current signal is output.

[0107] In some embodiments, in conjunction with reference Figure 2 and Figure 11When performing the first write operation, namely the in-memory computation write operation (CIM Pgm), the control circuit 201 is configured to send a second command CMD2 through the first signal channel ①. The second command CMD2 includes write data and instructs that the write data be stored in the storage array 101. The write data mentioned here can be understood as the weight matrix mentioned in the previous embodiment, that is, the CIM write data. In other words, the second command CMD2 includes a first write instruction (CIM Pgm CMD), a first write address (CIM Pgm Add), and a weight matrix (CIM PgmInput data). The peripheral circuit 102 is configured to receive and respond to the second command CMD2, and store the weight matrix in the storage array 101. Here, during the storage of the weight matrix, multiple weights in the weight matrix can be stored in the storage array 101 according to a certain mapping rule. In this way, one CIM write operation is completed.

[0108] It should be noted that a complete write cycle includes one write operation (Pgm) and one write verification operation (Pgm Verify). Therefore, after performing the first write operation, a write verification operation is performed on the storage array to determine whether the weight matrix has been stored in the storage array, thereby ensuring the correctness and reliability of the first write operation. Here, the execution time of the first write operation (Pgm pluse) is, for example, Ta2, and the preparation time of the write verification operation (Verify ready) is, for example, Tb2.

[0109] In some embodiments, in conjunction with reference Figure 2 and Figure 11 When performing a write verification operation, i.e., in-memory computation programming verification (CIM Pgm Verify), the peripheral circuit 102 is configured to: send fourth synchronization control information through the second signal channel ②; the fourth synchronization control information includes the status information of the memory array 101, which is used to characterize whether the memory array 101 can currently perform the write verification operation (CIM Pgm Verify). The control circuit 201 is configured to: receive the fourth synchronization control information and send a second control signal to the analog-to-digital converter circuit 202; the second control signal is used to indicate the acquisition of the second in-memory computation current signal of the memory array. The analog-to-digital converter circuit 202 is configured to: in response to the second control signal, sense and acquire the second in-memory computation current signal output by the memory array 101 through the third signal channel ③, and convert the second in-memory computation current signal into CIM verification data; the control circuit 201 acquires the CIM verification data and the trigger signal that the analog-to-digital converter circuit 202 can end the sensing. In this process, the duration for the analog-to-digital converter circuit 202 to sense and acquire the in-memory computation current signal is, for example, Ts2, i.e., the sampling time of the analog-to-digital converter circuit 202 is Ts2.

[0110] The control circuit 201 is configured to verify the CIM write data (here, the weight matrix) against the CIM verification data, for example, by comparing the CIM write data with the CIM verification data. After verification, a fifth synchronization control message is sent through the second signal channel ②. The fifth synchronization control message includes a verification operation completion signal (CIM verifycompletion). Here, the duration from the completion of the verification operation to the end of the write verification operation is, for example, Tc.

[0111] The peripheral circuit 102 is configured to send a sixth synchronization control message via the second signal channel ②, the sixth synchronization control message including a signal that the verification data can be stored in the storage array. The control circuit 201 is configured to send a third control signal to the analog-to-digital conversion circuit 202, the third control signal indicating that the CIM verification data is transmitted to the storage array 101. In some embodiments, the CIM verification data can be transmitted to the storage array 101 via the third signal channel ③; in other embodiments, the CIM verification data can also be transmitted to the storage array 101 via the first signal channel ①, which is not limited in this disclosure. Thus, one CIM write verification operation is completed. That is, one complete write cycle is completed.

[0112] Next, based on the results of the verification operation, it is determined whether a second write loop is needed. If the verification result indicates that the write verification operation passed, no further write loop is needed; if the verification result indicates that the write verification operation failed, another write loop is needed. Thus, after several first write operations and write verification operations, the entire CIM write operation ends. In this case, the peripheral circuit 102 is configured to send seventh synchronization control information through the second signal channel ②; the seventh synchronization control information includes the CIM write operation end signal (CIM Pgm End).

[0113] In some embodiments, reference Figure 12 , Figure 12 This is a schematic diagram of the clock signal waveforms corresponding to each signal channel during the first write operation and write verification operation, as shown in an embodiment of this disclosure. (Refer to reference...) Figure 11 and Figure 12In the fifth time period T5, the second command CMD2 is transmitted through the first signal channel ①, and the CIM write data (here, the weight matrix) is stored in the storage array 101 according to the instructions of the second command CMD2. The second command CMD2 includes a first write instruction (CIM PgmCMD), a first write address (CIM Pgm Add), and a weight matrix (CIM Pgm Input data). The fifth time period T5 includes an execution time of, for example, Ta2 for the write operation (Pgm pluse), and a preparation time of, for example, Tb2 for the write verification operation (Verify ready).

[0114] In the sixth time period T6, the first semiconductor structure drives ( Figure 12 The NAND Drive generates fourth synchronization control information, including status information indicating that the storage array 101 can perform a write verification operation (CIM Pgm Verify), and transmits the fourth synchronization control information through the second signal channel ②. Then, the second memory current signal is transmitted through the third signal channel ③. Figure 12 The analog-to-digital converter (ADC) 202 converts the second memory current signal into verification data (marked as "Verify Current level"). Here, the ADC 202 senses and acquires the second memory current for a duration of Ts2. After verifying the CIM write data and CIM verification data, the control circuit 201 transmits the fifth synchronization control information through the second signal channel ②. The fifth synchronization control information includes a verification operation completion signal (CIM verify completion). Here, the duration from the completion of the verification operation to the end of the write verification operation is, for example, Tc. Next, the peripheral circuit 102 transmits the sixth synchronization control information through the second signal channel; and transmits the verification data through the third signal channel or the first signal channel. During this process, the verification data transfer and storage duration is Ts3.

[0115] During the seventh time period T7, the peripheral circuit 102 transmits the seventh synchronization control information through the second signal channel ②; the seventh synchronization control information includes the end signal of the CIM write operation (CIM Pgm End). It should be understood that the fifth time period T5 is earlier than the sixth time period T6; the sixth time period T6 is earlier than the seventh time period T7.

[0116] The following description, in conjunction with the accompanying diagram, illustrates the transmission of the three signal channels during the read / write operation specified in the ONFI protocol adaptation.

[0117] In some specific embodiments, when performing the second read operation, that is, when using a semiconductor device to perform a read operation adapted to the ONFI protocol, reference is made to... Figure 2The control circuit 201 is configured to send a third command CMD3 through the first signal channel ①; the third command CMD3 includes a second read instruction and a second read address. The peripheral circuit 102 is configured to receive and respond to the third command CMD3, and send the data stored in the storage array 101 (such as the second read data) to the control circuit 201 through the first signal channel ①.

[0118] In some specific embodiments, when performing the second write operation, i.e., when using a semiconductor device to perform a write operation adapted to the ONFI protocol, reference is made to... Figure 2 The control circuit 201 is configured to send a fourth command CMD4 via the first signal channel ①; the peripheral circuit 102 is configured to receive and respond to the fourth command CMD4, storing the write data contained in the fourth command CMD4 in the storage array 101 via the first signal channel ①. To distinguish it from CIM write data, this write data can be understood as ONFI write data. Similarly, when performing write verification operations conforming to the ONFI protocol, ONFI verification data is also transmitted via the first signal channel ①.

[0119] In this embodiment, when performing read / write operations conforming to the ONFI protocol, data or information is transmitted via the first signal channel ①. When performing read / write operations for in-memory computation (CIM), the first signal channel ①, the second signal channel ②, or the third signal channel ③ can be selected for transmission according to different requirements. This allows the semiconductor device to perform both read / write operations conforming to the ONFI protocol and read / write operations for in-memory computation (CIM), expanding the application range of the semiconductor device.

[0120] In the embodiments disclosed herein, the semiconductor device may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc. Specifically, the above-mentioned semiconductor device can be used in terminal products such as computers, televisions, set-top boxes, and automotive devices.

[0121] Based on a concept similar to the aforementioned semiconductor devices, this disclosure also provides a semiconductor structure, with reference to... Figure 13The semiconductor structure 800 includes a memory array 801, a peripheral circuit 802 coupled to the memory array 801, and a first bonding contact 803, a second bonding contact 804, and a third bonding contact 805 coupled to the peripheral circuit 802; wherein, the first bonding contact 803 is configured to transmit a first signal; the second bonding contact 804 is configured to transmit a second signal; and the third bonding contact 805 is configured to transmit a third signal; the information contents of the first signal, the second signal, and the third signal are different.

[0122] In some embodiments, the information content of the first signal includes system information adapted to the ONFI protocol and system information interacting with peripheral circuits during the execution of in-memory computation; the information content of the second signal includes synchronization control information interacting with peripheral circuits during the execution of in-memory computation; and the information content of the third signal includes system information interacting with the memory array during the execution of in-memory computation.

[0123] In some embodiments, the semiconductor structure 800 includes a first sub-semiconductor structure 810 on which a memory array 801 is formed and a second sub-semiconductor structure 820 on which a peripheral circuit 802 is formed; the first sub-semiconductor structure 810 further includes a first bonding layer 710 and a second bonding layer 720 located on opposite sides of the memory array 801; the second sub-semiconductor structure 820 further includes a third bonding layer 730 on which a first bonding contact 803, a second bonding contact 804 and a third bonding contact 805 are formed; the second bonding layer 720 and the third bonding layer 730 are bonded together.

[0124] In some embodiments, the semiconductor structure 800 further includes: a first connection structure 807 that penetrates the memory array 801 and is connected to a first bonding contact 803; a second connection structure 808 that penetrates the memory array 801 and is connected to a second bonding contact 804; and a third connection structure 809 that penetrates the memory array 801 and is connected to a third bonding contact 805.

[0125] In some embodiments, the first bonding layer 710 further includes bonding contacts A, B, and C; the second bonding layer 720 further includes bonding contacts D, E, F, G, and H; and the third bonding layer 730 further includes bonding contacts I and J. Specifically, bonding contact A is connected to first bonding contact 803 via first connection structure 807 and bonding contact D to form a channel for transmitting a first signal; bonding contact B is connected to second bonding contact 804 via second connection structure 808 and bonding contact E to form a channel for transmitting a second signal; and bonding contact C is connected to third bonding contact 805 via third connection structure 809 and bonding contact F to form a channel for transmitting a third signal.

[0126] In some embodiments, the semiconductor structure 800 further includes a bit line 806; the bit line 806 is located between the peripheral circuit 802 and the memory array 801; the memory array 801 is coupled to the peripheral circuit 802 through the bit line 806.

[0127] Based on a concept similar to the aforementioned semiconductor devices, this disclosure also provides a method for manufacturing a semiconductor device, wherein the method includes the following steps: forming a first semiconductor structure and a second semiconductor structure bonded together; the first semiconductor structure includes a memory array, a peripheral circuit coupled to the memory array, and a first bonding contact, a second bonding contact, and a third bonding contact respectively coupled to the peripheral circuit; the second semiconductor structure includes a control circuit, an analog-to-digital converter circuit coupled to the control circuit, a fourth bonding contact and a fifth bonding contact respectively coupled to the control circuit, and a sixth bonding contact coupled to the analog-to-digital converter circuit; wherein the first bonding contact and the fourth bonding contact are coupled to form a first signal channel; the second bonding contact and the fifth bonding contact are coupled to form a second signal channel; the third bonding contact and the sixth bonding contact are coupled to form a third signal channel; the first signal channel, the second signal channel, and the third signal channel transmit different information.

[0128] In some embodiments, the first signal channel transmits system information adapted to the ONFI protocol and system information between the control circuit and the peripheral circuit during the execution of in-memory computation; the second signal channel transmits synchronization control information between the peripheral circuit and the control circuit during the execution of in-memory computation; and the third signal channel transmits system information between the storage array and the analog-to-digital conversion circuit during the execution of in-memory computation.

[0129] In some embodiments, the method further includes: forming a bit line between the peripheral circuitry and the memory array, and coupling the memory array to the peripheral circuitry via the bit line.

[0130] In some embodiments, the formation of the first semiconductor structure and the second semiconductor structure with bonding connection includes: forming a memory array, and a first bonding layer and a second bonding layer located on opposite sides of the memory array to form a first sub-semiconductor structure; forming peripheral circuitry, and a fourth bonding layer including a first bonding contact, a second bonding contact, and a third bonding contact to form a second sub-semiconductor structure; forming a control circuit, an analog-to-digital conversion circuit, and a fourth bonding layer including a fourth bonding contact, a fifth bonding contact, and a sixth bonding contact to form a second semiconductor structure; bonding the fourth bonding layer to the first bonding layer, and bonding the second bonding layer to the third bonding layer to form the first semiconductor structure and the second semiconductor structure with bonding connection.

[0131] In some embodiments, the method further includes: forming a first connection structure that extends through the memory array and is respectively connected to a first bonding contact and a fourth bonding contact; forming a second connection structure that extends through the memory array and is respectively connected to a second bonding contact and a fifth bonding contact; and forming a third connection structure that extends through the memory array and is respectively connected to a third bonding contact and a sixth bonding contact.

[0132] Based on a concept similar to the aforementioned semiconductor device, this disclosure also provides a method for operating a semiconductor device, the semiconductor device including the semiconductor device described in the above embodiments of this disclosure; the method includes: when performing a first read operation, a control circuit transmits a first command to a peripheral circuit through a first signal channel; the first command includes a first read instruction, a first read address, and input vector data; in response to the first command, the peripheral circuit transmits first synchronization control information to the control circuit through a second signal channel; the first synchronization control information includes a first read operation start sensing trigger signal; the control circuit instructs an analog-to-digital converter circuit to acquire a first storage current signal through a third signal channel and convert the first storage current signal into first read data; the control circuit transmits second synchronization control information to the peripheral circuit through the second signal channel; the second synchronization control information includes a trigger signal indicating the completion of the first read operation sensing; and the peripheral circuit transmits third synchronization control information through the second signal channel; the third synchronization control information includes a first read operation end signal.

[0133] In some embodiments, the operation method further includes: when performing a write operation, the control circuit sends a second command to the peripheral circuit through a first signal channel; the second command includes write data; in response to the second command, the peripheral circuit stores the write data in a storage array.

[0134] In some embodiments, the operation method further includes: when performing a write verification operation, the peripheral circuit transmits fourth synchronization control information to the control circuit through a second signal channel; the fourth synchronization control information includes the status information of the storage array; the control circuit instructs the analog-to-digital conversion circuit to acquire a second computing current signal through a third signal channel and convert the second computing current signal into verification data; and verifies the data using the written data and the verification data; the control circuit sends fifth synchronization control information to the peripheral circuit through the second signal channel. The fifth synchronization control information includes a signal that the write verification operation has been completed; the peripheral circuit transmits sixth synchronization control information through the second signal channel; the sixth synchronization control information includes a signal that the verification data can be stored in the storage array; the control circuit transmits verification data to the peripheral circuit through a third signal channel or a first signal channel; the peripheral circuit transmits seventh synchronization control information to the control circuit through the second signal channel; the seventh synchronization control information includes a signal that the write operation has ended.

[0135] In some embodiments, the operation method further includes: when performing a second read operation, the control circuit transmits a third command through a first signal channel; the third command includes a second read instruction and a second read address; in response to the third command, the peripheral circuit transmits the second read data stored in the memory array to the control circuit through the first signal channel.

[0136] Based on the above-described semiconductor device, this disclosure also provides a packaging structure. Figure 14 This is a schematic diagram of a packaging structure provided in an embodiment of the present disclosure, as shown below. Figure 14 As shown, the packaging structure includes: a packaging substrate 902, a semiconductor device 901 as described in the above embodiment, and a molding compound 903; the semiconductor device 901 is disposed on the packaging substrate 902; and the molding compound 903 encapsulates the semiconductor device 901.

[0137] In some embodiments, such as Figure 14 As shown, the packaging substrate 902 includes a substrate 905 and a redistribution layer 904 formed on the substrate. A connection circuit is formed in the redistribution layer 904, and a semiconductor device 901 is disposed on the side of the redistribution layer 904 away from the substrate 905.

[0138] Based on the above-described semiconductor devices, embodiments of this disclosure provide a storage device. Figure 15 A schematic diagram of an exemplary in-memory computing device with semiconductor devices provided in embodiments of this disclosure, such as... Figure 15 As shown, the memory computing device includes a semiconductor device 1002 as described in any of the above embodiments.

[0139] In some embodiments, such as Figure 15 As shown, the in-memory computing device also includes a host 1001 coupled to the semiconductor device 1002.

[0140] In this disclosure, the in-memory computing device can be applied to an electronic device, which may be a mobile phone, smartphone, smartwatch, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable device having an in-memory computing device therein. Figure 15As shown, the in-memory computing device may include a host 1001 and a semiconductor device 1002. The semiconductor device 1002 may include one or more memory devices 1003 and a memory controller 1004. The host 1001 may include a processor of an electronic device, such as a central processing unit (CPU), or a system-on-a-chip (SoC), such as an application processor (AP). The host 1001 may be configured to send data to or receive data from the semiconductor device 1002. The memory device 1003 includes a memory array and peripheral circuitry coupled to the memory array. Here, the memory device 1003 may be the first semiconductor structure in the above embodiments, and the memory controller 1004 may be the second semiconductor structure in the above embodiments.

[0141] In some embodiments, memory controller 1004 is coupled to memory device 1003 and host 1001 and is configured to control memory device 1003. Memory controller 1004 can manage data stored in memory device 1003 and communicate with host 1001. In some embodiments, memory controller 1004 is designed to operate in low duty cycle environments, such as in secure digital cards, compact flash cards (CFC), universal serial bus (USB) flash drives, or in other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. In other embodiments, memory controller 1004 is designed to operate in high duty cycle environments, such as in solid-state drives or embedded multi-media cards (eMMC).

[0142] In some embodiments, the memory controller 1004 and one or more memory devices 1003 can be integrated into various types of storage devices, that is, the semiconductor device 1002 can be implemented and packaged into different types of terminal electronic products.

[0143] In such Figure 16In one example shown, the memory controller 1004 and a single memory device 1003 can be integrated into a memory card 1101. The memory card 1101 can be a compact flash memory card, a smart media card (SMC), a memory stick (MS), a multi-media card (MMC) such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card such as a Mini SD card, Micro SD card, SDHC card, etc., or a general-purpose flash memory card. The memory card 1101 may also include a connection between the memory card 1101 and a host device (e.g., Figure 15 The memory card connector 1102 is coupled to the host 1001. In such a... Figure 17 In another example shown, the memory controller 1004 and multiple memory devices 1003 may be integrated into the SSD 1103. The SSD 1103 may also include components for connecting the SSD 1103 to host devices (e.g., ...). Figure 15 The SSD connector 1104 is coupled to the host 1001. In some embodiments, the storage capacity and / or operating speed of the SSD 1103 is greater than the storage capacity and / or operating speed of the memory card 1101.

[0144] It should be understood that the phrases "some embodiments" or "embodiments of this disclosure" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "some embodiments" or "embodiments of this disclosure" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments of this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0145] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A first semiconductor structure and a second semiconductor structure bonded together; The first semiconductor structure includes a memory array, peripheral circuitry coupled to the memory array, and a first bonding contact, a second bonding contact, and a third bonding contact, respectively coupled to the peripheral circuitry. The second semiconductor structure includes a control circuit, an analog-to-digital converter circuit coupled to the control circuit, a fourth bonding contact and a fifth bonding contact respectively coupled to the control circuit, and a sixth bonding contact coupled to the analog-to-digital converter circuit. Wherein, the first bonding contact and the fourth bonding contact form a first signal channel; the second bonding contact and the fifth bonding contact form a second signal channel; the third bonding contact and the sixth bonding contact form a third signal channel; the first signal channel, the second signal channel and the third signal channel are configured to transmit different information.

2. The semiconductor device according to claim 1, characterized in that, The first signal channel is configured to transmit system information adapted to the ONFI protocol and system information between the control circuit and the peripheral circuit during the execution of in-memory computation; the second signal channel is configured to transmit synchronization control information between the peripheral circuit and the control circuit during the execution of in-memory computation; and the third signal channel is configured to transmit system information between the memory array and the analog-to-digital converter circuit during the execution of in-memory computation.

3. The semiconductor device according to claim 2, characterized in that, When performing the first read operation, The control circuit is configured to send a first command through the first signal channel; The peripheral circuit is configured to: in response to the first command, send first synchronization control information through the second signal channel; the first synchronization control information includes the first read operation start sensing trigger signal; The control circuit is configured to send a first control signal to the analog-to-digital conversion circuit; The analog-to-digital conversion circuit is configured to: in response to the first control signal, acquire the first computing current signal output by the storage array through the third signal channel; And, convert the first storage current signal into the first read data; The control circuit is configured to send second synchronization control information through the second signal channel; the second synchronization control information includes a trigger signal indicating that the first read operation has been sensed as complete. The peripheral circuit is configured to send third synchronization control information through the second signal channel; the third synchronization control information includes the first read operation end signal.

4. The semiconductor device according to claim 3, characterized in that, In the first time period, the first command is transmitted through the first signal channel; During the second time period, the first synchronization control information is transmitted through the second signal channel; and the first storage current signal is transmitted through the third signal channel. The first time period is earlier than the second time period; During the third time period, second synchronization control information is transmitted through the second signal channel; the second time period is earlier than the third time period. In the fourth time period, third synchronization control information is transmitted through the second signal channel; the third time period is earlier than the fourth time period.

5. The semiconductor device according to claim 2, characterized in that, When performing a write operation, The control circuit is configured to send a second command through the first signal channel; the second command includes writing data. The peripheral circuitry is configured to, in response to the second command, store the write data to the storage array.

6. The semiconductor device according to claim 5, characterized in that, When performing a write verification operation, The peripheral circuit is configured to send fourth synchronization control information through the second signal channel; the fourth synchronization control information includes the status information of the storage array. The control circuit is configured to send a second control signal to the analog-to-digital conversion circuit. The analog-to-digital conversion circuit is configured to: in response to the second control signal, acquire the second memory current signal output by the memory array through the third signal channel; and convert the second memory current signal into verification data. The control circuit is configured to: verify the written data and the verification data, and send fifth synchronization control information through the second signal channel; the fifth synchronization control information includes a signal indicating that the verification operation has been completed. The peripheral circuit is configured to send a sixth synchronization control information via the second signal channel; the sixth synchronization control information includes a signal that can store the verification data in the storage array. The control circuit is configured to: send a third control signal to the analog-to-digital conversion circuit; the analog-to-digital conversion circuit is configured to: in response to the third control signal, store the verification data to the storage array through the third signal channel; or, the control circuit is configured to: store the verification data to the storage array through the first signal channel; The peripheral circuit is configured to send seventh synchronization control information through the second signal channel; the seventh synchronization control information includes the end signal of the write operation.

7. The semiconductor device according to claim 6, characterized in that, During the fifth time period, the second command is transmitted through the first signal channel; During the sixth time period, the fourth synchronization control information is transmitted through the second signal channel; the second storage current signal is transmitted through the third signal channel. The fifth synchronization control information and the sixth synchronization control information are transmitted through the second signal channel, respectively. The verification data is transmitted through the third signal channel or the first signal channel; The fifth time period is earlier than the sixth time period; During the seventh time period, the seventh synchronization control information is transmitted through the second signal channel; The sixth time period is earlier than the seventh time period.

8. The semiconductor device according to claim 1, characterized in that, When performing the second read operation, The control circuit is configured to send a third command through the first signal channel; The peripheral circuit is configured to, in response to the third command, send the second read data stored in the storage array to the control circuit through the first signal channel.

9. The semiconductor device according to claim 1, characterized in that, The first semiconductor structure further includes a bit line located between the peripheral circuit and the memory array; the memory array is coupled to the peripheral circuit via the bit line.

10. The semiconductor device according to claim 1, characterized in that, The first semiconductor structure includes a first sub-semiconductor structure on which the memory array is formed and a second sub-semiconductor structure on which the peripheral circuit is formed; the first sub-semiconductor structure further includes a first bonding layer and a second bonding layer located on opposite sides of the memory array; the second sub-semiconductor structure further includes a third bonding layer on which the first bonding contact, the second bonding contact and the third bonding contact are formed; the second semiconductor structure includes a fourth bonding layer on which the fourth bonding contact, the fifth bonding contact and the sixth bonding contact are formed. The fourth bonding layer is bonded to the first bonding layer; the second bonding layer is bonded to the third bonding layer.

11. The semiconductor device according to claim 10, characterized in that, The semiconductor device further includes: a first connection structure that extends through the memory array and is respectively connected to the first bonding contact and the fourth bonding contact; a second connection structure that extends through the memory array and is respectively connected to the second bonding contact and the fifth bonding contact; and a third connection structure that extends through the memory array and is respectively connected to the third bonding contact and the sixth bonding contact.

12. The semiconductor device according to claim 1, characterized in that, The second semiconductor structure includes a three-dimensional NAND-type memory.

13. A packaging structure, characterized in that, include: The packaging substrate, the semiconductor device as described in any one of claims 1 to 12, and the molding layer; The semiconductor device is disposed on the packaging substrate; The molding compound encapsulates the semiconductor device.

14. A storage computing device, characterized in that, include: The semiconductor device as described in any one of claims 1 to 12.

15. A semiconductor structure, characterized in that, The semiconductor structure includes a memory array, peripheral circuitry coupled to the memory array, and a first bonding contact, a second bonding contact, and a third bonding contact, each respectively coupled to the peripheral circuitry. Wherein, the first bonding contact is configured to transmit a first signal; the second bonding contact is configured to transmit a second signal; and the third bonding contact is configured to transmit a third signal; the information content of the first signal, the second signal, and the third signal is different.

16. The semiconductor structure according to claim 15, characterized in that, The information content of the first signal includes system information adapted to the ONFI protocol and system information interacting with the peripheral circuit during the execution of in-memory computation; the information content of the second signal includes synchronization control information interacting with the peripheral circuit during the execution of in-memory computation; the information content of the third signal includes system information interacting with the memory array during the execution of in-memory computation.

17. The semiconductor structure according to claim 15, characterized in that, The semiconductor structure includes a first sub-semiconductor structure on which the memory array is formed and a second sub-semiconductor structure on which the peripheral circuit is formed; the first sub-semiconductor structure further includes a first bonding layer and a second bonding layer located on opposite sides of the memory array; the second sub-semiconductor structure further includes a third bonding layer on which the first bonding contact, the second bonding contact and the third bonding contact are formed; the second bonding layer and the third bonding layer are bonded together.

18. The semiconductor structure according to claim 17, characterized in that, The semiconductor structure further includes: a first connection structure that extends through the memory array and is connected to the first bonding contact; A second connection structure extends through the storage array and connects to the second bonding contact; and... The third connection structure extends through the storage array and is connected to the third bonding contact.

19. The semiconductor structure according to claim 15, characterized in that, The semiconductor structure further includes: a bit line located between the peripheral circuit and the memory array; the memory array is coupled to the peripheral circuit via the bit line.

20. A method for manufacturing a semiconductor device, characterized in that, The method includes: forming a first semiconductor structure and a second semiconductor structure that are bonded together; The first semiconductor structure includes a memory array, peripheral circuitry coupled to the memory array, and a first bonding contact, a second bonding contact, and a third bonding contact, each coupled to the peripheral circuitry. The second semiconductor structure includes a control circuit, an analog-to-digital converter circuit coupled to the control circuit, a fourth bonding contact and a fifth bonding contact respectively coupled to the control circuit, and a sixth bonding contact coupled to the analog-to-digital converter circuit. Wherein, the first bonding contact is coupled to the fourth bonding contact to form a first signal channel; the second bonding contact is coupled to the fifth bonding contact to form a second signal channel; the third bonding contact is coupled to the sixth bonding contact to form a third signal channel; the first signal channel, the second signal channel and the third signal channel transmit different information.

21. The manufacturing method according to claim 20, characterized in that, The first signal channel transmits system information adapted to the ONFI protocol and system information between the control circuit and the peripheral circuit during the execution of in-memory computation; the second signal channel transmits synchronization control information between the peripheral circuit and the control circuit during the execution of in-memory computation; and the third signal channel transmits system information between the storage array and the analog-to-digital converter circuit during the execution of in-memory computation.

22. The manufacturing method according to claim 21, characterized in that, The method further includes: A bit line is formed between the peripheral circuit and the memory array, and the memory array is coupled to the peripheral circuit through the bit line.

23. The manufacturing method according to claim 22, characterized in that, The first semiconductor structure and the second semiconductor structure forming the bonding connection include: The memory array, and a first bonding layer and a second bonding layer located on opposite sides of the memory array, are formed to form a first sub-semiconductor structure; The peripheral circuit and a third bonding layer comprising the first bonding contact, the second bonding contact and the third bonding contact are formed to form a second sub-semiconductor structure; The control circuit, the analog-to-digital conversion circuit, and a fourth bonding layer including the fourth bonding contact, the fifth bonding contact, and the sixth bonding contact are formed to form a second semiconductor structure; The fourth bonding layer is bonded to the first bonding layer, and the second bonding layer is bonded to the third bonding layer to form a first semiconductor structure and a second semiconductor structure with bonding connections.

24. The manufacturing method according to claim 23, characterized in that, The method further includes: A first connection structure is formed that extends through the storage array and is respectively connected to the first bonding contact and the fourth bonding contact; A second connection structure is formed, extending through the memory array and respectively connected to the second bonding contact and the fifth bonding contact; and... A third connection structure is formed that runs through the storage array and is respectively connected to the third bonding contact and the sixth bonding contact.

25. A method of operating a semiconductor device, characterized in that, The semiconductor device includes the semiconductor device according to any one of claims 1 to 12; the operation method includes: When performing the first read operation, the control circuit transmits a first command to the peripheral circuit through the first signal channel; the first command includes a first read instruction, a first read address, and input vector data. In response to the first command, the peripheral circuit transmits first synchronization control information to the control circuit through the second signal channel; the first synchronization control information includes the first read operation start sensing trigger signal; The control circuit instructs the analog-to-digital conversion circuit to acquire the first storage current signal through the third signal channel and convert the first storage current signal into the first read data. The control circuit transmits second synchronization control information to the peripheral circuit through the second signal channel; the second synchronization control information includes a trigger signal indicating the completion of the first read operation sensing; and... The peripheral circuit transmits third synchronization control information through the second signal channel; the third synchronization control information includes the first read operation end signal.

26. The operating method according to claim 25, characterized in that, The operation method further includes: When performing a write operation, the control circuit sends a second command to the peripheral circuit through the first signal channel; the second command includes writing data. In response to the second command, the peripheral circuitry stores the write data to the storage array.

27. The operating method according to claim 26, characterized in that, The operation method further includes: When performing a write verification operation, the peripheral circuit transmits fourth synchronization control information to the control circuit through the second signal channel; the fourth synchronization control information includes the status information of the storage array. The control circuit instructs the analog-to-digital conversion circuit to acquire the second storage current signal through the third signal channel and convert the second storage current signal into verification data; and to verify the written data with the verification data. The control circuit sends a fifth synchronization control message to the peripheral circuit through the second signal channel; the fifth synchronization control message includes a signal indicating that the write verification operation has been completed. The peripheral circuit transmits sixth synchronization control information through the second signal channel; the sixth synchronization control information includes a signal that can store verification data into the storage array. The control circuit transmits the verification data to the peripheral circuit through the third signal channel or the first signal channel; The peripheral circuit transmits seventh synchronization control information to the control circuit through the second signal channel; the seventh synchronization control information includes a write operation end signal.

28. The operating method according to claim 25, characterized in that, The operation method further includes: When performing the second read operation, the control circuit transmits a third command through the first signal channel; the third command includes a second read instruction and a second read address; In response to the third command, the peripheral circuit transmits the second read data stored in the memory array to the control circuit through the first signal channel.

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