Storage system, device, controller, control method, and storage medium

Abstract

The application discloses a storage system, a controller, a device, a control method of the storage system and a medium, and relates to the technical field of storage. The storage system comprises a memory device comprising a plurality of memory blocks; and a memory controller configured to: in response to power-on after power-off of the storage system, acquire a first voltage offset group of a first memory block; and based on the first voltage offset group and a second voltage offset group, adjust a retention time corresponding to at least one memory block in the memory device, wherein the second voltage offset group is a voltage offset group of the first memory block acquired before power-off of the storage system. The power-off time of the storage system can be predicted through the first voltage offset group and the second voltage offset group, and the power-off time is added to the retention time of the memory block, thereby improving the recording accuracy of the retention time of the memory block, and improving the timeliness and accuracy when the storage system performs a reliability measure on the memory block based on the retention time.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a storage system, device, controller, control method and storage medium. Background Technology

[0002] In solid-state drives (SSDs), data retention time refers to the time that data is stored in storage blocks after it has been programmed. As retention time increases, data reliability decreases, and corresponding measures need to be implemented to ensure data reliability.

[0003] The power loss time of SSDs should also be taken into account during the retention period. How to predict the power loss time of SSDs has become an urgent problem to be solved. Summary of the Invention

[0004] This application provides a storage system, device, controller, control method, and storage medium. The technical solution is as follows:

[0005] On one hand, a storage system is provided, the storage system comprising: a memory device and a memory controller;

[0006] A memory device, comprising multiple memory blocks; and

[0007] The memory controller is configured as follows:

[0008] In response to power-on after a power outage in the storage system, the first voltage offset group of the first storage block is acquired; and

[0009] Based on the first voltage offset group and the second voltage offset group, the retention time corresponding to at least one memory block in the memory device is adjusted, wherein the second voltage offset group is the voltage offset group of the first memory block obtained before the power failure of the memory system.

[0010] In an optional embodiment, the first storage block meets a first preset requirement;

[0011] The first preset requirement includes:

[0012] The retention time of the first storage block is less than the first preset duration;

[0013] The programmed temperature is within the preset temperature range;

[0014] The programming time of the first storage block reaches the second preset time.

[0015] In an optional embodiment, the memory controller is further configured to:

[0016] In response to the failure of the first storage block to match the first preset requirement, a second storage block that meets the second preset requirement is determined;

[0017] In response to power-on after a power outage in the storage system, the third voltage offset group of the second storage block is acquired; and

[0018] The retention time corresponding to at least one memory block in the memory device is adjusted based on the third voltage offset group and the fourth voltage offset group, wherein the fourth voltage offset group is the voltage offset group of the second memory block obtained before the power failure of the memory system.

[0019] The retention time corresponding to at least one memory block in the memory device is adjusted based on the third voltage offset group and the fourth voltage offset group.

[0020] In an optional embodiment, the second preset requirement includes:

[0021] The retention time of the second storage block is less than the third preset duration, and the retention time of the second storage block is less than or equal to the retention time of other programmed storage blocks in the memory device;

[0022] The programmed temperature is within the preset temperature range;

[0023] The second storage block is programmed for a period of time equal to the fourth preset duration.

[0024] In an optional embodiment, the memory controller is further configured to:

[0025] In response to the absence of a memory block that meets the second preset requirement in the memory device, the first memory block is used as the memory block for adjusting the retention time.

[0026] In an optional embodiment, the memory controller is further configured to:

[0027] During the operation of the storage system, the second voltage offset group of the first storage block is periodically acquired;

[0028] In response to a power failure in the storage system, the most recently acquired second voltage offset set is written to the memory device; and

[0029] In response to power-on after a power outage of the storage system, the second voltage offset group is read from the memory device.

[0030] In an optional embodiment, the memory controller is further configured to:

[0031] During the operation of the storage system, a read operation is performed on the first storage block using at least two candidate voltage offset groups to obtain the read results of at least two candidate voltage offset groups;

[0032] Based on the reading results and the at least two candidate voltage offset groups, the second voltage offset group is determined.

[0033] In an optional embodiment, the memory controller is further configured to:

[0034] Obtain the first voltage offset corresponding to the first programming state from the first voltage offset group; and,

[0035] Obtain the second voltage offset corresponding to the first programming state from the second voltage offset group.

[0036] In an optional embodiment, the memory controller is further configured to:

[0037] Obtain the first hold time corresponding to the first voltage offset;

[0038] Obtain the second hold time corresponding to the second voltage offset;

[0039] The power-down time of the storage system is obtained based on the first hold time and the second hold time;

[0040] The retention time corresponding to each of the at least one storage block is adjusted by the power-down time.

[0041] In an optional embodiment, the memory controller is further configured to:

[0042] The first retention time is determined based on the historical erase / write count of the first memory block and the first voltage offset.

[0043] The second hold time is determined based on the historical number of erase / write operations and the second voltage offset.

[0044] In an optional embodiment, the storage system includes a solid-state drive (SSD).

[0045] On the other hand, a memory controller is provided, the memory controller comprising:

[0046] The buffer is configured to buffer voltage offsets or groups of voltage offsets;

[0047] The one or more processors are configured to:

[0048] In response to power-on after a power outage in the storage system, the first voltage offset group of the first storage block is acquired; and

[0049] The retention time of at least one memory block in the memory device is adjusted based on the first voltage offset group and the second voltage offset group, wherein the second voltage offset group is the voltage offset group of the first memory block obtained before the power failure of the memory system.

[0050] On the other hand, an electronic device is provided, the electronic device comprising:

[0051] The storage system provided in any of the above embodiments, and

[0052] A host coupled to the storage system.

[0053] On the other hand, a control method for a storage system is provided, the method comprising:

[0054] In response to power-on after a power outage of the storage system, the first voltage offset group of the first storage block is obtained;

[0055] Based on the first voltage offset group and the second voltage offset group, the retention time corresponding to at least one memory block in the memory device is adjusted, wherein the second voltage offset group is the voltage offset group of the first memory block obtained before the power failure of the memory system.

[0056] In an optional embodiment, the first storage block meets a first preset requirement;

[0057] The first preset requirement includes:

[0058] The retention time of the first storage block is less than the first preset duration;

[0059] The programmed temperature is within the preset temperature range;

[0060] The programming time of the first storage block reaches the second preset time.

[0061] In an optional embodiment, the method further includes:

[0062] In response to the failure of the first storage block to match the first preset requirement, a second storage block that meets the second preset requirement is determined;

[0063] In response to power-on after a power outage of the storage system, the third voltage offset group of the second storage block is obtained;

[0064] The retention time corresponding to at least one memory block in the memory device is adjusted based on the third voltage offset group and the fourth voltage offset group, wherein the fourth voltage offset group is the voltage offset group of the second memory block obtained before the power failure of the memory system.

[0065] In an optional embodiment, the second preset requirement includes:

[0066] The retention time of the second storage block is less than the third preset duration, and the retention time of the second storage block is less than or equal to the retention time of other programmed storage blocks in the memory device;

[0067] The programmed temperature is within the preset temperature range;

[0068] The second storage block is programmed for a period of time equal to the fourth preset duration.

[0069] In an optional embodiment, the method further includes:

[0070] In response to the absence of a memory block that meets the second preset requirement in the memory device, the first memory block is used as the memory block for adjusting the retention time.

[0071] In an optional embodiment, the method further includes:

[0072] During the operation of the storage system, the second voltage offset group of the first storage block is periodically acquired;

[0073] In response to a power failure in the storage system, the most recently acquired second voltage offset set is written to the memory device; and

[0074] In response to power-on after a power outage of the storage system, the second voltage offset group is read from the memory device.

[0075] In an optional embodiment, the method further includes:

[0076] During the operation of the storage system, a read operation is performed on the first storage block using at least two candidate voltage offset groups to obtain the read results of at least two candidate voltage offset groups;

[0077] Based on the reading results and the at least two candidate voltage offset groups, the second voltage offset group is determined.

[0078] In an optional embodiment, the method further includes:

[0079] Obtain the first voltage offset corresponding to the first programming state from the first voltage offset group; and,

[0080] Obtain the second voltage offset corresponding to the first programming state from the second voltage offset group.

[0081] In an optional embodiment, adjusting the hold time corresponding to at least one memory block based on the first voltage offset and the second voltage offset includes:

[0082] Obtain the first hold time corresponding to the first voltage offset;

[0083] Obtain the second hold time corresponding to the second voltage offset;

[0084] The power-down time of the storage system is obtained based on the first hold time and the second hold time;

[0085] The retention time corresponding to each of the at least one storage block is adjusted by the power-down time.

[0086] In an optional embodiment, obtaining the first hold time corresponding to the first voltage offset includes:

[0087] The first retention time is determined based on the historical erase / write count of the first memory block and the first voltage offset.

[0088] The step of obtaining the second hold time corresponding to the second voltage offset includes:

[0089] The second hold time is determined based on the historical number of erase / write operations and the second voltage offset.

[0090] In an optional embodiment, the storage system includes a solid-state drive (SSD).

[0091] On the other hand, a non-volatile readable storage medium is provided, wherein at least one computer program is stored in the storage medium, the at least one computer program being loaded and executed by a processor to implement the control method of the storage system as described in any of the above embodiments.

[0092] The technical solution provided in this application may include the following beneficial effects:

[0093] When the storage system experiences a power outage and subsequent power restoration, the first voltage offset group of the first storage block is acquired. By using the first voltage offset group and the second voltage offset group acquired before the power outage, the power outage time of the storage system is predicted. The power outage time is then added to the hold time of the storage block, and the hold time of the storage block is adjusted. This improves the accuracy of recording the hold time of the storage block, thereby improving the timeliness and accuracy of the storage system in implementing reliability measures for the storage block based on the hold time, and ultimately improving the operational stability of the storage system. Attached Figure Description

[0094] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0095] Figure 1 This is a schematic diagram of a computer system provided in one embodiment of this application;

[0096] Figure 2 This is a schematic diagram of the structure of a storage system involved in this application;

[0097] Figure 3 This is a schematic diagram of the structure of a memory device provided in an embodiment of this application;

[0098] Figure 4 This is a circuit diagram of a memory device provided in an embodiment of this application;

[0099] Figure 5 This is a schematic diagram of a storage system provided in an embodiment of this application;

[0100] Figure 6 This is a schematic diagram of the TLC programming threshold voltage distribution provided in an exemplary embodiment of this application;

[0101] Figure 7 This is a schematic diagram of the structure of a memory controller provided in an embodiment of this application;

[0102] Figure 8 This is a schematic diagram of a computer system provided in an embodiment of this application;

[0103] Figure 9 This is a flowchart of a control method for a storage system provided in an embodiment of this application;

[0104] Figure 10 This is a flowchart of another control method for a storage system provided in an embodiment of this application. Detailed Implementation

[0105] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0106] The computer system provided in the embodiments of this application may include a host and a storage system. Figure 1 This is a schematic diagram of a computer system provided in one embodiment of this application. Figure 1As shown, system 100 includes a storage system 102 and a host 108 coupled to the storage system 102. The storage system 102 includes a memory device 104 and a memory controller 106 coupled to the memory device 104 and configured to control the memory device 104.

[0107] In an alternative embodiment, system 100 can be integrated into various types of electronic devices. These electronic devices may include mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, and so on.

[0108] The storage system 102 can be implemented as a storage system of the type such as Universal Flash Storage (UFS) or Solid State Disk (SSD). In this embodiment, the storage system 102 is implemented as an SSD for illustration.

[0109] As another example Figure 2 This is a schematic diagram of the structure of a storage system involved in this application. Figure 2 As shown, the storage system 102 may be a solid-state drive (SSD), and the storage system 102 includes a memory device 104 and a memory controller 106. The storage system 102 may also include a connector that couples the storage system 102 to the host 108.

[0110] In an alternative embodiment, the memory device 104 may be implemented as a NAND flash memory, such as a 3D (3-Dimensional) NAND flash memory. The structure of the memory device 104 will be explained below.

[0111] Figure 3 This is a schematic diagram of the structure of a memory device provided in an embodiment of this application. Figure 3 As shown, the memory device 104 includes peripheral circuitry 300 and a memory array 310.

[0112] The peripheral circuitry 300 is used to write data to and read data from the memory array 310. The peripheral circuitry 300 includes: a voltage generator 302, a page buffer / sensor amplifier 304, a column decoder / bit line (BL) driver 306, a row decoder / word line (WL) driver 308, control logic 312, a register 314, an input / output interface 316, and a data bus 318. It should be understood that in some examples, it may also include... Figure 3 Additional peripheral circuitry not shown.

[0113] Voltage generator 302 can be configured to be controlled by control logic 312 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 310.

[0114] Page buffer / sensor amplifier 304 can be configured to read data from memory array 310 and program (write) data to memory array 310 according to control signals from control logic 312. In one example, page buffer / sensor amplifier 304 can store a page of programming data (write data) to be programmed into a page of memory array 310. In another example, page buffer / sensor amplifier 304 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to a selected word line. In yet another example, page buffer / sensor amplifier 304 can also sense a low-power signal from a bit line representing a data bit stored in the memory cell and amplify a small voltage swing to a recognizable logic level during a read operation.

[0115] The column decoder / bit line driver 306 can be configured to be controlled by control logic 312 and to select one or more memory strings (e.g., NAND memory strings) by applying a bit line voltage generated from voltage generator 302.

[0116] The row decoder / word line driver 308 can be configured to be controlled by control logic 312 and to select / deselect blocks of the memory array 310 and to select / deselect word lines of the blocks. The row decoder / word line driver 308 can also be configured to drive word lines using a word line voltage (VWL) generated from a voltage generator 302. In some embodiments, the row decoder / word line driver 308 can also select / deselect and drive source-select gate lines and drain-select gate lines. Illustratively, the row decoder / word line driver 308 is configured to perform an erase operation on memory cells coupled to one or more selected word lines.

[0117] Peripheral logic unit 312 can be coupled to other components of each peripheral circuit described above and is configured to control the operation of other components of each peripheral circuit.

[0118] Register 314 can be coupled to peripheral logic unit 312 and includes a status register, a command register and an address register for storing status information, command opcode (OP code) and command address for controlling the operation of each peripheral circuit.

[0119] Input / output circuitry 316 can be coupled to peripheral logic unit 312 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to peripheral logic unit 312, as well as to buffer status information received from peripheral logic unit 312 and relay it to the host. Input / output circuitry 316 can also be coupled to column decoder / bit line driver 306 via data bus 318 and acts as a data input / output interface and data buffer to buffer data and relay it to or from memory array 310.

[0120] Figure 4 This is a circuit diagram of a memory device provided in an embodiment of this application. Figure 4 As shown, the memory device 104 includes:

[0121] Storage array 310 includes multiple rows of storage cells.

[0122] Multiple word lines 420 are coupled to multiple rows of memory cells.

[0123] Peripheral circuit 300 is coupled to multiple word lines 420 and configured to perform operations such as programming (i.e., writing data) or reading data on selected memory lines among multiple memory cell lines, wherein the selected memory cell line is the memory cell line coupled to the selected word line, in order to perform operations such as programming or reading data.

[0124] The storage array 310 may be a flash memory storage array (such as a NAND flash memory array). The storage array 310 includes a plurality of storage strings 411 arranged in an array, each storage string 411 extending vertically above a substrate (not shown). In some embodiments, each storage string 411 includes a plurality of storage cells 412 that are serially coupled and vertically stacked. Storage cells 412 include, but are not limited to, single-level cells (SLC), multi-level cells (MLC), trinary-level cells (TLC), and quad-level cells (QLC).

[0125] like Figure 4As shown, each memory string 411 may further include a source select gate (SSG) 413 located at the bottom and a drain select gate (DSG) 414 located at the top. The source select gate is also called the bottom select gate (BSG) or source selector, and the drain select gate is also called the top select gate (TSG) or drain selector. The source select gate 413 and the drain select gate 414 can be configured to activate the selected memory string 411 during read and program operations.

[0126] In some embodiments, the drain selection gate 414 of each memory string 411 is coupled to a corresponding bit line 415, and data can be read from or written to the bit line 415 via an output bus (not shown).

[0127] In some embodiments, each memory string 411 is configured to apply a selection voltage (e.g., higher than the threshold voltage of the transistor having the drain select gate 414) or a deselect voltage (e.g., 0V) to the corresponding drain select gate 414 via one or more DSG lines 416. And / or, in some embodiments, each memory string 411 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having the source select gate 413) or a deselect voltage (e.g., 0V) to the corresponding source select gate 413 via one or more SSG lines 417.

[0128] like Figure 4 As shown, the storage string 411 can be organized into multiple blocks 440. For any one of the multiple blocks 440, the block 440 can have a source line (SL) 418. The sources of all storage strings 411 in the block 440 are coupled through the source line 418. The source line is also called the common source line or array common source (ACS).

[0129] The source line 418 can be used for grounding, so that the sources of each memory cell in the memory string of block 440 can be grounded in some subsequent operations. Optionally, in some other operations, the sources of each memory cell in the memory string of block 440 can also be connected to a high voltage through the source line 418.

[0130] Each block 440 is the basic data unit used for the erase operation, meaning that all memory cells 412 on the same block 440 are erased simultaneously. To erase memory cells 412 in a selected block, an erase voltage (Vers) (e.g., a high positive voltage (20V or higher)) can be biased and coupled to the source line of the selected block.

[0131] It should be understood that, in other embodiments, erasure operations may be performed at the half-block level, at the quarter-block level, or at any suitable fractional level with any suitable number of blocks or blocks.

[0132] like Figure 4 As shown, the same layer of storage cells 412 of adjacent storage strings 411 in the same block 440 can be coupled through word lines 420. Word lines 420 are used to select which layer of storage cells 412 in the block 440 is affected by read and program operations.

[0133] In some embodiments, each word line 420 is coupled to the page to which the memory cell 412 belongs, and a page is a basic unit of data used for programming operations. The size of a page may be related to the number of memory strings 411 coupled by word lines 420 in a block 440. Each word line 420 may be coupled to the control gate (i.e., gate electrode) of each memory cell 412 in the corresponding page. It is understood that a memory cell row is a plurality of memory cells 412 located on the same page.

[0134] It should be noted that within a block 440, storage units at the same level correspond to the same word line, but storage units at the same level can be divided into one or more pages. That is, a word line can couple one or more pages.

[0135] Peripheral circuitry 300 can be coupled to memory array 310 via bit line 415, word line 420, source line 418, SSG line 417, and DSG line 416. Peripheral circuitry 300 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory array 310 by applying voltage and / or current signals to memory cells 412 and sensing voltage and / or current signals from memory cells 412 via bit line 415, word line 420, source line 418, SSG line 417, and DSG line 416.

[0136] In storage systems such as solid-state drives (SSDs), power failure refers to the loss of external power supply to the SSD. The data retention time of an SSD refers to the time data is stored in a storage block after being programmed. As the retention time increases, electrons in the storage layer of the storage cell may be lost under the influence of the intrinsic electric field, leading to a decrease in data reliability. Appropriate measures need to be taken to ensure data reliability, such as moving the data from the current storage block to another storage block.

[0137] The power loss time of SSDs should also be taken into account during the retention period. How to predict the power loss time of SSDs has become an urgent problem to be solved.

[0138] Based on this, this application provides a storage system 102 that can add the power failure time to the retention time of the storage block, adjust the retention time of the storage block, improve the recording accuracy of the retention time of the storage block, thereby improving the timeliness and accuracy of the storage system 102 in performing reliability measures on the storage block based on the retention time, and improving the operational stability of the storage system 102.

[0139] Figure 5 This is a schematic diagram of a storage system 102 provided in an embodiment of this application. Figure 5 As shown, the storage system 102 includes a memory device 104 and a memory controller 106, wherein the memory device 104 includes multiple memory blocks. Optionally, the storage system 102 includes solid-state drives (SSDs), universal flash storage (UFS), embedded multi-media cards (eMMC), and other systems. Optionally, in this embodiment, the memory device 104 is described as including a three-level storage cell (TLC) as an example. The memory device 104 may also include a two-level storage cell (MLC), a four-level storage cell (QLC), etc., and this embodiment does not limit the scope of the application.

[0140] The memory controller 106 is configured to: in response to power-on after a power failure of the memory system 102, acquire a first voltage offset group of the first memory block; and adjust the hold time corresponding to at least one memory block in the memory device 104 based on the first voltage offset group and the second voltage offset group, wherein the second voltage offset group is the voltage offset group of the first memory block acquired before the power failure of the memory system.

[0141] That is, in some embodiments, during the operation of the storage system 102 before power failure, the second voltage offset group of the first storage block is obtained.

[0142] In some embodiments, the power-down time of the storage system 102 is determined based on a first voltage offset group and a second voltage offset group, thereby adding the power-down time to the hold time of the storage blocks in the memory device 104, thus updating the hold time of the storage blocks in the memory device 104. In some embodiments, a fitting relationship between the voltage offset group and the hold time is constructed, thereby determining the power-down time of the storage system 102 based on the hold time determined by the first voltage offset group and the second voltage offset group of the first storage block, and then updating the hold time corresponding to at least one storage block in the memory device 104, improving the accuracy of hold time determination and the accuracy of hold time prediction for the storage blocks in the memory device 104.

[0143] Optionally, the second voltage offset group is an offset group obtained by the storage system 102 during operation for the first storage block to express the offset of multiple threshold voltage distributions in the first storage block. That is, multiple distinct voltages of multiple threshold voltage distributions in the first storage block are obtained. If there is a certain time interval between the current time and the time when the first storage block is programmed, the multiple distinct voltages obtained at the moment are offset relative to the multiple distinct voltages when the first storage block is programmed. The second voltage offset group is used to express this offset. Figure 6 This is a schematic diagram of the TLC programming threshold voltage distribution provided in an exemplary embodiment of this application. When the memory cell in the first memory block is programmed, the threshold voltage distribution of each state is as follows: Figure 6 The solid curve 610 in the figure shows the voltage difference between programming states P6 and P7. Taking programming state P7 as an example, the voltage difference between programming states P6 and P7 is Vrd1. After a certain time interval, programming states P6 and P7 shift, and the voltage difference between programming states P6 and P7 becomes Vrd2. Taking programming state P6 as an example, the voltage difference between programming states P5 and P6 is Vrd3. After a certain time interval, programming states P5 and P6 shift, and the voltage difference between programming states P5 and P6 becomes Vrd4. Taking programming state P5 as an example, the voltage difference between programming states P4 and P5 is Vrd5. After a certain time interval, programming states P4 and P5 shift, and the voltage difference between programming states P4 and P5 becomes Vrd6. Taking programming state P4 as an example, the distinguishing voltage between programming states P3 and P4 is Vrd7. After a certain time interval, programming states P3 and P4 shift, and the distinguishing voltage between them becomes Vrd8. Similarly, taking programming state P3 as an example, the distinguishing voltage between programming states P2 and P3 is Vrd9. After a certain time interval, programming states P2 and P3 shift, and the distinguishing voltage between them becomes Vrd10. Likewise, taking programming state P2 as an example, the distinguishing voltage between programming states P1 and P2 is Vrd11. After a certain time interval, programming states P1 and P2 shift, and the distinguishing voltage between them becomes Vrd12. Taking the programming state P1 as an example, the distinguishing voltage between the erase state P0 and the programming state P1 is Vrd13. However, after a certain period of time, the erase state P0 and the programming state P1 become offset, and the distinguishing voltage between the erase state P0 and the programming state P1 is Vrd14.

[0144] After the second voltage offset group is acquired, a power failure event occurs in the storage system 102. The first voltage offset group is an offset group acquired for the first storage block to express the offset of multiple threshold voltage distributions in the first storage block when the storage system 102 is powered on again after a power failure. That is, the second voltage offset group is the voltage offset group acquired before the storage system 102 is powered on, and the first voltage offset group is the voltage offset group acquired when the storage system 102 is powered on again after a power failure, with at least the power failure time of the storage system 102 between the two.

[0145] The aforementioned power failure event can be either a user-initiated event that terminates the power supply to the storage system 102, or an event where the host 108 or the storage system 102 stops supplying power due to an operational error. In other words, a power failure event refers to an event where the storage system 102 terminates its operation due to a power supply interruption. In the storage system 102, the method for detecting a power failure event includes at least one of the following: (1) The memory controller 106 monitors the power supply voltage in real time, and determines that a power failure event has occurred when it detects a sudden drop in power supply voltage or a voltage below a threshold. (2) When the memory controller 106 receives an interrupt signal, it determines that a power failure event has occurred, wherein the interrupt signal can be sent by the power management chip inside the storage system 102, or by other external devices connected to the storage system 102.

[0146] The storage system 102 provided in this application embodiment determines the power-down time of the storage system 102 by acquiring a first voltage offset group and a second voltage offset group, thereby adjusting the retention time corresponding to at least one storage block in the memory device 104 based on the power-down time. In some embodiments, at least one storage block refers to a storage block in the memory device 104 on which data has been written. After data is written to a storage block, the storage system 102 stores and updates the retention time corresponding to the storage block. In some embodiments, at least one storage block refers to a storage block in the memory device 104 on which valid data has been written. Valid data refers to data that is meaningful to the user or application and can be used normally. Optionally, valid data refers to data that has been processed by the application, conforms to business logic, and can be queried, modified, or used for other operations. Correspondingly, invalid data refers to data generated due to erroneous write operations, data corruption, or temporary placeholders.

[0147] In some embodiments, the retention time of a storage block is stored in a specified location in the storage system 102, such as in a specified storage block; or, a time counter is configured for each storage block, and the retention time of the storage block is stored and updated through the time counter.

[0148] The first storage block is a storage block in the memory device 104 in which data has been written. In some embodiments, the first storage block is randomly determined from the storage blocks in the memory device 104 in which data has been written; or, the first storage block is a storage block in the memory device 104 that meets the first preset requirements.

[0149] In some embodiments, when the memory device 104 includes a plurality of memory blocks that meet a first preset requirement, a first memory block is randomly determined from the plurality of memory blocks that meet the first preset requirement; or, the first memory block that meets the first preset requirement is selected as the first memory block; or, the memory block with the shortest programming completion time is selected from the plurality of memory blocks that meet the first preset requirement as the first memory block; or, the memory block with the shortest retention time is selected from the plurality of memory blocks that meet the first preset requirement as the first memory block. The above methods for determining the first memory block are merely illustrative examples, and the embodiments of this application do not limit this approach.

[0150] The first preset requirements include: 1.1 The retention time of the first storage block is less than the first preset duration; 1.2 The programming temperature of the first storage block is within the preset temperature range; 1.3 The programming time of the first storage block reaches the second preset duration.

[0151] By setting a first preset requirement to constrain the selection process of the first storage block, the additional impact of high temperature, low temperature, excessively long holding time, and insufficient programming completion time on the holding time prediction is avoided, which leads to the problem of low accuracy in the holding time prediction and improves the accuracy of power failure time prediction.

[0152] 1.1 "The retention time of the first storage block is less than the first preset duration" means that after data is written to the first storage block, the data is retained in the storage unit of the first storage block for less than the first preset duration. For example, if the first preset duration is 3 days, then the retention time of the first storage block is less than 3 days.

[0153] 1.2 The programming temperature of the first storage block is within a preset temperature range, meaning that the operating temperature of the storage system 102 is within the preset temperature range when the storage cells in the first storage block are being programmed. In some embodiments, during the programming process of the storage cells in the first storage block, the operating temperature of the storage system 102 is collected by a temperature sensor. Optionally, the operating temperature collected by the temperature sensor represents the programming temperature of the first storage block during programming.

[0154] Taking a temperature anomaly tag as an example, illustratively, the preset temperature range is between 20°C and 60°C, where the preset temperature range may or may not include 20°C, and may or may not include 60°C. During the programming process of the storage cells in the storage block, temperature data is collected by a temperature sensor. When the temperature data exceeds the preset temperature range, a temperature anomaly tag is stored in the designated storage location corresponding to the storage block. During the acquisition of the first storage block, if the designated storage location corresponding to the storage block does not contain a temperature anomaly tag, it is determined that the programming temperature of the storage block is within the preset temperature range.

[0155] Taking a normal temperature label as an example, illustratively, the preset temperature range is between 20°C and 60°C, where the preset temperature range may or may not include 20°C, and may or may not include 60°C. During the programming process of the storage cells in the storage block, temperature data is collected by a temperature sensor. If the temperature data exceeds the preset temperature range during programming, a normal temperature label is stored in the designated storage location corresponding to the storage block. During the acquisition of the first storage block, if the designated storage location corresponding to the storage block includes a normal temperature label, it is determined that the programming temperature of the storage block is within the preset temperature range.

[0156] In some embodiments, when the storage cells in the first storage block are programmed, the operating temperature value of the storage system 102 during the programming process is collected by a temperature sensor and stored in a designated storage location. Optionally, the maximum and minimum temperature values ​​collected during the programming process are stored in the designated storage location, or the average temperature value collected during the programming process is stored in the designated storage location. Subsequently, the programming temperature of the first storage block is determined based on the temperature value in the designated storage location to see if it is within a preset temperature range.

[0157] Optionally, the first voltage offset group and the second voltage offset group are voltage offset groups read from the first memory block when the temperature is within a preset temperature range. By constraining the programming temperature of the first memory block, the problem of inaccurate reading results of the voltage offset group caused by cross-temperature reads and writes to the first memory block is avoided.

[0158] 1.3 The time taken for the first storage block to complete programming reaches the second preset time. The time taken for the first storage block to complete programming refers to the time during which the storage cells in the first storage block are programmed and the storage block is ready to perform other operations. Illustratively, the completion of the first storage block programming means that the first storage block changes from an open state to a closed state, indicating that the first storage block has completed the programming operation and no longer accepts new data writes. At this time, the state of the storage block may include: 1. Data integrity: The data in the first storage block has been correctly programmed and verified; 2. Status marking: The first storage block is marked as "closed," indicating that its programming process has been completed; 3. Availability: The first storage block can be used by other operations (such as reading or erasing).

[0159] For illustrative purposes, the second preset duration is 10 minutes. If the first storage block is in a closed state for 10 minutes, it means that the first storage block has been programmed for the second preset duration.

[0160] In some embodiments, the duration for which the first storage block is in a closed state refers to the duration from the start time of the most recent switch to the closed state to the current time, that is, the duration for which the first storage block is continuously in a closed state. Illustratively, if the first storage block is in a closed state at a first moment within a historical time period, switches from a closed state to an open state at a second moment, and switches back from an open state to a closed state at a third moment, then the duration for which the first storage block is in a closed state refers to the duration from the third moment to the current time.

[0161] When determining the first storage block based on the first preset requirement, at least one of the following situations is included:

[0162] First, if the storage block stores storage block information related to the first preset requirement, then the storage blocks in the memory device 104 are scanned to obtain the storage block information of each storage block, and the first storage block is determined based on the scan results.

[0163] Second, the memory controller 106 stores memory block information related to the first preset requirement for each memory block. For example, the cache of the memory controller 106 caches memory block information related to the first preset requirement for each memory block, and the first memory block is determined based on the memory block information cached in the cache.

[0164] Third, if the designated storage block in the memory device 104 stores storage block information related to the first preset requirement, then a read operation is performed on the designated storage block, and the first storage block is determined based on the read storage block information.

[0165] It is worth noting that the above-described method for determining the first storage block is merely an illustrative example, and the embodiments of this application do not limit it.

[0166] In some embodiments, the memory controller 106 is further configured to: determine a second memory block that meets a second preset requirement in response to a failure of the first memory block to match a first preset requirement; acquire a third voltage offset group of the second memory block in response to power-on after a power outage of the memory system 102; and adjust the hold time corresponding to at least one memory block in the memory device 104 based on the third voltage offset group and the fourth voltage offset group, wherein the fourth voltage offset group is the voltage offset group of the second memory block acquired before the power outage of the memory system 102.

[0167] Schematic, during the operation of the storage system 102, in response to the failure of the first storage block to match the first preset requirement, a second storage block that meets the second preset requirement is determined; a fourth voltage offset group of the second storage block is obtained; in response to the power-on of the storage system 102 after a power outage, a third voltage offset group of the second storage block is obtained, and the retention time corresponding to at least one storage block in the memory device 104 is adjusted based on the third voltage offset group and the fourth voltage offset group.

[0168] The second preset requirements include: 2.1 The retention time of the second storage block is less than the third preset duration, and the retention time of the second storage block is less than or equal to the retention time of other programmed storage blocks in the memory device 104; 2.2 The programming temperature of the second storage block is within a preset temperature range; 2.3 The duration for which the second storage block is programmed reaches the fourth preset duration.

[0169] By setting a second preset requirement to constrain the selection process of the second storage block, the additional impact of high temperature, low temperature, excessively long hold time, and insufficient programming completion time on hold time prediction is avoided, which leads to low accuracy in hold time prediction and improves the accuracy of power failure time prediction.

[0170] Specifically, 2.1, "the retention time of the second storage block is less than the third preset duration, and the retention time of the second storage block is less than or equal to the retention time of other programmed storage blocks in the memory device 104," means that after data is written to the second storage block, the data is retained in the storage cells of the second storage block for less than the third preset duration, and the retention time of the second storage block is the shortest among the programmed storage blocks in the memory device 104. A programmed storage block refers to a storage block in a closed state. The third preset duration may be the same as or different from the first preset duration. For example, if the third preset duration is the same as the first preset duration (3 days), then the retention time of the second storage block is less than 3 days.

[0171] 2.2 The programming temperature of the second storage block is within a preset temperature range, which means that the operating temperature of the storage system 102 is within the preset temperature range when the storage cells in the second storage block are being programmed. In some embodiments, during the programming process of the storage cells in the second storage block, the operating temperature of the storage system 102 is collected by a temperature sensor. Optionally, the operating temperature collected by the temperature sensor represents the programming temperature of the second storage block during programming.

[0172] In some embodiments, when the storage cells in the second storage block are within a preset temperature range during programming, a normal temperature tag is stored at a designated location corresponding to the second storage block; or, when the storage cells in the second storage block are not within the preset temperature range during programming, a temperature abnormality tag is stored at a designated location corresponding to the second storage block. The second storage block whose programming temperature is within the preset temperature range is determined from the memory device 104 based on the normal temperature tag or the temperature abnormality tag.

[0173] Taking a temperature anomaly tag as an example, illustratively, the preset temperature range is between 20°C and 60°C, where the preset temperature range may or may not include 20°C, and may or may not include 60°C. During the programming process of the storage cells in the storage block, temperature data is collected by a temperature sensor. When the temperature data exceeds the preset temperature range, a temperature anomaly tag is stored at a designated location corresponding to the storage block. During the acquisition of the second storage block, if the designated location corresponding to the storage block does not contain a temperature anomaly tag, it is determined that the programming temperature of the storage block is within the preset temperature range.

[0174] In some embodiments, when the storage cells in the second storage block are programmed, the operating temperature value of the storage system 102 during the programming process is collected by a temperature sensor and stored in a designated storage location corresponding to the second storage block. Optionally, the maximum and minimum temperature values ​​collected during the programming process are stored in the designated storage location corresponding to the second storage block, or the average temperature value collected during the programming process is stored in the designated storage location corresponding to the second storage block. Subsequently, the programming temperature of the second storage block is determined based on the temperature value in the designated storage location to see if it is within a preset temperature range.

[0175] 2.3 The second storage block programming completion time reaches the fourth preset time. The second storage block programming completion time refers to the time during which the storage cells in the second storage block are programmed and the storage block is ready to perform other operations. For illustration, the second storage block programming completion means that the second storage block changes from an open state to a closed state, indicating that the second storage block has completed the programming operation and no longer accepts new data writing.

[0176] The fourth preset duration may be the same as or different from the second preset duration. For example, if the fourth and second preset durations are the same, and both are 10 minutes, then if the second storage block remains in a closed state for 10 minutes, it means that the programming of the second storage block has been completed for the second preset duration.

[0177] When determining the second storage block based on the second preset requirements, at least one of the following situations applies:

[0178] First, if the storage block stores storage block information related to the second preset requirement, then the storage blocks in the memory device 104 are scanned to obtain the storage block information of each storage block, and the second storage block is determined based on the scan results.

[0179] Second, the memory controller 106 stores memory block information related to the second preset requirement for each memory block. For example, the memory controller 106 caches memory block information related to the second preset requirement for each memory block in its cache, and then the second memory block is determined based on the memory block information cached in the cache.

[0180] Third, if the designated storage block in the memory device 104 stores storage block information related to the second preset requirement, then a read operation is performed on the designated storage block, and the second storage block is determined based on the read storage block information.

[0181] It is worth noting that the above-described method for determining the second storage block is merely an illustrative example, and the embodiments of this application do not limit it.

[0182] The second storage block is determined when the first storage block fails to match the first preset requirement. Optionally, the memory controller 106 acquires the storage block information of the first storage block according to a preset first cycle and determines whether the storage block information of the first storage block matches the first preset requirement. For example, the memory controller 106 acquires the storage block information of the first storage block every 10 seconds and determines whether the storage block information of the first storage block matches the first preset requirement. The memory controller 106 is also configured to determine the second storage block when the storage block information of the first storage block fails to match the first preset requirement. For example, if the retention time of the first storage block exceeds the first preset time, the second storage block is determined.

[0183] If the storage block information of the first storage block matches the first preset requirement, then continue to acquire and update the second voltage offset group of the first storage block.

[0184] In an optional embodiment, the memory controller 106 is further configured to use the first memory block as the memory block for adjusting the hold time in response to the absence of a memory block in the memory device 104 that meets the second preset requirement. That is, when the first memory block fails to match the first preset requirement, the memory controller 106 searches for a second memory block according to the second preset requirement. If no second memory block in the memory device 104 meets the second preset requirement, the first memory block is continued to be used as the memory block for adjusting the hold time, that is, the second voltage offset group of the first memory block is continued to be acquired.

[0185] In an optional embodiment, during the operation of the storage system, the memory controller 106 periodically acquires a second voltage offset group of the first storage block. Schematic, the memory controller 106 acquires the second voltage offset group of the first storage block according to a preset second cycle. The second cycle may be the same as the first cycle described above, or the second cycle may be different from the first cycle described above.

[0186] By periodically acquiring the second voltage offset group, the problem of not being able to acquire the second voltage offset group in time due to abnormal power failure is avoided. The second voltage offset group is periodically acquired and stored, and the acquired second voltage offset group is stored in the cache. Thus, when the storage system 102 is powered off, the most recently written second voltage offset group can be directly retrieved from the cache and written into the memory device 104 so that it can be retrieved in time after the storage system 102 is powered on, thereby improving the reliability of predicting the power failure time.

[0187] When the first cycle and the second cycle are the same preset cycle, optionally, the memory controller 106 obtains the storage block information of the first storage block according to the preset cycle, and determines whether the storage block information of the first storage block matches the first preset requirement. When the storage block information of the first storage block matches the first preset requirement, the second voltage offset group of the first storage block is obtained.

[0188] When the first cycle and the second cycle are different preset cycles, optionally, the memory controller 106 obtains the storage block information of the first storage block according to the first cycle, and determines whether the storage block information of the first storage block matches the first preset requirement. When the storage block information of the first storage block matches the first preset requirement, the second voltage offset group of the first storage block is collected at the moment when the second cycle is most recently reached after the current moment. When the storage block information of the first storage block fails to match the first preset requirement, the second storage block is determined, and the fourth voltage offset group of the second storage block is collected at the moment when the second cycle is most recently reached after the current moment.

[0189] In some embodiments, when the first storage block is used as the storage block for adjusting the retention time, the storage block identifier of the first storage block is saved, such as a logical address or other identification information; similarly, when the second storage block is used as the storage block for adjusting the retention time, the storage block identifier of the second storage block is saved. The storage block identifier is stored in the cache of the memory controller 106 and saved to the memory device 104 when the memory system 102 loses power; alternatively, the storage block identifier is stored at a designated address in the memory device 104.

[0190] The voltage offset groups described above are explained below. Specifically, the second voltage offset group is the voltage offset group collected for the first storage block during the operation of the storage system 102; the first voltage offset group is the voltage offset group collected for the first storage block after the storage system 102 has been powered off and then powered on again; the fourth voltage offset group is the voltage offset group collected for the second storage block after the second storage block is determined based on the second preset requirement, in the event that the first storage block fails to match the first preset requirement during the operation of the storage system 102; and the third voltage offset group is the voltage offset group collected for the second storage block after the storage system 102 has been powered off and then powered on again.

[0191] The explanation will take the first voltage offset group and the second voltage offset group as examples.

[0192] Second voltage offset group: In some embodiments, the memory controller 106 is further configured to: periodically acquire a second voltage offset group of the first memory block during the operation of the memory system 102; write the most recently acquired second voltage offset group to the memory device 104 in response to a power failure of the memory system 102; and read the second voltage offset group from the memory device 104 in response to a power failure and subsequent power-on of the memory system 102.

[0193] When obtaining the second voltage offset group of the first storage block, optionally, a default threshold voltage group is first used, and an error correction code (ECC) engine is used to correct the error bits of the first storage block.

[0194] Taking ECC error correction as an example, before writing user data to the first storage block, the user data is first ECC encoded to generate check data, and then the check data and user data are written to the flash memory. During user data verification, the user data and check data are processed through ECC error correction to determine the number of bits where the user data has been flipped.

[0195] Taking LDPC error correction as an example, when reading user data, the user data includes original information bits and redundant parity bits, with each information bit and parity bit corresponding to a variable node. During initialization, the variable node stores the received bit values, and each parity check equation corresponds to a parity node. During initialization, the parity node records the initial messages of its connected variable nodes, typically set to zero or a null value. Message passing is the core step in LDPC decoding, exchanging information between variable nodes and parity nodes iteratively to gradually update the confidence level of each bit's correctness. For each variable node, messages are received from all connected parity nodes (except the currently processed parity node), and combined with its own received values, the message to be sent to each parity node is calculated. For each parity node, messages are received from all connected variable nodes (except the currently processed parity node), and the message to be sent to each variable node is calculated according to parity constraints. After several message passing iterations, the decoder needs to perform a hard decision on each variable node, i.e., determine the final estimated value of each bit.

[0196] The voltage offset group corresponding to the threshold voltage group is adjusted based on the number of error bits in the read result, and the first memory block is read using the adjusted voltage offset group to obtain the read result; the voltage offset group is iterated and updated multiple times until ECC decoding is successful. That is, by adjusting the voltage offset group, a set of distinguishing voltages that differentiates multiple threshold voltage distributions is obtained, and the voltage offset group corresponding to this set of distinguishing voltages is obtained.

[0197] Optionally, during the operation of the storage system 102, a read operation is performed on the first storage block using at least two candidate voltage offset groups to obtain the read results of at least two candidate voltage offset groups; based on the read results and at least two candidate voltage offset groups, a second voltage offset group is determined.

[0198] Optionally, the voltage offset group when ECC decoding is successful can be used as the second voltage offset group.

[0199] To illustrate, taking the storage cells in the first storage block as an example including TLC, each storage cell can store 3 bits of data, meaning the storage cell can be programmed into an erase state and seven programming states corresponding to bit codes 111, 110, 100, 000, 010, 011, 001, and 101. To illustrate, Figure 6 This is a schematic diagram of the TLC programming threshold voltage distribution provided in an exemplary embodiment of this application. When the memory cell in the first memory block is programmed, the threshold voltage distribution of each state is as follows: Figure 6The solid curve 610 in the figure shows that the storage layer of the memory cell is surrounded by an insulator. Over time, electrons stored in the storage layer of the memory cell may be lost under the influence of the intrinsic electric field. This loss is particularly pronounced as the insulation effect of the tunnel oxide layer deteriorates with increasing write cycles. When the amount of lost electrons reaches a certain level, the bits in the memory cell flip. That is, as the retention time increases, electrons are lost from the memory cell, resulting in a shift in the threshold voltage. Taking a leftward shift of the threshold voltage as an example... Figure 6 The dashed curve 620 is shown in the figure.

[0200] Optionally, the voltage offsets corresponding to different programming states may be the same or different, wherein, with Figure 6 Taking the TLC shown as an example, the second voltage offset group includes at least one of the following: a voltage offset for distinguishing the voltage between erase state P0 and programming state P1, a voltage offset for distinguishing the voltage between programming state P1 and programming state P2, a voltage offset for distinguishing the voltage between programming state P2 and programming state P3, a voltage offset for distinguishing the voltage between programming state P3 and programming state P4, a voltage offset for distinguishing the voltage between programming state P4 and programming state P5, a voltage offset for distinguishing the voltage between programming state P5 and programming state P6, and a voltage offset for distinguishing the voltage between programming state P6 and programming state P7.

[0201] In some embodiments, a second hold time corresponding to the second voltage offset group is obtained. Obtaining the second hold time includes at least one of the following methods:

[0202] First, obtain the second voltage offset corresponding to the first programming state from the second voltage offset group; then obtain the second hold time corresponding to the second voltage offset.

[0203] The second voltage offset is obtained for the first programming state, which more intuitively reflects the offset of the threshold voltage distribution between the various programming states in the first memory block, and improves the efficiency of obtaining the second hold time.

[0204] To illustrate, taking a first memory block including a TLC as an example, the second voltage offset corresponding to programming state P7 is obtained from the second voltage offset group. This second voltage offset is used to distinguish between programming states P6 and P7, and the second hold time corresponding to the second voltage offset is obtained. Here, the first programming state can be any programming state, or it can be a pre-defined specified programming state.

[0205] Second, the average value of at least two voltage offsets in the second voltage offset group is obtained as the second voltage offset; the second holding time corresponding to the second voltage offset is obtained.

[0206] Among them, at least two voltage offsets can be implemented as all voltage offsets in the first voltage offset group, or as a partial voltage offset.

[0207] The average of at least two voltage offsets is obtained for at least two programming states as the second voltage offset, thereby more accurately reflecting the offset of the threshold voltage distribution between the programming states in the first memory block and improving the accuracy of obtaining the second hold time.

[0208] To illustrate, taking the first memory block as an example including TLC, the average value of the voltage offsets corresponding to programming states P5, P6, and P7 in the second voltage offset group is obtained as the second voltage offset. That is, the voltage offset between programming states P4 and P5, the voltage offset between programming states P5 and P6, and the voltage offset between programming states P6 and P7 are obtained, and the average value of the above voltage offsets is calculated as the second voltage offset.

[0209] It is worth noting that the above method for determining the second voltage offset is merely an illustrative example, and the embodiments of this application do not limit it.

[0210] Optionally, during the operation of the storage system 102, the memory controller 106 is further configured to: periodically acquire the second voltage offset of the first storage block and write the second voltage offset into a cache; and in response to receiving a power-down signal from the storage system 102, write the most recently written second voltage offset from the cache into the memory device 104. Alternatively, during the operation of the storage system 102, it periodically acquires a group of second voltage offsets of the first storage block and writes the group of second voltage offsets into a cache; in response to receiving a power-down signal from the storage system 102, it writes the most recently written group of second voltage offsets from the cache into the memory device 104; and after the storage system 102 is powered on, it reads the group of second voltage offsets from the memory device 104 and acquires the second voltage offset.

[0211] Taking SSD as an example, a backup capacitor can be soldered on the SSD's printed circuit board (PCB). After a power failure event occurs, the backup capacitor provides power to the SSD and writes the second voltage offset of the most recent write in the cache into the memory device 104.

[0212] In some embodiments, the aforementioned power failure event is merely an illustrative example. In response to a preset trigger event generated by the storage system 102, the second voltage offset is written into the memory device 104, such as when an abnormal event occurs in the operating temperature of the storage system 102, such as exceeding a preset temperature range. This application embodiment does not limit the timing of writing the second voltage offset into the memory device 104.

[0213] First voltage offset group: In response to power-on after a power outage in the storage system 102, a first voltage offset group corresponding to the first storage block is obtained. Optionally, the storage block corresponding to the second voltage offset group obtained by the storage system during power outage, i.e., the aforementioned first storage block, is first determined, and then the second voltage offset group corresponding to the first storage block is obtained. In some embodiments, when storing the second voltage offset group, the storage block identifier of the storage block corresponding to the second voltage offset group is also stored. The storage block identifier includes at least one of the following identifiers: storage block address, storage block number, etc.

[0214] In some embodiments, a first voltage offset group is acquired during a preset phase of power-on of the storage system 102. Indicatively, the power-on process of the storage system 102 includes at least one of the following phases: 1. Power-on, wherein the storage system 102 is connected to a power source, and the power management unit is activated to supply power to each module of the storage system 102; 2. Hardware self-test, performing self-tests on each hardware module and interface in the storage system 102; 3. Controller initialization, such as firmware loading, basic function initialization, etc.; 4. Storage medium initialization, such as detecting whether the storage medium is correctly connected, acquiring attribute data of the storage medium, etc.; 5. File system and logical structure initialization; 6. Driver interaction with the operating system, such as the host 108 operating system identifying and loading the driver used to drive the storage system 102; 7. Data integrity verification and recovery, used for data verification and recovery; 8. System ready.

[0215] In some embodiments, during the data integrity verification and recovery phase, the second voltage offset stored when the system was powered off is obtained; and a first voltage offset group is obtained for the first storage block.

[0216] In some embodiments, the method for obtaining the first voltage offset group is the same as the method for obtaining the second voltage offset group described above, and will not be repeated here.

[0217] In some embodiments, a first hold time corresponding to a first voltage offset group is obtained. Obtaining the first hold time includes at least one of the following methods:

[0218] First, obtain the first voltage offset corresponding to the first programming state from the first voltage offset group; obtain the first hold time corresponding to the first voltage offset.

[0219] To illustrate, taking a first memory block including a TLC as an example, the first voltage offset corresponding to programming state P7 is obtained from the first voltage offset group. This first voltage offset is used to distinguish between programming state P6 and programming state P7, and the first hold time corresponding to the first voltage offset is obtained. Here, the first programming state is any programming state, or the first programming state is a pre-set specified programming state.

[0220] Second, the average value of at least two voltage offsets in the first voltage offset group is obtained as the first voltage offset; the first holding time corresponding to the first voltage offset is obtained.

[0221] To illustrate, taking the first memory block as an example including TLC, the average value of the voltage offsets corresponding to programming states P5, P6, and P7 in the first voltage offset group is obtained as the first voltage offset. That is, the voltage offset between programming states P4 and P5, the voltage offset between programming states P5 and P6, and the voltage offset between programming states P6 and P7 are obtained, and the average value of the above voltage offsets is calculated as the first voltage offset.

[0222] It is worth noting that the above method for determining the first voltage offset is only an illustrative example, and the embodiments of this application do not limit it. The rules for obtaining the first voltage offset and the second voltage offset are the same.

[0223] Optionally, the power-down time of the storage system is obtained based on the first hold time and the second hold time, and the hold time corresponding to at least one storage block is adjusted based on the power-down time. The first hold time is the hold time collected for the first storage block after a system power-down. The time difference between the first hold time and the second hold time is taken as the power-down time, and the hold time corresponding to at least one storage block is adjusted based on the power-down time, for example, by adding the power-down time to the hold time of at least one storage block to obtain the updated hold time of at least one storage block.

[0224] In some embodiments, when determining the first holding time based on the first voltage offset, the first holding time is calculated using a pre-set fitting formula and the first voltage offset.

[0225] Optionally, since data retention capability is related to the number of flash memory erase / write cycles, generally, the more erase / write cycles, the worse the data retention capability and the shorter the data retention period. Therefore, a first retention time is determined based on the historical erase / write cycles of the first memory block and a first voltage offset; and a second retention time is determined based on the historical erase / write cycles and a second voltage offset.

[0226] The illustrative fitting formula between voltage offset and holding time is shown below:

[0227] (1) PE 0-1K: y=a1x 2 -b1x+c1;

[0228] (2) PE 1-3K: y=a2x 2 -b2x+c2;

[0229] (3) PE 3-7K: y=a3x 2 -b3x+c3;

[0230] (4) PE≥7K: y=a4x 2 -b4x+c4.

[0231] Among them, a1, b1, c1, a2, b2, c2, a3, b3, c3, a4, b4, and c4 are pre-set known parameters, and the four fitting formulas are different.

[0232] For illustration purposes, a1 has a value of 1.53, b1 has a value of 12.73, and c1 has a value of 28.09.

[0233] Among them, PE 0-1K refers to the number of historical erase / write cycles in the range of 0 to 1000, taking 0 and excluding 1000; PE 1-3K refers to the number of historical erase / write cycles in the range of 1000 to 3000, taking 1000 and excluding 3000; PE 3-7K refers to the number of historical erase / write cycles in the range of 3000 to 7000, taking 3000 and excluding 7000; PE≥7K refers to the number of historical erase / write cycles in the range of 7000 or greater.

[0234] In some embodiments, the historical erase / write counts of the first memory block are stored in a designated storage location corresponding to the first memory block. The historical erase / write counts of the first memory block are obtained from the designated storage location corresponding to the first memory block, and the first hold time corresponding to the first voltage offset of the first memory block is calculated based on the historical erase / write counts and the corresponding fitting formula.

[0235] It is worth noting that the historical erase / write count ranges corresponding to the above-described fitting formulas are merely illustrative examples. Other granularities can be used to divide the historical erase / write count ranges corresponding to the fitting formulas, such as 0-1K, 1-2K, 2-3K, and so on. This application does not limit the method of dividing the historical erase / write count ranges. Furthermore, the formula form of the above-described fitting formulas is merely illustrative. The above-described fitting formulas can also be implemented as third-order formulas, square root formulas, or other arbitrary forms. This application does not limit the formula form of the fitting formulas.

[0236] When predicting the retention time, the historical write / erase count of the first storage block is taken into account to avoid the problem that the retention time prediction accuracy of the first storage block is poor due to too few or too many historical write / erase counts. By dividing the write / erase count into intervals, the retention time of the first storage block before and after power failure is predicted based on the intervals corresponding to the historical write / erase counts of the first storage block. This improves the prediction accuracy of the power failure time and reduces the impact of the historical write / erase counts on the prediction of the power failure time.

[0237] Based on the historical write / erase count of the first memory block, the corresponding fitting formula is used for calculation. For example, if the historical write / erase count of the first memory block is 3200, then formula (3) is used to calculate the retention time corresponding to the first voltage offset and the second voltage offset. Here, x corresponds to the voltage offset, and y is the calculated retention time. Substituting the first voltage offset as the value of x into formula (3) yields the first retention time rttTime1, and substituting the second voltage offset as the value of x into formula (3) yields the second retention time rttTime2. The power-off time tPowerOff = rttTime1 - rttTime2 is then calculated.

[0238] The power-down time tPowerOff is added to the hold time of each memory block in the memory device 104 that has been written with data to obtain the updated hold time for each memory block.

[0239] It is worth noting that the above embodiments are illustrated by taking the acquisition of the first voltage offset group and the second voltage offset group based on the first storage block as an example. In some embodiments, when the third voltage offset group and the fourth voltage offset group are acquired based on the second storage block, the acquisition method can refer to the above process of acquiring the first voltage offset group and the second voltage offset group, which will not be repeated here.

[0240] Optionally, when the first storage block fails to match the first preset requirement, after obtaining the second storage block, the second storage block is regarded as the updated first storage block, and the same judgment logic and data acquisition logic are performed on the second storage block as on the first storage block.

[0241] In summary, the storage system provided in this application, when the storage system experiences a power outage and then power-on, acquires a first voltage offset group of the first storage block. It then uses the first voltage offset group and a second voltage offset group acquired before the power outage to predict the power outage time of the storage system. This power outage time is added to the storage block's hold time, adjusting the hold time and improving the accuracy of the storage block's hold time recording. This enhances the timeliness and accuracy of the storage system in implementing reliability measures based on the hold time, thereby improving the operational stability of the storage system.

[0242] Figure 7 This is a schematic diagram of the structure of a memory controller 106 provided in an embodiment of this application. Figure 7 As shown, the memory controller 106 includes a cache 701 and one or more processors 702.

[0243] The buffer 701 is configured to cache voltage offsets or groups of voltage offsets. In this embodiment, the example is described using the memory 701 configured to cache voltage offsets. Optionally, the buffer 701 includes a buffer and a cache in the memory controller 106, wherein both the buffer and the cache can be implemented as dynamic random access memory (DRAM) or static random access memory (SRAM). Illustratively, the first voltage offset is cached in the buffer, or the first voltage offset is cached in the cache; this is not limited here.

[0244] One or more processors 602 are configured to: in response to power-on after a power failure of the storage system 102, acquire a first voltage offset group of a first storage block; and adjust the hold time corresponding to at least one storage block in the memory device 104 based on the first voltage offset group and a second voltage offset group, wherein the second voltage offset group is the voltage offset group of the first storage block acquired before the power failure of the storage system 102.

[0245] In an optional embodiment, the first storage block meets a first preset requirement;

[0246] The first pre-defined requirement includes:

[0247] The retention time of the first storage block is less than the first preset duration;

[0248] The programmed temperature is within the preset temperature range;

[0249] The programming time for the first storage block is completed reaches the second preset time.

[0250] In an optional embodiment, one or more processors 602 are further configured to:

[0251] In response to the failure of the first storage block to match the first preset requirement, a second storage block that meets the second preset requirement is determined;

[0252] In response to power-on after a power outage in storage system 102, the third voltage offset group of the second storage block is acquired; and

[0253] The retention time of at least one memory block in the memory device 104 is adjusted based on the third voltage offset group and the fourth voltage offset group, wherein the fourth voltage offset group is the voltage offset group of the second memory block obtained before the power failure of the memory system 102.

[0254] In an optional embodiment, the second preset requirement includes:

[0255] The retention time of the second storage block is less than the third preset duration, and the retention time of the second storage block is less than or equal to the retention time of other programmed storage blocks in the memory device 104.

[0256] The programmed temperature is within the preset temperature range;

[0257] The second storage block is programmed for a period of time until the fourth preset duration is reached.

[0258] In an optional embodiment, one or more processors 602 are further configured to:

[0259] In response to the absence of a memory block in the memory device 104 that meets the second preset requirement, the first memory block is used as the memory block for adjusting the holding time.

[0260] In an optional embodiment, one or more processors 602 are further configured to:

[0261] During the operation of the storage system 102, the second voltage offset group of the first storage block is periodically acquired; and the acquired second voltage offset group is written into the cache 701.

[0262] In response to a power failure in storage system 102, the second voltage offset group of the most recently written cache 701 is written to memory device 104; and

[0263] In response to power-on after a power failure of the storage system 102, the second voltage offset group is read from the memory device 104.

[0264] In an optional embodiment, one or more processors 602 are further configured to:

[0265] During the operation of the storage system 102, a read operation is performed on the first storage block using at least two candidate voltage offset groups to obtain the read results of at least two candidate voltage offset groups;

[0266] Based on the reading results and at least two candidate voltage offset groups, a second voltage offset group is determined.

[0267] In an optional embodiment, one or more processors 602 are further configured to:

[0268] Obtain the first voltage offset corresponding to the first programming state from the first voltage offset group; and,

[0269] Obtain the second voltage offset corresponding to the first programming state from the second voltage offset group.

[0270] In an optional embodiment, one or more processors 602 are further configured to:

[0271] Obtain the first hold time corresponding to the first voltage offset;

[0272] Obtain the second hold time corresponding to the second voltage offset;

[0273] Based on the first hold time and the second hold time, the power-down time of the storage system 102 is obtained;

[0274] Adjust the hold time of at least one storage block by adjusting the power-down time.

[0275] In an optional embodiment, one or more processors 602 are further configured to:

[0276] The first hold time is determined based on the historical erase / write count of the first memory block and the first voltage offset.

[0277] The second hold time is determined based on the historical number of erase / write cycles and the second voltage offset.

[0278] In an optional embodiment, the storage system 102 includes a solid-state drive (SSD).

[0279] The following explanation uses the storage system provided in this application, implemented as a solid-state drive (SSD), as an example.

[0280] Figure 8 This is a schematic diagram of a computer system provided in an embodiment of this application. For example... Figure 8 As shown, the computer system includes a solid-state drive (SSD) and a host 108.

[0281] The solid-state drive (SSD) includes a storage device 104 and a storage controller 106. Illustratively, the storage controller 106 may be implemented as a System-on-Chip (SOC) chip within the SSD; or the storage controller 106 may be integrated onto the SOC chip within the SSD.

[0282] Memory device 104: This is the part of the SSD used for storing data, typically composed of flash memory (such as NAND flash memory). Memory device 104 is responsible for storing user data and system metadata.

[0283] The memory controller 106 is the core control unit in an SSD, responsible for managing data read / write operations, address mapping, error detection, and correction. The components of the memory controller 106 are as follows:

[0284] Buffer 701: Used for temporary data storage to improve data read and write speed. During write operations, user data is first written to buffer 701, and then gradually written to memory device 104. This reduces frequent access to memory device 104 and improves overall performance.

[0285] One or more processors 702: execute the core control logic of the SSD, such as the control method of the storage system in this application.

[0286] Read-Only Memory (ROM) 703: The ROM is used to store firmware and boot code, which runs when the SSD is powered on, initializes the memory controller 106 and starts the storage system 102.

[0287] Tightly Coupled Memory (TCM) 704: This is a high-speed memory used to store frequently accessed data and code. Tightly coupled memory can provide low-latency access, improving processor performance.

[0288] Hardware Accelerator 705: Used to accelerate specific operations, such as data encryption, decryption, and compression.

[0289] Error Correction Code (ECC) Engine 706: Used to detect and correct errors during data transmission. By adding redundant information to the original data, the ECC engine 706 uses this additional information at the receiving end to identify and correct potential errors, significantly improving data integrity and reliability.

[0290] Flash controller 707: Directly manages the operation of flash memory (such as NAND flash), including read / write operations, block management, wear leveling, and garbage collection. Flash controller 707 ensures efficient and reliable operation of the flash memory.

[0291] First interface 708: The first interface is used to connect the host 108 and the memory controller 106, ensuring that the host 108 can perform efficient data exchange with the SSD. For example... Figure 8 As shown, "lane0-lane4" between the first interface 708 and the host represents the physical connection channel between the memory controller 106 and the host.

[0292] Second interface 709: The second interface is used to connect the memory device 104 and the memory controller 106, enabling data transmission between the memory device 104 and the memory controller 106. For example... Figure 8 As shown, "Channel#0-Channel#N" between the second interface 709 and the memory device 104 represent independent data channels for data exchange between the memory controller 106 and the memory device 104.

[0293] In this application, the tightly coupled memory (TCM) 704 or the cache in the memory controller 106 Figure 8 The target code (not shown) runs in the memory device 104 and is used to implement the control method of the storage system provided in this application.

[0294] Next, the specific process of the control method for the storage system involved in this application will be described.

[0295] Figure 9 This is a flowchart illustrating a control method for a storage system according to an embodiment of this application. The storage system 102 provided in this application includes a memory device 104 and a memory controller 106. Optionally, the storage system 102 includes a solid-state drive (SSD). Optionally, the memory device 104 includes a three-level storage cell (TLC).

[0296] The control method for the aforementioned storage system is executed by the memory controller 106. This method includes steps 910 to 930.

[0297] Step 910: In response to power-on after a power outage in the storage system, obtain the first voltage offset group of the first storage block.

[0298] In some embodiments, a second voltage offset group of the first storage block is obtained before the storage system 102 loses power.

[0299] Optionally, the memory controller 106 includes a buffer 601, which is used to buffer the voltage offset group or voltage offset obtained in this embodiment.

[0300] Optionally, the second voltage offset group is an offset group obtained by the storage system 102 during operation for the first storage block to express the offset of multiple threshold voltage distributions in the first storage block. That is, multiple distinct voltages of multiple threshold voltage distributions in the first storage block are obtained. If there is a certain time interval between the current time and the time when the first storage block is programmed, the multiple distinct voltages obtained at the moment are offset relative to the multiple distinct voltages when the first storage block is programmed. The first voltage offset group is used to express this offset.

[0301] The first storage block is a storage block in the memory device 104 in which data has been written. In some embodiments, the first storage block is randomly determined from the storage blocks in the memory device 104 in which data has been written; or, the first storage block is a storage block in the memory device 104 that meets the first preset requirements.

[0302] In some embodiments, when the memory device 104 includes a plurality of memory blocks that meet a first preset requirement, a first memory block is randomly determined from the plurality of memory blocks that meet the first preset requirement; or, the first memory block that meets the first preset requirement is selected as the first memory block; or, the memory block with the shortest programming completion time is selected from the plurality of memory blocks that meet the first preset requirement as the first memory block; or, the memory block with the shortest retention time is selected from the plurality of memory blocks that meet the first preset requirement as the first memory block. The above methods for determining the first memory block are merely illustrative examples, and the embodiments of this application do not limit this approach.

[0303] The first preset requirements include: 1.1 The retention time of the first storage block is less than the first preset duration; 1.2 The programming temperature of the first storage block is within the preset temperature range; 1.3 The programming time of the first storage block reaches the second preset duration.

[0304] Indicatively, the first preset requirements include: ① Retention time less than 3 days; ② Programming temperature between [20, 60]℃, excluding high and low temperatures to prevent the influence of search valley caused by cross-temperature writes and reads; ③ Close time greater than 10 minutes.

[0305] During the operation of the storage system 102, in response to the failure of the first storage block to match the first preset requirement, a second storage block that meets the second preset requirement is determined; in response to the power-on of the storage system 102 after a power outage, a third voltage offset group of the second storage block is obtained, and the retention time corresponding to at least one storage block in the memory device 104 is adjusted based on the third voltage offset group and the fourth voltage offset group, wherein the fourth voltage offset group is the voltage offset group of the second storage block obtained before the power outage of the storage system 102.

[0306] The second preset requirement includes: 2.1 The retention time of the second storage block is less than the third preset duration, and the retention time of the second storage block is less than or equal to the retention time of other programmed storage blocks in the memory device; 2.2 The programming temperature of the second storage block is within a preset temperature range; 2.3 The duration for which the second storage block is programmed reaches the fourth preset duration.

[0307] Indicatively, the second preset requirements include: ① Retention time is less than 3 days, and the retention time is the shortest among all close blocks; ② Programming temperature is between [20, 60]℃; ③ Close time is greater than 10 minutes.

[0308] In response to the absence of a memory block in the memory device 104 that meets the second preset requirement, the first memory block is used as the memory block for adjusting the hold time. That is, when the first memory block fails to match the first preset requirement, the memory controller 106 searches for a second memory block according to the second preset requirement. If there is no second memory block in the memory device 104 that meets the second preset requirement, the first memory block is continued to be used as the memory block for adjusting the hold time, that is, the first voltage offset group of the first memory block is continued to be acquired.

[0309] In some embodiments, during the operation of the storage system 102, a second voltage offset group of the first storage block is periodically acquired; in response to a power failure of the storage system 102, the most recently acquired second voltage offset group is written to the memory device 104; in response to a power-on of the storage system 102, the second voltage offset group is read from the memory device 104.

[0310] Optionally, during the operation of the storage system 102, a read operation is performed on the first storage block using at least two candidate voltage offset groups to obtain the read results of at least two candidate voltage offset groups; based on the read results and at least two candidate voltage offset groups, a second voltage offset group is determined.

[0311] In some embodiments, a voltage valley is searched for in the first storage block to obtain a first voltage offset group.

[0312] In some embodiments, when the storage system 102 loses power, the storage block identifier of the first storage block, the second voltage offset group or the second voltage offset corresponding to the second voltage offset group, and the retention time of the first storage block are stored in the memory device 104.

[0313] After acquiring the second voltage offset group, a power failure event occurs in the storage system 102. The first voltage offset group is an offset group acquired for the first storage block to express the offset of multiple threshold voltage distributions in the first storage block when the storage system 102 is powered on again after a power failure. That is, there is at least a power failure time of the storage system 102 between acquiring the first voltage offset group and the second voltage offset group.

[0314] After the storage system 102 is powered on, a first voltage offset group corresponding to the first storage block is obtained. Optionally, the storage block corresponding to the second voltage offset group obtained when the storage system is powered off, i.e., the aforementioned first storage block, is first determined first, and then the second voltage offset group corresponding to the first storage block is obtained. In some embodiments, when storing the second voltage offset group, the storage block identifier of the storage block corresponding to the second voltage offset group is stored accordingly. The storage block identifier includes at least one of the following identifiers: storage block address, storage block number, etc.

[0315] In some embodiments, a first voltage offset group is acquired during a preset phase when the storage system 102 is powered on.

[0316] In some embodiments, the method for obtaining the first voltage offset group is the same as the method for obtaining the second voltage offset group described above, and will not be repeated here.

[0317] Taking a solid-state drive (SSD) as an example, in this embodiment of the application, the first voltage offset group is obtained during the SSD power-on initialization process.

[0318] In some embodiments, during the power-on initialization process of the storage system 102, the voltage valley of the first storage block is searched to obtain the first voltage offset group.

[0319] Step 920: Based on the first voltage offset group and the second voltage offset group, adjust the hold time corresponding to at least one memory block in the memory device.

[0320] In some embodiments, the power-down time of the storage system 102 is predicted based on a first voltage offset group and a second voltage offset group, and the power-down time is accumulated onto all valid storage blocks (valid blk) of the memory device 104, wherein a valid storage block refers to a storage block that has been written with data and has a corresponding retention time.

[0321] In summary, the control method for the storage system provided in this application obtains a first voltage offset group of the first storage block when the storage system experiences a power outage and subsequent power-on. It then predicts the power outage time of the storage system using the first voltage offset group and a second voltage offset group obtained before the power outage, and adds the power outage time to the storage block's hold time. This adjusts the hold time of the storage block, improving the accuracy of the record of the storage block's hold time. Consequently, it enhances the timeliness and accuracy of the storage system in implementing reliability measures for the storage block based on the hold time, thereby improving the operational stability of the storage system.

[0322] Figure 10 This is a flowchart illustrating a control method for a storage system according to an embodiment of this application. The storage system 102 provided in this application includes a memory device 104 and a memory controller 106. Optionally, the storage system 102 includes a solid-state drive (SSD). Optionally, the memory device 104 includes a three-level storage cell (TLC).

[0323] The control method for the aforementioned storage system is executed by the memory controller 106. This method includes steps 1010 to 1060.

[0324] Step 1010: Obtain the second voltage offset group of the first storage block.

[0325] Optionally, during the operation of the storage system 102, a second voltage offset group of the first storage block is periodically acquired and stored in a cache. In the event of a power failure in the storage system 102, the most recently acquired second voltage offset group is written into the memory device 104 for use after the storage system 102 is powered on again.

[0326] Optionally, the memory controller 106 includes a buffer 601, which is used to buffer the voltage offset group or voltage offset obtained in this embodiment.

[0327] Optionally, the second voltage offset group is an offset group obtained by the storage system 102 during operation for the first storage block to express the offset of multiple threshold voltage distributions in the first storage block. That is, it obtains the distinguishing voltages of multiple threshold voltage distributions in the first storage block. The distinguishing voltages are offset relative to the distinguishing voltages after the first storage block is programmed. The second voltage offset group is used to express this offset.

[0328] Step 1020: In response to power-on after a power outage in the storage system, obtain the first voltage offset group of the first storage block.

[0329] After acquiring the second voltage offset group, a power failure event occurs in the storage system 102. The first voltage offset group is an offset group acquired for the first storage block to express the offset of multiple threshold voltage distributions in the first storage block when the storage system 102 is powered on again after a power failure. That is, there is at least a power failure time of the storage system 102 between acquiring the first voltage offset group and the second voltage offset group.

[0330] Step 1030: Obtain the second holding time corresponding to the second voltage offset group.

[0331] In some embodiments, step 1030 may be performed before step 1020, when the storage system is powered off, to obtain the second hold time corresponding to the second voltage offset group and store the second hold time in the memory device 104; or step 1030 may also be performed after the storage system is powered on, such as after step 1020, after obtaining the first voltage offset group, to determine the second hold time corresponding to the second voltage offset group.

[0332] Optionally, a second voltage offset corresponding to the first programming state is obtained from the second voltage offset group, and a second holding time corresponding to the second voltage offset is obtained.

[0333] In some embodiments, the second retention time is determined based on the historical number of erase / write operations of the first memory block and the second voltage offset.

[0334] Step 1040: Obtain the first holding time corresponding to the first voltage offset group.

[0335] Optionally, the first voltage offset corresponding to the first programming state is obtained from the first voltage offset group, and the first holding time corresponding to the first voltage offset is obtained.

[0336] In some embodiments, the first retention time is determined based on the historical number of erase / write operations of the first memory block and the first voltage offset.

[0337] Step 1050: Based on the first hold time and the second hold time, obtain the power-down time of the storage system.

[0338] In some embodiments, when determining the first holding time based on the first voltage offset, the first holding time is calculated using a pre-set fitting formula and the first voltage offset.

[0339] Optionally, since data retention capability is related to the number of flash memory erase / write cycles, generally, the more erase / write cycles, the worse the data retention capability and the shorter the data retention period. Therefore, a first retention time is determined based on the historical erase / write cycles of the first memory block and a first voltage offset; and a second retention time is determined based on the historical erase / write cycles and a second voltage offset.

[0340] The illustrative fitting formula between voltage offset and holding time is shown below:

[0341] (1) PE 0-1K: y=a1x 2 -b1x+c1;

[0342] (2) PE 1-3K: y=a2x 2 -b2x+c2;

[0343] (3) PE 3-7K: y=a3x 2 -b3x+c3;

[0344] (4) PE≥7K: y=a4x 2 -b4x+c4.

[0345] Among them, a1, b1, c1, a2, b2, c2, a3, b3, c3, a4, b4, and c4 are pre-set known parameters, and the four fitting formulas are different.

[0346] Among them, PE 0-1K refers to the number of historical erase / write cycles in the range of 0 to 1000, taking 0 and excluding 1000; PE 1-3K refers to the number of historical erase / write cycles in the range of 1000 to 3000, taking 1000 and excluding 3000; PE 3-7K refers to the number of historical erase / write cycles in the range of 3000 to 7000, taking 3000 and excluding 7000; PE≥7K refers to the number of historical erase / write cycles in the range of 7000 or greater.

[0347] In some embodiments, the historical erase / write counts of the first memory block are stored in a designated storage location corresponding to the first memory block. The historical erase / write counts of the first memory block are obtained from the designated storage location corresponding to the first memory block, and the first hold time corresponding to the first voltage offset of the first memory block is calculated based on the historical erase / write counts and the corresponding fitting formula.

[0348] It is worth noting that the historical erase / write count ranges corresponding to the above-described fitting formulas are merely illustrative examples. Other granularities can be used to divide the historical erase / write count ranges corresponding to the fitting formulas, such as 0-1K, 1-2K, 2-3K, and so on. This application does not limit the method of dividing the historical erase / write count ranges. Furthermore, the formula form of the above-described fitting formulas is merely illustrative. The above-described fitting formulas can also be implemented as third-order formulas, square root formulas, or other arbitrary forms. This application does not limit the formula form of the fitting formulas.

[0349] Based on the historical write / erase count of the first memory block, the corresponding fitting formula is used for calculation. For example, if the historical write / erase count of the first memory block is 3200, then formula (3) is used to calculate the retention time corresponding to the first voltage offset and the second voltage offset. Here, x corresponds to the voltage offset, and y is the calculated retention time. Substituting the first voltage offset as the value of x into formula (3) yields the first retention time rttTime1, and substituting the second voltage offset as the value of x into formula (3) yields the second retention time rttTime2. The power-off time tPowerOff = rttTime1 - rttTime2 is then calculated.

[0350] Step 1060: Adjust the retention time of at least one storage block according to the power-down time.

[0351] In summary, the control method for the storage system provided in this application obtains a first voltage offset group of the first storage block when the storage system experiences a power outage and subsequent power-on. It then predicts the power outage time of the storage system using the first voltage offset group and a second voltage offset group obtained before the power outage, and adds the power outage time to the storage block's hold time. This adjusts the hold time of the storage block, improving the accuracy of the record of the storage block's hold time. Consequently, it enhances the timeliness and accuracy of the storage system in implementing reliability measures for the storage block based on the hold time, thereby improving the operational stability of the storage system.

[0352] This application provides an electronic device, which includes a storage system 102 as described in any of the above embodiments, and a host 108 coupled to the storage system 102. The electronic device may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality device, augmented reality device, etc.

[0353] This application provides a computer-readable storage medium storing at least one computer program. This computer program is loaded and executed by a processor to implement the control method of the storage system described in any of the above embodiments. Optionally, the computer-readable storage medium is a non-transitory-readable storage medium. Illustratively, at least one computer program is stored in the memory device 104 of a solid-state drive (SSD), runs in the TCM (Tightly Coupled Memory) of the SSD's memory controller 106 or in the cache of the memory controller 106, and is executed by the processor of the SSD's memory controller 106 to implement the control method of the storage system described in any of the above embodiments.

[0354] This application provides a computer program stored in a computer-readable storage medium. A processor reads the computer program from the computer-readable storage medium, causing the processor to load and execute it to implement the control method of the storage system provided in the above-described method embodiments.

[0355] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "at least one" means one or more, and the term "multiple" means two or more, unless otherwise expressly defined.

[0356] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0357] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A storage system, characterized in that, The storage system includes: A memory device, comprising multiple memory blocks; and The memory controller is configured as follows: In response to power-on after a power outage in the storage system, the first voltage offset group of the first storage block is acquired; and Based on the first voltage offset group and the second voltage offset group, the retention time corresponding to at least one memory block in the memory device is adjusted, wherein the second voltage offset group is the voltage offset group of the first memory block obtained before the power failure of the memory system.

2. The storage system according to claim 1, characterized in that, The first storage block meets the first preset requirements; The first preset requirement includes: The retention time of the first storage block is less than the first preset duration; The programmed temperature is within the preset temperature range; The programming time of the first storage block reaches the second preset time.

3. The storage system according to claim 2, characterized in that, The memory controller is further configured to: In response to the failure of the first storage block to match the first preset requirement, a second storage block that meets the second preset requirement is determined; In response to power-on after a power outage of the storage system, the third voltage offset group of the second storage block is obtained; as well as The retention time corresponding to at least one memory block in the memory device is adjusted based on the third voltage offset group and the fourth voltage offset group, wherein the fourth voltage offset group is the voltage offset group of the second memory block obtained before the power failure of the memory system.

4. The storage system according to claim 3, characterized in that, The second preset requirement includes: The retention time of the second storage block is less than the third preset duration, and the retention time of the second storage block is less than or equal to the retention time of other programmed storage blocks in the memory device; The programmed temperature is within the preset temperature range; The second storage block is programmed for a period of time equal to the fourth preset duration.

5. The storage system according to claim 3, characterized in that, The memory controller is further configured to: In response to the absence of a memory block that meets the second preset requirement in the memory device, the first memory block is used as the memory block for adjusting the retention time.

6. The storage system according to any one of claims 1 to 5, characterized in that, The memory controller is further configured to: During the operation of the storage system, the second voltage offset group of the first storage block is periodically acquired; In response to a power failure of the storage system, the most recently acquired second voltage offset group is written to the memory device; as well as In response to power-on after a power outage of the storage system, the second voltage offset group is read from the memory device.

7. The storage system according to any one of claims 1 to 5, characterized in that, The memory controller is further configured to: During the operation of the storage system, a read operation is performed on the first storage block using at least two candidate voltage offset groups to obtain the read results of at least two candidate voltage offset groups; Based on the reading results and the at least two candidate voltage offset groups, the second voltage offset group is determined.

8. The storage system according to any one of claims 1 to 5, characterized in that, The memory controller is further configured to: Obtain the first voltage offset corresponding to the first programming state from the first voltage offset group; and, Obtain the second voltage offset corresponding to the first programming state from the second voltage offset group.

9. The storage system according to claim 8, characterized in that, The memory controller is further configured to: Obtain the first hold time corresponding to the first voltage offset; Obtain the second hold time corresponding to the second voltage offset; The power-down time of the storage system is obtained based on the first hold time and the second hold time; The retention time corresponding to each of the at least one storage block is adjusted by the power-down time.

10. The storage system according to claim 9, characterized in that, The memory controller is further configured to: The first retention time is determined based on the historical erase / write count of the first memory block and the first voltage offset. The second hold time is determined based on the historical number of erase / write operations and the second voltage offset.

11. The storage system according to any one of claims 1 to 5, characterized in that, The storage system includes solid-state drives (SSDs).

12. A memory controller, characterized in that, The memory controller includes: The buffer is configured to buffer voltage offsets or groups of voltage offsets; The one or more processors are configured to: In response to power-on after a power outage in the storage system, the first voltage offset group of the first storage block is acquired; and The retention time of at least one memory block in the memory device is adjusted based on the first voltage offset group and the second voltage offset group, wherein the second voltage offset group is the voltage offset group of the first memory block obtained before the power failure of the memory system.

13. An electronic device, characterized in that, The electronic device includes: The storage system as described in any one of claims 1 to 11, and A host coupled to the storage system.

14. A control method for a storage system, characterized in that, The method includes: In response to power-on after a power outage of the storage system, the first voltage offset group of the first storage block is obtained; Based on the first voltage offset group and the second voltage offset group, the retention time corresponding to at least one memory block in the memory device is adjusted, wherein the second voltage offset group is the voltage offset group of the first memory block obtained before the power failure of the memory system.

15. The method according to claim 14, characterized in that, The first storage block meets the first preset requirements; The first preset requirement includes: The retention time of the first storage block is less than the first preset duration; The programmed temperature is within the preset temperature range; The programming time of the first storage block reaches the second preset time.

16. The method according to claim 15, characterized in that, The method further includes: In response to the failure of the first storage block to match the first preset requirement, a second storage block that meets the second preset requirement is determined; In response to power-on after a power outage of the storage system, the third voltage offset group of the second storage block is obtained; The retention time corresponding to at least one memory block in the memory device is adjusted based on the third voltage offset group and the fourth voltage offset group, wherein the fourth voltage offset group is the voltage offset group of the second memory block obtained before the power failure of the memory system.

17. The method according to claim 16, characterized in that, The second preset requirement includes: The retention time of the second storage block is less than the third preset duration, and the retention time of the second storage block is less than or equal to the retention time of other programmed storage blocks in the memory device; The programmed temperature is within the preset temperature range; The second storage block is programmed for a period of time equal to the fourth preset duration.

18. The method according to claim 16, characterized in that, The method further includes: In response to the absence of a memory block that meets the second preset requirement in the memory device, the first memory block is used as the memory block for adjusting the retention time.

19. The method according to any one of claims 14 to 18, characterized in that, The method further includes: During the operation of the storage system, the second voltage offset group of the first storage block is periodically acquired; In response to a power failure in the storage system, the most recently acquired second voltage offset set is written to the memory device; and In response to power-on after a power outage of the storage system, the second voltage offset group is read from the memory device.

20. The method according to any one of claims 14 to 18, characterized in that, The method further includes: During the operation of the storage system, a read operation is performed on the first storage block using at least two candidate voltage offset groups to obtain the read results of at least two candidate voltage offset groups; Based on the reading results and the at least two candidate voltage offset groups, the second voltage offset group is determined.

21. The method according to any one of claims 14 to 18, characterized in that, The method further includes: Obtain the first voltage offset corresponding to the first programming state from the first voltage offset group; and, Obtain the second voltage offset corresponding to the first programming state from the second voltage offset group.

22. The method according to claim 21, characterized in that, The adjustment of the hold time corresponding to at least one memory block based on the first voltage offset and the second voltage offset includes: Obtain the first hold time corresponding to the first voltage offset; Obtain the second hold time corresponding to the second voltage offset; The power-down time of the storage system is obtained based on the first hold time and the second hold time; The retention time corresponding to each of the at least one storage block is adjusted by the power-down time.

23. The method according to claim 22, characterized in that, The step of obtaining the first hold time corresponding to the first voltage offset includes: The first retention time is determined based on the historical erase / write count of the first memory block and the first voltage offset. The step of obtaining the second hold time corresponding to the second voltage offset includes: The second hold time is determined based on the historical number of erase / write operations and the second voltage offset.

24. The method according to any one of claims 14 to 18, characterized in that, The storage system includes solid-state drives (SSDs).

25. A non-volatile readable storage medium, characterized in that, The storage medium stores at least one computer program, which is loaded and executed by a processor to implement the control method of the storage system as described in any one of claims 14 to 24.

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