Correction method, correction device, in-memory computing device, and electronic device

Abstract

The application provides a correction method, a correction device, a storage-computation device and electronic equipment, and relates to the technical field of semiconductors. The correction method is used for correction of a storage circuit, the storage circuit comprises a plurality of correction units, one correction unit comprises one or more storage cell groups, and the correction method comprises the following steps: obtaining a first correction unit; determining first correction data based on a first mapping relationship and the first correction unit, wherein the first mapping relationship is used for indicating correction data corresponding to a plurality of correction units, the plurality of correction units comprise the first correction unit, and the first correction data is correction data corresponding to the first correction unit in the first mapping relationship; and correcting a first storage cell group based on the first correction data, wherein the first correction unit comprises the first storage cell group. This scheme can improve the reliability of the storage-computation integrated architecture.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a calibration method, calibration apparatus, memory computing device, and electronic device. Background Technology

[0002] In traditional computing paradigms, such as the von Neumann architecture, storage and computation are physically separated. When processing data using this paradigm, data is frequently transferred between storage devices and computing devices, resulting in data transmission latency and energy consumption. With the development of technologies such as big data and artificial intelligence, the volume of data processing is growing rapidly, and the demand for data transmission is also increasing rapidly. The resulting transmission latency and energy consumption are becoming increasingly prominent, restricting the development of data processing capabilities and making traditional computing paradigms unable to meet the demands of processing power.

[0003] In-memory computing (IMC) architecture physically merges storage and computation. This physical fusion includes, for example, integrating storage and computation components close together through packaging processes; integrating processing circuitry within memory to achieve in-memory processing integration; or implementing computation through storage devices or storing data in computing devices to achieve tight integration of storage and computation. IMC architecture can reduce data transfer requirements, lower transmission latency and energy consumption, and greatly improve data processing efficiency. However, IMC architecture still faces challenges; for example, its reliability still needs improvement. Summary of the Invention

[0004] This application provides a calibration method, calibration device, in-memory computing device, and electronic device that can improve the reliability of in-memory computing architecture.

[0005] In a first aspect, a calibration method is provided for calibrating a storage circuit, the storage circuit including multiple calibration units, each calibration unit including one or more storage cell groups, the calibration method including: obtaining a first calibration unit; determining first calibration data based on a first mapping relationship and the first calibration unit, wherein the first mapping relationship is used to indicate calibration data corresponding to the multiple calibration units, the multiple calibration units including the first calibration unit, and the first calibration data being the calibration data corresponding to the first calibration unit in the first mapping relationship; and calibrating a first storage cell group based on the first calibration data, wherein the first calibration unit includes the first storage cell group.

[0006] The technical solution of this application embodiment corrects the storage unit group by correcting the correction data corresponding to the correction unit in the mapping relationship, thereby reducing the difference in calculation results between different storage unit groups caused by the different voltage drops due to the difference in distance between different storage unit groups and the output circuit, correcting the data in different storage unit groups, and improving the computing performance of the in-memory computing architecture.

[0007] In some implementations of the first aspect, the correction data includes a set of output ranges or output sets, where one output range in the output range set corresponds to one correction result.

[0008] In some implementations of the first aspect, the first correction data includes a first output range set or a first output set, and the first storage cell group is corrected based on the first correction data, including: obtaining the first output of the first storage cell group; determining the target output range to which the first output belongs in the first output range set or the target output with the smallest absolute value of the difference between the first output and the first output in the first output set; and determining the first correction result corresponding to the target output range or the target output as the calculation result of the first storage cell group.

[0009] In some implementations of the first aspect, the correction data includes a result correction value, and the first correction data includes a first result correction value; based on the first correction data, the first storage cell group is corrected, including: based on the first result correction value, the output of the first storage cell group is corrected to obtain the calculation result of the first storage cell group.

[0010] In some implementations of the first aspect, the correction data includes a programmed correction value, and the first correction data includes a first programmed correction value; based on the first correction data, the first storage cell group is corrected, including: based on the first programmed correction value, the programming of the weight data stored in the first storage cell group is corrected, wherein the corrected weight data is used for calculation of the first storage cell group.

[0011] In some implementations of the first aspect, a correction unit includes a group of storage cells; in the first mapping, the correction unit is identified by an identifier index of its group of storage cells or by an identifier index of its corresponding output line.

[0012] In some implementations of the first aspect, the storage circuit includes multiple sets of storage cells, each set of storage cells includes multiple groups of storage cells, and outputs signals through a set of output lines; a correction unit includes a set of storage cells, and in the first mapping relationship, the correction unit is identified by the identifier index of its included set of storage cells or by the identifier index of its corresponding set of output lines.

[0013] In some implementations of the first aspect, the storage circuit includes multiple storage units, wherein a set of storage units is a storage unit, or a storage unit includes multiple sets of storage units.

[0014] In some implementations of the first aspect, the correction method further includes: acquiring first environmental information, the first environmental information being used to indicate a first environmental parameter of the storage circuit or the first correction unit; determining a first mapping relationship based on the first environmental information and a second mapping relationship, wherein the second mapping relationship is used to indicate multiple mapping relationships corresponding to multiple environmental parameter ranges, the multiple environmental parameter ranges including the first environmental parameter range, the first environmental parameter belonging to the first environmental parameter range, and the first mapping relationship being the mapping relationship corresponding to the first environmental parameter range in the second mapping relationship.

[0015] Through the technical solution of this application embodiment, the external environmental factors of the storage circuit will also affect the calculation results. By correcting the storage unit group through the mapping relationship corresponding to the environmental parameter range, the influence of environmental factors on the calculation results of different storage unit groups is corrected, thereby improving the calculation performance.

[0016] In a second aspect, a correction apparatus is provided, comprising: a memory for storing a first mapping relationship, and a processor for executing any of the correction methods of the first aspect.

[0017] For a description of the beneficial effects of the second aspect, please refer to the description of the beneficial effects of the first aspect, which will not be repeated here.

[0018] Thirdly, a storage device is provided, including: a storage circuit, and a correction device as described in the second aspect.

[0019] For a description of the third aspect, please refer to the description of the first aspect; it will not be repeated here.

[0020] Fourthly, an electronic device is provided, comprising: the storage and computing device of the third aspect.

[0021] Fifthly, a computer program product is provided, the computer program product including instructions that, when executed by a processor, cause any of the correction methods of the first aspect above to be executed.

[0022] In a sixth aspect, a computer-readable medium is provided that stores instructions which, when executed by a processor, cause any of the correction methods of the first aspect above to be performed. Attached Figure Description

[0023] Figure 1 A schematic diagram of a memory computing device according to an exemplary embodiment of this application is shown.

[0024] Figure 2 A schematic diagram of a memory computing device according to an exemplary embodiment of this application is shown.

[0025] Figure 3A flowchart illustrating a correction method according to an exemplary embodiment of this application is shown.

[0026] Figure 4 An example diagram of a mapping relationship provided by an embodiment of this application is shown.

[0027] Figure 5 A schematic diagram of another correction method according to an exemplary embodiment of this application is shown.

[0028] Figure 6 An example diagram illustrating another mapping relationship provided by an embodiment of this application is shown.

[0029] Figure 7 An example diagram of another mapping relationship provided by an embodiment of this application is shown.

[0030] Figure 8 A schematic diagram of a storage circuit according to an exemplary embodiment of this application is shown.

[0031] Figure 9 A schematic diagram of another storage circuit according to an exemplary embodiment of this application is shown.

[0032] Figure 10 A schematic diagram of another storage circuit according to an exemplary embodiment of this application is shown.

[0033] Figure 11 A schematic diagram of another correction method according to an exemplary embodiment of this application is shown.

[0034] Figure 12 An example diagram of another mapping relationship provided by an embodiment of this application is shown.

[0035] Figure 13 A schematic diagram of a correction device according to an exemplary embodiment of this application is shown.

[0036] Figure 14 A schematic diagram of an electronic device according to an exemplary embodiment of this application is shown. Detailed Implementation

[0037] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0038] To keep the drawings concise, the figures in this application only schematically show the parts related to the corresponding embodiments, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, some figures only schematically show some structures or components, and there may actually be more or fewer identical or similar structures or components.

[0039] The business scenarios described in the embodiments of this application are for illustrative purposes only and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0040] In this application, unless otherwise expressly specified and limited, "connection" includes direct or indirect connection between objects: connected objects may be directly connected through a medium (e.g., wires, traces, etc.), or indirectly connected through other components, or may be an internal connection. "Coupling" includes signal connection between objects, which may be achieved directly through a medium (e.g., wires, traces, etc.), or through other components. "Grounding" includes direct grounding or indirect grounding, with indirect grounding including, for example, grounding through other components.

[0041] In this application, unless otherwise expressly specified and limited, ordinal numbers, such as "first," "second," etc., are used only to distinguish the objects being described and should not be construed as indicating or implying the relative importance or order between the objects being described. Furthermore, ordinal numbers do not represent the quantity of the objects being described. "Multiple" includes two or more, and other quantifiers are similar. "Or," "and / or," etc., are used to describe the relationship between objects, indicating a non-exclusive inclusion. For example, "A and / or B," "A or B" can include: "A alone," "B alone," or "A and B." Similarly, "A, B, and / or C," "A, B, or C" can include: "A alone," "B alone," "C alone," "A and B," "A and C," "B and C," or "A, B, and C." Additionally, the " / " in this application is used to indicate an "or" relationship between preceding and following objects. The meaning of "one or more of A and B" or "at least one of A and B" in this application is the same as the meaning of "A and / or B" or "A or B" above. "One or more of A, B and C" or "at least one of A, B and C" has the same meaning as "A, B and / or C" or "A, B or C" above.

[0042] In in-memory computing technology, storage and computation (or arithmetic) are physically integrated. This physical integration includes, for example, integrating storage and computation components close together through processes such as packaging; integrating processing circuits with processing capabilities within the memory to achieve integrated processing functions within the memory; or implementing computation through storage devices or storing data in computing devices to achieve tight integration of storage and computation. According to some embodiments, an in-memory computing device may include a storage circuit and a processing circuit (or control circuit); the storage circuit is used to store data; the processing circuit (or control circuit) is used to control the operation of the storage circuit, such as controlling the writing, reading, computation, or sensing of computation results. For example, the processing circuit can call up data stored in the storage circuit and perform computation based on the called data; or the processing circuit can control the computation of the storage circuit; or the processing circuit can be used to read or sense the computation results of the storage circuit and process the computation results. This application does not limit the type of memory, which may include, but is not limited to, non-volatile memory (NVM) or volatile memory (VM). Volatile memory may include, but is not limited to, static random access memory (SRAM) or dynamic random access memory (DRAM); non-volatile memory may include, but is not limited to, flash memory, resistive random access memory (RRAM), magnetic random access memory (MRAM), ferroelectric memory (FeRAM), or phase change memory (PCM).

[0043] For ease of understanding, Figure 1 A schematic diagram of an in-memory computing device according to an exemplary embodiment of this application is shown. This in-memory computing device is described as an example of implementing in-memory computing using memory as a carrier.

[0044] like Figure 1As shown, the in-memory computing device 100 may include a storage circuit (or in-memory computing circuit) 110 and a control circuit 120. The storage circuit 110 can be used to store weight data (also referred to as weights); the control circuit 120 can be used to control the operating state of the storage circuit 110. The operating states of the storage circuit 110 include, for example, a programming state and a calculation state. In the programming state, weight data is written into the storage circuit 110. In the calculation state, the storage circuit 110 receives an input signal Sin and converts the input signal Sin into an output signal Sout based on the weight data. The storage circuit 110 can store multiple weight data, which can be equivalent to at least one vector (or matrix). The storage circuit 110 can store weight data in units of storage cells, which can also be called storage units or storage structures. For example, the storage circuit 110 includes a storage cell array, which includes multiple storage cells arranged in an array.

[0045] The storage unit may include a semiconductor device and utilize the conductivity of the semiconductor device, such as electrical conductance or transconductance, to store weight data. For example, the storage unit may include a resistive storage device or a transistor storage device. For example, weight data can be stored by controlling the conductivity of the resistive storage device, or by controlling the transconductance of the transistor storage device. Alternatively, the storage unit may utilize the energy stored in an energy storage element to store weight data, such as the charge stored in a capacitor; this energy storage element may be connected to the semiconductor device, and the stored energy may act on the semiconductor device, causing the semiconductor device to generate a corresponding conductivity.

[0046] The storage circuit 110 can perform calculations in groups. For example, a storage cell array includes at least one storage cell group, and each storage cell group includes multiple storage cells that can store multiple weight data. These multiple weight data can be equivalent to a first data vector (or a first data matrix). In programming mode, the weight data is written into the storage cells, which is equivalent to writing the first data vector (or the first data matrix) into the storage cell group in the storage cell array. In calculation mode, the storage circuit 110 receives an input signal, and the conduction capability of the storage cells can change the input signal to obtain an output signal. Accumulating the output signals in the storage cell group and outputting them can achieve an equivalent multiplication operation. The storage cell array can include a one-dimensional array, a two-dimensional array, or a three-dimensional array, etc., and the storage cell group includes multiple storage cells located in the same row or column of the storage cell array, or multiple storage cells located in multiple rows or columns, etc., and these multiple storage cells can be output collinearly.

[0047] In some possible embodiments, the in-memory computing device 100 may further include an input circuit 130 and an output circuit 140. The input circuit 130 can convert input data D1 into at least one input signal Sin and provide it to the storage circuit 110; the storage circuit 110 converts the received input signal Sin into an output signal Sout based on weight data; the output circuit 140 can convert the output signal Sout into output data D2 and output it. The at least one input signal can be equivalent to a second data vector (or a second data matrix), and the output data D2 can be equivalent to the product of a first data vector (or a first data matrix) and a second data vector (or a second data matrix).

[0048] As an example, Figure 2 A schematic diagram of yet another memory computing device according to an exemplary embodiment of this application is shown.

[0049] like Figure 2 As shown, the in-memory computing device 200 includes one or more memory cell arrays 210. The memory cell array 210 includes a plurality of memory cells S. ij Where i∈[1,m], j∈[1,n], m is the number of rows in the storage cell array, and n is the number of columns in the storage cell array. Storage cell S ij It can store weight data W ij When the memory cell array 210 is in the programming state, memory cell S ij The conduction capability can be controlled based on weight data to achieve a target state, thereby achieving the storage of weight data. When the storage cell array 210 is in the calculation state, it can be controlled through storage cell S. ij The input terminal IN is directed to the storage unit S ij Provide an input signal, such as an input voltage V i Storage unit S ij The output terminal OUT outputs its output signal, such as the output current. Multiple memory cells (e.g., S...) 1j -S mj The output terminals of the memory can be collinear. According to Kirchhoff's laws, the output signals of multiple memory cells are accumulated to obtain the output signal I. j Satisfy the following formula:

[0050]

[0051] In some possible embodiments, the input data includes digital input signals, such as the input signal V of the storage cell array 210. iThe input signal may include an analog signal. The input circuit 230 may include, for example, a digital-to-analog converter (DAC) to convert the digital signal into an analog signal and provide it to the memory cell array 210. In some possible embodiments, the input signal to the memory cell array 210 may include a digital signal, which is represented by the signal's waveform characteristics, such as pulse width, amplitude, or area. The input circuit 230 may adjust the waveform of the signal based on the input data to obtain the input signal, which is then provided to the memory cell array 210.

[0052] In some possible embodiments, the output circuit 240 may include at least one conversion circuit for converting the output signal of the memory cell array 210 and outputting it to a subsequent circuit. This conversion may include one or more signal type conversions, signal magnitude conversions, such as current-to-voltage conversion, analog-to-digital conversion, amplification, etc. For example, the output circuit 240 may include a first conversion circuit 241 for performing a first conversion on the output signal of the memory cell array 210. For instance, if the output signal of the memory cell array 210 includes a current signal, the first conversion circuit 241 can convert the current signal into a voltage signal. Alternatively, the output circuit 240 may include a second conversion circuit 242 for performing a second conversion on the output signal of the memory cell array 210. The second conversion may be implemented, for example, through a sampling circuit. Optionally, the signal converted by the first conversion circuit 241 may be further provided to the second conversion circuit 242 for a second conversion. For example, the first conversion circuit 241 may include a transimpedance amplifier (TIA) to convert a current signal into a voltage signal; the second conversion circuit 242 may include an analog-to-digital converter (ADC) to convert the analog signal into a digital signal for subsequent circuitry. Alternatively, the output circuit may include a sense amplifier (SA) that can sense, amplify, or process the signal obtained from the memory cell array 210 or the first conversion circuit 241. Furthermore, in Figure 2 In the example, the in-memory computing device 200 may further include a control circuit 220, which can be used to control the memory cells S in the memory cell array 210. ij The running state, such as the programming state and computation state mentioned above.

[0053] Figure 2 This is merely an example illustrating a connection method of storage cells in a storage cell array 210, except... Figure 2Besides the connection method shown, other connection methods can also be used. For example, the input terminals of the memory cells are connected in columns with collinearity, and the output terminals of the memory cells are connected in rows with collinearity. Furthermore, the input terminals of the memory cells may include the gate of a transistor memory device, or the input terminals of the memory cells may include the source or drain of a transistor memory device; this application does not limit the specific type of memory cell. This application also does not limit the type of memory cell; for example, the memory cell may include, but is not limited to, transistors, memristors, magnetic tunnel junctions (MTJs), or phase-change structures. This application also does not limit the type of transistor, including, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs), floating-gate transistors (FGTs), ferroelectric field-effect transistors (FeFETs), and thin-film transistors. A memory cell may include multiple transistors; for example, a memory cell may include a first transistor and a second transistor, wherein the gate of the first transistor (which may be referred to as a "read transistor" or "read tube") and the source or drain of the second transistor (which may be referred to as a "write transistor" or "write tube") are connected, and the charge stored at the gate of the first transistor can be used to characterize weight data. Optionally, the gate of the first transistor may also be connected to a capacitor to increase the stability and duration of the stored charge.

[0054] In in-memory computing systems, the demand for increased storage capacity and density is growing to accommodate larger-scale application scenarios. However, as the scale of storage circuits increases, the reliability of computational results in in-memory computing systems faces challenges. For example, during operation, storage circuits supply operating voltage to their storage cells. In large-scale storage circuits, the physical trace lengths of storage cells relative to this operating voltage supply vary, resulting in differences in the equivalent resistance of different storage cells from this supply. This equivalent resistance leads to voltage drops (e.g., IR drop), which in turn causes variations in the supply voltage of the storage cells. In large-scale storage circuits, the voltage drops in different computing regions can vary significantly, leading to substantial discrepancies in computational results across different regions and ultimately reducing the reliability of the in-memory computing system.

[0055] A memory computing region may include one or more memory cell groups, with the output terminals of the memory cells within each group connected to the same output line. When performing calculations using the memory cells of a memory cell group, the output current of the memory cells within the group converges on the output line and is output to the output circuit. For example, an operating voltage can be applied to the output terminals of the memory cells via the output line. The equivalent resistance of the output lines of different memory cell groups may differ, thus affecting the voltage drop across different memory cell groups and resulting in different operating conditions. This difference in operating conditions may cause significant deviations in calculation results between different memory computing regions, thereby affecting the reliability of the calculation results of the in-memory computing system.

[0056] In view of this, embodiments of this application provide a calibration method for calibrating a storage circuit. The storage circuit includes multiple calibration units, meaning it can be divided into multiple calibration units, and each calibration unit may include one or more groups of storage cells. This calibration method can be executed by a calibration device (e.g., the control circuit in the above embodiments). As an example, Figure 3 A flowchart illustrating a correction method according to an exemplary embodiment of this application is shown.

[0057] like Figure 3 As shown, the correction method 300 may include the following steps.

[0058] S310, obtain the first calibration unit.

[0059] S320, based on the first mapping relationship and the first correction unit, determine the first correction data, wherein the first mapping relationship is used to indicate the correction data corresponding to multiple correction units, the multiple correction units include the above-mentioned first correction units, and the first correction data is the correction data corresponding to the above-mentioned first correction units in the first mapping relationship.

[0060] S330, based on the first correction data, the first storage cell group is corrected, wherein the first correction unit includes the first storage cell group.

[0061] This application embodiment considers the impact of voltage drop on different computing regions of the storage circuit. It divides the storage circuit into multiple correction units and configures corresponding correction data for each unit. The correction data is used to correct the storage cell groups within each correction unit, thus correcting the differences in operating conditions between different correction units and reducing the impact of these differences on the calculation results of the storage circuit. Therefore, through the technical solution of this application embodiment, by using the correspondence between correction units and correction data in the mapping relationship and applying corresponding correction data to the storage cell groups, the impact of voltage drop can be specifically reduced within the storage circuit. This makes the degree of voltage drop impact on different computing regions of the storage circuit more consistent, improving the reliability of the in-memory computing architecture.

[0062] The mapping relationship can be obtained through simulation or experimentation of the storage circuit in the early stage, and stored in the control device so that the control device can make corrections based on the mapping relationship.

[0063] The above corrections can include pre-correction and post-correction. Pre-correction refers to reducing or offsetting the effect of voltage drop differences by adjusting the weight data before calculation; post-correction refers to reducing or offsetting the effect of voltage drop differences by adjusting the calculation results after calculation.

[0064] This application does not limit the content of the mapping relationship, as long as it enables correction at the correction unit level. For example, in one post-correction implementation, a set of output ranges corresponding to the correction unit can be set, and correction results corresponding to different output ranges within the set can be established. Thus, the correction result can be directly obtained based on the outputs of the correction unit and the memory cell group. As another example, in another post-correction implementation, a correction value corresponding to the correction unit can be set, and this correction value can be used to correct the outputs of the memory cell group.

[0065] The following description is in conjunction with the accompanying drawings.

[0066] Please refer to Figure 4 This is an example diagram of a mapping relationship provided in an embodiment of this application. For example... Figure 4 As shown, the correction data includes an output range set Sq, where an output range Aqr in the output range set Sq corresponds to a correction result r, where r∈[1,R], q∈[1,Q], R represents the number of correction results, Q represents the number of correction units, and R and Q are positive integers greater than 1. Thus, when the output of the storage unit group is obtained, the target output range in which the output lies can be determined, and the correction result corresponding to the target output range can be determined, thereby using the correction result as the calculation result of the storage unit group. For example, Figure 5 A schematic diagram of another correction method according to an exemplary embodiment of this application is shown. Figure 5 As shown, the correction method 500 may include the following steps:

[0067] S510: Obtain the first calibration unit.

[0068] S520: Determine the first correction data based on the first mapping relationship and the first correction unit.

[0069] S531: Obtain the first output of the first storage unit group.

[0070] S532: Determine the target output range to which the first output belongs within the first output range set.

[0071] S533: Determine the first correction result corresponding to the target output range as the calculation result of the first storage unit group.

[0072] The first correction unit can be any correction unit in the storage circuit, and the first storage cell group is any storage cell group within the first correction unit. Taking the current correction unit to be corrected as correction unit 1 as an example, other correction units are described similarly; the output of the storage cell group in correction unit 1 is read, assuming that the output of this storage cell group is within the output range A. 13 Then the output range A 13 For the target output range, the corresponding correction result 3 can be the calculation result of the storage cell group. By setting this mapping relationship, the calculation result of the storage cell group can be obtained directly, simplifying the correction logic of the calculation result and facilitating the rapid acquisition of the corrected calculation result.

[0073] Figure 4 The output range set shown can be replaced with the output set, the output range can be replaced with the output, and the first correction data can include the first output set. The above step S532 can be replaced with: determining the target output with the smallest absolute value of the difference between the first output and the first output in the first output set; S533 can be replaced with: determining the first correction result corresponding to the target output as the calculation result of the first storage unit group.

[0074] This application does not limit the form of the output of the storage cell group. The output of the storage cell group may include analog signals or digital signals. For example, the output of the storage cell group may include a current signal that has not been converted by the output circuit, or a voltage signal that has undergone a first conversion by the output circuit, or a digital signal that has undergone a first conversion and a second conversion by the output circuit, etc. Exemplarily, the output of the storage cell group may include a signal output by multiple storage cells in the storage cell group via collinear output lines at the output terminal. Or the output of the storage cell group may include a signal obtained after the signal has been converted (e.g., one or more of current-to-voltage conversion, analog-to-digital conversion, amplification, etc.). In some embodiments, the correction data includes a result correction value. The first correction data includes a first result correction value, and the above step S330 may include the following step: based on the first result correction value, correct the output of the first storage cell group to obtain the calculation result of the first storage cell group. In this way, the correspondence between the correction unit and the correction data in the mapping relationship is simple, which can simplify the data capacity of the mapping relationship and thus save the storage space of the mapping relationship.

[0075] For example, please refer to Figure 6 This illustrates an example diagram of another mapping relationship provided in an embodiment of this application. For example... Figure 6As shown, the correction data includes the result correction value. The correction unit q corresponds to the result correction value Vq. When the output of the storage unit group belonging to the correction unit q is read, the output is corrected based on the result correction value Vq to obtain the calculation result of the storage unit group. Wherein, q∈[1,Q], and Q represents the number of correction units.

[0076] This application does not restrict the sign of the correction value. For example, the resulting correction value Vq can include positive or negative values. A positive value represents adding the absolute value of the correction value to the output for correction. A negative value represents subtracting the absolute value of the correction value from the output for correction.

[0077] In some embodiments of this application, correction data is used for pre-correction. For example, the correction data includes a programmed correction value; the first correction data includes a first programmed correction value; step S330 above may include the following step: based on the first programmed correction value, correcting the programming of the weight data stored in the first memory cell group, wherein the corrected weight data is used for calculation of the first memory cell group. Thus, the influence of voltage drop on different computing regions in the memory circuit during calculation can be considered during the programming stage, and correction can be completed during the programming stage. This can save or reduce the time spent on correction during the calculation process, improving the computing speed or rate of the memory computing device or system.

[0078] For example, please refer to Figure 7 This illustrates an example diagram of yet another mapping relationship provided in the embodiments of this application. For example... Figure 7 As shown, the correction data includes programming correction values, with each correction unit q corresponding to a programming correction value Pq. When programming a group of storage cells belonging to that correction unit q, the programming of that group of storage cells is corrected based on the programming correction value Pq to adjust the programming result, i.e., the stored weight data. Here, q∈[1,Q], and Q represents the number of correction units.

[0079] According to some embodiments, programming correction may include correction of the programming voltage or programming current, or correction of the verification current, to adjust the weight data stored in the memory cells. This adjustment can be used to correct the impact of voltage drop during calculation on the calculation results. For example, in the first programming process of the first memory cell group, the programming voltage, programming current, or verification current of the memory cells in the first memory cell group can be corrected based on a first programming correction value. In this way, the weight data stored in the programmed first memory cell group can correct the impact of voltage drop on the calculation results during calculation.

[0080] In some embodiments, after the programming of the memory cell group of the memory circuit is corrected, the calculation result of the memory circuit can be obtained directly from the output circuit during the calculation process without further correction of the calculation result.

[0081] This application does not limit the sign of the correction value. For example, the programming correction value Pq can include positive or negative values. A positive value represents an increase in bias value based on the current weight data, or an increase in voltage or current value based on the programming voltage, programming current, or verification current corresponding to the current weight data. A negative value represents a decrease in bias value based on the current weight data, or a decrease in voltage or current value based on the programming voltage, programming current, or verification current corresponding to the current weight data.

[0082] According to some embodiments, programming corrections can be applied only to programming non-"0" data. The current contribution of "0" data in the calculation can be ignored, so programming corrections can be excluded from programming "0" data.

[0083] According to some embodiments, whether it is pre-calibration or post-calibration, the calibration objective may include correcting the effect of voltage drop. For example, the output change caused by voltage drop in the calibration unit is corrected so that the effect of voltage drop is reduced to a more uniform order of magnitude, and the effect of voltage drop differences between different calibration units is made more uniform.

[0084] According to some embodiments, whether pre-correction or post-correction, the correction target can include reducing the difference in the impact of voltage drop between different correction units. For example, any correction unit can be selected as the target correction unit. For instance, the correction unit least affected by voltage drop, the correction unit most affected by voltage drop, or the correction unit moderately affected by voltage drop can be selected as the target correction unit, such that the difference in the impact of voltage drop on other correction units after correction is similar to that of the target correction unit.

[0085] According to the solution provided in the embodiments of this application, the correction target of the mapping relationship can be flexibly set while reducing the difference in the impact of voltage drop.

[0086] This application does not restrict the form of the mapping relationship. The mapping relationship can be expressed in the form of tables, formulas, or linked data to represent the correspondence between elements.

[0087] In some embodiments, the correction unit may include a group of storage cells. In the first mapping relationship described above, the correction unit is identified by the identifier index of its included group of storage cells or by the identifier index of its corresponding output line. This allows for finer-grained correction and, through a mapping relationship with a larger amount of data, more accurate correction.

[0088] In some embodiments, a correction unit may include multiple memory cell groups. For example, a memory circuit may be divided into multiple memory cell sets, each containing multiple memory cell groups, and outputs a signal through an output line set; or, the output lines of the memory circuit may be divided into multiple output line sets, with one output line set corresponding to one memory cell set. The goal of this division is to group memory cell groups with similar voltage drops into one memory cell set, thereby reducing the amount of data in the first mapping relationship. For example, multiple memory cell groups that are physically close may be grouped into one memory cell set; or multiple output lines that are physically close may be grouped into one output line set. In this case, a correction unit includes one memory cell set, and in the first mapping relationship, the correction unit is identified by the identifier index of the memory cell set it includes or by the identifier index of its corresponding output line set. In this way, a relatively accurate correction target can be achieved with a relatively small amount of data in the first mapping relationship.

[0089] In some embodiments, the correction unit may include a memory unit, or a set of memory units, for example, a memory unit. A memory unit can serve as another memory unit of a memory circuit, which is the unit used for computation by the memory circuit, i.e., the memory space opened or introduced in a single computation. Thus, using memory units as the correction unit allows the memory unit group of memory units to share correction data, further reducing the amount of data in the first mapping relationship.

[0090] The following description is in conjunction with the accompanying drawings.

[0091] Figure 8 A schematic diagram of a storage circuit according to an exemplary embodiment of this application is shown.

[0092] like Figure 8 As shown, the storage circuit 800 may include multiple memory computing units, and each memory computing unit includes a group of memory cells. The physical trace lengths of the output lines of the memory cell groups within the memory computing units are relatively close. Using the memory computing unit as a correction unit can reduce the amount of data in the first mapping relationship and reduce the impact of voltage drop differences between different memory computing units. This better balances the reliability requirements of the memory computing device or system with the storage resources and correction computing power requirements brought about by the mapping relationship.

[0093] For example, the correction unit may include a storage unit. The first correction unit includes storage unit 1. The second correction unit includes storage unit 2. The third correction unit includes storage unit 3. The fourth correction unit includes storage unit 4. The fifth correction unit includes storage unit 5. The sixth correction unit includes storage unit 6.

[0094] In some embodiments, the in-memory computing units may be further divided into in-memory computing unit groups. For example, a correction unit may include an in-memory computing unit group, and an in-memory computing unit group may include multiple in-memory computing units. For instance, a first correction unit may include a first in-memory computing unit group, which includes in-memory computing units 1 and 2. A second correction unit may include a second in-memory computing unit group, which may include in-memory computing units 3 and 4. A third correction unit may include a third in-memory computing unit group, which may include in-memory computing units 5 and 6.

[0095] In this embodiment, the in-memory computing unit may include a storage unit within a storage circuit for performing computational functions. The in-memory computing unit can be used for in-memory computation and / or near-memory computation. For example, in in-memory computation, the in-memory computing unit can perform analog domain multiplication and accumulation calculations within the unit based on stored weight data and input data received by the in-memory computing unit. Alternatively, in near-memory computation, the weight data stored in the in-memory computing unit can be read out, and a processing circuit outside the storage circuit performs digital domain multiplication and accumulation calculations. The processing circuit can be packaged together with the storage circuit to implement near-memory computation. The processing circuit may include a control circuit, or can be integrated with the control circuit, for example, implemented as a system-on-chip (SOC). For example, the in-memory computing unit may include... Figure 2 Storage cell array 210.

[0096] In some embodiments, the storage circuitry may include a three-dimensional storage array, which may have greater storage density or storage capacity, enabling the in-memory computing system to support larger model deployments. As an example, Figure 9 A schematic diagram of another storage circuit according to an exemplary embodiment of this application is shown.

[0097] like Figure 9 As shown, the storage circuit 900 includes multiple storage units P1-P1 arranged along the X direction. x Where x is a positive integer greater than 1. A storage unit P u Includes multiple memory cell blocks B arranged along the Y direction u1 -B uy Where u∈[1,x], and y is a positive integer greater than 1. A storage unit block B uv Includes multiple memory cell arrays A arranged along the Z direction uv1 -A uvz Where v∈[1,y], and z is a positive integer greater than 1. Storage cell array A uvw The storage cell array A has a two-dimensional structure. uvwThis includes storage cells arranged along the X and Y directions, where w ∈ [1, z]. A storage cell array may include multiple subarrays of storage cells arranged along the Y direction (illustrated as E in the figure), and a subarray of storage cells may include multiple storage cells arranged along the X direction. For example, as shown... Figure 2 The storage cell array 210 shown may include one or more storage cell arrays, and when it includes multiple storage cell arrays, the multiple storage cell arrays may be located in the same storage unit P. u The multiple storage cell arrays are located in different storage cell blocks. In some embodiments, the multiple storage cell arrays may be located in the same storage unit P. u In the same layer along the Z direction, multiple memory cell arrays in that same layer can be referred to as a sub-memory cell (e.g., A shown in the figure). xw A sub-in-memory unit can include multiple groups of memory cells. A group of memory cells can include memory cells from multiple memory cell blocks arranged along the Y direction with the same X-coordinate position. The outputs of these memory cells are collinearly connected to the same output line and can be used to perform multiply-accumulate calculations. For example, memory cell block B... u1 -B uy The output terminals of storage cells with the same X coordinate located on the same layer in the Z direction can be connected to the same output line.

[0098] According to some embodiments, memory cell groups of different sub-in-memory units can share an output line. For example, memory cell groups of different sub-in-memory units within an in-memory unit that have the same X-coordinate position can share an output line. According to some embodiments, a correction unit may include an output line, or multiple memory cell groups of different sub-in-memory units sharing an output line.

[0099] For ease of distinction, in some embodiments of this application, the Y direction may be referred to as the first direction, the X direction as the second direction, and the Z direction as the third direction. The X, Y, and Z directions can be any three distinct directions in three-dimensional space. In some examples, any two of the X, Y, and Z directions are perpendicular to each other.

[0100] In some examples, the storage circuitry includes, but is not limited to, NAND flash memory; the storage unit is called, for example, a plane or a bank; the storage unit block is called, for example, a block; and the storage unit subarray is called, for example, a page. This application is not limited thereto, and storage circuitry with different three-dimensional structures may have different names.

[0101] In some embodiments of this application, Figure 9 A storage unit P is shown. u Multiple memory cell arrays located on the same layer in the Z direction can belong to the same sub-memory cell, for example, Figure 9In-memory computing unit P x Multiple memory cell arrays located in the w-th layer form array A. xw Array A xw They can belong to the same sub-memory unit. This array A xw The storage units in the memory can perform the same calculation, such as a multiply-accumulate calculation.

[0102] In some embodiments, the calibration unit may include a group of memory cells or an output line. For example, the calibration unit may include a group of memory cells, and the first calibration unit may include a first group of memory cells; or, the calibration unit may include an output line, and the first calibration unit may include a first output line, with the output terminals of the memory cells in the first group of memory cells connected to the first output line. Figure 10 A schematic diagram of another storage circuit according to an exemplary embodiment of this application is shown.

[0103] like Figure 10 As shown, the storage circuit 1000 may include one or more storage units 1010, each storage unit 1010 including a storage cell array, the storage cell array including multiple storage cells S ij Where i∈[1,m], j∈[1,n], m is the number of rows in the memory cell array, and n is the number of columns in the memory cell array. The memory cell array includes n memory cell groups and n output lines L1 to Ln. The output terminals of memory cells within a memory cell group can be connected to the same output line for collinear output. The memory cell groups or output lines within the memory computing unit 1010 may be affected differently by voltage drops. The correction unit may include memory cell groups or output lines, which can correct for differences in the effects of voltage drops on memory cell groups within the memory computing unit 1010. In this way, the reliability of the memory computing device or memory computing system can be improved with a smaller correction granularity.

[0104] In some embodiments, the memory cell group within the memory cell can be divided into multiple memory cell sets, or the output line can be divided into multiple output line groups. The correction unit can then include a memory cell set or an output line group. This allows memory cells within a memory cell set or corresponding output line group to share correction data. Compared to using a memory cell group or output line as the correction unit, this saves data overhead associated with mapping relationships. Furthermore, compared to using the memory cell as the correction unit, it allows for finer-grained correction of the impact of voltage drop differences on the calculation results within the memory cell group of the memory cell within the memory cell.

[0105] For example, the calibration unit may include the output line group of the memory unit 1010. The output lines L1 to Ln of the memory unit 1010 may be divided into multiple output line groups. The number of output lines included in different output line groups may be the same or different. The division method of the output line groups is similar to that described in the above embodiments. For example, the division may be based on the equivalent resistance of the output line, or the physical trace length or physical location of the output line, and output lines with similar equivalent resistance or physical trace length or physical location may be grouped together.

[0106] In some embodiments of this application, the calibration unit can also be calibrated based on environmental factors, thereby reducing the impact of environmental factors such as temperature on the reliability of the in-memory computing system.

[0107] For example, Figure 11 A schematic diagram of another correction method according to an exemplary embodiment of this application is shown. Figure 11 As shown, the correction method 1100 may include the following steps:

[0108] S1111, obtain the first calibration unit.

[0109] S1112, Obtain first environmental information, the first environmental information is used to indicate the first environmental parameter of the storage circuit or the first calibration unit.

[0110] S1113, Based on the first environmental information and the second mapping relationship, determine the first mapping relationship.

[0111] S1120, Based on the first mapping relationship and the first correction unit, determine the first correction data.

[0112] S1130, Based on the first correction data, the first storage cell group is corrected.

[0113] The second mapping relationship is used to indicate multiple mapping relationships corresponding to multiple environmental parameter ranges. The multiple environmental parameter ranges include the first environmental parameter range, the first environmental parameter belongs to the first environmental parameter range, and the first mapping relationship is the mapping relationship corresponding to the first environmental parameter range in the second mapping relationship.

[0114] This application's embodiments take into account the impact of environmental factors, such as temperature, on the calculation results. During correction, environmental factors are considered. By using environmental information to confirm the applicable mapping relationship under the current environmental conditions, and based on this applicable mapping relationship, the impact of voltage drop is reduced. Therefore, while correcting the impact of voltage drop on the calculation results, the impact of environmental factors on the calculation results can also be corrected, further improving the reliability of the in-memory computing architecture. For example, when the environmental factor is temperature, the impact of temperature on the calculation results can be corrected simultaneously with the impact of voltage drop.

[0115] For example, please refer to Figure 12 The diagram illustrates another example of a mapping relationship provided in the embodiments of this application. Figure 12 This illustrates the mapping relationship (or second mapping relationship) between environmental parameters and the mapping relationship. For example... Figure 12 As shown, the mapping relationships include mapping relationship 1 to mapping relationship G. Any mapping relationship from mapping relationship 1 to mapping relationship G can be used to indicate the correction data corresponding to multiple correction units, where G is a positive integer greater than 1, representing the number of mapping relationships. Environmental parameters include environmental parameter ranges H1 to H... G The environmental parameter range Hg corresponds to the mapping relationship g, where g∈[1,G]. Thus, upon obtaining the first environmental information, the target environmental parameter range of the indicated environmental parameter can be determined, and the mapping relationship (or first mapping relationship) corresponding to the target environmental parameter range can be determined. This mapping relationship can then be used as a mapping relationship to correct the influence of voltage drop. The description of the first mapping relationship can refer to the description of any of the above embodiments, which is equivalent to setting corresponding first mapping relationships for environmental parameters of different ranges.

[0116] According to some embodiments, the environmental information may include environmental information shared by the storage circuit. For example, a sensor may be set in a certain area of ​​the storage circuit, or multiple sensors may be set in different areas. The calibration unit may share the environmental information obtained by the sensor in that area, or it may share the average value of the environmental information obtained by multiple sensors. The first environmental information obtained in step S1112 can be used to indicate the environmental parameters of the storage circuit. Step S1112 may be executed before, after, or synchronously with step S1111.

[0117] According to some embodiments, the environmental information may include environmental information of different regions of the storage circuit. For example, different sensors may be set in different regions of the storage circuit to obtain environmental information of different regions. The first environmental information obtained in step S1112 includes the environmental information of the region where the first calibration unit is located. Thus, the first environmental information can be used to indicate the first environmental parameter of the first calibration unit.

[0118] In some embodiments, the in-memory computing device may include a temperature sensor. For example, the storage circuitry of the storage device may include a temperature sensor. As another example, a control device may include a temperature sensor. The in-memory computing device may include a temperature sensor shared by the storage circuitry, or the in-memory computing device may include multiple temperature sensors corresponding to multiple regions of the storage circuitry.

[0119] In some embodiments, the in-memory computing device may employ other methods to compensate for the effects of environmental factors (such as temperature). This eliminates the need to set different first mapping relationships for different environmental parameter ranges, simplifies the data capacity of the mapping relationships, saves storage space, and improves the correction rate or speed of the in-memory computing device or system.

[0120] This application embodiment also provides a calibration device, which may be located in or include the above-mentioned control circuit, and the calibration device may be located in Figure 1 or Figure 2 The control circuit 120 / 220 shown, or independent of the control circuit 120 / 220. The calibration device includes a memory and a processor; the memory stores the mapping relationship, and the processor can be used to execute any of the above calibration methods.

[0121] The calibration device may include a processor connected to a memory containing instructions. The processor calls the instructions stored in the memory to implement any of the control methods described above. The memory may be internal to the calibration device or external to the calibration device.

[0122] This application also provides a calibration device, which can be found in the embodiments of this application. Figure 13 . Figure 13 A schematic diagram of a correction device according to an exemplary embodiment of this application is shown. Figure 13 As shown, the correction device 1300 includes: a memory 1310, which can be used to store mapping relationships; and a processor (or processing circuit) 1320, which can be used to execute any of the correction methods provided in the above embodiments.

[0123] For example, in some embodiments, the processing circuit may include an application-specific integrated circuit (ASIC), which implements some or all of the functions of the correction device by designing the logical relationships between the devices within the circuit; as another example, in some embodiments, the processing circuit may be implemented by a programmable logic device (PLD) circuit, which may include a large number of logic devices, and the logical relationships between the logic devices are configured through a configuration file, thereby implementing some or all of the functions of the correction device.

[0124] Optionally, the correction device provided in this application embodiment can be implemented by a processor calling a program; or by a hardware circuit; or partially by a processor calling a program and partially by a hardware circuit.

[0125] In some possible embodiments, the processor or processing circuit is a circuit with signal processing capabilities. For example, the processor may be a circuit with instruction read and execute capabilities. In other possible embodiments, the processor can implement its functions through the logical relationships of hardware circuits, which are fixed or reconfigurable. For example, the processor may be a hardware circuit implemented as an ASIC or PLD, such as a field-programmable gate array (FPGA). In a reconfigurable hardware circuit, the process of the processor loading a configuration document and configuring the hardware circuit can be understood as the process of the processor loading instructions to implement the functions of some or all of the above units. This application does not limit the type of processor, such as a central processing unit (CPU), microcontroller unit (MCU), graphics processing unit (GPU), or digital signal processor. Alternatively, it may be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as a neural network processing unit (NPU), tensor processing unit (TPU), deep learning processing unit (DPU), etc.

[0126] This application also provides a memory computing device, which includes: a storage circuit including a plurality of storage cell groups; and a correction device for performing any of the correction methods proposed in this application to correct the calculation results of the storage circuit.

[0127] This application also provides a computer program product, which includes instructions that, when executed by a processor, cause any of the control methods described in the above embodiments to be executed.

[0128] This application also provides a computer-readable medium storing instructions that, when executed by a processor, cause any of the control methods described in the above embodiments to be executed.

[0129] In the above method embodiments, the order of the process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0130] This application also provides an electronic device, which can be found in [reference 1]. Figure 14 . Figure 14 A schematic diagram of an electronic device according to an exemplary embodiment of this application is shown. Figure 14 As shown, the electronic device 1400 may include any of the above-mentioned in-memory computing devices 1410 for processing data of the electronic device. The electronic device may also include an input / output device 1420 for receiving user input or outputting processing results. This application does not limit the input type and output type; for example, input may include voice input, text input, image input, or video input. Output may include text output, voice output, image output, or video output. The electronic device may also include a processor 1430, which can process data provided to the in-memory computing device 1410 or process the output data of the in-memory computing device 1410. The output of the input / output device 1420 may be based on the output of the processor 1430 or the output of the in-memory computing device 1410.

[0131] This application does not limit the type of electronic device. For example, according to some embodiments, the electronic device may include wearable devices. Wearable devices include, but are not limited to: head-mounted devices (e.g., helmets or hats), devices worn on the ears (e.g., headphones), devices worn on the wrist (e.g., watches), and devices worn on other parts of the body (e.g., electronic necklaces, medical monitoring devices, or glasses). According to some embodiments, the electronic device may include portable terminals. For example, the electronic device may include, but is not limited to, mobile phones, general-purpose computing devices (e.g., laptops or tablets), personal digital assistants, etc. According to some embodiments, the electronic device may include other types of edge devices, such as personal computers, in-vehicle computers or in-vehicle computing platforms, or smart home electronic products. According to some embodiments, the electronic device may also include devices such as servers.

[0132] In the above embodiments, the descriptions of different embodiments each have their own emphasis. Parts not described in detail or recorded in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the different embodiments described above can be freely combined as needed. Moreover, as technology evolves, the elements described in this application can be replaced by equivalent elements appearing after this application.

Claims

1. A calibration method, characterized in that, For calibration of a storage circuit, the storage circuit comprising multiple calibration units, each calibration unit comprising one or more groups of storage cells, the calibration method comprising: Obtain the first calibration unit; Based on the first mapping relationship and the first correction unit, first correction data is determined, wherein the first mapping relationship is used to indicate the correction data corresponding to the plurality of correction units, the plurality of correction units include the first correction unit, and the first correction data is the correction data corresponding to the first correction unit in the first mapping relationship; Based on the first correction data, the first storage cell group is corrected, wherein the first correction unit includes the first storage cell group.

2. The correction method according to claim 1, characterized in that, The correction data includes an output range set or an output set, where one output range in the output range set corresponds to one correction result.

3. The correction method according to claim 2, characterized in that, The first correction data includes a first output range set or a first output set, and the step of correcting the first memory cell group based on the first correction data includes: Obtain the first output of the first storage unit group; Determine the target output range to which the first output belongs within the first output range set, or the target output with the smallest absolute value of the difference between the first output and the first output in the first output set; The target output range or the first correction result corresponding to the target output is determined as the calculation result of the first storage unit group.

4. The correction method according to claim 1, characterized in that, The correction data includes result correction values, and the first correction data includes a first result correction value; the step of correcting the first storage unit group based on the first correction data includes: Based on the first result correction value, the output of the first storage cell group is corrected to obtain the calculation result of the first storage cell group.

5. The correction method according to claim 1 or 2, characterized in that, The correction data includes a programming correction value, and the first correction data includes a first programming correction value; the step of correcting the first memory cell group based on the first correction data includes: Based on the first programming correction value, the programming of the weight data stored in the first storage cell group is corrected, wherein the corrected weight data is used for calculation of the first storage cell group.

6. The correction method according to any one of claims 1 to 5, characterized in that, A calibration unit consists of a group of storage cells; In the first mapping relationship, the correction unit is identified by the identifier index of its included group of storage cells or by the identifier index of its corresponding output line.

7. The correction method according to any one of claims 1 to 5, characterized in that, The storage circuit includes multiple sets of storage cells, each set of storage cells includes multiple groups of storage cells, and outputs signals through a set of output lines. A correction unit includes a set of storage cells, and in the first mapping, the correction unit is identified by the identifier index of the set of storage cells it includes or by the identifier index of its corresponding set of output lines.

8. The correction method according to claim 7, characterized in that, The storage circuit includes multiple storage units, wherein a set of storage units constitutes a storage unit, or a storage unit includes multiple sets of storage units.

9. The correction method according to any one of claims 1-8, characterized in that, Also includes: Acquire first environmental information, which is used to indicate the first environmental parameter of the storage circuit or the first calibration unit; Based on the first environmental information and the second mapping relationship, the first mapping relationship is determined, wherein the second mapping relationship is used to indicate multiple mapping relationships corresponding to multiple environmental parameter ranges, the multiple environmental parameter ranges include a first environmental parameter range, the first environmental parameter belongs to the first environmental parameter range, and the first mapping relationship is the mapping relationship corresponding to the first environmental parameter range in the second mapping relationship.

10. A calibration device, characterized in that, include: A memory and a processor, the memory being used to store a first mapping relationship, and the processor being used to execute the correction method as described in any one of claims 1 to 9.

11. A storage computing device, characterized in that, include: The storage circuit, and the correction device as described in claim 10.

12. An electronic device, characterized in that, include: The storage device as described in claim 11.

Images