Total dose test and test method for flash memory

Abstract

The application relates to a total dose test and test method of a Flash memory, which comprises the following steps: parallel power-on of multiple pieces of Flash memories to be tested and simultaneous irradiation in the same radiation field; selection of an i-th channel of a tested device, enabling of a control line group of the channel, connection of a data end of the channel with a shared data bus, and inactivation of control line groups of other tested device channels and setting of the data ends of the other tested device channels to a high resistance state; preset test data is written into the memory; data of the Flash memory to be tested is read back; the steps are repeated until test of all channels under a current total dose node is completed; and test data is summarized to determine whether the Flash memories to be tested are failed. The application has the beneficial effect that the application effectively avoids chip selection conflict and multiple device simultaneous response problems caused by simple parallel connection of multiple pieces of Flash, and significantly reduces radiation source machine time consumption.

Description

Technical Field

[0001] This invention relates to the field of total dose effect testing technology for memory, and more specifically, to a total dose test and testing method for Flash memory. Background Technology

[0002] Flash memory boasts advantages such as high speed, large capacity, low power consumption, and high reliability, and has been gradually applied in satellite remote sensing, aerospace exploration, and other space applications with high reliability requirements. Since most Flash memory devices are commercial or near-commercial, their adaptability and degradation patterns in the radiation environment typically require total dose testing before being used in space.

[0003] The total dose effect is mainly manifested in the following ways: radiation generates electron-hole pairs in the oxide layer of floating-gate MOS devices, leading to oxide layer trap charges and interface state trap charges, causing threshold voltage drift, transconductance changes, and increased leakage current; radiation may also generate defects such as interstitial atoms and lattice vacancies in the semiconductor, creating bulk traps or recombination centers, reducing minority carrier lifetime, and decreasing carrier mobility and donor and acceptor compensation. The above degradation ultimately manifests as device electrical parameter drift, abnormal erase / write times, decreased read / write rates, and abnormal data retention or read / write functions.

[0004] Existing total dose testing methods for Flash memory typically employ single-chip testing or simple parallel testing of multiple chips. Single-chip testing requires a long irradiation machine, resulting in poor cross-sectional comparability between samples. While simple parallel testing of multiple chips allows simultaneous irradiation of samples from the same batch, directly connecting the chip select, read enable, write enable, reset, or data ports of multiple devices in parallel can easily lead to problems such as multiple devices simultaneously responding to control commands, multiple data outputs, simultaneously driving a shared bus, and mutual interference between data readbacks from different devices. This is especially true when the bidirectional data bus DQ[0:m] is simply connected in parallel, which can easily cause bus contention, distorted bit error statistics, and difficulties in failure location. Therefore, a total dose testing device and method are needed that can still achieve "independent chip selection, data isolation, sequential read / write, and branch monitoring" under the premise of "multiple chips being parallelly biased and simultaneously irradiated." Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a total dose test and testing method for Flash memory.

[0006] Firstly, a total dose test and testing method for Flash memory is provided, including:

[0007] S1. Power on multiple Flash memory chips under test in parallel and expose them to the same radiation field simultaneously.

[0008] S2. At the current preset total dose node, select the i-th device under test channel, enable the control line group of the channel, and connect its data terminal to the shared data bus. At the same time, disable the control line groups of other device under test channels and set their data terminals to high impedance.

[0009] S3. Send erase and write commands to the selected i-th Flash memory to write the preset test data into the memory.

[0010] S4. Read back the data of the Flash memory under test, compare the read-back data with the preset test data, count the number of error bits and record the electrical parameters;

[0011] S5. After completing the test of the i-th channel, switch to the next channel of the device under test and repeat steps S2 to S4 until all channels under the current total dose node are tested.

[0012] S6. Summarize the test data of each channel at the current total dose node, and compare it with the preset failure criteria to determine whether each Flash memory under test has failed.

[0013] Preferably, in S3, the preset test data is an alternating feature code, including 55H and AAH; in S4, the electrical parameters include read current, write current, erase time, write time, readback time, and read / write rate.

[0014] Preferably, in S4, the read / write error rate is calculated as follows: the readback data is compared bit by bit with the original write data, and the number of error bits is counted. The read / write error rate is calculated as: number of error bits / total number of test bits, where the total number of test bits is the number of test bits for the entire array or the number of test bits selected based on a preset address range.

[0015] Preferably, in S6, the preset failure criteria include one or more of the following: abnormal standby current, abnormal read / write current, excessive erase time, excessive write time, read / write rate below a threshold, read / write error rate above a threshold, or read / write function failure; when any device under test meets the failure criteria, its corresponding failure dose or failure time is recorded.

[0016] As a preferred embodiment, in S4, the readback and comparison process includes: reading back the storage array data in address order; comparing the readback data with the original written data bit by bit; calculating the number of error bits, read / write error rate, readback time, and read / write rate; and synchronously acquiring and recording the read / write current corresponding to the current channel of the device under test.

[0017] In a second aspect, a total dose testing and measurement apparatus for a Flash memory is provided, for performing any of the methods described in the first aspect, including:

[0018] An external safety testing room and a radiation testing room are connected to the radiation testing room via a first photoelectric converter, a radiation-resistant optical fiber, and a second photoelectric converter.

[0019] The external safety test room is equipped with a host computer, an FPGA test board, a DC regulated power supply, and a high-precision current / voltage meter.

[0020] The radiation test chamber is equipped with a lead protective enclosure and a test fixture plate, and the second photoelectric converter is disposed inside the lead protective enclosure;

[0021] The test fixture board includes a control decoding / timing module, an address buffer, a bidirectional tri-state data buffer / multiplexer, a parallel power supply network, a branch current detection / protection unit, and multiple detachable magnetic test sockets. Each of the detachable magnetic test sockets is used to install a Flash memory under test, forming a corresponding channel for the device under test.

[0022] The control decoding / timing module is used to output an independent and valid control line group to the currently selected channel of the device under test, while invalidating the control line groups of other channels; the address buffer is used to distribute the address signal to all channels; the bidirectional tri-state data buffer / multiplexer is used to connect the data terminal to the shared data bus only when the corresponding channel is selected, otherwise it is set to a high impedance state; the parallel power supply network is used to provide operating bias to all channels in parallel; the branch current detection / protection unit is used to collect the current signal of each channel and perform protection in case of overcurrent.

[0023] Preferably, the control line group includes a chip select control signal, and one or more of the following configured based on the interface type of the Flash memory under test: write enable control signal, output enable control signal, read enable control signal, reset control signal, command latch control signal, address latch control signal, or write protect control signal; at any test moment, the control decoding / timing module enables the control line group of only one channel of the device under test to be in an active state.

[0024] Preferably, the parallel power supply network provides VCC and VPP bias to each device under test channel in a star or equal impedance distribution manner.

[0025] Preferably, the test fixture plate also includes a power input terminal for connecting an external bias power supply; the detachable magnetic test base is positioned and fixed through positioning holes and magnetic fixing positions, and is provided with a flip-up test base cover for pressing the Flash memory under test.

[0026] The beneficial effects of this invention are:

[0027] 1. In this invention, all Flash memory chips under test are powered on in parallel and irradiated simultaneously during irradiation. The decoding / timing module outputs independent chip select and read / write control signals to each DUT, which effectively avoids chip select conflicts and simultaneous response problems caused by simple parallel connection of multiple Flash chips. It significantly reduces the time consumption of the radiation source and improves the horizontal comparability of samples in the same batch under the same radiation conditions.

[0028] 2. This invention isolates the data terminals of each DUT through a bidirectional tri-state data buffer / multiplexer, allowing only the selected DUT to access the shared data bus, thus avoiding data bus contention, readback data crosstalk, and bit error statistics distortion. At the same time, combined with the branch current detection / protection unit, it achieves in-situ current monitoring and abnormal branch protection while ensuring parallel bias, thereby improving the controllability, safety, and failure location capability of the total dose test process.

[0029] 3. This invention achieves long-distance isolated communication between the external safety test room and the radiation test room through a first photoelectric converter, a second photoelectric converter and radiation-resistant optical fiber, effectively reducing high-frequency signal attenuation and electromagnetic interference caused by long-distance cable transmission, and improving the stability and reliability of in-situ dynamic testing.

[0030] 4. By correlating and recording read / write error rate, current change, erase time, write time, readback time, and read / write rate with the total dose node, this invention can obtain the lateral dispersion and total dose degradation law of the same batch of samples, providing data basis for device screening, lifetime assessment, and space application adaptability evaluation. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the parallel connection structure of multiple Flash memory chips according to the present invention;

[0032] Figure 2 This is a schematic diagram of the sequential read / write control flow of the present invention;

[0033] Figure 3 This is a schematic diagram of the read / write error rate statistics process of the present invention;

[0034] Figure 4 This is a schematic diagram of the test fixture plate structure of the present invention;

[0035] Explanation of the attached diagram labels: 1 is the parallel power supply and signal distribution area, 2 is the power input terminal, 3 is the test socket mounting area, 4 is the detachable magnetic test socket, 5 is the positioning hole and magnetic fixing position, and 6 is the flip-up test socket cover. Detailed Implementation

[0036] The present invention will be further described below with reference to embodiments. The description of the embodiments below is only for the purpose of helping to understand the present invention. It should be noted that those skilled in the art can make several modifications to the present invention without departing from the principle of the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

[0037] Example 1:

[0038] To address the problems of existing technologies, Embodiment 1 of this application provides a total dose test and testing method for Flash memory. By improving the parallel connection structure of multiple Flash memories on the test fixture board, the problems of chip select conflict, data bus conflict and test data distortion caused by simple parallel connection of multiple Flash memories are solved. Under the condition that the same batch of samples are powered on in parallel and irradiated at the same time, the sequential erasure and write, sequential readback, independent bit error statistics and in-situ parameter monitoring of each tested Flash memory are realized.

[0039] Specifically, the method provided in this application includes:

[0040] S1. Power on multiple Flash memory chips under test in parallel and expose them to the same radiation field simultaneously.

[0041] S2. At the current preset total dose node, select the i-th device under test channel, enable the control line group of the channel, and connect its data terminal to the shared data bus. At the same time, disable the control line groups of other device under test channels and set their data terminals to high impedance.

[0042] S3. Send erase and write commands to the selected i-th Flash memory to write the preset test data to the memory.

[0043] In S3, the preset test data is an alternating feature code, including 55H and AAH; in S4, the electrical parameters include read current, write current, erase time, write time, readback time, and read / write rate.

[0044] S4. Read back the data of the Flash memory under test, compare the read-back data with the preset test data, count the number of error bits and record the electrical parameters.

[0045] In S4, the read / write error rate is calculated as follows: the readback data is compared bit by bit with the original write data, and the number of error bits is counted. The read / write error rate = number of error bits / total number of test bits, where the total number of test bits is the number of test bits for the entire array or the number of test bits selected based on a preset address range.

[0046] Furthermore, the readback and comparison process includes: reading back the storage array data in address order; comparing the readback data with the original written data bit by bit; calculating the number of error bits, read / write error rate, readback time, and read / write rate; and synchronously acquiring and recording the read / write current corresponding to the current channel of the device under test.

[0047] S5. After completing the test of the i-th channel, switch to the next channel of the device under test and repeat steps S2 to S4 until all channels under the current total dose node are tested.

[0048] S6. Summarize the test data of each channel at the current total dose node, and compare it with the preset failure criteria to determine whether each Flash memory under test has failed.

[0049] In S6, the preset failure criteria include one or more of the following: abnormal standby current, abnormal read / write current, excessive erase time, excessive write time, read / write rate below a threshold, read / write error rate above a threshold, or read / write function failure; when any device under test meets the failure criteria, its corresponding failure dose or failure time is recorded.

[0050] Example 2:

[0051] Based on Example 1, Example 2 of this application provides a more specific total dose test and testing method for Flash memory, including:

[0052] S1 (Parallel Power-On and Static Bias): All Flash memories under test are powered on simultaneously through a parallel power supply network and irradiated simultaneously in the same radiation field; the host computer records the bias voltage, standby current and environmental parameters under this total dose node.

[0053] S2 (Select DUTi): The control decoder / timing module enables only the independent control line group of the i-th Flash Memory Under Test (DUT) according to the test command, while deactivating the control signals of other DUTs; the bidirectional tri-state data buffer / multiplexer only conducts the data channel corresponding to DUTi, keeping the data terminals of other DUTs in a high-impedance state. This step ensures that only one DUT is connected to the shared data bus at any given time.

[0054] S3 (Erase and Write): The FPGA test board sends an erase command to the selected DUTi and records the erase time. Then, it sends a write command to write the preset test data to the DUTi. To enhance the exposure capability of potential device degradation, alternating 55H and AAH signature codes can be used for writing, making it easier to detect read / write anomalies caused by threshold drift, parasitic leakage, or cell coupling.

[0055] S4 (Readback and Comparison): The FPGA test board reads back the DUTi's memory array data in address order and compares the readback data bit by bit with the original written data, calculating the number of error bits, read / write error rate, readback time, and read / write rate; simultaneously, it records the read / write current and other relevant electrical parameters corresponding to the DUTi. This readback and comparison process can be performed using... Figure 3 The process shown is implemented.

[0056] S5 (Switch to the next DUT): After completing the DUTi test, the control decoding / timing module shuts down the DUTi control line and data buffer channel, and switches to the next DUTi+1. Repeat S2 to S4 until all DUT tests under this total dose node are completed.

[0057] S6 (Record and Criterion): The host computer summarizes the standby current, read / write current, erase time, write time, readback time, read / write rate, read / write error rate, and abnormal status of each DUT at the total dose node, and compares them with the preset failure threshold. When any key performance indicator exceeds the failure threshold, the corresponding DUT is determined to have failed, and its failure dose or failure time is recorded for subsequent lifetime assessment and degradation pattern analysis.

[0058] In this embodiment, the read / write error rate is defined as the proportion of the number of erroneous bits obtained by comparing the read-back data with the original written data bit by bit after writing preset test data, relative to the total number of bits in the test. If the number of erroneous bits of the i-th Flash memory under test at a certain total dose node is... The total number of test bits is The read / write error rate of the DUT is... Represented as:

[0059]

[0060] Where i = 1, 2, ..., N, N is the number of Flash memory units to be tested; the total number of bits tested. The test bit depth can be the full array bit depth, or it can be the bit depth selected according to a preset address range, page, block, or sector. By comparing the read / write error rate, standby current, read / write current, erase time, write time, readback time, and read / write rate changes of different DUTs at the same total dose node, and combining the changing trends of the above parameters at different total dose nodes, the lateral dispersion and total dose degradation law of the same batch of samples can be obtained.

[0061] To ensure the normal operation of the second photoelectric converter within the radiation test chamber, the thickness of the lead protective enclosure can be configured according to Lambert-Beer's law. Let the initial incident radiation intensity within the test chamber be... The safe radiation intensity threshold that the internal components of the second photoelectric converter can withstand is... The linear attenuation coefficient of lead material for corresponding energy rays is: The lead protective casing thickness is Then the transmission intensity satisfy:

[0062]

[0063] Therefore, the critical thickness of the lead protective casing can be determined as follows:

[0064]

[0065] While meeting radiation shielding requirements, the shape, thickness, and heat dissipation structure of the lead protective shell can be optimized in combination with the heat dissipation requirements of the second photoelectric converter to achieve a balance between shielding effectiveness and device operating stability.

[0066] Furthermore, the testing method also includes: during the total dose test, all DUTs are powered on in parallel under the same dose rate and irradiated simultaneously; when the preset total dose node is reached, the devices under test are selected one by one according to the DUT number order, and erase, write, read back and data comparison operations are performed in sequence, while parameters such as standby current, read and write current, erase time, write time, read back time, read and write rate and read and write error rate are collected simultaneously; after all DUT tests are completed, the functional degradation data and electrical parameter degradation data of each device under test at the total dose node are obtained.

[0067] In addition, in the testing method, the failure criteria can be preset according to the model of the Flash device under test, the test specifications, or the product application requirements. When a device under test exhibits abnormal standby current, abnormal read / write current, excessive erase time, excessive write time, read / write rate below the threshold, read / write error rate above the threshold, or read / write function failure at any total dose node, the device under test is determined to be faulty, and the corresponding failure dose or failure time is recorded.

[0068] It should be noted that this invention is not limited to NOR Flash, NAND Flash, or other non-volatile memories with chip select, address, data, and read / write control interfaces. For devices under test with different package types and interface definitions, adaptation can be achieved by changing the test socket, adjusting the control decoding logic, expanding the address bit width, or modifying the data buffer bit width.

[0069] It should be noted that the parts in this embodiment that are the same as or similar to those in Embodiment 1 can be referred to each other, and will not be repeated in this application.

[0070] Example 3:

[0071] Based on Example 2, Example 3 of this application provides a total dose testing and testing device for Flash memory, such as... Figure 1As shown, the testing apparatus is arranged across the external safety testing room and the radiation testing room, and includes:

[0072] An external safety testing room and a radiation testing room are connected by a first photoelectric converter, a radiation-resistant optical fiber, and a second photoelectric converter.

[0073] The external safety testing chamber is equipped with a host computer, an FPGA test board, a DC regulated power supply, and a high-precision current / voltmeter. The host computer is used for test task management and data storage; the FPGA test board is used to generate the underlying test timing sequence; the DC regulated power supply provides a stable bias; the high-precision current / voltmeter is used for in-situ monitoring of electrical parameters; and the first photoelectric converter is used to convert external test electrical signals into optical signals.

[0074] The radiation test chamber is equipped with a lead-shielded enclosure and a test fixture plate. The second photoelectric converter is disposed inside the lead-shielded enclosure. The second photoelectric converter receives optical signals from the first photoelectric converter via radiation-resistant optical fiber and converts these optical signals back into electrical signals, which are then input into the test fixture plate. The lead-shielded enclosure provides radiation shielding protection for the second photoelectric converter. The test fixture plate carries multiple Flash memories under test and enables parallel biasing and sequential testing.

[0075] The test fixture board includes a control decoding / timing module, an address buffer, a bidirectional tri-state data buffer / multiplexer, a parallel power supply network, a branch current detection / protection unit, and multiple detachable magnetic test sockets. Each detachable magnetic test socket is used to install a Flash memory under test, forming a corresponding channel for the device under test.

[0076] Specifically, such as Figure 1 and Figure 4 As shown, the test fixture board does not simply connect all the pins of multiple Flash chips in parallel. Instead, it adopts a connection method of "shared address, independent control, data isolation, and sequential read / write" based on parallel bias. Specifically, the address bus A[0:n] is fanned out by the address buffer to all DUTs; the control decoding / timing module outputs independent control line groups according to the selected DUT number; the data terminals DQ[0:m] of each DUT are connected to the bidirectional tri-state data buffer / multiplexer, and this module is selectively connected to the shared data bus; VCC and VPP are simultaneously distributed to each DUT channel through the parallel power supply network.

[0077] The control decoding / timing module is used to output an independent and valid control line group to the currently selected channel of the device under test, while invalidating the control line groups of other channels; the address buffer is used to distribute the address signal to all channels; the bidirectional tri-state data buffer / multiplexer is used to connect the data terminal to the shared data bus only when the corresponding channel is selected, otherwise it is set to a high impedance state; the parallel power supply network is used to provide operating bias to all channels in parallel; the branch current detection / protection unit is used to collect the current signal of each channel and perform protection in case of overcurrent.

[0078] Specifically, at any given time during a read / write test, the control decoding / timing module enables only the chip select and read / write control signals of one DUTi, while the bidirectional tri-state data buffer / multiplexer only conducts the data channel corresponding to that DUTi; the control lines of the remaining DUTs remain inactive, and the data buffer channels remain in a high-impedance state. In this way, even if all DUTs are powered on in parallel and irradiated simultaneously during the irradiation process, the data path actually involved in erasing, writing, and reading back is only the selected DUTi, effectively avoiding chip select conflicts, bus contention, and multi-chip data aliasing.

[0079] The control line group includes a chip select control signal, and one or more of the following configured based on the interface type of the Flash memory under test: write enable control signal, output enable control signal, read enable control signal, reset control signal, command latch control signal, address latch control signal, or write protect control signal; at any test moment, the control decoding / timing module enables the control line group of only one channel of the device under test to be in an active state.

[0080] For example, for parallel Flash memory, the independent control line group can be configured as signals such as CEi#, OEi#, WEi#, and RESETi#; for Flash memory, the independent control line group can be configured as signals such as CEi#, WEi#, REi#, CLEi, ALEi, WPi#, and R / Bi#. The signal names mentioned above can be replaced with equivalents according to the specific device datasheet, but it should be ensured that only the selected DUTi can respond to erase, write, or readback commands at any given time.

[0081] The parallel power supply network provides VCC and VPP bias to each device under test channel in a star or equal impedance distribution manner.

[0082] The branch current detection / protection unit can be installed in each DUT power supply branch to collect standby current, read current, and write current separately for single-chip device failure location; it can also be installed in the main power supply branch to collect the total current change trend and combine it with the DUT sequential test timing for fault diagnosis. This unit can also perform current limiting, alarm, or disconnection protection on the corresponding branch when abnormal overcurrent is detected to prevent faulty devices from affecting the irradiation tests of other devices.

[0083] The test fixture plate also includes a power input terminal for connecting an external bias power supply; the detachable magnetic test base is positioned and fixed through positioning holes and magnetic fixing positions, and is provided with a flip-up test base cover for pressing the Flash memory under test.

[0084] For example, such as Figure 4 As shown, the test fixture plate includes: 1 is a parallel power supply and signal distribution area, 2 is a power input terminal, 3 is a test socket mounting area, 4 is a detachable magnetic test socket, 5 is a positioning hole and magnetic fixing position, and 6 is a flip-top test socket cover. The parallel power supply and signal distribution area is used to distribute VCC, VPP, address bus, control signals, and data bus to each test socket mounting area; the power input terminal is used to connect an external bias power supply; the detachable magnetic test socket is used to install the Flash memory under test; the positioning hole and magnetic fixing position are used to achieve quick positioning and fixing of the test socket; the flip-top test socket cover is used to press the Flash memory under test to ensure the stability of the electrical connection during the irradiation test.

[0085] During the static monitoring phase, the host computer applies a preset bias voltage, such as a 3.3V operating voltage or other operating voltages set according to device requirements, to all the DUTs by controlling the DC regulated power supply; all DUTs are synchronously powered on through a parallel power supply network and are simultaneously irradiated in the same radiation field; high-precision current / voltmeters and branch current detection / protection units are used to collect standby current and power supply parameters to reflect the device bias degradation characteristics under total dose environment.

[0086] When the cumulative dose reaches the preset total dose threshold, in-situ dynamic function testing is performed. The host computer sends test commands to the FPGA test board; the FPGA test board generates the underlying clock, address, control, and data sequences, which are transmitted to the test fixture board via the first photoelectric converter, radiation-resistant optical fiber, and the second photoelectric converter; the test fixture board then... Figure 2 The sequential control flow shown performs erase, write, read-back, and comparison operations on each DUT piece by piece. This sequential control flow specifically includes the following steps.

[0087] It should be noted that the device provided in this embodiment is the same as the device corresponding to the method provided in embodiment 2. Therefore, the parts that are the same or similar to those in embodiment 2 in this embodiment can be referred to each other, and will not be described again in this application.

[0088] Example 4:

[0089] Based on Embodiment 3, Embodiment 4 of this application provides a more specific total dose testing and testing device for Flash memory, including: an external safety testing room and a radiation testing room. The external safety testing room is equipped with a host computer, an FPGA test board, a DC regulated power supply, a high-precision ammeter / voltmeter, and a first photoelectric converter; the radiation testing room is equipped with a second photoelectric converter, a lead protective enclosure, and a test fixture plate. The first and second photoelectric converters are connected via radiation-resistant optical fiber to achieve long-distance, cross-regional transmission of control signals and test data.

[0090] The host computer is used to configure the test mode, set the total dose node, control the start and stop of the test, and receive and store the test results; the FPGA test board generates the test clock, address bus, control signal group and erase / write / readback commands, and performs logical comparison and error bit statistics on the readback data; the DC regulated power supply is used to provide VCC and necessary VPP bias to the device under test; and the high-precision ammeter / voltmeter is used to monitor the voltage and current of the power supply branch in situ.

[0091] The test fixture is placed in the radiation test chamber and includes a control decoding / timing module, an address buffer, a bidirectional tri-state data buffer / multiplexer, a parallel power supply network, a branch current detection / protection unit, and multiple detachable magnetic test sockets. Each detachable magnetic test socket mounts a Flash memory under test, forming a DUT channel.

[0092] The control decoding / timing module receives control signal groups from the FPGA test board and outputs corresponding independent control line groups based on the currently selected device under test (DUT) number DUTi. These independent control line groups include a chip select control signal CEi#, a write enable control signal WEi#, and one or more of the following configured according to the interface type of the Flash memory under test: output enable control signal OEi#, read enable control signal REi#, reset control signal RESETi#, command latch control signal CLEi, address latch control signal ALEi, or write protect control signal WPi#; where i = 1, 2, ..., N, N is the number of Flash memories under test, and "#" indicates active low. At any given test time, only one DUTi's control line group is allowed to be active, while the remaining DUT control line groups remain inactive.

[0093] The address buffer is used to fan out the shared address bus A[0:n] to all DUT channels so that each DUT can receive the test address. Since only the selected DUT responds to the control command, the unselected DUTs do not perform erase, write or read operations even though they receive the address signal.

[0094] The bidirectional tri-state data buffer / multiplexer is connected to the data terminals DQ[0:m] of each DUT and the shared data bus. When DUTi is selected, its corresponding data buffer channel is turned on, enabling bidirectional data interaction between DUTi and the shared data bus; when DUTi is not selected, its corresponding data buffer channel remains in a high-impedance state, thereby avoiding bus contention caused by multiple DUTs simultaneously driving the shared data bus.

[0095] The parallel power supply network provides VCC and VPP bias to each DUT channel in a star or equal impedance distribution manner, ensuring that all Flash memories under test are powered on, biased, and irradiated in parallel during the total dose irradiation process. The branch current detection / protection unit is connected in series in each DUT power supply branch or the main power supply branch to collect standby current, read current, write current, and abnormal overcurrent information, and to perform current limiting, alarm, or disconnection protection in the event of an overcurrent.

[0096] The second photoelectric converter is housed inside a lead-protected enclosure, which is used to reduce the damage to sensitive components inside the second photoelectric converter caused by the radiation environment. The electrical signal restored by the second photoelectric converter is input to the test fixture board to ensure the stability of test control and data transmission within the radiation test chamber.

[0097] It should be noted that the parts in this embodiment that are the same as or similar to those in Embodiment 3 can be referred to each other, and will not be repeated in this application. Furthermore, the above embodiments are only preferred embodiments of the present invention. Equivalent substitutions or modifications made by those skilled in the art to the control signal type, number of DUT channels, branch detection method, photoelectric converter model, test feature code, and power supply distribution method without departing from the technical concept of the present invention should all fall within the protection scope of the present invention.

Claims

1. A total dose test and testing method for a Flash memory, characterized in that, include: S1. Power on multiple Flash memory chips under test in parallel and expose them to the same radiation field simultaneously. S2. At the current preset total dose node, select the i-th device under test channel, enable the control line group of the channel, and connect its data terminal to the shared data bus. At the same time, disable the control line groups of other device under test channels and set their data terminals to high impedance. S3. Send erase and write commands to the selected i-th Flash memory to write the preset test data into the memory. S4. Read back the data of the Flash memory under test, compare the read-back data with the preset test data, count the number of error bits and record the electrical parameters; S5. After completing the test of the i-th channel, switch to the next channel of the device under test and repeat steps S2 to S4 until all channels under the current total dose node are tested. S6. Summarize the test data of each channel at the current total dose node, and compare it with the preset failure criteria to determine whether each Flash memory under test has failed.

2. The total dose test and testing method for Flash memory according to claim 1, characterized in that, In S3, the preset test data is an alternating feature code, including 55H and AAH; in S4, the electrical parameters include read current, write current, erase time, write time, readback time, and read / write rate.

3. The total dose test and testing method for Flash memory according to claim 2, characterized in that, In S4, the read / write error rate is calculated as follows: the readback data is compared bit by bit with the original write data, and the number of error bits is counted. The read / write error rate = number of error bits / total number of test bits, where the total number of test bits is the number of test bits for the entire array or the number of test bits selected based on a preset address range.

4. The total dose test and testing method for Flash memory according to claim 3, characterized in that, In S6, the preset failure criteria include one or more of the following: abnormal standby current, abnormal read / write current, excessive erase time, excessive write time, read / write rate below a threshold, read / write error rate above a threshold, or read / write function failure; when any device under test meets the failure criteria, its corresponding failure dose or failure time is recorded.

5. The total dose test and testing method for Flash memory according to claim 4, characterized in that, In S4, the readback and comparison process includes: reading back the storage array data in address order; comparing the readback data with the original written data bit by bit; calculating the number of error bits, read / write error rate, readback time, and read / write rate; and synchronously acquiring and recording the read / write current corresponding to the current channel of the device under test.

6. A total dose testing and testing device for Flash memory, characterized in that, For performing the method according to any one of claims 1 to 5, comprising: An external safety testing room and a radiation testing room are connected to the radiation testing room via a first photoelectric converter, a radiation-resistant optical fiber, and a second photoelectric converter. The external safety test room is equipped with a host computer, an FPGA test board, a DC regulated power supply, and a high-precision current / voltage meter. The radiation test chamber is equipped with a lead protective enclosure and a test fixture plate, and the second photoelectric converter is disposed inside the lead protective enclosure; The test fixture board includes a control decoding / timing module, an address buffer, a bidirectional tri-state data buffer / multiplexer, a parallel power supply network, a branch current detection / protection unit, and multiple detachable magnetic test sockets. Each of the detachable magnetic test sockets is used to install a Flash memory under test, forming a corresponding channel for the device under test. The control decoding / timing module is used to output an independent and valid control line group to the currently selected channel of the device under test, while invalidating the control line groups of other channels; the address buffer is used to distribute the address signal to all channels; the bidirectional tri-state data buffer / multiplexer is used to connect the data terminal to the shared data bus only when the corresponding channel is selected, otherwise it is set to a high impedance state; the parallel power supply network is used to provide operating bias to all channels in parallel; the branch current detection / protection unit is used to collect the current signal of each channel and perform protection in case of overcurrent.

7. The total dose testing and apparatus for Flash memory according to claim 6, characterized in that, The control line group includes a chip select control signal, and one or more of the following configured based on the interface type of the Flash memory under test: write enable control signal, output enable control signal, read enable control signal, reset control signal, command latch control signal, address latch control signal, or write protect control signal; at any test moment, the control decoding / timing module enables the control line group of only one channel of the device under test to be in an active state.

8. The total dose testing and apparatus for Flash memory according to claim 7, characterized in that, The parallel power supply network provides VCC and VPP bias to each device under test channel in a star or equal impedance configuration.

9. The total dose testing and apparatus for Flash memory according to claim 8, characterized in that, The test fixture plate also includes a power input terminal for connecting an external bias power supply; the detachable magnetic test base is positioned and fixed through positioning holes and magnetic fixing positions, and is provided with a flip-up test base cover for pressing the Flash memory under test.

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