Failure data storage control method, chip parallel test method, failure data storage device, chip parallel test system, chip automatic test equipment and computer program product

Abstract

The embodiment of the application discloses a failure data storage control method, a chip parallel test method, a failure data storage device, a chip parallel test system, a chip automatic test equipment and a computer program product, and belongs to the field of integrated circuit automatic test. The method comprises the following steps: obtaining an address-continuous storage interval from a preset failure data storage address and assigning the storage interval to a currently failed test chip during a test process; when the storage interval is fully assigned, obtaining at least one new assignable storage interval from all or part of the assigned storage intervals, and assigning the new assignable storage interval to a currently or subsequently failed test chip; and accessing the failure data storage interval assigned to the test chip, and processing the failure data of the test chip. The application can significantly improve the failure data storage space utilization, the read-write efficiency and the system throughput capacity.

Description

Technical Field

[0001] This application relates to the field of automated testing of integrated circuits, and in particular to a failure data storage control method, a chip parallel testing method, a failure data storage device, a chip parallel testing system, a chip automated testing equipment, and a computer program product. Background Technology

[0002] In automated test equipment (ATE) for integrated circuits, the data failure memory (DFM) is usually an external DRAM storage module of FPGA / ASIC. It is used to capture and temporarily store key data such as failure address, failure I / O bit, failure count, and failure cycle generated by the device under test (DUT) during the test vector execution cycle in real time. It is the core data carrier for chip defect location, yield analysis and failure diagnosis.

[0003] Existing DFM technologies generally adopt a storage architecture that is tiled in rows according to IO channels. This architecture suffers from severe invalid data redundancy and low read and parsing efficiency. Summary of the Invention

[0004] This application provides a method for controlling the storage of failed data, a method for parallel testing of chips, a parallel testing system for chips, automated testing equipment for chips, and a computer program product, which can significantly improve the utilization rate, read and write efficiency, and system throughput of the storage space for failed data.

[0005] In a first aspect, this application provides a method for controlling the storage of failed data, applied to an automated chip testing device having a storage module and a main control module, the method comprising: During the test, a contiguous storage range is obtained from the preset failure data storage address and allocated to the currently failed chip under test. When the storage range is fully allocated, at least one new allocable storage range is obtained from all or part of the allocated storage ranges and allocated to the currently or subsequently failed chip under test. Access the failure data storage area allocated to the chip under test and process the failure data of the chip under test.

[0006] Optionally, obtaining at least one new allocatable storage region from all or part of the allocated storage regions specifically includes: In response to the need to allocate storage space for a failed chip under test, the system queries whether the preset available space list is empty. If it is, the system performs a reallocation operation on some or all of the storage spaces currently allocated to each chip under test to obtain the new available storage space. The available space list is used to store the currently available storage space. The new allocable storage range is then backfilled into the available range linked list.

[0007] Optionally, the initial allocatable storage range stored in the available range linked list is all the preset invalid data storage addresses; and / or, the reallocation operation is set as a binary search operation.

[0008] Optionally, the binary search operation specifically includes: Calculate the midpoint address of at least one currently allocated memory region; Using the midpoint address as the starting address of the new available range, a new allocatable storage range is obtained.

[0009] Optionally, after querying whether the preset available range linked list is empty, the method further includes: In response to the query finding that the available interval linked list is not empty, an allocatable storage interval is retrieved from the preset available interval linked list and allocated to the currently failed chip under test according to the failure triggering order of the tested chips.

[0010] Optionally, the process of accessing the failure data storage area allocated to the chip under test and processing the failure data of the chip under test specifically includes: Obtain the memory space allocated to the chip under test, and write the failure data of the chip under test into that memory space.

[0011] Optionally, the process of accessing the failure data storage area allocated to the chip under test and processing the failure data of the chip under test specifically includes: According to the read command issued by the host computer, the failure data storage range of the target chip under test is obtained from the preset address mapping table of the chip under test, and the failure data of the target chip under test is read.

[0012] Optionally, the process of accessing the failure data storage area allocated to the chip under test and processing the failure data of the chip under test specifically includes: According to the erase command issued by the host computer, the failure data storage range of the target chip is obtained from the preset address mapping table of the chip under test, the starting address and length of the area to be erased are generated, and the failure data in the area to be erased is erased.

[0013] Optionally, accessing the failure data storage area allocated to the chip under test and processing the failure data of the chip under test further includes: The failure data generated by each chip under test is encapsulated into standardized data frames according to a preset frame format. The failure data includes at least the failure address, failure I / O bit combination, and failure period; and / or The storage module is accessed via a data bus, the address input port of the storage module is connected via an address bus, and / or the read / write instruction output port of the main control module is connected via a control bus.

[0014] Optionally, the preset available range linked list is stored in the main control module.

[0015] Optionally, the failed data storage control method further includes: Analyze the chip-on-demand status of each IO channel of the main control module to determine the valid and idle channels; Send a hardware shutdown signal, which is used to set the drive output of the idle channel to a high impedance state and cut off its connection to the write enable signal and clock enable signal of the memory module.

[0016] Secondly, this application provides a chip parallel testing method, applied to chip automated testing equipment, the chip parallel testing method including the steps of the failure data storage and control method described in the first aspect.

[0017] Thirdly, this application provides a failure data storage control circuit, applied to an automated chip testing device having a storage module and a main control module, the failure data storage control circuit comprising: The storage address allocation module is used to obtain a contiguous storage range from the preset failure data storage address of the storage module during the test and allocate it to the currently failed chip under test. When the storage range is fully allocated, it performs a reallocation operation on all or part of the allocated storage ranges to obtain new allocable storage ranges and allocates them to the chip under test that needs to store failure data. The failure data processing module is used to obtain and access the storage area of ​​failure data allocated to the chip under test by the storage address allocation module, and to process the failure data of the chip under test.

[0018] Optionally, the storage address allocation module specifically includes: Available interval storage units are used to store the currently allocable storage interval into a preset available interval linked list; The available interval allocation unit is used to retrieve an allocatable storage interval from the available interval linked list and allocate it to the currently failed chip under test according to the failure triggering order of the chip under test; The available interval regeneration unit is used to perform a binary search operation on some or all of the memory intervals currently allocated to each chip under test when the available interval linked list is empty but there are still failed chips under test that need to be allocated addresses. The new allocatable memory intervals obtained by the binary search operation are then filled back into the available interval linked list.

[0019] Optionally, the available interval regeneration unit specifically includes: An arithmetic logic unit, connected to the read port of the available interval linked list, is used to calculate the midpoint address of any currently allocated storage interval; The interval backfilling unit is used to take the midpoint address as the new available interval boundary and backfill the new allocable storage interval into the available interval linked list.

[0020] Optionally, the storage address allocation module further includes: An allocation state machine, connected to the output of the available interval regeneration unit and the write port of the available interval linked list, is used to control the timing of the available interval allocation unit's allocation of storage intervals and the available interval regeneration unit's backfilling of storage intervals according to the arrival order of the failed DUT trigger signals; and / or The initial storage range for the available range storage unit stored in the available range linked list is the address for all preset failed data storage.

[0021] Optionally, the failure data storage control circuit further includes: The channel control module, connected to the IO channel, is used to determine the valid and idle channels based on the IO channel's mounting status, and to shut down the idle channel via hardware. This hardware shutdown includes setting the drive output of the idle channel to a high impedance state and disabling the write enable signal and the write clock signal.

[0022] Optionally, the channel control module specifically includes: The channel scan register array is used to latch the mounting status bits of the chip under test for each IO channel; A mask generation logic unit is connected to the output of the channel scanning register array and is used to output a valid channel mask and an idle channel mask according to the mounting status bit. The three-state control drive unit is connected to the idle channel mask output terminal of the mask generation logic unit and is used to set the drive output of the idle channel to a high-impedance state. The clock gating unit is connected to the idle channel mask output terminal of the mask generation logic unit and is used to cut off the enable and write clock supply of the idle channel.

[0023] Optionally, the failure data processing module specifically includes: The failure data writing unit is used to obtain the storage area allocated to the chip under test by the storage address allocation module, and write the failure data of the current chip under test into that storage area; and / or The failure data reading unit is used to obtain the failure data storage range of the target chip under test from a preset address mapping table of the chip under test according to the reading instruction issued by the host computer, and read the failure data of the target chip under test; and / or The failure data erasure unit is connected to the output of the address mapping table. It is used to obtain the failure data storage range of the target chip from the preset chip under test address mapping table according to the erasure command issued by the host computer, generate the starting address and length of the area to be erased, and erase the failure data in the area to be erased.

[0024] Optionally, the failure data processing module further includes: The data frame assembly unit, whose input is connected to the IO channel, is used to encapsulate the failure address, failure IO bit combination, and failure period of the chip under test into a standardized data frame according to a preset frame format. The data bus interface unit is used to connect to the address input port of the storage module via the address bus, and / or to the read / write instruction output port of the main control module via the control bus.

[0025] Fourthly, this application provides a failed data storage device, including the failed data storage control circuit described in the third aspect; or including a processing module, the processing module being used to execute the steps in the failed data storage control method described in the first aspect.

[0026] Fifthly, this application provides a chip parallel testing system, including the failure data storage device described in the fourth aspect.

[0027] In a sixth aspect, this application provides an automated chip testing device, including a processor and a memory, wherein the memory is coupled to the processor and is used to store computer program code, the computer program code including computer instructions, wherein when the processor reads the computer instructions from the memory, the computer executes steps in the failure data storage control method as described in the first aspect or the chip parallel testing method as described in the second aspect.

[0028] In a seventh aspect, this application provides a computer program product comprising: computer program code, which, when executed on a computer, causes the computer to perform steps in the failure data storage control method described in the first aspect or the chip parallel testing method described in the second aspect.

[0029] The beneficial effects of this application are: This application allocates the storage space required for the failure data of the chip under test in real time during the test process, and performs a reallocation operation on the allocated space after all storage spaces are allocated to regenerate new space. This enables the failure data storage address to be dynamically and adaptively adjusted according to the unpredictable failure triggering order in the test process, which effectively improves the space utilization, read and write efficiency and system throughput of the failure data storage address. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a flowchart illustrating the failure data storage control method according to an embodiment of this application.

[0032] Figure 2 This is a schematic diagram of the process of obtaining a storage area in the failure data storage control method of this application embodiment.

[0033] Figure 3 This is a schematic flowchart of the failure data processing in the failure data storage control method of this application embodiment.

[0034] Figure 4 This is a schematic diagram of the structure of the failure data storage control circuit according to an embodiment of this application.

[0035] Figure 5 This is a schematic diagram of the storage address allocation module in the failure data storage control circuit of this application embodiment.

[0036] Figure 6 This is a schematic diagram of the available interval regeneration unit in the failed data storage control circuit of this application embodiment.

[0037] Figure 7 This is a schematic diagram of the channel control module in the failure data storage control circuit of this application embodiment.

[0038] Figure 8 This is a schematic diagram of the structure of the failure data processing module in the failure data storage control circuit of this application embodiment.

[0039] Explanation of reference numerals in the attached figures: 100. Storage address allocation module; 110. Available interval storage unit; 120. Available interval allocation unit; 130. Available interval regeneration unit; 140. Allocation state machine; 131. Arithmetic logic unit; 132. Interval backfilling unit. 200 Failure data processing module; 210 Failure data writing unit; 220 Failure data reading unit; 230 Failure data erasing unit; 240 Data frame assembly unit; 250 Data bus interface unit. 300. Channel control module; 310. Channel scan register array; 320. Mask generation logic unit; 330. Three-state control drive unit; 340. Clock gating unit. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be described in detail below with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0041] It should be noted that: throughout the accompanying drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions; in the description of this application, the terms "center," "longitudinal," "lateral," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; in the description of this application, "first," "second," etc., are only used to distinguish each other, and do not indicate their degree of importance or order, etc.

[0042] In the description of this application, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to fixed connections, movable connections, or detachable connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal communication between two components, etc. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0043] Existing DFM technologies generally adopt a row-based storage architecture for IO channels, that is, the test results of all IO channels are written globally on a row-by-row basis. Idle channels without DUTs or channels with DUTs but no failures are also written with filler data such as P (Pass). The storage space utilization rate drops sharply as the number of channels and test depth increase. Extracting failure data of a single DUT requires a full traversal of the DFM and filtering the failure IO information of the target DUT row by row. The time spent on data migration and parsing increases linearly with the number of channels and storage depth.

[0044] To address the problems of invalid data redundancy, rigid address allocation methods, and high read traversal overhead in existing technologies, this application provides a failure data storage control method, a chip parallel testing method, a failure data storage control circuit, a failure data storage device, a chip parallel testing system, a chip automated testing equipment, and a computer program product. The aim is to achieve real-time allocation of storage addresses according to the failure triggering order during ATE testing, and to regenerate new available space by performing a binary search operation on the allocated interval when the address space is exhausted, thereby significantly improving storage density and read efficiency.

[0045] Please refer to Figure 1 This application provides a method for controlling the storage of failed data, applied to an automated chip testing device with a storage module and a main control module. The method for controlling the storage of failed data includes: In step S300, during the test, a contiguous storage range is obtained from the preset failure data storage address and allocated to the currently failed chip under test. When the storage range is fully allocated, at least one new allocable storage range is obtained from all or part of the allocated storage ranges and allocated to the currently or subsequently failed chip under test. In step S400, the failure data storage area allocated to the chip under test is accessed, and the failure data of the chip under test is processed.

[0046] During ATE testing, multiple DUTs are tested in parallel, and the failure time and amount of failure data for each DUT are unpredictable. This embodiment continuously monitors failure events during test execution. Whenever a DUT fails, a contiguous storage range is immediately obtained from the preset failure data storage address in the DFM storage module and allocated to that DUT. The key is that when all preset storage ranges have been allocated (i.e., there is no available unallocated space), the test does not terminate with an error. Instead, the allocated storage ranges (a DUT may be allocated 2GB of address space, but the actual written failure data may only be a few MB, leaving the remaining space physically free) are compressed to release the address space not occupied by actual written data, forming new available storage ranges, thus continuing to allocate space for subsequent failed DUTs.

[0047] The core of this application's embodiment lies in a two-stage dynamic closed-loop process: real-time allocation during test operation and re-allocation triggered after allocation is completed.

[0048] Phase 1 (Real-time Allocation): During the test, whenever a DUT fails, a continuous range is immediately allocated from the preset storage address.

[0049] The second phase (reallocation): When all preset addresses have been allocated, the test is not terminated. Instead, the allocated range is compressed to release the unfilled address space and form a new available range.

[0050] Please refer to Figure 2 In at least one possible implementation, obtaining at least one new allocatable storage region from all or part of the allocated storage regions specifically includes: In step S301, in response to the need to allocate storage space for the failed chip under test, the system queries whether the preset available space list is empty. If so, the system performs a reallocation operation on some or all of the storage spaces currently allocated to each chip under test to obtain the new available storage space. The available space list is used to store the currently available storage space, i.e., all preset failed data storage addresses. In step S302, the new allocable storage interval is backfilled into the available interval linked list.

[0051] The available range linked list in this application embodiment is a data structure that stores contiguous address ranges that have not yet been allocated to any DUT. Its initial state contains an initial storage range, which corresponds to the entire physical address space of the DFM storage module.

[0052] In this embodiment of the application, a storage interval is taken from the available interval linked list and allocated to the currently failed DUT according to the real-time order of failure triggering. Each time a DUT is allocated, the storage interval in the available interval linked list is reduced by one, until all available storage intervals are exhausted and the available interval linked list is empty.

[0053] In this embodiment, when the available interval linked list is empty (i.e., all address spaces have been allocated) but there are still new failed DUTs that need to be allocated, a reallocation operation is performed on the storage intervals already allocated to each DUT. New available intervals are divided from each allocated interval and filled back into the available interval linked list. The available interval linked list realizes the dynamic recording of the allocation status. The "relocation triggered when the linked list is empty" realizes the adaptive regeneration of space, thereby realizing the continuous iterative cycle of "allocation → exhaustion → regeneration → reallocation".

[0054] In at least one possible implementation, the redistribution operation is configured as a binary search operation. The binary search operation does not require prior knowledge of the total number of failed DUTs or the amount of failure data for each DUT; it only requires knowledge of the boundary values ​​of the currently allocated intervals to complete the calculation. This allows the system to continuously respond to unpredictable, non-uniform failure distributions with minimal hardware overhead, ensuring that space utilization approximates the actual total amount of failure data while meeting the stringent real-time and deterministic requirements of ATE testing.

[0055] In at least one possible implementation, the binary search operation specifically includes: Calculate the midpoint address Mid_i of at least one currently allocated memory range [Start_i, End_i]: Mid_i = (Start_i + End_i) >> 1; Using the midpoint address Mid_i as the starting address of the new available interval, a new allocatable storage interval [Mid_i, End_i] is obtained.

[0056] ATE testing has strict real-time constraints, and address reassignment must be completed in nanoseconds. However, the binary search operation only requires a right shift operation (>>1) to calculate the midpoint address in a single clock cycle in the FPGA.

[0057] Please continue to refer to this. Figure 2 In at least one possible implementation, after querying whether the preset available range linked list is empty, the method further includes: In step S303, in response to the query finding that the available interval linked list is not empty, an allocatable storage interval is retrieved from the preset available interval linked list and allocated to the currently failed chip under test according to the failure triggering order of the chip under test.

[0058] Please refer to Figure 3 In at least one possible implementation, accessing the failure data storage area allocated to the chip under test and processing the failure data of the chip under test specifically includes: In step S401, the storage area allocated to the chip under test is obtained, and the failure data of the current chip under test is written into the storage area.

[0059] In step S402, according to the read instruction issued by the host computer, the failure data storage range of the target chip under test is obtained from the preset address mapping table of the chip under test, and the failure data of the target chip under test is read.

[0060] In step S403, according to the erase command issued by the host computer, the failure data storage range of the target chip under test is obtained from the preset chip under test address mapping table, the starting address and length of the area to be erased are generated, and the failure data in the area to be erased is erased.

[0061] In at least one possible implementation, accessing the failure data storage area allocated to the chip under test and processing the failure data of the chip under test further includes: The failure data generated by each chip under test is encapsulated into standardized data frames according to a preset frame format. The failure data includes at least the failure address, failure I / O bits, and failure period; and / or The storage module is accessed via a data bus, the address input port of the storage module is connected via an address bus, and / or the read / write instruction output port of the main control module is connected via a control bus.

[0062] In at least one possible implementation, the preset available range linked list is obtained from the FPGA; and / or, the preset chip under test address mapping table is obtained from the FPGA.

[0063] Please continue to refer to this. Figure 1 In at least one possible implementation, the failed data storage control method further includes: In step S100, the chip-on-demand status of each IO channel of the main control module is analyzed to determine the valid and idle channels; In step S200, a hardware shutdown signal is sent, which is used to set the drive output of the idle channel to a high impedance state and cut off its connection to the write enable signal and clock enable signal of the memory module.

[0064] In ATE parallel testing scenarios, not all IO channels are equipped with the DUT. Idle channels without a DUT are not generating any valid data during testing. These channels will write invalid P (Pass) padding data to the DFM, resulting in wasted storage space.

[0065] This embodiment of the application obtains the DUT mounting status of each IO channel by parsing the test configuration file (Socket file, DUT Map, etc.). For idle channels without mounted DUTs, the channel control module 300 performs a triple hardware shutdown: Set to high impedance state: Sets the I / O driver output of the idle channel to a high impedance state (HiZ), disconnecting the physical output of the channel from the electrical level; Disable write enable signal: Cut off the write enable path from the idle channel to the DFM; Disconnect write clock signal: Stop providing DFM write clock to idle channels.

[0066] Hardware shutdown is completed during the test initialization phase. Triple hardware shutdown is implemented simultaneously at three physical levels: the driver output stage, the enable control stage, and the clock supply stage, ensuring that no data is written to the DFM under any electrical conditions on the idle channel.

[0067] Based on the same concept as the above embodiments, this application also provides a chip parallel testing method, including the aforementioned failure data storage control method. This chip parallel testing method can be applied to parallel testing scenarios such as aging testing, wafer testing, and finished product testing of memory chips.

[0068] Please refer to Figure 4 This application also provides a failed data storage control circuit, applied to an automated chip testing device having a storage module and a main control module. The failed data storage control circuit includes: The storage address allocation module 100 is used to obtain a continuous storage range from the failure data storage address preset by the storage module during the test and allocate it to the currently failed chip under test. When the storage range is fully allocated, it performs a reallocation operation on all or part of the allocated storage ranges to obtain new allocable storage ranges and allocates them to the chip under test that needs to store failure data. The failure data processing module 200 is used to obtain and access the storage area of ​​failure data allocated to the chip under test by the storage address allocation module, and to process the failure data of the chip under test.

[0069] In an FPGA, the memory address allocation module 100 of this embodiment can be implemented using register + MUX combinational logic. A register stores the number of currently allocated intervals, and combinational logic determines whether all intervals have been allocated. When a new failed DUT is triggered, if there are unallocated memory intervals, they are allocated directly; otherwise, a reallocation operation is triggered. The entire logic can complete the judgment and allocation within one clock cycle.

[0070] Please refer to Figure 5 In at least one possible implementation, the storage address allocation module 100 specifically includes: Available interval storage unit 110 is used to store the currently allocable storage interval into a preset available interval linked list; The available interval allocation unit 120 is used to retrieve an allocatable storage interval from the available interval linked list and allocate it to the currently failed chip under test according to the failure triggering order of the chip under test. The available interval regeneration unit 130 is used to perform a binary search operation on some or all of the memory intervals currently allocated to each chip under test when the available interval linked list is empty but there are still failed chips under test that need to be allocated addresses, and then fill the new allocable memory intervals obtained by the binary search operation back into the available interval linked list.

[0071] In an FPGA, the available range linked list of this application embodiment can be stored in on-chip BRAM (Block RAM). BRAM has the characteristics of high speed and low latency, supporting the completion of linked list read and update operations within one clock cycle. The available range allocation unit 120 and the available range regeneration unit 130 can be implemented by combinational logic, automatically completing address allocation or regeneration operations according to the current linked list state and failure trigger signal.

[0072] Please refer to Figure 6 In at least one possible implementation, the available interval regeneration unit 130 specifically includes: Arithmetic logic unit 131, connected to the read port of the available interval linked list, is used to calculate the midpoint address Mid_i = (Start_i + End_i) >> 1 of any currently allocated storage interval [Start_i, End_i], where i represents the current storage interval number and >> represents a right shift operation by one bit; The interval backfilling unit 132 is used to take the midpoint address Mid_i as the new available interval boundary and backfill the new allocable storage interval [Mid_i, End_i] into the available interval linked list.

[0073] The core of the binary search operation is calculating the address of the midpoint of the allocated interval. The formula for calculating the midpoint address is: Mid_i=(Start_i+End_i)>>1; The value >>1 indicates a right shift operation. In digital circuits, a right shift by one bit is equivalent to division by 2 (rounding down), but in hardware implementation, it only requires shifting the entire binary data one bit to the least significant bit, without involving any dividers or multipliers.

[0074] For example, for the interval [0, 8GB] already assigned to DUT1, its midpoint address is (0+8GB) >> 1 = 4GB. After performing a binary search, [0, 4GB] is retained for DUT1, and [4GB, 8GB] is added back to the available interval list as a new available interval.

[0075] The interval backfilling unit 132 uses the calculated midpoint address as the starting address of the new available interval and the end address of the original interval as the end address of the new available interval, and writes [Mid_i, End_i] into the available interval linked list.

[0076] This application embodiment utilizes the >>1 shift operation to realize midpoint calculation, which can be completed in a single clock cycle in FPGA, much faster than the division operation of general processors, and realizes address regeneration in nanosecond time.

[0077] In the FPGA, the arithmetic logic unit 131 can implement the >>1 operation by shifting the entire binary data on the address bus one bit to the right. This requires no logic gates; it only requires physical routing to connect the high-order data line to the low-order data line, resulting in near-zero latency. The adder calculates Start_i + End_i, and the result is fed into the shifter to perform a right shift operation by one bit.

[0078] The interval backfill unit 132 can be implemented through a set of registers to temporarily store the calculated midpoint address and the end address of the original interval, and write them into the available interval linked list in the BRAM in the next clock cycle.

[0079] Please continue to refer to this. Figure 5 In at least one possible implementation, the storage address allocation module 100 further includes: A state machine 140, connected to the output of the available interval regeneration unit 130 and the write port of the available interval linked list, is used to control the timing of the available interval allocation unit's allocation of storage intervals and the available interval regeneration unit's backfilling of storage intervals according to the arrival order of the failed DUT trigger signals; and / or The initial storage range of the available range storage unit 110 is the address of all preset failed data storage in the available range linked list.

[0080] Because failure DUT trigger signals arrive asynchronously during ATE testing, multiple failure triggers may occur within the same clock cycle. The allocation state machine 140 is responsible for arbitrating and sequencing these trigger signals, ensuring that each failure DUT receives address allocation in sequence.

[0081] The workflow for allocating state machine 140 is as follows: Idle state: Waiting for a failure trigger signal. When a trigger signal is received, check if the available range linked list is empty.

[0082] Allocation state: If the linked list is not empty, take an available range from the linked list and allocate it to the current DUT, update the linked list, and return to the free state.

[0083] Regeneration: If the linked list is empty, start the available interval regeneration unit 130 to perform a binary search operation, fill the newly generated available interval back into the linked list, and then return to the allocation state to continue allocation.

[0084] This application embodiment uses the entire space as the initial storage area, and then dynamically divides it according to the actual failure triggering order, avoiding any wasted reservations. The allocation state machine 140 ensures that the timing of address allocation is deterministic and orderly in scenarios where multiple DUTs fail simultaneously.

[0085] The allocation state machine 140 in this embodiment can be implemented using a finite state machine (FSM). The state register stores the current state, and the combinational logic calculates the next state and output signals (allocation enable, regeneration enable) based on the current state and input signals (failure trigger, linked list state). The operating clock of the state machine is synchronized with the master clock of the ATE test to ensure that address allocation and test vector scheduling are synchronized.

[0086] Please continue to refer to this. Figure 4 In at least one possible implementation, the failure data storage control circuit further includes: The channel control module 300 is connected to the IO channel and is used to determine the valid channel and the idle channel according to the IO channel's mounting status, and to shut down the idle channel through hardware. The hardware shutdown includes setting the idle channel to a high impedance state and disabling the write enable signal and the write clock signal.

[0087] In the FPGA, the channel control module 300 of this embodiment can achieve high-impedance state setting by configuring the tri-state control register in the IOB (Input / OutputBlock), and cut off the write clock by using the clock gating cell 340. All control logic is completed during the test initialization phase and does not affect the real-time performance during the test.

[0088] Please refer to Figure 7 In at least one possible implementation, the channel control module 300 specifically includes: The channel scan register array 310 is used to latch the mounting status bits of the chip under test for each IO channel; The mask generation logic unit 320 is connected to the output of the channel scanning register array and is used to output the valid channel mask and the idle channel mask according to the mounting status bit. The three-state control drive unit 330 is connected to the idle channel mask output terminal of the mask generation logic unit and is used to put the idle channel into a high-impedance state. The clock gating unit 340 is connected to the idle channel mask output terminal of the mask generation logic unit and is used to cut off the enable and write clock supply of the idle channel.

[0089] During parallel testing, the channel scan register array 310 latches the DUT mounting status of each IO channel during system initialization. Each channel corresponds to a status bit; for example, 1 indicates that a DUT is mounted, and 0 indicates that it is idle. The mask generation logic unit 320 generates two masks based on these status bits: a valid channel mask (the set of channels with DUTs mounted) and an idle channel mask (the set of channels without DUTs mounted).

[0090] The tri-state control drive unit 330 receives the idle channel mask and sets the corresponding channel's IO driver to a high-impedance state. The clock gating unit 340 receives the idle channel mask and cuts off the write clock supply to the corresponding channel.

[0091] The channel scanning register array 310 in this embodiment can be implemented using a set of D flip-flops, each flip-flop corresponding to an IO channel; the mask generation logic unit 320 can be implemented using a set of MUX combinational logic, directly generating a mask signal based on the output of the register array; the tri-state control drive unit 330 and the clock gating unit 340 are respectively connected to the tri-state control terminal of the IOB and the clock distribution network.

[0092] Please refer to Figure 8 In at least one possible implementation, the failure data processing module 200 specifically includes: The failure data writing unit 210 is used to obtain the storage area allocated to the chip under test by the storage address allocation module, and write the failure data of the current chip under test into that storage area; and / or The failure data reading unit 220 is used to obtain the failure data storage range of the target chip under test from a preset address mapping table of the chip under test according to the reading instruction issued by the host computer, and read the failure data of the target chip under test; and / or The failure data erasure unit 230 is connected to the output end of the address mapping table. It is used to obtain the failure data storage range of the target chip from the preset chip under test address mapping table according to the erasure command issued by the host computer, generate the starting address and length of the area to be erased, and erase the failure data in the area to be erased.

[0093] The address mapping table is a data structure that stores the mapping relationship between DUT numbers and physical addresses, and it is stored in the on-chip BRAM of the main control module (FPGA). Each DUT corresponds to one address mapping table record, which includes: DUT number, storage start address, allocated range size, and occupancy status.

[0094] When the DUT fails, the failure data writing unit obtains the storage range allocated to the DUT from the storage address allocation module and writes data such as the failure address, failure IO bit combination, and failure period into the range.

[0095] The failure data reading unit responds to the read command from the host computer, directly locates the storage base address of the target DUT through the address mapping table, and initiates targeted continuous reading without having to traverse the entire DFM.

[0096] The failed data erasure unit responds to the erase command from the host computer, locates the storage area of ​​the target DUT through the address mapping table, generates the starting address and length of the area to be erased, and performs targeted erasure.

[0097] In this embodiment, the address mapping table can be stored in the on-chip BRAM of the FPGA main control module, supporting lookup within one clock cycle. The failure data writing unit 210 and the failure data reading unit 220 control the read and write timing of the DFM storage module through a state machine. The failure data erasure unit 230 sends an erase command to the DFM storage module, and the erasure operation is completed internally by the DFM storage module.

[0098] Please continue to refer to this. Figure 8 In at least one possible implementation, the failure data processing module 200 further includes: The data frame assembly unit 240 has its input end connected to the IO channel and is used to encapsulate the failure address, failure IO bit combination, and failure period of the chip under test into a standardized data frame according to a preset frame format. The data bus interface unit 250 is used to connect to the address input port of the storage module via the address bus, and / or to the read / write instruction output port of the main control module via the control bus.

[0099] During parallel testing, the data frame assembly unit 240 encapsulates the raw failure data (failure address, failure I / O bit combination, failure period) output from the I / O channel into standardized data frames according to a unified frame format. The standardized data frames have fixed headers, data bodies, and trailers, facilitating subsequent storage, retrieval, and parsing.

[0100] The data bus interface unit 250 allows data to be transferred directly between the storage module and the cache without CPU intervention, which greatly improves data transfer efficiency.

[0101] The data frame assembly unit 240 in this embodiment can be implemented using a set of registers and combinational logic to concatenate input data into a complete frame according to a preset frame format. The data bus interface unit 250 can be implemented using a DMA controller, including a source address register, a destination address register, a transmission length counter, and a state machine.

[0102] Compared with the prior art, the failure data storage control circuit of the present application embodiment has at least the following beneficial effects: Real-time allocation during test runs to adapt to unpredictable failure distributions: Unlike existing technologies that configure addresses once before testing, this application's embodiment allocates addresses in real time according to the failure triggering order during test operation, which can closely follow the actual failure distribution without needing to know the number of DUTs and the failure depth.

[0103] Automatic regeneration when address space is exhausted improves storage utilization. When all address ranges have been allocated, this embodiment of the application regenerates new space by performing a binary search operation on the allocated ranges, thereby achieving a DFM storage space utilization rate that is close to the actual total amount of failed data.

[0104] Displacement operations enable nanosecond-level address calculations: By using the (Start+End)>>1 shift operation to calculate the midpoint address, nanosecond-level address regeneration response can be achieved in an FPGA with only a single clock cycle.

[0105] Triple physical layer shutdown at the source eliminates invalid data: By performing a triple physical layer shutdown on the idle channel—high impedance, write enable cut-off, and write clock cut-off—invalid padding data is eliminated from the source of data generation.

[0106] Direct addressing eliminates the overhead of full traversal: By directly locating the base address of the target DUT using an address mapping table, targeted reading and erasing are achieved.

[0107] This application also provides a failed data storage device, which includes the failed data storage control circuit described in any of the foregoing embodiments.

[0108] This application also provides a failed data storage device, including a processing module, which is used to execute the steps in the failed data storage control method described in any of the foregoing embodiments.

[0109] This application also provides a parallel chip testing system, including the failure data storage device described in any of the foregoing embodiments. This parallel chip testing system can be applied to parallel testing scenarios such as aging testing, wafer testing, and finished product testing of memory chips.

[0110] This application also provides an automated chip testing device, including a processor and a memory. The memory is coupled to the processor and stores computer program code, which includes computer instructions. When the processor reads the computer instructions from the memory, the computer executes steps in the failure data storage control method or the chip parallel testing method described in the foregoing embodiments. This automated chip testing device can be an ATE (Automatic Test Equipment) machine, including an FPGA main control module, a DFM (Digital Function Meter) storage module, I / O channels, and a host computer interface.

[0111] This application also provides a computer program product, which includes computer program code. When the computer program code is run on a computer, it causes the computer to perform the steps in the failure data storage control method or the chip parallel testing method described in the foregoing embodiments.

[0112] The following uses an 8GB deep DFM as an example to describe in detail the implementation process of the failure data storage control method of this application embodiment.

[0113] This example is based on an ATE hardware platform equipped with an 8GB DFM storage module, an FPGA main control module, m-channel IO units, and n-station parallel testing, which fully implements the entire process of failure data capture, binary address allocation, continuous space writing, targeted reading, and on-demand erasure. The details are as follows.

[0114] System initialization and channel configuration: The host computer configures the test items, test vectors, socket files, and DUT Map files, and sends them to the FPGA main control module. The FPGA main control module starts the channel control module 300 to scan all channels from IO1 to IOm, identifying valid DUT channels and idle NULL channels. The channel control module 300 performs hardware shutdown on idle IO channels: setting the idle channel to a high-impedance state, disabling the write enable signal, and cutting off the write path and clock enable from the idle channel to the DFM memory module, filtering out invalid data writes at the source and avoiding space waste.

[0115] Can be initialized using a range linked list: A range-linked list can be initialized to contain a range: [0x000000000, 0x1FFFFFFFF], with a size of 8GB. This range corresponds to the entire physical address space of the DFM storage module.

[0116] Test execution and address allocation: The FPGA main control module drives the effective IO channels to apply test stimuli to DUT1-DUTn in parallel according to the test vector timing sequence, collects the DUT output response and compares it with the expected value; when the DUT has at least 1 bit output value that is inconsistent with the expected value, it is determined to be a failed DUT and triggers the DFM storage request; the effective channels output information such as the failure address, failure IO bit combination, and failure period, while the idle channels remain closed and have no data output.

[0117] The first failed DUT (DUT1): There is an allocatable storage range [0, 8GB] in the available range linked list. The available range allocation unit 120 retrieves this storage range from the linked list and allocates it to DUT1. DUT1 writes the failed data into the [0, 8GB] range. At this point, the available range linked list becomes empty {}.

[0118] The second failed DUT (DUT2): The available range list is empty. The available range regeneration unit 130 initiates a binary search operation, performing a binary search on the storage range [0, 8GB] already allocated to DUT1: The midpoint Mid is calculated as (0 + 8GB) >> 1 = 4GB.

[0119] The [0, 4GB] range is retained for DUT1, and the [4GB, 8GB] range is added back to the available range list as a new available storage range, making the list {[4GB, 8GB]}. The available range allocation unit 120 then retrieves the [4GB, 8GB] range from the available range list and allocates it to DUT2.

[0120] The third failed DUT (DUT3): The available range list is empty again. The available range regeneration unit 130 performs a binary search on the allocated DUT1 storage range [0, 4GB] and DUT2 storage range [4GB, 8GB] respectively: The [0, 4GB] → midpoint 2GB → [0, 2GB] of DUT1 is reserved for DUT1, and [2GB, 4GB] is backfilled into the available interval linked list. The [4GB, 8GB] → midpoint 6GB → [4GB, 6GB] interval of DUT2 is reserved for DUT2, and [6GB, 8GB] is backfilled into the available interval linked list; The available range linked list becomes {[2GB, 4GB], [6GB, 8GB]}. The range allocation unit 120 can be used to retrieve [2GB, 4GB] and allocate it to DUT3.

[0121] The above process continues iteratively, generating new available storage regions after each round of binary search. The system continuously executes the cycle of "allocation → exhaustion → binary search regeneration → reallocation" until all failed DUTs obtain storage regions. Each failed DUT occupies a contiguous physical storage region, without overwriting or interfering with each other.

[0122] Address mapping table maintenance: The on-chip BRAM cache address mapping table of the FPGA main control module records the number, storage start address, range size and occupancy status of each DUT, supporting fast addressing by the host computer.

[0123] Targeted reading and erasing: The host computer issues a read command specifying the DUT number; The FPGA main control module queries the address mapping table to directly obtain the starting address of the target DUT's storage; The DFM storage module reads all invalid data continuously from this starting address, without needing to traverse the entire data or filter it line by line. The host computer parses the data and outputs information such as the number of failures, the distribution of failed I / Os, and the failure addresses. After the test is completed, it supports erasing the corresponding storage area by DUT granularity or erasing the entire chip, and quickly proceeding to the next round of testing.

[0124] The failure data storage control method, chip parallel testing method, failure data storage control circuit, failure data storage device, chip parallel testing system, chip automated testing equipment, and computer program product provided in this application can be widely applied to parallel testing scenarios such as aging testing, wafer testing, and finished product testing of memory chips. Its core mechanism—real-time allocation during test operation and regeneration allocation upon exhaustion—can adapt to unpredictable non-uniform failure distributions, significantly improving DFM storage density and read efficiency.

[0125] In the parallel testing scenario of ATE (Automatic Test Equipment), this application's embodiments systematically eliminate invalid data writing from the source of data generation, and achieve independent continuous storage and dynamic address allocation at the DUT (Data Under Test) level. This significantly improves the read / write efficiency of invalid data while increasing storage space utilization. It can be directly integrated into the FPGA main control module of existing ATE equipment as the core logic of the DFM (Data Flow Metering) storage controller, achieving performance improvements without modifying the ATE hardware architecture.

[0126] Those skilled in the art will recognize that the functions described in the embodiments of this application in one or more of the above examples can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0127] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the appended claims.

Claims

1. A method for controlling the storage of failed data, applied to an automated chip testing device having a storage module and a main control module, characterized in that, The method for controlling the storage of failed data includes: During the test, a contiguous storage range is obtained from the preset failure data storage address and allocated to the currently failed chip under test. When the storage range is fully allocated, at least one new allocable storage range is obtained from all or part of the allocated storage ranges and allocated to the currently or subsequently failed chip under test. Access the failure data storage area allocated to the chip under test and process the failure data of the chip under test.

2. The method for controlling the storage of failed data according to claim 1, characterized in that, Obtaining at least one new allocatable storage region from all or part of the already allocated storage regions specifically includes: In response to the need to allocate storage space for a failed chip under test, the system queries whether the preset available space list is empty. If it is, the system performs a reallocation operation on some or all of the storage spaces currently allocated to each chip under test to obtain the new available storage space. The available space list is used to store the currently available storage space. The new allocable storage range is then backfilled into the available range linked list.

3. The method for controlling the storage of failed data according to claim 2, characterized in that, The initially allocatable storage range stored in the available range linked list is the address of all preset failed data storage; and / or, the reallocation operation is set as a binary search operation.

4. The method for controlling the storage of failed data according to claim 3, characterized in that, The binary search operation specifically includes: Calculate the midpoint address of at least one currently allocated memory region; Using the midpoint address as the starting address of the new available range, a new allocatable storage range is obtained.

5. The method for controlling the storage of failed data according to claim 2, characterized in that, After checking whether the preset available range linked list is empty, the following steps are also included: In response to the query finding that the available interval linked list is not empty, an allocatable storage interval is retrieved from the preset available interval linked list and allocated to the currently failed chip under test according to the failure triggering order of the tested chips.

6. The method for controlling the storage of failed data according to any one of claims 1-5, characterized in that, The access to the failure data storage area allocated to the chip under test, and the processing of the failure data of the chip under test specifically include: Obtain the memory space allocated to the chip under test, and write the failure data of the chip under test into that memory space.

7. The method for controlling the storage of failed data according to any one of claims 1-5, characterized in that, The process of accessing the failure data storage area allocated to the chip under test and processing the failure data of the chip under test specifically includes: According to the read command issued by the host computer, the failure data storage range of the target chip under test is obtained from the preset address mapping table of the chip under test, and the failure data of the target chip under test is read.

8. The method for controlling the storage of failed data according to any one of claims 1-5, characterized in that, The access to the failure data storage area allocated to the chip under test, and the processing of the failure data of the chip under test specifically include: According to the erase command issued by the host computer, the failure data storage range of the target chip is obtained from the preset address mapping table of the chip under test, the starting address and length of the area to be erased are generated, and the failure data in the area to be erased is erased.

9. The method for controlling the storage of failed data according to claim 7, characterized in that, The process of accessing the failure data storage area allocated to the chip under test and processing the failure data of the chip under test further includes: The failure data generated by each chip under test is encapsulated into standardized data frames according to a preset frame format. The failure data includes at least the failure address, failure I / O bit combination, and failure period; and / or The storage module is accessed via a data bus, the address input port of the storage module is connected via an address bus, and / or the read / write instruction output port of the main control module is connected via a control bus.

10. The method for controlling the storage of failed data according to claim 2, characterized in that, The preset available interval linked list is stored in the main control module.

11. The method for controlling the storage of failed data according to any one of claims 1-5, characterized in that, The method for controlling the storage of failed data also includes: Analyze the chip-on-demand status of each IO channel of the main control module to determine the valid and idle channels; Send a hardware shutdown signal, which is used to set the drive output of the idle channel to a high impedance state and cut off its connection to the write enable signal and clock enable signal of the memory module.

12. A parallel chip testing method, applied to automated chip testing equipment, characterized in that, The chip parallel testing method includes the steps of the failure data storage control method as described in any one of claims 1-11.

13. A failed data storage device, characterized in that, It includes a processing module, which is used to perform the steps in the failure data storage control method as described in any one of claims 1-11.

14. A parallel chip testing system, characterized in that, It includes the failure data storage device as described in claim 13.

15. An automated chip testing device, characterized in that, The device includes a processor and a memory coupled to the processor. The memory is used to store computer program code, which includes computer instructions. The processor reads the computer instructions from the memory to cause the processor to perform the steps in the failure data storage control method as described in any one of claims 1-11 or the chip parallel testing method as described in claim 12.

16. A computer program product, characterized in that, The computer program product includes: computer program code, which, when run on a computer, causes the computer to perform the steps in the failure data storage control method as described in any one of claims 1-11 or the chip parallel testing method as described in claim 12.

Images