Row hammer test method of storage device, computer device, storage medium and program product

Abstract

The application relates to the technical field of memory reliability test, and specifically discloses a row hammer test method of a memory device, computer equipment, a storage medium and a program product. The method comprises the following steps: setting an initial knocking strength parameter, wherein the knocking strength parameter at least comprises a total number of row activation knocks; generating a row hammer test excitation sequence according to the current total number of row activation knocks, and applying the row hammer test excitation sequence to an attack row of a tested memory device; obtaining a feedback result representing whether a bit flip occurs according to a data state of a victim row in the tested memory device; adjusting the total number of row activation knocks by a preset adjustment step according to the feedback result, and returning to the step of applying the row hammer test excitation sequence to the attack row of the tested memory device until the total number of row activation knocks converges to a target row refresh critical trigger interval; and performing a steady-state randomization row hammer test based on the converged total number of row activation knocks, and outputting a quantitative index for evaluating row hammer reliability. Thus, the false pass and missed detection problems of the traditional test are solved.

Description

Technical Field

[0001] This application relates to the field of memory reliability testing technology, and in particular to a hammer test method for memory devices, computer equipment, storage media, and program products. Background Technology

[0002] To address the data flipping issue caused by the row hammer effect in DRAM, the JEDEC standard integrates a TRR (Target Row Refresh) hardware protection mechanism within the DDR5 DRAM chip. This hardware mechanism mainly consists of a built-in row access counter, a TRR trigger statistics counter, an on-chip threshold comparator, and an automatic refresh execution unit for the affected rows. Its working principle is as follows: when the system continuously performs high-frequency activation knocking operations on the same attacking row, the on-chip counter continuously accumulates the number of accesses. Once the count reaches the DRAM's built-in private trigger threshold, the hardware will automatically perform special supplementary refresh operations on the adjacent affected rows to the left and right. By compensating for leakage charge in the storage capacitors and suppressing inter-row charge crosstalk, it avoids bit flipping errors caused by the row hammer effect.

[0003] However, the core TRR control logic of major storage vendors is a closed, black-box proprietary technology. The JEDEC standard only defines the basic functional framework of TRR, without uniformly specifying the TRR trigger threshold, counting sampling rules, refresh execution timing, count clearing logic, and bypass protection mechanisms. Existing storage chips do not provide external interfaces for reading, writing, and controlling the TRR counter and threshold register, making it impossible for current testing equipment to read the TRR status, modify the threshold, and control the count.

[0004] Currently, mainstream row-based hammer testing solutions in the industry generally adopt standardized test patterns with a fixed number of cycles. Stress testing is conducted through a single cycle of alternating taps on adjacent attack rows. This type of solution can only mechanically issue a fixed number of row activation commands. When the fixed number of taps triggers the on-chip TRR protection mechanism, the hardware automatically completes the refresh and error correction of the victim row. The test equipment determines that the test is qualified if no bit flips are detected, which easily generates a large number of false pass judgments. At the same time, the fixed periodic tap sequence is easily captured by the TRR counting logic and continuously triggers the protection refresh, making it difficult to approach the TRR critical trigger range and unable to effectively reproduce various hardware vulnerabilities that can bypass TRR protection. Summary of the Invention

[0005] Therefore, it is necessary to provide a hammer test method, computer equipment, storage medium, and program product for storage devices to address the above problems.

[0006] According to a first aspect of the embodiments of this application, a method for testing the line hammer of a storage device is provided, comprising: Set initial tapping intensity parameters, which include at least the total number of row activation taps in a single round of testing; A row hammer test stimulus sequence is generated based on the current total number of row activation knocks and applied to the attack row of the storage device under test; Based on the data status of the affected row in the tested storage device, obtain a feedback result indicating whether a bit flip has occurred; Based on the feedback results, the total number of row activation taps is adjusted by a preset adjustment step size, and the process returns to the step of applying the attack row to the tested storage device until the total number of row activation taps converges to the target row refresh critical trigger interval. Based on the total number of row activations after convergence, a steady-state randomized row hammer test is performed, and a quantitative index for evaluating the reliability of the row hammer is output.

[0007] In one embodiment, the step of adjusting the total number of row activation taps by a preset adjustment step size based on the feedback result includes: If a bit flip is detected in the current round of testing, the total number of row activation taps in the next round of testing is reduced by a preset adjustment step size; If no bit flip is detected in the current round of testing, the total number of row activation taps in the next round of testing is increased by a preset adjustment step size.

[0008] In one embodiment, the target row refresh critical trigger interval is defined by a critical trigger threshold; The critical trigger threshold satisfies the following formula: in, The critical trigger threshold is used to determine the number of row activation taps required to trigger a target row refresh action. The probability that a target row refresh action is triggered inside the storage device when the total number of row activation taps is H; The target row refresh critical trigger interval is: , The value range is 1 to 10.

[0009] In one embodiment, the convergence of the total number of row activation taps to the target row refresh critical trigger interval includes: the total number of row activation taps remains within the target row refresh critical trigger interval in multiple consecutive iterations.

[0010] In one embodiment, in the steady-state randomized hammer test, the hammer test excitation sequence is a dynamic aperiodic sequence; the method for generating the dynamic aperiodic sequence includes any one or more of the following: Randomly insert idle waiting windows into the basic sequence of alternating hits in adjacent attack lines; Randomly adjust the length of the striking segment in a single round of testing; Randomly change the typing order between the attack lines; Dynamically switch the attack line combination involved in the tapping.

[0011] In one embodiment, the quantification metrics include target row refresh shielding efficiency, row hammer test effectiveness, and target row refresh protection robustness. The target row refresh masking efficiency is expressed as: in, To improve the filtering efficiency of the target row. and These represent the total number of bit flips and the total number of hits during the steady-state randomized row hammer test, respectively. The validity of the hammer test is expressed as follows: in, To verify the validity of the hammer test; The robustness of the target row refresh protection is represented as follows: in, Refresh the protection robustness for the target row. This refers to the critical trigger threshold. The number of hits during the first bit flip is detected during the steady-state randomized hammer test.

[0012] In one embodiment, the line hammer test method for the storage device further includes: For each iteration, record the total number of row activation taps and the corresponding bit flip observation samples; The target row refresh trigger probability function is fitted based on multi-round bit-flipping samples, and the critical trigger threshold is updated.

[0013] According to a second aspect of the embodiments of this application, a computer device is provided, comprising: At least one processor; And a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the hammer test method for the memory device as described above.

[0014] According to a third aspect of the embodiments of this application, a computer-readable storage medium is provided, on which a computer program is stored, wherein the computer program, when executed by a processor, implements the hammer test method of the storage device as described above.

[0015] According to a fourth aspect of the embodiments of this application, a computer program product is provided, including a computer program that, when executed by a processor, implements the hammer test method for a storage device as described above.

[0016] The row hammer test method for storage devices provided in this application generates a row hammer test stimulus sequence based on an initially set total number of row activation knocks and applies it to the attack row of the storage device under test. Then, based on the bit flipping situation of the victim row in the north-side storage device, the total number of activation knocks is adjusted with a preset adjustment step size and the process is repeated until the total number of row activation knocks converges to the target row refresh critical trigger interval. Finally, a steady-state randomization test is performed based on the converged knock count and a quantitative index is output. That is, by using the directly observable physical phenomenon of bit flipping as a feedback signal, the total number of row activation knocks is automatically driven to approach and stabilize within the critical trigger range of TRR. Since the above method uses the actual data flipping state of the affected row as the basis for regulation, rather than relying on any manufacturer's proprietary TRR register information, it can adapt to memory chips of different manufacturers, different processes, and different capacities. When the total number of knocks converges to the critical trigger range, the steady-state test continues to apply pressure at the protection boundary state of "about to trigger, critical trigger, partial trigger". It will not miss the original defect due to the low stress, nor will it produce a false pass judgment due to the high stress triggering the complete shielding of TRR. It fundamentally solves the conflict between the traditional fixed sequence test stress and the TRR hardware protection mechanism of "either insufficient or excessive". Attached Figure Description

[0017] Figure 1 A flowchart illustrating a method for performing a line hammer test on a storage device according to an embodiment of this application; Figure 2 A flowchart of step S700 in a method for testing a storage device according to an embodiment of this application; Figure 3 A partial flowchart of a hammer test method for a storage device provided in another embodiment of this application. Detailed Implementation

[0018] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0019] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0020] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0022] Traditional hammer testing methods mainly suffer from the following three technical problems: First, there's the issue of false pass / fail judgment. Existing testing solutions cannot detect, characterize, or control TRR triggering behavior. During testing, the specific triggering timing, probability, and true triggering threshold of TRR cannot be identified. When a fixed number of hits triggers the on-chip TRR protection mechanism, the hardware automatically completes the faulty row refresh and error correction. The testing equipment detects no bit flips and judges the test as pass. This result only proves that the TRR hardware protection is effective; it cannot truly reflect the DRAM chip's inherent resistance to row hammer interference, easily generating a large number of false pass / fail judgments and causing defective chips to go undetected.

[0023] Second, there is the issue of testing blind spots. Fixed periodic tap sequences are easily captured by the TRR counting logic and continuously trigger protection refreshes. It is impossible to adaptively adjust the tap interval, cycle frequency, and idle silence window, making it difficult to approach the critical trigger range of TRR. Therefore, it is impossible to effectively reproduce various new hardware vulnerabilities that can bypass TRR protection, resulting in serious testing blind spots.

[0024] Third, there is a lack of quantitative assessment. Traditional tests only output binary pass / fail results indicating whether bit flips have occurred, lacking quantitative assessment indicators such as TRR trigger threshold, protection margin, protection efficiency, and vulnerability trigger probability. This makes it impossible to provide effective data support for DRAM process optimization, server RAS firmware tuning, and memory refresh strategy optimization.

[0025] Furthermore, the TRR counting rules and trigger thresholds of memory chips from different manufacturers vary significantly, resulting in extremely poor adaptability of fixed test sequences. Changing chip models requires manual iterative debugging of test parameters, leading to long test development cycles and weak versatility.

[0026] To address the aforementioned issues, this application provides a hammer test method for storage devices, a computer device, a computer-readable storage medium, and a computer program product.

[0027] Reference Figure 1 In one embodiment, a hammer test method for a storage device is provided, comprising the following steps: Step S100: Set initial tapping intensity parameters, wherein the tapping intensity parameters include at least the total number of row activation taps in a single round of testing.

[0028] At the start of the test, initial tapping intensity parameters need to be set. These tapping intensity parameters are a set of parameters characterizing the intensity of the row hammer test stimulus, and include at least the total number of row activation taps in a single round of testing. The total number of row activation taps H refers to the total number of loops in which the ACT activation command is executed on the attack row in a single round of testing, i.e., the number of times the ACT-PRE loop tapping sequence is issued.

[0029] In an optional implementation, the initial impact intensity parameters also include an initial impact frequency and an initial idle window. The initial impact frequency controls the execution speed of the hammer strikes, and the initial idle window manages the waiting time between adjacent impact operations. In another optional implementation, before the test begins, iterative convergence criteria, maximum iteration limits, and quantitative report output specifications need to be pre-configured to determine reasonable parameter boundaries for the entire closed-loop test process.

[0030] Step S300: Generate a row hammer test stimulus sequence based on the current total number of row activation knocks, and apply it to the attack row of the storage device under test.

[0031] The attack row is the target physical row in the storage device under test (DUT) that undergoes repeated row activation and precharge operations. In an optional implementation, the row hammer test stimulus sequence is dynamically generated by a row hammer pattern generator. This generator supports selecting the attack row to be stressed as needed, configuring the total number of row hammer strikes per round, adjusting the row hammer execution frequency, controlling the idle refresh window duration, and can also generate randomized access sequences that disrupt the inherent periodic patterns (for subsequent steady-state randomized row hammer tests). The generated row hammer test stimulus sequence can be sent to the DUT.

[0032] Specifically, the raw data for the hammer test stimulus is a pattern composed of 0 and 1 bits, generated by the hammer pattern generator. This pattern includes parameters such as the number of attack row loop hits, the ACT hit timing, the length of the inter-row idle window, and the random perturbation sequence. In each iteration, the hammer pattern generator can dynamically adjust these parameters based on the feedback from the previous test to precisely and stably control the overall hammer hit intensity within the TRR critical trigger range. Inside, The iteration process is described below. The iterative method of this invention is based on the feedback result of the bit flipping of the victim row. Iteratively update the total number of active taps for each row. ACT keying sequence Inline free window length and random perturbation sequences Generate a new round of hammer test stimulus sequence until Converge to the target row refresh critical trigger interval.

[0033] Step S500: Based on the data status of the affected row in the tested storage device, obtain a feedback result indicating whether a bit flip has occurred.

[0034] Based on the data status of the victim row in the tested storage device, feedback results indicating whether bit flips have occurred can be obtained. The victim row is the target physical row physically adjacent to the attack row (usually left and right adjacent rows) used to observe data flips caused by inter-row crosstalk. In an optional implementation, the feedback result is obtained by completely reading the CacheLine data of all victim rows, collecting CE-correctable bit flip events using the ECC register, and counting the total number of bit flips in this round of testing.

[0035] Step S700: Based on the feedback result, adjust the total number of row activation taps with a preset adjustment step size, and return to the step of applying the attack row to the tested storage device until the total number of row activation taps converges to the target row refresh critical trigger interval.

[0036] In this embodiment, the preset adjustment step size is a fixed unit step size. In an optional implementation, the increase or decrease in the total number of row activation taps in a single iteration is 1. If a bit flip is detected, it means that the current tap intensity has exceeded the TRR critical region, and the total number of row activation taps in the next round of testing needs to be reduced; if no bit flip is detected, it means that the current tap intensity is below the TRR critical region, and the total number of row activation taps in the next round of testing needs to be increased. In this way, through the binary (with / without bit flip) feedback of each round of test results, the tap intensity is driven to continuously approach the critical range.

[0037] Then, the process returns to the step of applying the attack line to the storage device under test. That is, the row hammer test stimulus sequence is regenerated using the adjusted total number of row activation knocks and pressure is applied again to enter the next iteration. This process is repeated until the total number of row activation knocks converges to the target row refresh critical trigger interval.

[0038] Step S900: Based on the total number of row activation taps after convergence, perform a steady-state randomized row hammer test and output a quantitative index for evaluating the reliability of the row hammer.

[0039] Once the total number of row activation knocks converges to the critical trigger interval for the target row refresh, the steady-state testing phase can begin. This involves performing a steady-state randomized row hammer test based on the converged total number of row activation knocks. The steady-state randomized row hammer test refers to a test process that continuously applies pressure within the critical trigger interval. It can employ methods such as inserting random idle waiting windows and configuring aperiodic knock sequences to circumvent the TRR periodicity prediction mechanism. This effectively exposes the inherent row hammer charge leakage and crosstalk defects of the DRAM memory cell itself, accurately reproduces various TRR bypass vulnerabilities, and significantly improves the probability of vulnerability detection.

[0040] Finally, quantitative metrics for evaluating row refresh reliability can be output. In this embodiment, these quantitative metrics include, but are not limited to, standardized evaluation parameters such as target row refresh shielding efficiency, row refresh test effectiveness, and target row refresh protection robustness. These quantitative metrics can be output to a test report, which can be used for DRAM chip reliability grading and defect screening in production lines, as well as providing quantitative data support for DRAM manufacturers' memory process iteration and server-side firmware optimization.

[0041] The row hammer test method for storage devices provided in this application generates a row hammer test stimulus sequence based on an initially set total number of row activation knocks and applies it to the attack row of the storage device under test. Then, based on the bit flipping situation of the victim row in the north-side storage device, the total number of activation knocks is adjusted with a preset adjustment step size and the process is repeated until the total number of row activation knocks converges to the target row refresh critical trigger interval. Finally, a steady-state randomization test is performed based on the converged knock count and a quantitative index is output. That is, by using the directly observable physical phenomenon of bit flipping as a feedback signal, the total number of row activation knocks is automatically driven to approach and stabilize within the critical trigger range of TRR. Since the above method uses the actual data flipping state of the affected row as the basis for regulation, rather than relying on any manufacturer's proprietary TRR register information, it can adapt to memory chips of different manufacturers, different processes, and different capacities. When the total number of knocks converges to the critical trigger range, the steady-state test continues to apply pressure at the protection boundary state of "about to trigger, critical trigger, partial trigger". It will not miss the original defect due to the low stress, nor will it produce a false pass judgment due to the high stress triggering the complete shielding of TRR. It fundamentally solves the natural conflict between the traditional fixed sequence test stress and the TRR hardware protection mechanism of "either insufficient or excessive".

[0042] Reference Figure 2 In one embodiment, step S700, namely the step of adjusting the total number of row activation taps with a preset adjustment step size based on the feedback result, may further include: Step S710: If a bit flip is detected in the current round of testing, the total number of row activation taps in the next round of testing is reduced by a preset adjustment step size. Step S720: If no bit flip is detected in the current round of testing, increase the total number of row activation taps in the next round of testing according to the preset adjustment step size.

[0043] In this application, bit flip events are a key observation indicator characterizing whether TRR protection has been triggered. In row hammer testing, the relationship between bit flip occurrence and TRR hardware triggering state is not a simple linear correspondence. Specifically: when the total number of row activation knocks is far below the critical trigger threshold, TRR hardware protection has not yet been activated, but the knock stress itself is insufficient to generate significant charge crosstalk, so the bit flip phenomenon is slight or non-existent; when the number of knocks approaches and just exceeds the critical trigger threshold, the TRR protection mechanism is in a boundary state between partial triggering and critical triggering. At this time, the hardware refresh has not yet been able to completely suppress inter-row charge crosstalk, and the charge in the storage capacitor of the victim row leaks due to coupling effects, and the bit flip probability reaches its peak. This is precisely the critical test interval that the closed-loop iteration of this application aims to maintain stably; when the number of knocks significantly exceeds the critical trigger threshold, the TRR hardware has been continuously and fully triggered, and the hardware automatically performs a special supplementary refresh on the victim row, effectively shielding the charge crosstalk and eliminating bit flips.

[0044] Based on the above principles, in this embodiment, the detection of a bit flip is regarded as an indication signal that the tap intensity is within the critical range (at which point it needs to be adjusted downwards to return to the inside of the critical range), and the absence of a detected bit flip is regarded as an indication signal that the tap intensity is far below or far above the critical range (at which point it needs to be adjusted upwards to approach the critical range). By repeatedly performing the above bidirectional adjustment, the total number of row activation taps can form a reciprocating oscillation near the critical trigger range and gradually converge.

[0045] It should be noted that the bit flip probability in the hammer test exhibits a single-peak variation with the number of hits. Specifically, when the number of hits is far below the threshold, there is insufficient stress and no flip; when it approaches and just exceeds the threshold, the flip probability reaches its peak; and when it significantly exceeds the threshold, there is no flip due to complete shielding by the TRR. In this application, the iteration during the aforementioned convergence phase has a unidirectional motion constraint. Starting with an initial number of hits far below the threshold, it monotonically increases with a fixed step size to approach the critical region. During this process, when no flip is detected, an upward adjustment operation is performed to continuously approach the peak region; when the number of hits just exceeds the threshold and enters or crosses the peak region, a flip is detected, and a downward adjustment operation is performed to revert. Through the alternating oscillations of "no flip → upward adjustment" and "flip → downward adjustment," the number of hits swings back and forth on both sides of the critical peak range and gradually converges. Since the iteration monotonically increases from the initial stage where the number of hits has not exceeded the peak, and the convergence criterion requires the number of hits to remain within the critical range for multiple consecutive rounds, the two states of no detected flip (i.e., insufficient stress before exceeding the peak and exceeding the peak and being completely shielded) will not be confused.

[0046] In one optional implementation, the preset adjustment step size is a fixed unit step size, corresponding to an increase or decrease of 1 in the total number of row activation taps in a single iteration. Using a fixed unit step size can ensure the smoothness and stability of the iteration process, avoiding convergence oscillations caused by an excessively large step size or slow convergence caused by an excessively small step size.

[0047] In one embodiment, the target row refresh critical trigger interval is defined by a critical trigger threshold; The critical trigger threshold satisfies the following formula: in, The critical trigger threshold is a characteristic critical point of the chip's TRR protection mechanism, used to determine the number of row activation taps required to trigger a target row refresh (TRR) action, i.e., how many row taps are needed to activate TRR protection. It is used for row hammer reliability testing and memory controller parameter calibration. The number of taps corresponding to the fastest increase in TRR trigger probability is determined by the x-axis corresponding to the steepest point on the curve relating the number of taps H to the TRR trigger probability. This is the total number of times the Row Hammer is activated. The probability that a target row refresh action is triggered inside the storage device when the total number of row activation taps is H; The target row refresh critical trigger interval is: , The value range is 1 to 10.

[0048] First, the probability function This indicates the total number of active taps in the row. The probability that a Target Row Refresh (TRR) action is triggered within the memory device. It should be noted that TRR triggering is not a deterministic event. With the same number of keystrokes, due to factors such as DRAM internal refresh scheduling, temperature variations, and voltage fluctuations, TRR may be triggered in one round but not in the next. Therefore, using trigger probability to characterize its behavior is more reasonable. Based on this, the critical trigger threshold... Defined as Follow The number of taps corresponding to the maximum value of the derivative when the value changes. In other words, This is the inflection point where the TRR triggering probability abruptly changes from low-probability, occasional triggering to high-probability, frequent triggering; that is, the critical boundary point where TRR begins to trigger on a large scale. The critical triggering threshold... It is the dividing point that distinguishes between the occasional triggering of TRR and the continuous triggering of TRR, and it is also the target that the closed-loop iteration aims to approach.

[0049] The target row refresh critical trigger interval is defined as follows: That is, using the critical trigger threshold Centered on, with The neighborhood range of the boundary offset. The value range is 1 to 10, which is used to flexibly control the width of the critical interval. By stabilizing the total number of row activation taps within this range, the test condition can be kept in the protection boundary state of "about to trigger, critical trigger, partial trigger". It will not completely eliminate bit flips due to continuous TRR refresh, nor will it cause insufficient stress due to too few taps.

[0050] In an optional implementation, The value can be flexibly set according to the manufacturing process, manufacturer characteristics, or test accuracy requirements of the memory device under test. For example, for memory chips with relatively mature manufacturing processes and good consistency in TRR triggering behavior, a smaller value can be used. Values ​​(e.g., 1-3) are used to achieve more precise critical positioning; for scenarios with large process fluctuations or requiring rapid screening, larger values ​​can be used. Values ​​(such as 5~10) can be used to accelerate the convergence speed.

[0051] In one embodiment, the convergence of the total number of row activation taps to the target row refresh critical trigger interval in step S700 includes: the total number of row activation taps remains within the target row refresh critical trigger interval in multiple consecutive iterations.

[0052] During the closed-loop iteration process, the evolution of the total number of row activation taps near the critical trigger interval typically exhibits a gradual approach, oscillation, and eventual stabilization. To objectively determine whether the iteration is complete and whether it is possible to exit the loop and enter the steady-state testing phase, it is necessary to set clear convergence criteria.

[0053] The so-called continuous multi-round iterations usually involve three or more rounds, and the specific number of rounds can be pre-configured according to the test accuracy requirements. For example, after several rounds of iterative adjustments, when the total number of row activation taps has been stable within the critical trigger range for three consecutive rounds, and no longer jumps significantly out of the range due to a single round of adjustment, it indicates that the iteration process has converged.

[0054] It should be noted that convergence determination can also be combined with other auxiliary conditions. In an optional implementation, the convergence determination condition may further include: the target row refresh trigger probability curve obtained by fitting multiple rounds of iterative samples reaches a stable state, i.e. The fitted value no longer changes significantly with the addition of new samples. In another optional implementation, convergence determination may further include: the number of iterations reaching a preset maximum number of iterations. When any of the above conditions are met, the iteration is considered to have converged.

[0055] In one embodiment, in the steady-state randomized hammer test, the hammer test excitation sequence is a dynamic aperiodic sequence; the method for generating the dynamic aperiodic sequence includes any one or more of the following: Randomly insert idle waiting windows into the basic sequence of alternating hits in adjacent attack lines; Randomly adjust the length of the striking segment in a single round of testing; Randomly change the typing order between the attack lines; Dynamically switch the attack line combination involved in the tapping.

[0056] Specifically, in traditional fixed-cycle testing schemes, row hammer testing stimuli typically employ a single-cycle pattern of alternating ABAB strikes on adjacent attack rows. This fixed-cycle striking sequence is highly predictable and easily captured by the on-chip TRR counter logic of the DRAM. The TRR counter can predict the activation time of the next attack row based on the fixed striking rhythm, triggering the protection refresh in advance, thus preventing the test stress from effectively approaching the TRR critical trigger range. Furthermore, the fixed-cycle sequence cannot reproduce various hardware vulnerabilities that can bypass TRR protection, such as TRRespass, variable-rhythm row hammers, and multi-faceted row hammers.

[0057] To address the aforementioned issues, this application introduces a dynamic randomization mechanism in the steady-state testing phase. That is, the hammer test excitation sequence is no longer a fixed periodic sequence, but a dynamic aperiodic sequence, which can be generated through any one or more combinations of the following four methods: The first method involves randomly inserting idle waiting windows into the basic sequence of alternating knocks between adjacent attack lines. Specifically, during the execution of the AB alternating knock sequence, several operation-free intervals (clock cycles) are randomly inserted between certain knock operations. The insertion position and duration of these idle windows are randomly determined without a fixed pattern. The insertion of idle windows can effectively disrupt the DRAM TRR continuous counting logic, preventing the counter from accumulating access counts at a fixed rhythm, thereby weakening the predictive ability of TRR and exposing more inherent defects.

[0058] The second method involves randomly adjusting the tapping segment length in a single round of testing. Specifically, in a basic loop unit, the traditional approach is to tap A and B once each, while this application allows for random adjustment of the number of consecutive taps for each attack line in a single round. For example, the number of consecutive taps for a segment A might be 3, the next segment might be 7, the segment after that might be 2, and so on. This random variation in tapping segment length makes it difficult to establish a stable counting model for the TRR counter.

[0059] The third method involves randomly changing the typing order among the attack lines. Specifically, when more than two attack lines are involved, the typing order is no longer fixed as a fixed rotation of ABC, but is randomly generated in different orders such as ACB, BAC, and CBA. This randomization increases the unpredictability of the test sequence, helping to break TRR's ability to identify fixed access patterns.

[0060] The fourth method involves dynamically switching the attack line combinations involved in the tapping. Specifically, it supports the dynamic switching of multiple adjacent attack line combinations, distributing or concentrating the tapping stress on different attack line combinations during testing. For example, the first segment focuses on attack lines A and B, the next segment dynamically switches to attack lines A and C, and then the next segment switches to B and C. This method is particularly suitable for reproducing TRR bypass vulnerabilities such as the Multiple-Aggressor RowHammer, which uses multiple attack lines to apply pressure simultaneously or alternately, causing the TRR protection mechanism to fail because it cannot respond to interference from multiple directions at the same time.

[0061] The four methods described above can be used individually or in any combination to generate highly randomized and unpredictable hammer test sequences. By using non-periodic random sequences, the predictability of TRR counts can be eliminated, significantly increasing the probability of vulnerability detection and achieving full coverage detection of various TRR bypass vulnerabilities.

[0062] In one embodiment, the quantification metrics include target row refresh shielding efficiency, row hammer test effectiveness, and target row refresh protection robustness.

[0063] The target row refresh masking efficiency is expressed as: in, To improve the filtering efficiency of the target row. and These represent the total number of bit flips and the total number of hits during the steady-state randomized row hammer test, respectively.

[0064] The target row refresh shielding efficiency (TRR) is used to quantitatively evaluate the shielding capability of the TRR hardware protection mechanism against inter-row charge crosstalk. It characterizes the proportion of the total number of hits where no bit flip occurs. A value closer to 1 indicates a stronger shielding capability against charge crosstalk by the TRR hardware, and better resistance to row hammer interference in the memory device. Conversely, a significantly low value indicates a defect in the TRR protection mechanism or insufficient native isolation performance of the DRAM memory array. This indicator can be directly used for reliability grading and defect screening of DRAM chips in the production line.

[0065] The validity of the hammer test is expressed as follows: in, To determine the validity of the hammer test.

[0066] The effectiveness (E) of the horizontal hammer test characterizes the detection efficiency of horizontal hammer defects under the current critical test conditions. Specifically, it represents the proportion of defect samples actually detected out of the total test samples under TRR critical trigger boundary pressure conditions. This metric can be used to compare the native interference immunity of DRAMs from different processes and manufacturers. Higher effectiveness indicates that the test method is more effective in exposing the native horizontal hammer charge leakage and crosstalk interference defects of the DRAM memory cell itself. For process iteration and optimization, this metric can quantify the actual effect of improvement measures.

[0067] The robustness of the target row refresh protection is represented as follows: in, Refresh the protection robustness for the target row. This refers to the critical trigger threshold. The number of hits during the first bit flip is detected during the steady-state randomized hammer test.

[0068] The target line refresh protection robustness R is used to quantitatively evaluate the margin and robustness of the TRR hardware protection mechanism. Specifically, it is the ratio between the critical point at which the TRR protection mechanism begins to take effect on a large scale and the number of knocks that first occur when a bit flip happens. The smaller the value, the more likely the DRAM memory cells will have charge leakage problems before the TRR is triggered on a large scale, resulting in poor native reliability; the larger the value, the higher the TRR protection margin and the better the memory reliability.

[0069] Reference Figure 3 In one embodiment, the line hammer test method for the storage device provided in this embodiment further includes: Step S810: For each iteration, record the total number of row activation taps and the corresponding bit flip observation samples. Step S820: Fit the target row refresh trigger probability function based on multi-round bit flip samples, and update the critical trigger threshold.

[0070] During the closed-loop iteration process, each round of testing generates a set of observation samples, including the total number of current row activation taps. And the corresponding bit flip observation results (whether a bit flip occurred, the number of bit flips, etc.).

[0071] Specifically, after each iteration, the total number of row activation taps and the corresponding bit-flip observation samples for the current round are recorded and stored in the fitting array. As the number of iterations increases, the number of accumulated samples in the array gradually increases, providing a more sufficient data foundation for probability fitting. Based on the accumulated bit-flip observation samples from multiple rounds, the target row refresh trigger probability function can be fitted in real time. That is, the total number of taps activated in different rows. Under the following conditions, the frequency of TRR triggering is statistically analyzed (i.e., in the same or similar situations). The ratio of the number of rounds that triggered TRR to the total number of test rounds (under this value) is used as... The estimated value is... As the sample size increases, this estimate gradually converges to the true probability.

[0072] exist After the function is updated, the critical trigger threshold can be recalculated. That is, repositioning The number of taps corresponding to the maximum value of the derivative. Due to the addition of new observation samples, The shape of the curve may change. It is also dynamically updated, making the estimation of the critical trigger threshold closer and closer to the actual private threshold within the DRAM chip.

[0073] The above process ensures the convergence of the entire closed-loop iteration process. That is, as the number of iterations increases, the estimation accuracy of the critical trigger threshold gradually improves, and the total number of row activation knocks can oscillate around the true critical threshold and eventually stabilize within the critical interval.

[0074] Based on the same inventive concept, in one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the above-described hammer test method for the memory device.

[0075] The computer device includes a processor, memory, and a network interface connected via a system bus. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores various types of data related to the hammer test method for the storage device. The network interface communicates with external terminals via a network connection. When the computer program is executed by the processor, it implements a hammer test method for the storage device.

[0076] Based on the same inventive concept, in one embodiment, a computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the steps of the above-described hammer test method for the storage device.

[0077] Based on the same inventive concept, in one embodiment, a computer program product is also provided, including a computer program that, when executed by a processor, implements the steps of the above-described hammer test method for the storage device.

[0078] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0079] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0080] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for testing the line hammer of a storage device, characterized in that, include: Set initial tapping intensity parameters, which include at least the total number of row activation taps in a single round of testing; A row hammer test stimulus sequence is generated based on the current total number of row activation knocks and applied to the attack row of the storage device under test; Based on the data status of the affected row in the tested storage device, obtain a feedback result indicating whether a bit flip has occurred; Based on the feedback results, the total number of row activation taps is adjusted by a preset adjustment step size, and the process returns to the step of applying the attack row to the tested storage device until the total number of row activation taps converges to the target row refresh critical trigger interval. Based on the total number of row activations after convergence, a steady-state randomized row hammer test is performed, and a quantitative index for evaluating the reliability of the row hammer is output.

2. The method for testing the line hammer of a storage device according to claim 1, characterized in that, The step of adjusting the total number of row activation taps according to the feedback result with a preset adjustment step size includes: If a bit flip is detected in the current round of testing, the total number of row activation taps in the next round of testing is reduced by a preset adjustment step size; If no bit flip is detected in the current round of testing, the total number of row activation taps in the next round of testing is increased by a preset adjustment step size.

3. The method for testing the line hammer of a storage device according to claim 1, characterized in that, The target row refresh critical trigger interval is defined by the critical trigger threshold; The critical trigger threshold satisfies the following formula: in, The critical trigger threshold is used to determine the number of row activation taps required to trigger a target row refresh action. The probability that a target row refresh action is triggered inside the storage device when the total number of row activation taps is H; The target row refresh critical trigger interval is: , The value range is 1 to 10.

4. The method for testing the line hammer of a storage device according to claim 1, characterized in that, The convergence of the total number of row activation taps to the target row refresh critical trigger interval includes: the total number of row activation taps remains within the target row refresh critical trigger interval in multiple consecutive iterations.

5. The method for testing the line hammer of a storage device according to claim 1, characterized in that, In the steady-state randomized moving hammer test, the moving hammer test excitation sequence is a dynamic aperiodic sequence; the method for generating the dynamic aperiodic sequence includes any one or more of the following: Randomly insert idle waiting windows into the basic sequence of alternating hits in adjacent attack lines; Randomly adjust the length of the striking segment in a single round of testing; Randomly change the typing order between the attack lines; Dynamically switch the attack line combination involved in the tapping.

6. The method for testing the line hammer of a storage device according to claim 1, characterized in that, The quantitative indicators include target row refresh shielding efficiency, row hammer test effectiveness, and target row refresh protection robustness. The target row refresh masking efficiency is expressed as: in, To improve the filtering efficiency of the target row. and These represent the total number of bit flips and the total number of hits during the steady-state randomized row hammer test, respectively. The validity of the hammer test is expressed as follows: in, To verify the validity of the hammer test; The robustness of the target row refresh protection is represented as follows: in, Refresh the protection robustness for the target row. This refers to the critical trigger threshold. The number of hits during the first bit flip is detected during the steady-state randomized hammer test.

7. The method for testing the line hammer of a storage device according to claim 3, characterized in that, The hammer test method for the storage device further includes: For each iteration, record the total number of row activation taps and the corresponding bit flip observation samples; The target row refresh trigger probability function is fitted based on multi-round bit-flipping samples, and the critical trigger threshold is updated.

8. A computer device, characterized in that, include: At least one processor; And a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the hammer test method of the memory device as described in any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the hammer test method for the storage device according to any one of claims 1 to 7.

10. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program implements the hammer test method for the storage device according to any one of claims 1 to 7.

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