Multi-lane memory card packet test system and method based on stable pattern table

Abstract

The application belongs to the technical field of multi-channel memory card testing, and specifically discloses a multi-channel memory card grouping test system and method based on a stable mode table, which comprises a central mode management and dispatcher, a shared data generation and distribution module, and multiple test channels; the central mode management and dispatcher obtains the final stable mode and working frequency of each channel; the stable mode table is used to divide the same-frequency test groups, and the channel mask of each same-frequency test group is generated; the shared data generation and distribution module configures the working parameters according to the working frequency, bus mode, bus width, data block parameters and data rhythm of the current same-frequency test group, and distributes the test data matched with the group to the test channels enabled by the current same-frequency test group channel mask. The application can maintain the overall parallel efficiency under normal conditions and keep the uniform data rhythm within the group when the channel capacity is inconsistent.

Description

Technical Field

[0001] This invention relates to the field of multi-channel memory card testing technology, and in particular to a multi-channel memory card group testing system and method based on a stable mode table. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] An SD card is a non-volatile memory card based on semiconductor flash memory technology. UHS-I (Ultra High Speed ​​Phase I) is a common speed specification for the SD card bus interface. UHS-I mode requires conditions to be met in multiple stages, such as initialization, power supply voltage, bus width, clock frequency, tuning, and read / write stability, before it can stably enter the target high-speed mode.

[0004] In a multi-channel unified parallel testing approach, the upper-layer testing program typically pre-sets a unified working mode and frequency based on the testing objectives, and each test channel executes the test according to the same configuration. This approach is suitable for situations where the capabilities and link conditions of the cards under test in each channel are basically the same.

[0005] However, in multi-channel testing scenarios, the capability levels, PCB traces, voltage switching results, and high-speed read / write stability of different SD cards may not be consistent. If all channels are still forced to use the same highest mode, some channels may continue to fail during voltage switching, tuning, or high-speed read / write phases. On the other hand, if the mode is uniformly reduced to ensure compatibility with weaker channels, the stronger channels will not be able to be tested in their actual stable high-speed mode, thus reducing the testing value of the stronger channels. Summary of the Invention

[0006] To address the issue of inconsistent stable operating capabilities among different test channels in multi-channel testing systems using shared clock and test data resources, this invention proposes a multi-channel memory card grouping testing system and method based on a stable mode table. First, the stable UHS mode of each channel is confirmed. When different stable modes or different operating frequencies are detected, dynamic same-frequency grouping is performed, and each same-frequency test group is scheduled sequentially according to a preset priority. This ensures that the multi-channel testing system maintains overall parallel efficiency under normal conditions while maintaining a unified data rhythm within each group even when channel capabilities are inconsistent.

[0007] In some implementations, the following technical solutions are adopted: A multi-channel memory card grouping test system based on a stable mode table includes: a central mode management and scheduler, a shared data generation and distribution module, and multiple test channels; The central mode management and scheduler is configured to control each test channel to perform capability identification and candidate mode verification, thereby obtaining the final stable mode and operating frequency of each channel; write the final stable mode, operating frequency, stage failure code and status of each channel into the stable mode table, and divide the test channels with the same final stable mode and operating frequency into the same frequency test group according to the stable mode table, and generate the channel mask for each same frequency test group. The shared data generation and distribution module is configured to configure its operating parameters according to the operating frequency, bus mode, bus width, data block parameters, and data rhythm of the current same-frequency test group, so that it only distributes test data matching the group to the test channels with the channel mask enabled in the current same-frequency test group.

[0008] As a further embodiment, the central mode management and scheduler includes: The candidate mode verification module is configured to sequentially perform voltage status verification, mode status verification, tuning status verification, and read / write comparison verification on the target test channel under each candidate mode. The stable mode table configuration module is configured to write the corresponding candidate mode and operating frequency into the stable mode table if all stages of verification pass; if any stage of verification fails, the generated stage failure code is written into the stable mode table. The abnormal state marking module is configured to mark the corresponding target test channel as abnormal if there are still verification failures after the candidate mode queue is exhausted, so that it will not participate in the data distribution of the current same frequency test group.

[0009] As a further option, the central mode management and scheduler also includes: The same-frequency group mask generation module is configured to divide test channels with the same final stable mode and operating frequency into same-frequency test groups according to the stable mode table, and generate channel masks for each same-frequency test group. The priority scheduling module is configured to determine the scheduling order of each same-frequency test group according to the working frequency and / or preset mode level from high to low; and to control the channel mask enable of each same-frequency test group according to the scheduling order.

[0010] As a further step, each test channel includes: The SD controller is configured to perform SD card initialization, mode switching, tuning commands, and read / write commands. The mode register is configured to store the current candidate mode, the current operating mode, the final stable mode, and the operating frequency; The voltage status unit is configured to record whether the voltage switching was successful. The Tuning state unit is configured to record whether the tuning passed in the current candidate mode; The read / write comparison unit is configured to verify whether the data link is stable under the current candidate mode; The stable mode output interface is configured to feed back the final stable mode and stage verification results to the stable mode table.

[0011] As a further provision, the stable mode table records at least the number of each test channel, the final stable mode, the operating frequency, the stage failure code, the channel status, the same-frequency test group number, and the same-frequency test group priority.

[0012] As a further option, the stage failure code includes at least one of the following: target mode not supported, abnormal voltage state, mode switching failure, tuning failure, read / write comparison failure, timeout, and no available candidate mode.

[0013] As a further option, the channel mask is determined by the final stable mode, operating frequency, and channel state in the stable mode table; The channel mask is an N-bit enable vector, with each bit corresponding to the enable state of a test channel; N is the number of test channels; the channel mask bits corresponding to abnormal state channels remain invalid.

[0014] In other embodiments, the following technical solutions are adopted: A multi-channel memory card grouping test method based on a stable pattern table includes: Perform UHS candidate mode verification for each test channel, determine the final stable mode and corresponding operating frequency for each test channel based on the verification results, and generate a stable mode table; Based on the stable mode table, test channels with the same final stable mode and operating frequency are divided into same-frequency test groups, corresponding channel masks are generated for each same-frequency test group, and the scheduling priority of each same-frequency test group is determined. Before starting each same-frequency test group, configure the working parameters of the shared data generation and distribution module according to the current same-frequency test group's operating frequency, bus mode, bus width, data block parameters, and data rhythm, so that it only distributes test data matching the group to the test channels with the current same-frequency test group's channel mask enabled.

[0015] As a further solution, it also includes: the test channels in the current same-frequency test group execute tests in parallel, and after receiving the test completion status of all enabled channels in the current same-frequency test group, it switches to the next priority same-frequency test group until all normal test channels have completed the test. For test channels that have not obtained a final stable mode, mark them as abnormal in the stable mode table so that they are not included in the test scheduling of the same frequency test group.

[0016] As a further step, UHS candidate mode verification is performed separately for each test channel, specifically as follows: Control each test channel to complete initialization, and read SD card capability information, controller capability information, and channel historical status; For each test channel, a candidate pattern queue is generated based on the capability identification results, controller configuration, channel history failure records, and test strategy. Select a candidate mode from the candidate mode queue as the current candidate mode, and perform the corresponding voltage status confirmation, mode configuration, bus width configuration and clock frequency configuration. Then, perform voltage status verification, mode status verification, tuning status verification and read / write comparison verification in sequence. If all stages of the verification of the current candidate mode pass, the candidate mode is recorded as the final stable mode of the test channel, and the corresponding operating frequency is written into the stable mode table. If any stage of verification fails, a corresponding stage failure code will be generated. Determine if a next candidate mode exists. If it does, downgrade to the next candidate mode and re-verify. If it does not exist, mark the channel as abnormal and prevent it from participating in the data distribution of the current same-frequency test group.

[0017] Compared with the prior art, the beneficial effects of the present invention are: When a multi-channel SD card has different stable modes or different operating frequencies, this invention uses a stable mode table, a channel mask for the same frequency test group, and priorities to achieve high-speed group priority and low-speed group subsequent group testing, avoiding a few low-speed channels forcing all channels to uniformly reduce speed; the shared data generation and distribution module synchronously switches the operating frequency, bus mode, bus width, and data rhythm when switching groups, and only supplies data to the channels enabled by the current group mask, thereby ensuring that each group obtains data that matches its stable mode.

[0018] This invention does not pre-assign the same final test mode to all channels. Instead, it forms an independent candidate mode queue for each test channel and verifies them step by step according to a preset priority. A candidate mode is only determined as the final stable mode of the channel after it has passed verification in stages such as voltage status, mode switching, tuning, and read / write comparison. If any stage fails, only the next candidate mode for that channel is updated, without affecting other channels that have already been successfully verified.

[0019] This invention, through a phase failure code and candidate mode update mechanism, can downgrade a failed channel to an available mode or mark it as an abnormal state, thereby preventing a single low-capacity or abnormal channel from forcing all channels to slow down together, and preventing the central scheduler from waiting indefinitely for that channel to complete.

[0020] After candidate mode verification is completed in each test channel, this invention dynamically generates a stable mode table based on the actual verification results. The contents of this table are derived from the actual candidate mode verification results of each channel and serve as a unified control basis for subsequent dynamic grouping, group mask generation, priority scheduling, and shared data resource configuration. This realizes the state transition and decoupling between channel-level dynamic verification results and group-level shared resource scheduling.

[0021] Other features and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the multi-channel memory card grouping test system architecture based on a stable mode table in an embodiment of the present invention; Figure 2 This is a flowchart of a multi-channel memory card grouping test method based on a stable mode table in an embodiment of the present invention; Figure 3 This is an example of a stable mode representation in an embodiment of the present invention. Detailed Implementation

[0023] It should be noted that the following detailed description is illustrative and intended to provide further explanation of the invention. Unless otherwise specified, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0024] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0025] Terminology Explanation: UHS: short for Ultra High Speed, usually refers to ultra-high speed mode. For most FPGA developers, UHS mode usually refers to sub-modes such as SDR50, DDR50 or SDR104 under UHS-I.

[0026] Tuning: In UHS-I high-speed mode, the host sends a specific tuning sequence to the SD card to return known data, and the host adjusts the sampling clock phase accordingly to find the optimal sampling point.

[0027] Example 1 To reduce redundant usage of the FPGA's internal MMCM (Mixed-Mode Clock Manager), BUFG (Global Clock Buffer), BRAM (Block Random Access Memory), and data generation logic, multiple test channels share configurable clock resources and a shared data generation and distribution module. Therefore, channels operating in parallel at the same time not only require identical clock frequencies but also compatibility in bus mode, data transmission edges, bus width, and data rhythm configurations.

[0028] While different SD cards may claim to support the same UHS mode in their protocol capability information, the highest mode they can stably operate in may differ under different physical channels, PCB links, and voltage conditions. If grouping is done solely based on nominal capabilities, a channel that claims to support the target mode may actually fail during voltage switching, tuning, or high-speed read / write phases, thus preventing the established test group from executing stably.

[0029] Based on this, in one or more embodiments, a multi-channel memory card grouping test system based on a stable mode table is disclosed, combined with Figure 1 It mainly includes: a central mode management and scheduler, a shared data generation and distribution module, and multiple test channels; among them, the central mode management and scheduler and the shared data generation and distribution module are integrated into the FPGA.

[0030] Specifically, the central mode management and scheduler includes: (1) The candidate mode verification module is configured to perform voltage status verification, mode status verification, tuning status verification and read / write comparison verification sequentially on the target test channel under each candidate mode.

[0031] In this embodiment, the candidate pattern verification module specifically includes: (1-1) The candidate mode generation unit is configured to generate a candidate mode queue for each test channel based on the capability identification results, controller configuration, channel historical failure records, and test strategy. The capability identification results are primarily derived from the card capabilities obtained during SD card initialization and function query; the controller configuration is derived from the FPGA's design parameters or configuration registers; the historical failure records are derived from the candidate mode verification results of the current channel or the state data saved from previous tests; and the test strategy is configured by the upper-layer software to specify the set of modes allowed for testing in this batch, mode priorities, whether automatic degradation is allowed, and the maximum number of retries.

[0032] When generating candidate modes, the intersection of card capabilities and controller capabilities is first calculated to obtain a set of modes that the hardware can attempt. Then, a testing strategy is used to filter and sort this set. Finally, historical failure records are used to downgrade or eliminate modes that have failed multiple times, thus forming a queue of candidate modes actually executed by that channel. This avoids mechanically traversing all speed modes for each channel. On the one hand, it avoids trying modes that are not supported by the protocol or cannot be executed by the current controller. On the other hand, it avoids repeatedly performing voltage switching, tuning, and read / write verification on known long-term unstable high-speed modes, thereby reducing meaningless mode switching and shared clock reconfiguration, and improving the testing efficiency of the multi-channel stable mode confirmation phase.

[0033] The candidate mode queue may include one or more of SDR104, SDR50, DDR50, SDR25, SDR12, and default or high-speed modes, and is arranged according to a preset priority.

[0034] In a specific test task, a target operating frequency can be pre-configured for each mode to be verified. For example, SDR50 can be configured to correspond to 100MHz, SDR25 to 50MHz, and DDR50 to 50MHz DDR. After the candidate mode completes phase verification at the target frequency, the mode that actually passes the verification is written into the stable mode table along with its corresponding operating frequency.

[0035] The candidate mode queue in this embodiment is not a simple fixed list of modes, but is dynamically generated based on channel capabilities, controller capabilities, historical failure records, and testing strategies. For example, if the capability information of a channel indicates that SDR104 is not supported, SDR104 will not be included in the candidate mode queue; if the historical record of a channel shows that SDR104 has failed to tune multiple times, the priority of SDR104 can be reduced or the test can start directly from SDR50.

[0036] (1-2) The candidate mode verification unit is configured to: retrieve the current candidate mode from the candidate mode queue for the target channel, perform the corresponding voltage status confirmation, mode configuration, bus width configuration and clock frequency configuration, and sequentially perform voltage status verification, mode status verification, tuning status verification and read / write comparison verification; the specific implementation process of these verifications is existing technology, so it will not be described in detail.

[0037] (1-3) The candidate mode update unit is configured as follows: if all stages of the verification of the current candidate mode pass, the candidate mode is recorded as the final stable mode of the test channel, and the corresponding working frequency is written into the stable mode table; if any stage verification fails, the corresponding stage failure code is generated; it is determined whether there is a next candidate mode. If there is, it is downgraded to the next candidate mode and the candidate mode verification is re-executed; if there is no candidate mode, the test channel is marked as abnormal, so that it does not participate in the data distribution of the current same-frequency test group.

[0038] The stage failure codes describe the stages in the candidate mode verification process where failures occur, and their role is to drive updates to the candidate mode queue and the stable mode table status. For example, F01 indicates that the target mode is not supported, F02 indicates an abnormal voltage state, F03 indicates a mode switching failure, F04 indicates a tuning failure, F05 indicates a read / write comparison failure, F06 indicates a timeout, and F07 indicates that no candidate modes are available. Candidate mode updates and stable mode table maintenance are performed based on the failure codes output at each stage.

[0039] Due to differences in SD cards, PCB channels, voltage, and timing conditions, directly grouping channels based on the declared capabilities of the SD cards might incorrectly classify channels that cannot actually operate stably in the target mode into the high-speed group. The purpose of candidate mode verification in this embodiment is to convert the theoretical capabilities supported by the SD card into the stable operating capabilities that have been verified in actual physical testing of the channels. Different channels may achieve different final stable modes; for example, CH0 and CH1 can operate stably at SDR50, while CH2, after failing to tune under SDR50 and degrading, can only operate stably at SDR25.

[0040] After candidate mode verification, subsequent scheduling no longer uses unverified nominal capabilities, but rather the final stable mode and operating frequency that has been verified for each channel. This ensures that the shared clock and shared data rhythm of subsequent test groups are based on verified operating conditions, reducing the probability of mode failures occurring again during formal batch testing, leading to regrouping or interruptions.

[0041] (2) The stable mode table configuration module is configured to write the corresponding candidate mode and working frequency into the stable mode table if the verification of each stage passes; if the verification of any stage fails, the generated stage failure code is written into the stable mode table.

[0042] In this embodiment, the stable mode table is a key data structure connecting the candidate mode verification phase and the same-frequency test group test scheduling phase. This table includes at least the channel number, the highest candidate mode, the final stable mode, the operating frequency, the phase failure code, the number of retries, the same-frequency test group number, the group priority, and the channel status. Figure 3A structural example of a stable pattern table is given.

[0043] The highest candidate mode refers to the highest-level mode that the channel is allowed to try first in this task, considering the capabilities of the SD card, the host controller, and the current test strategy. It is not necessarily equal to the highest mode theoretically supported by the SD card protocol. For example, if the card supports SDR104, but the host controller is only configured to SDR50 in this test, then the highest candidate mode is SDR50. The final stable mode refers to the final stable mode of the test channel after verification by the candidate modes. The stage failure code is used to identify at which stage the current candidate mode failed during the verification process, such as target mode not supported, 1.8V voltage switching abnormality, mode switching failure, tuning failure, read / write comparison failure, verification timeout, and candidate mode exhaustion. The retry count records the number of verification retries that have occurred during the candidate mode verification process. It can record the retry count for the current mode or the cumulative retry count during the entire candidate mode confirmation process; in this embodiment, it is preferred to record the cumulative retry count and set a maximum allowed value to prevent a certain abnormal channel from repeatedly verifying for a long time and occupying shared test resources. Channel status is used to indicate whether the channel has achieved a stable mode, such as at least distinguishing between "verification in progress", "stable and available", and "abnormal isolation".

[0044] In this embodiment, both the stage failure code and the channel status are retained in the stable mode table as the status basis for subsequent candidate mode updates, anomaly isolation and scheduling determination, while retaining the failure reasons in the process of forming the stable mode of each channel.

[0045] The stable mode table serves as a control state table between the candidate mode verification phase and the shared resource scheduling phase. Since the completion times of candidate verification for each test channel may differ, if the central scheduler directly uses the real-time changing verification states of each channel for grouping, inconsistencies can easily arise where some channels are still undergoing downgrade verification while others have already begun grouping. Therefore, this embodiment centrally writes the finally confirmed stable mode, operating frequency, channel status, and failure information for each channel into the stable mode table. Only after a candidate mode has completed all stages of verification is its corresponding final stable mode, operating frequency, and channel status submitted to the stable mode table. The same-frequency test group mask and subsequent shared clock and data path configurations are all generated based on this stable mode table, thereby preventing temporary states during the verification process from directly affecting the formal test scheduling.

[0046] By using a stable mode table, the mode, frequency, and status information scattered across various test channels are converted into structured control information that the central scheduler can read uniformly. This allows the central scheduler to generate each test group and its channel mask based on the stable mode table without having to re-query the internal status of each SD controller, and further prioritize the test groups.

[0047] Meanwhile, when all candidate modes of a channel fail to be verified, its channel status is marked as abnormal in the stable mode table. This allows the channel to be directly excluded during subsequent group mask generation, thus preventing abnormal channels from continuing to occupy shared data resources or blocking other normal channels.

[0048] (3) An abnormal state marking module is configured to mark the corresponding target test channel as an abnormal state when there is still a verification failure after the candidate mode queue is exhausted, so that it does not participate in the data distribution of the same frequency test group.

[0049] Specifically, for a given test channel, if all candidate modes in the candidate mode queue fail to be verified, the test channel is marked as abnormal, its channel mask is set to always be invalid, and it no longer participates in the data distribution of the same frequency test group. This ensures the consistency of data distribution, prevents bad channels from polluting the same frequency test group, avoids invalid retries, and saves test time.

[0050] Optionally, after the current normal test task is completed, an independent process such as anomaly recovery, re-initialization, low-speed retesting, or fault location can be entered; the specific process of anomaly recovery can adopt existing technology, and this embodiment does not make specific limitations.

[0051] It should be noted that in actual verification, a test channel may be compatible with multiple modes simultaneously, for example, a channel may be able to run stably on both SDR50 and SDR25. Therefore, this embodiment preferably verifies the candidate modes in descending order of priority. Once a candidate mode has been fully verified, it is determined as the final stable mode for this test task, and verification of lower-level modes is stopped, ensuring that only one final stable mode for this scheduling is stored in the stable mode table.

[0052] (4) The same frequency group mask generation module is configured to divide the test channels with the same final stable mode and working frequency into same frequency test groups according to the stable mode table, and generate the channel mask of each same frequency test group.

[0053] In this embodiment, the same-frequency group mask generation module generates same-frequency test groups based on the stable mode table. For example, channels with both final stable mode and operating frequency of SDR50 form the SDR50 same-frequency test group, channels with both final stable mode and operating frequency of SDR25 form the SDR25 same-frequency test group, and abnormal channels are added to the abnormal set.

[0054] When generating a test group with the same frequency, not only are the mode names compared, but also the actual operating frequencies in the stable mode table are compared. Only normal channels whose final stable mode and operating frequency both meet the group configuration conditions can enter the same group, thus ensuring that the operating frequencies in a test group are consistent.

[0055] In this embodiment, the channel mask of the same frequency test group is determined by the final stable mode, operating frequency and channel status in the stable mode table; the channel mask is specifically a set of N-bit enable vectors, each bit corresponding to the enable state of a physical test channel; the mask bits corresponding to abnormal state channels remain invalid; N is the number of test channels.

[0056] A bit set to 1 indicates that the channel belongs to the current test group and is allowed to receive test commands and data from the current group; a bit set to 0 indicates that the current group does not enable the channel. For example, if the system contains 8 test channels CH0 to CH7, and SDR50 consists of CH0, CH1, and CH5, with bits 0 to 7 corresponding to CH0 to CH7 respectively, then the mask for this group can be represented as 8'b00100011; if another SDR25 group consists of CH2 and CH6, then the corresponding mask is 8'b01000100. Abnormal channels maintain a mask bit of 0 in all normal test groups.

[0057] When all normal channels have the same final stable mode and the same operating frequency, the same frequency group mask generation module generates a single same frequency test group channel mask containing all normal channels, and all normal channels are directly tested in parallel as a whole. When different final stable modes or different operating frequencies are detected, the same-frequency group mask generation module divides the channels with the same final stable mode and operating frequency into multiple same-frequency test groups according to the stable mode table, and generates the channel mask for each group.

[0058] For example, the system contains 5 test channels, CH0 to CH4. After the candidate mode verification is completed, the stable mode table records: the final stable mode of CH0 and CH1 is SDR50, CH is DDR50, CH3 is SDR25, and CH4 did not obtain a usable stable mode and was marked as abnormal.

[0059] Bits 0 to 4 of the pre-configured 5-bit mask correspond to CH0 to CH4 respectively. Therefore, the channel mask for SDR50 group G1 is 5'b00011; the channel mask for DDR50 group G2 is 5'b00100; and the channel mask for SDR25 group G3 is 5'b01000. Bit 4 of CH4 remains 0 in all normal test group masks, thus it will not receive data requests or start signals from normal test groups. When scheduling G1, 00011 is loaded; when scheduling G2, it switches to 00100; and when scheduling G3, it switches to 01000. In this way, the same multi-channel hardware can dynamically select the channel currently participating in the test using different mask groups.

[0060] In this embodiment, the test group channel mask is not a fixed enable mask generated based on the channel number pre-specified by the software, but rather a group-level channel selection result dynamically obtained based on the final stable mode in the stable mode table, the actual operating frequency, and the channel status. The test group to which a channel belongs is not a fixed configuration before the test begins, but is determined only after each channel has completed candidate mode verification.

[0061] Meanwhile, the test group channel mask is not only used to select which channels are working, but also bound to the operating frequency, bus mode, bus width, data block parameters, and data rhythm of the current test group. When scheduling a test group, the shared data generation / distribution module responds only to the corresponding channels based on the current group mask, and switches to the operating parameters corresponding to that group; after all enabled channels in the current group have been completed, the group configuration and the next mask are switched simultaneously.

[0062] Therefore, in this embodiment, the channel mask for each test group serves as a control carrier for converting the grouping results formed by the actual stability capabilities of each channel into hardware enable relationships for shared test resources. By simultaneously constraining the channel participation relationships and the service objects of shared data resources through the same set of masks, it is possible to ensure that the current configuration of the shared data module is consistent with the actual enabled test channels, thus preventing channels in different stability modes from mistakenly sharing the same data rhythm.

[0063] (5) The priority scheduling module is configured to determine the scheduling order of each test group at the same frequency in descending order of working frequency and / or preset mode level; and to control the channel mask enable of each test channel in accordance with the scheduling order.

[0064] In this embodiment, the high-frequency co-frequency test group can be given priority to occupy channel resources first, and then released to the next group in priority order after completion, until all normal channels have completed the test; the rigorous test of the high-frequency group is completed by utilizing the initial stable state of the channel, avoiding the impact of channel state changes such as temperature drift and power fluctuation on the accuracy of high-frequency test; by enabling the channel mask, only one co-frequency test group is active at any given time, which can avoid the problem of mutual interference and resource contention between the high-frequency group and the low-frequency group.

[0065] Of course, the order in which these test groups use shared clock and shared data resources can also be determined by the central mode management and scheduler. For example, when forming three test groups—SDR104, SDR50, and SDR25—they can be executed sequentially from highest to lowest preset mode level; after all channels in the current group are enabled, the shared resource configuration is switched to the next group. Alternatively, when two modes have the same nominal clock frequency but different transmission methods, such as SDR25 and DDR50, their order can be preset by the upper-level test strategy, without being forced to compare only based on clock frequency.

[0066] The shared data generation and distribution module is configured to configure its operating parameters according to the operating frequency, bus mode, bus width, data block parameters, and data rhythm of the current same-frequency test group, so that it only distributes test data matching the group to the test channels with the channel mask enabled in the current same-frequency test group.

[0067] In this embodiment, the shared data generation and distribution means that multiple test channels are not configured with complete independent test data generators, but the test data required for this test is generated or cached uniformly on the central side. Then, according to the channel mask of the current test group, the same test data is distributed to the transmission cache of the corresponding test channel, and finally sent to the corresponding SD card according to the current bus mode.

[0068] In practice, test data can be written to the central shared cache by the upper-layer software, or generated by the counter or other hardware logic in the FPGA according to preset rules; this is existing technology and will not be described in detail in this embodiment.

[0069] Specifically, in the shared data generation and distribution architecture, before scheduling each same-frequency test group, the shared data generation and distribution module reconfigures its operating parameters based on the current group's operating frequency, bus mode, bus width, data block parameters, and data rhythm. This ensures that it only distributes test data matching the current group to the test channels whose channel masks are enabled. Only one same-frequency test group is active at a time: when scheduling a high-speed same-frequency test group, the shared data generation and distribution module switches to the operating frequency, bus mode, bus width, and data rhythm corresponding to that group, and only responds to data requests from channels whose channel masks are enabled in that group. Test channels within the current group execute tests in parallel. After all channels in the group have completed their tests, the module switches to the next priority same-frequency test group, continuing until all normal channels have completed their tests. This approach maintains multi-channel parallelism within the same-frequency test group while preventing different frequency groups from simultaneously competing for the same shared data stream.

[0070] As an optional implementation, to ensure that each channel within the current same-frequency test group receives data matching its configuration, each test channel can be configured with an independent transmission buffer and handshake signals for data requests, data validity, and test completion. The shared data generation and distribution module responds only to channel requests within the group based on the current group's channel mask and generates or distributes the same test pattern according to the current group configuration; each channel can absorb minor differences in response timing within the group through independent buffers without altering the unified pattern and data rhythm of the same-frequency test group.

[0071] Each test channel includes an SD controller, a mode register, a voltage status unit, a tuning status unit, a read / write comparison unit, and a stable mode output interface. The SD controller executes SD card initialization, mode switching, tuning commands, and read / write commands. The mode register stores the current candidate mode, current operating mode, final stable mode, and operating frequency. The voltage status unit records whether voltage switching was successful. The tuning status unit records whether tuning passed under the current candidate mode. The read / write comparison unit verifies the stability of the data link under the candidate mode. The stable mode output interface feeds back the final stable mode and stage verification results to the stable mode table maintenance module. Each test channel can also be configured with a send buffer and a data request / completion handshake interface.

[0072] It should be noted that the same-frequency grouping in this embodiment differs from the calibration grouping in the phase calibration process. Phase calibration grouping pre-divides channels into several calibration batches, with the main purpose of enabling multiple channels to perform CMD19 phase scanning at off-peak times, reducing instantaneous bus load and power supply noise when multiple channels perform CMD19 scanning simultaneously. In this embodiment, the same-frequency grouping is based on the final stable UHS mode and operating frequency obtained after phased verification of each test channel. Its purpose is to solve the data supply mismatch and channel congestion problems caused by different frequency channels sharing the same data flow rhythm under a multi-channel shared data generation and distribution architecture. The two differ in their grouping basis, formation timing, and the technical problems they solve.

[0073] This embodiment of the multi-channel memory card group testing system based on the stable mode table can test all normal channels as a whole in parallel when all normal channels have the same stable mode and operating frequency, without sacrificing the parallel efficiency under ideal conditions. When there are different stable modes or different operating frequencies, the system can achieve high-speed group priority and low-speed group subsequent group testing through the stable mode table, channel mask of the same frequency test group and group priority, avoiding the forced uniform speed reduction of all channels by a few low-speed channels.

[0074] The shared data generation and distribution module synchronously switches the operating frequency, bus mode, bus width, and data rhythm during group switching, and only supplies data to channels enabled by the current group mask. This ensures that each group receives data that matches its stable mode, avoiding data rhythm conflicts, buffering complexity, and channel blocking caused by different frequency channels sharing the same central data stream. At the same time, through the stage failure code and candidate mode update mechanism, failed channels are downgraded to available modes or marked as abnormal states to avoid blocking other channels and improve testing efficiency.

[0075] Example 2 In one or more embodiments, a multi-channel memory card grouping test method based on a stable mode table is disclosed. Based on the system implementation in Embodiment 1, the central mode management and scheduler first controls each test channel to perform capability identification and candidate mode verification, obtaining the final stable mode and operating frequency of each channel. Subsequently, the stable mode table configuration module writes the final stable mode, stage failure code, and status of each channel into the stable mode table, and the same-frequency group mask generation module divides the same-frequency test groups according to the stable mode table.

[0076] In the shared data generation and distribution architecture, the upper-layer test task scheduling module first determines whether all normal channels are in the same final stable mode and the same operating frequency. If they are consistent, for example, channels 0 to 7 are all stable at SDR50, then a channel mask covering channels 0 to 7 for the same frequency test group is generated, and all normal channels complete the test in parallel at once. If they are inconsistent, for example, channels 0, 1, and 5 are stable at SDR50, while channels 2 and 6 are stable at SDR25, then SDR50 and SDR25 same-frequency test groups are formed respectively. The scheduling module first configures the shared data generation and distribution module to execute the higher-speed same-frequency test group. After all channels in this group have completed, the data rhythm and channel mask are switched, and then the lower-speed same-frequency test group is executed until all normal channels have completed the test. This maintains maximum parallelism where possible while avoiding the problem of different frequency channels sharing the same data supply rhythm.

[0077] In this embodiment, the phased verification does not separately protect voltage switching, phase calibration, or read / write tests themselves. Instead, it uses these verification results as a unified input for determining the stability of candidate modes at different stages. Only when the current candidate mode meets preset conditions in voltage state, mode state, tuning state, and read / write comparison is it written into the stable mode table. The failure codes output at each stage are only used for candidate mode updates, stable mode table maintenance, and generation of same-frequency test groups.

[0078] For test channels that have not yet achieved a final stable mode, the central mode management and scheduler marks the channel as abnormal in the stable mode table, preventing it from participating in the data distribution of the current same-frequency test group. This abnormal status marking ensures that the current batch test tasks are not blocked by abnormal channels; further recovery, retesting, or fault location for the abnormal channel can be performed by subsequent abnormal handling procedures.

[0079] Combination Figure 2 The specific process of the multi-channel memory card grouping test method based on the stable mode table in this embodiment is as follows: S1: The central mode management and scheduler controls each test channel to complete initialization in the default mode and reads the SD card capability information, controller capability information and channel historical status.

[0080] Among them, SD card capability information refers to the capability information obtained from the card protocol response during the initialization process, such as the bus mode, speed mode, bus width, and whether the card supports the corresponding voltage and UHS function, etc.; specifically, it can be obtained through the initialization response, SCR (SD card configuration register) information, and CMD6 function query results.

[0081] Controller capability information refers to the test capabilities that the current FPGA can provide, such as the highest supported UHS mode, configurable clock range, whether it supports 1.8V switching, supported bus width, and whether it is configured with a tuning function. This information can be preset by the FPGA configuration register or upper-layer software.

[0082] Channel history status refers to the historical verification results of the previous or current batch for a certain physical test channel, such as the previous stable mode, the number of consecutive tuning failures in a certain mode, the number of read and write errors, etc. It can be stored in the dedicated embedded storage hard core, registers, or channel status table maintained by the upper-level software inside the FPGA.

[0083] S2: For each test channel, a candidate mode queue is generated based on the capability identification results, controller configuration, channel historical failure records and test strategy, and sorted according to preset priority.

[0084] The candidate mode queue is preferably formed according to the following logic: First, a basic mode sequence from high speed to low speed is set; then, modes that are not supported by the card are deleted according to the capabilities reported by the SD card; then, modes that the FPGA controller cannot execute are deleted according to the capabilities of the FPGA controller; then, modes that are allowed to be tested in this task are further selected according to the test strategy; finally, some modes are downgraded or skipped according to the historical failure information of the channel, and arranged according to the preset priority to obtain the final candidate mode queue of the channel.

[0085] For example: the base sequence is {SDR104, SDR50, DDR50, SDR25}. A certain card supports SDR104, SDR50, and SDR25, but the current host controller only supports up to SDR50. In this case, SDR104 is removed. If the test strategy prioritizes verifying the highest available mode, then {SDR50, SDR25} is obtained. If the channel history shows that SDR50 has experienced multiple consecutive tuning failures and the strategy is set to skip known unstable modes, the queue can be further adjusted to {SDR25}.

[0086] S3: For the target channel, retrieve the current candidate mode from the candidate mode queue, perform the corresponding voltage status confirmation, mode configuration, bus width configuration and clock frequency configuration, and then perform voltage status verification, mode status verification, tuning status verification and read / write comparison verification in sequence.

[0087] S4: If all stages of the verification of the current candidate mode pass, the candidate mode is recorded as the final stable mode of the test channel, and the corresponding operating frequency is written into the stable mode table; if any stage of verification fails, the corresponding stage failure code is generated.

[0088] S5: Determine if a next candidate mode exists. If it exists, downgrade to the next candidate mode and return to S3; if it does not exist, mark the channel as abnormal and prevent it from participating in the data distribution of the current same-frequency test group.

[0089] S6: After all target channels have completed the stable mode confirmation, confirm the final stable mode and operating frequency of each channel, and update the stable mode table. If the final stable mode and operating frequency of all normal channels are consistent, generate a channel mask for the same frequency group containing all normal channels; if there are different final stable modes or different operating frequencies, divide the test channels with the same final stable mode and operating frequency into multiple test groups for the same frequency, and generate channel masks for each group.

[0090] S7: Determine the scheduling priority based on the working frequency and / or preset mode level of each same-frequency test group, prioritize scheduling the high-speed same-frequency test group, and then schedule the lower-speed same-frequency test groups in turn.

[0091] S8: Before starting the current same-frequency test group, configure the shared data generation and distribution module according to the corresponding operating frequency, bus mode, bus width, data block parameters, and data rhythm of the group, and send test data only to the channels within the group through the current group channel mask; each test channel within the current group executes the test in parallel. After receiving the completion status of all enabled channels in the current group, the central mode management and scheduler switches the group configuration and group channel mask of the shared data generation and distribution module, and starts the next priority same-frequency test group until all normal channels have completed the test.

[0092] This embodiment of the method maintains the overall parallel efficiency under ideal conditions while avoiding data rhythm conflicts and channel blockages caused by different frequency channels sharing the central data stream.

[0093] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.

Claims

1. A multi-channel memory card grouping test system based on a stable pattern table, characterized in that, include: Centralized mode management and scheduler, shared data generation and distribution module, and multiple test channels; The central mode management and scheduler is configured to control each test channel to perform capability identification and candidate mode verification, thereby obtaining the final stable mode and operating frequency of each channel; write the final stable mode, operating frequency, stage failure code and status of each channel into the stable mode table, and divide the test channels with the same final stable mode and operating frequency into the same frequency test group according to the stable mode table, and generate the channel mask for each same frequency test group. The shared data generation and distribution module is configured to configure its operating parameters according to the operating frequency, bus mode, bus width, data block parameters, and data rhythm of the current same-frequency test group, so that it only distributes test data matching the group to the test channels with the channel mask enabled in the current same-frequency test group.

2. The multi-channel memory card grouping test system based on a stable pattern table as described in claim 1, characterized in that, The central mode management and scheduler includes: The candidate mode verification module is configured to sequentially perform voltage status verification, mode status verification, tuning status verification, and read / write comparison verification on the target test channel under each candidate mode. The stable mode table configuration module is configured to write the corresponding candidate mode and operating frequency into the stable mode table if all stages of verification pass; if any stage of verification fails, the generated stage failure code is written into the stable mode table. The abnormal state marking module is configured to mark the corresponding target test channel as abnormal if there are still verification failures after the candidate mode queue is exhausted, so that it will not participate in the data distribution of the current same frequency test group.

3. The multi-channel memory card grouping test system based on a stable pattern table as described in claim 1, characterized in that, The central mode management and scheduler also includes: The same-frequency group mask generation module is configured to divide test channels with the same final stable mode and operating frequency into same-frequency test groups according to the stable mode table, and generate channel masks for each same-frequency test group. The priority scheduling module is configured to determine the scheduling order of each same-frequency test group according to the working frequency and / or preset mode level from high to low; and to control the channel mask enable of each same-frequency test group according to the scheduling order.

4. The multi-channel memory card grouping test system based on a stable pattern table as described in claim 1, characterized in that, Each test channel includes: The SD controller is configured to perform SD card initialization, mode switching, tuning commands, and read / write commands. The mode register is configured to store the current candidate mode, the current operating mode, the final stable mode, and the operating frequency; The voltage status unit is configured to record whether the voltage switching was successful. The Tuning state unit is configured to record whether the tuning passed in the current candidate mode; The read / write comparison unit is configured to verify whether the data link is stable under the current candidate mode; The stable mode output interface is configured to feed back the final stable mode and stage verification results to the stable mode table.

5. The multi-channel memory card grouping test system based on a stable pattern table as described in claim 1, characterized in that, The stable mode table records at least the number, final stable mode, operating frequency, stage failure code, channel status, same-frequency test group number, and same-frequency test group priority for each test channel.

6. The multi-channel memory card grouping test system based on a stable pattern table as described in claim 1, characterized in that, The stage failure codes include at least one of the following: target mode not supported, abnormal voltage status, mode switching failure, tuning failure, read / write comparison failure, timeout, and no available candidate mode.

7. The multi-channel memory card grouping test system based on a stable pattern table as described in claim 1, characterized in that, The channel mask is determined by the final stable mode, operating frequency, and channel state in the stable mode table. The channel mask is an N-bit enable vector, with each bit corresponding to the enable state of a test channel; N is the number of test channels; the channel mask bits corresponding to abnormal state channels remain invalid.

8. A multi-channel memory card grouping test method based on a stable pattern table, characterized in that, include: Perform UHS candidate mode verification for each test channel, determine the final stable mode and corresponding operating frequency for each test channel based on the verification results, and generate a stable mode table; Based on the stable mode table, test channels with the same final stable mode and operating frequency are divided into same-frequency test groups, corresponding channel masks are generated for each same-frequency test group, and the scheduling priority of each same-frequency test group is determined. Before starting each same-frequency test group, configure the working parameters of the shared data generation and distribution module according to the current same-frequency test group's operating frequency, bus mode, bus width, data block parameters, and data rhythm, so that it only distributes test data matching the group to the test channels with the current same-frequency test group's channel mask enabled.

9. The multi-channel memory card grouping test method based on a stable pattern table as described in claim 8, characterized in that, Also includes: The test channels within the current same-frequency test group execute tests in parallel. After receiving the test completion status of all enabled channels in the current same-frequency test group, the test group switches to the next priority same-frequency test group until all normal test channels have completed the test. For test channels that have not obtained a final stable mode, mark them as abnormal in the stable mode table so that they are not included in the test scheduling of the same frequency test group.

10. The multi-channel memory card grouping test method based on a stable pattern table as described in claim 8, characterized in that, Perform UHS candidate mode verification for each test channel separately, specifically as follows: Control each test channel to complete initialization, and read SD card capability information, controller capability information, and channel historical status; For each test channel, a candidate pattern queue is generated based on the capability identification results, controller configuration, channel history failure records, and test strategy. Select a candidate mode from the candidate mode queue as the current candidate mode, and perform the corresponding voltage status confirmation, mode configuration, bus width configuration and clock frequency configuration. Then, perform voltage status verification, mode status verification, tuning status verification and read / write comparison verification in sequence. If all stages of the verification of the current candidate mode pass, the candidate mode is recorded as the final stable mode of the test channel, and the corresponding operating frequency is written into the stable mode table. If any stage of verification fails, a corresponding stage failure code will be generated. Determine if there is a next candidate pattern. If there is, downgrade to the next candidate pattern and re-verify. If it does not exist, the channel will be marked as abnormal and will not participate in the data distribution of the current same-frequency test group.

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