Sram write boundary variation extraction structure and method

Abstract

The application discloses a SRAM write boundary variation extraction structure, which comprises a test array formed by m*n SRAM units. In each SRAM unit, any one of the first and second bit line ends is a selected bit line end, and the other is an unselected bit line end; the word line end, the power voltage end and the unselected bit line end are connected together. In the test array, the power voltage ends of the SRAM units in the same row are connected to the power voltage line in the same row and to a test pad; the selected bit line ends of the SRAM units in the same column are connected to the bit line in the same column and to a test pad. All N well leading ends are connected together, all P well leading ends are connected together and all grounding ends are connected together and are respectively connected to a test pad. The application further discloses a SRAM write boundary variation extraction method. The application can reduce the chip area and improve the test speed and accuracy.

Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit manufacturing method, and more particularly to a structure for extracting write margin variations in Static Random Access Memory (SRAM). This invention also relates to a method for extracting SRAM write margin variations. Background Technology

[0002] In the past 20 to 30 years, with the rapid development of microelectronics technology, components have shrunk rapidly, chip density has increased, and computing performance has become high-speed. Semiconductor memory is also developing in a significant direction. Among volatile memories, SRAM has the characteristics of low power consumption and high performance, while DRAM has the characteristics of low cost and large storage capacity.

[0003] Currently, various types of memory, especially static random access memory (SRAM) circuits, are embedded in system-on-a-chip (SoC) to improve system performance. Since this circuit is compatible with current CMOS technology, it is usually used in the L1 / L2 high-speed cache in arithmetic chips, and naturally becomes the first choice for embedded memory. Therefore, SRAM has a considerable proportion in the function and application of digital chips.

[0004] The main functions of SRAM are writing, reading, and standby. The corresponding electrical performance is judged by the wafer acceptance test (WAT) write margin (also known as write margin), noise margin, and standby leakage.

[0005] In the SRAM Write margin test, the corresponding SRAM is written to during circuit operation, and the write capability is quantified to evaluate the read / write balance characteristics of the SRAM.

[0006] For the SRAM cell circuit of the SRAM circuit, please refer to [reference needed]. Figure 2AAs shown, it includes pull-up transistors PU101 and PU102, pull-down transistors PD101 and PD102, select transistors PG101 and PG102, storage nodes n101 and n102, bit lines BL1 and BL2, word line WL, power supply voltage terminal Vdd, and ground terminal Vss. Pull-up transistors PU101 and PU102 are both formed in N-wells, so they also have N-well leads NW. Pull-down transistors PD101 and PD102 are both formed in P-wells, so they also have P-well leads PW.

[0007] SRAM circuit write operation:

[0008] like Figure 2A As shown, when the initial internal signals are 0V and 1V for storage nodes n101 and n102 respectively, a signal needs to be added when writing is required:

[0009] When WL = 1V, the selector is turned on, making BL1 and BL2 1V and 0V respectively. This causes the signals of storage nodes n101 and n102 to be inverted, thus completing the write operation. Storage nodes n101 and n102 are then changed to 1V and 0V respectively.

[0010] The WAT SRAM write margin test quantifies the write capability of this SRAM.

[0011] Existing SRAM write boundary testing methods include the following steps:

[0012] First, set up the test structure (testkey, TSK).

[0013] like Figure 1 The above describes the layout diagram of the test pads for the test structure used in the existing SRAM write boundary test method; firstly, the layout of the SRAM array and the pin-out terminals for connecting probes, i.e., the test pads 101, must be designed on the TSK. Figure 1 The text shows that nine test pads 101 need to be set up, and each of the nine test pads is connected by a lead-out pin. Figure 2A The nine test pads shown, NW, PW, Vdd, Vss, BL1, BL2, WL, n101, and n102, can be connected to probes to apply test signals to each end of the SRAM cell.

[0014] Next, a write margin test is performed, including:

[0015] 1. For example Figure 2AAs shown, a write operation must be performed first, WL = 1V, to enable PG1 and PG2; BL1 and BL2 are set to 0V and 1V respectively; monitor the voltage status of n101 and n102, with the internal initial conditions being: n101 and n102 are 0V and 1V respectively.

[0016] 2. For example Figure 2B As shown, set both BL1 and BL2 to 1V and WL = 1V, which means switching the voltage of BL1 to 1V.

[0017] 3. Monitor the voltage status of n101 and n102 continuously. Figure 2B In this case, n101 and n102 remain unchanged, i.e., 0V and 1V respectively.

[0018] 4. For example Figure 2C As shown, WL = 1V (on), BL1 = 1V, and BL2 are scanned from 1V (high level) to 0V (low level).

[0019] 5. When the states of n101 and n102 are flipped, i.e. n101 and n102 are 1V and 0V respectively, it means that the writing is complete. At this time, the BL2 voltage is the voltage corresponding to the write margin voltage.

[0020] like Figure 3 The figure shows the voltage change curves of the storage node when performing BL2 voltage scanning using the existing SRAM write boundary test method; curve 102 is the voltage curve of storage node n102, and curve 103 is the voltage curve of storage node n101. The reversal points of n101 and n102 can be found from curves 102 and 103. The corresponding BL2 voltage at this time is the write boundary voltage.

[0021] Existing methods for testing SRAM write boundaries have the following drawbacks:

[0022] 1. TSK layout pin pads (test pads) are numerous and consume a lot of space.

[0023] 2. The tester needs to provide a number of source measurement unit (SMU) ports. Each SMU port needs to support both output and input.

[0024] 3. The test program (PGM) is relatively complex.

[0025] The above describes the measurement of the write boundary of an SRAM cell. When extracting the SRAM write boundary variation value, a large amount of data needs to be measured, that is, a large number of SRAM cells need to be measured to obtain a large number of write boundaries. Only in this way can the write boundary variation value be determined and analyzed, and then the essential characteristics of SRAM read / write, the stability of the manufacturing process, and the yield of SRAM / chip can be analyzed.

[0026] Existing SRAM write boundary mutation extraction methods require drawing a diagram for each SRAM cell. Figure 1 The TSK shown requires 9 pins out pads for each TSK, and the array is repeated to obtain more write margin data to calculate its standard deviation, which is the write margin variation.

[0027] This means that obtaining a large amount of write margin data requires significant resources, layout space, and testing time. Summary of the Invention

[0028] The technical problem to be solved by this invention is to provide an SRAM write boundary variation extraction structure that can reduce the number of test pads, reduce the layout area of ​​the extraction structure, and improve test speed and accuracy. To this end, this invention also provides an SRAM write boundary variation extraction method.

[0029] To solve the above-mentioned technical problems, the SRAM write boundary variation extraction structure provided by the present invention includes: a test array formed by arranging m×n SRAM cells, where m is greater than or equal to 1, n is greater than or equal to 1, and m×n is greater than or equal to 2.

[0030] Each SRAM cell has the following connection ports: word line terminal, power supply voltage terminal, ground terminal, N-well lead-out terminal, P-well lead-out terminal, first bit line terminal, and second bit line terminal; either the first bit line terminal or the second bit line terminal is a selected bit line terminal and the other is an unselected bit line terminal, and the word line terminal, the power supply voltage terminal, and the unselected bit line terminal are connected together.

[0031] The test array includes at least m×n+3 test pads.

[0032] In the test array, the power supply voltage terminals of each SRAM cell in the same row are connected to the power supply voltage line in the same row, and the power supply voltage line is led out through a corresponding test pad. The bit line terminals of each SRAM cell in the same column are connected to the bit line in the same column, and the bit line is led out through a corresponding test pad.

[0033] The N-well leads of each SRAM cell are connected together and led out through a corresponding test pad;

[0034] The P-well leads of each SRAM cell are connected together and led out through a corresponding test pad.

[0035] The ground terminals of each SRAM cell are connected together and led out through a corresponding test pad.

[0036] A further improvement is that the SRAM cell includes a first inverter and a second inverter, the output of the first inverter and the input of the second inverter are connected to a first memory node, and the output of the second inverter and the input of the first inverter are connected to a second memory node.

[0037] A further improvement is that the first source and drain of the first select transistor, composed of NMOS transistors, are connected to the first bit line terminal, the second source and drain are connected to the first memory node, and the gate is connected to the word line terminal.

[0038] The first source and drain of the second select transistor, which is composed of NMOS transistors, are connected to the second bit line terminal, the second source and drain are connected to the second memory node, and the gate is connected to the word line terminal.

[0039] A further improvement is that the first inverter includes a first pull-up transistor composed of PMOS transistors and a first pull-down transistor composed of NMOS transistors.

[0040] The source of the first pull-up transistor is connected to the power supply voltage terminal, the drain of the first pull-down transistor and the drain of the first pull-up transistor are connected to the first memory node, the source of the first pull-down transistor is connected to the ground terminal, and the gate of the first pull-up transistor and the gate of the first pull-down transistor are connected to the second memory node.

[0041] A further improvement is that the second inverter includes a second pull-up transistor composed of PMOS transistors and a second pull-down transistor composed of NMOS transistors.

[0042] The source of the second pull-up transistor is connected to the power supply voltage terminal, the drain of the second pull-down transistor and the drain of the second pull-up transistor are connected to the second memory node, the source of the second pull-down transistor is connected to the ground terminal, and the gate of the second pull-up transistor and the gate of the second pull-up transistor are connected to the first memory node.

[0043] A further improvement is that m equals 8, n equals 8, and the number of test pads is 22.

[0044] To solve the above-mentioned technical problems, the SRAM write boundary mutation extraction method provided by the present invention includes the following steps:

[0045] Step 1: Apply 1V to the test pad shared by all N-well leads, apply 0V to the test pad shared by all P-well leads, and apply 0V to the test pad shared by all ground terminals.

[0046] Step 2: Extract the write boundary of the selected SRAM cell, assuming the selected SRAM cell is located in the i-th row and j-th column, 1≤i≤m, 1≤j≤n, including the following sub-steps:

[0047] Step 2a: Apply a 1V voltage to the bit line in column j.

[0048] Step 2b: The voltage on the power supply line of the i-th row is 0V. Then, the voltage on the power supply line of the i-th row is switched to 1V. Then, the current of the bit line in the j-th column is measured. When the current of the bit line in the j-th column is detected to be 0A, the first state signal is written into the selected SRAM cell.

[0049] Step 2c: Scan the voltage of the bit line in column j from 1V to 0V, and simultaneously detect the current of the bit line in column j. When the current of the bit line in column j suddenly jumps from a negative value to a positive value, it indicates that the storage signal of the selected SRAM cell has switched from the first state signal to the inverted second state signal. At this time, the voltage of the corresponding bit line in column j is the write boundary.

[0050] Step 3: Change the values ​​of i and j, and then repeat step 2 until the write boundaries of all the SRAM cells in the test array are obtained.

[0051] Step 4: Obtain the SRAM write boundary variation value based on the write boundaries of all SRAM cells in the obtained test array.

[0052] A further improvement is that the SRAM cell includes a first inverter and a second inverter, the output of the first inverter and the input of the second inverter are connected to a first memory node, and the output of the second inverter and the input of the first inverter are connected to a second memory node.

[0053] A further improvement is that the first source and drain of the first select transistor, composed of NMOS transistors, are connected to the first bit line terminal, the second source and drain are connected to the first memory node, and the gate is connected to the word line terminal.

[0054] The first source and drain of the second select transistor, which is composed of NMOS transistors, are connected to the second bit line terminal, the second source and drain are connected to the second memory node, and the gate is connected to the word line terminal.

[0055] A further improvement is that the first inverter includes a first pull-up transistor composed of PMOS transistors and a first pull-down transistor composed of NMOS transistors.

[0056] The source of the first pull-up transistor is connected to the power supply voltage terminal, the drain of the first pull-down transistor and the drain of the first pull-up transistor are connected to the first memory node, the source of the first pull-down transistor is connected to the ground terminal, and the gate of the first pull-up transistor and the gate of the first pull-down transistor are connected to the second memory node.

[0057] A further improvement is that the second inverter includes a second pull-up transistor composed of PMOS transistors and a second pull-down transistor composed of NMOS transistors.

[0058] The source of the second pull-up transistor is connected to the power supply voltage terminal, the drain of the second pull-down transistor and the drain of the second pull-up transistor are connected to the second memory node, the source of the second pull-down transistor is connected to the ground terminal, and the gate of the second pull-up transistor and the gate of the second pull-up transistor are connected to the first memory node.

[0059] A further improvement is that m equals 8, n equals 8, and the number of test pads is 22.

[0060] A further improvement is that the initial value of i is 1, and the initial value of j is 1; in step three, each time the values ​​of i and j are changed, only one of i and j is incremented by 1, while the other remains unchanged or is changed to its initial value.

[0061] A further improvement is that, in step three, the logic for changing the values ​​of i and j each time is as follows:

[0062] When i < m, j remains unchanged and i is incremented by 1.

[0063] When i = m, when j < n, j is incremented by 1 and i is set to 1; when j = n, step three ends.

[0064] This invention provides a test array setup that allows for the creation of multiple SRAM cells for testing write boundaries. SRAM cells in the same row can share a single power supply line and a single test pad, while SRAM cells in the same column can share a single bit line and a single test pad. The word line and unselected bit line of each SRAM cell are connected to the power supply line. The N-well leads of all SRAM cells are connected together and share a single test pad, as are the P-well leads and ground lines of all SRAM cells. Since the memory nodes of each SRAM cell do not require lead-out or corresponding test pads, this invention reduces the number of test pads, the layout area of ​​the extraction structure, and ultimately the chip area.

[0065] Furthermore, the present invention uses SRAM cells and a test array, which can be implemented by simply setting the layout of the photomask and the layout of the metal interconnects. Therefore, the present invention does not require additional photomasks and will not increase costs.

[0066] This invention does not require any changes to the structure of the SRAM cell itself, so the manufacturing steps of the SRAM cell remain unchanged. With the change in the layout of the photomask, the subsequent metal interconnect process will not add any additional steps or complexity. Therefore, this invention does not require any additional process steps to increase complexity.

[0067] This invention, through the setting of a test array, can acquire a large amount of data, namely the write boundaries of SRAM cells, through testing. The more SRAM cells included in the test array, the more data is acquired, and the higher the accuracy of the obtained SRAM write boundary variation value. Therefore, this invention, through the setting of a test array, can improve the testing accuracy of SRAM write boundary variation values.

[0068] During testing, this invention, after applying a fixed voltage to the N-well, P-well, and ground terminals, only requires applying the corresponding voltage to the bit lines and power supply lines of the selected SRAM cells and testing the current of the bit lines to collect the write boundaries of each SRAM cell. This invention does not require testing the voltage of the memory nodes. Therefore, this invention can also reduce the number of SMUs in the test machine, simplify the test procedure, and improve the test speed. Since the test speed of each SRAM cell can be improved, combined with the test array, the time required to complete the SRAM write boundary variation value test can be greatly reduced. Therefore, this invention can also save test time. Attached Figure Description

[0069] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0070] Figure 1This is a diagram showing the arrangement of the test pads in the test structure used in existing SRAM write boundary testing methods;

[0071] Figures 2A-2C This is a circuit diagram showing the operation of SRAM cells in the existing SRAM write boundary test method.

[0072] Figure 3 The curves showing the change in storage node voltage during BL2 voltage scanning are obtained using existing SRAM write boundary testing methods.

[0073] Figure 4 This is a circuit diagram of the test array of the SRAM write boundary variation extraction structure according to an embodiment of the present invention;

[0074] Figure 5 This is a diagram showing the arrangement of the test pads in the SRAM write boundary variation extraction structure according to an embodiment of the present invention;

[0075] Figure 6A This is a simplified circuit diagram of the SRAM cell of the SRAM write boundary variation extraction structure in this embodiment of the invention when the first line terminal is the selected positioning line terminal;

[0076] Figure 6B This is a circuit diagram of the SRAM cell of the SRAM write boundary variation extraction structure in this embodiment of the invention when the first line terminal is the selected positioning line terminal;

[0077] Figure 7A This is a simplified circuit diagram of the SRAM cell of the SRAM write boundary variation extraction structure in this embodiment of the invention when the second bit line terminal is the selected bit line terminal;

[0078] Figure 7B This is a circuit diagram of the second bit line terminal of the SRAM cell in the SRAM write boundary variation extraction structure of the present invention when the bit line terminal is selected.

[0079] Figure 8A This is a layout diagram below the first metal layer of the SRAM cell in the SRAM write boundary variation extraction structure of the present invention.

[0080] Figure 8B This is a layout diagram below the first via layer of the SRAM cell in the SRAM write boundary variation extraction structure of the present invention.

[0081] Figure 8C This is a layout diagram below the second metal layer of the SRAM cell in the SRAM write boundary variation extraction structure of the embodiment of the present invention;

[0082] Figure 8D This is a layout diagram below the second via layer of the SRAM cell in the SRAM write boundary variation extraction structure of the embodiment of the present invention;

[0083] Figure 8E This is a layout diagram below the third metal layer of the SRAM cell in the SRAM write boundary variation extraction structure of the embodiment of the present invention;

[0084] Figures 9A-9C This is a circuit diagram illustrating the operation of a selected SRAM cell in the SRAM write boundary variation extraction method of this invention.

[0085] Figure 10 This is a curve showing the changes in BLa and BLb currents during BLb voltage scanning of a selected SRAM cell in the SRAM write boundary variation extraction method of this invention. Detailed Implementation

[0086] like Figure 4 The diagram shown is a circuit diagram of the test array of the SRAM write boundary mutation extraction structure according to an embodiment of the present invention. The SRAM write boundary mutation extraction structure according to an embodiment of the present invention includes: a test array formed by arranging m×n SRAM cells 201, where m is greater than or equal to 1, n is greater than or equal to 1, and m×n is greater than or equal to 2.

[0087] exist Figure 4 In the corresponding example, both m and n are equal to 8, and there are a total of 64 SRAM cells 201. Figure 4 The 64 SRAM cells 201 are also labeled with Bit01, Bit02 up to Bit64 respectively.

[0088] In other embodiments, the values ​​of m and n can be set as needed, for example, according to the required test accuracy. If the test accuracy requirement is not high, the values ​​of m and n can be decreased; conversely, if the test accuracy requirement increases, the values ​​of m and n can be increased.

[0089] like Figure 6A The diagram shown is a simplified circuit diagram of the SRAM cell 201 of the SRAM write boundary variation extraction structure in an embodiment of the present invention, where the first line terminal BLa is a selected line terminal; as shown Figure 7A The diagram shown is a simplified circuit diagram of the SRAM cell 201 of the SRAM write boundary variation extraction structure in an embodiment of the present invention when the second bit line terminal BLb is a selected bit line terminal; the connection ports of each SRAM cell 201 include: word line terminal WL, power supply voltage terminal Vdd, ground terminal Vss, N-well lead-out terminal NW, P-well lead-out terminal PW, first bit line terminal BLa and second bit line terminal BLb; either the first bit line terminal BLa or the second bit line terminal BLb is a selected bit line terminal and the other is an unselected bit line terminal, and the word line terminal WL, the power supply voltage terminal Vdd, and the unselected bit line terminal are connected together. Figure 6ASince the first bit line terminal BLa is the selected bit line terminal, the second bit line terminal BLb is the unselected bit line terminal. Therefore, the word line terminal WL, the power supply voltage terminal Vdd, and the second bit line terminal BLb are connected together. Figure 7A Since the second bit line terminal BLb is the selected bit line terminal and the first bit line terminal BLa is the unselected bit line terminal, the second bit line terminal BLb is the unselected bit line terminal. Therefore, the word line terminal WL, the power supply voltage terminal Vdd, and the first bit line terminal BLa are connected together.

[0090] In this embodiment of the invention, the test array can be used Figure 6A The connection structure of the SRAM cell 201 shown is as follows: Figure 4 The first bit, Bit01, corresponds to the SRAM cell shown in the figure; it can also be used Figure 7A The connection structure of the SRAM cell 201 shown is as follows: Figure 4 The SRAM cell corresponding to Bit49 is shown in the figure.

[0091] like Figure 5 The diagram shown is an arrangement of test pads 203 in the SRAM write boundary variation extraction structure according to an embodiment of the present invention; the test array includes at least m×n+3 test pads 203. Figure 5 The number of test pads 203 mentioned above is based on Figure 4 The test array described in the example is configured. Figure 5 The CCP includes 22 of the aforementioned test pads 203.

[0092] Combination Figure 4 As shown, in the test array, the power supply voltage terminal Vdd of each SRAM cell 201 in the same row is connected to the power supply voltage line in the same row, and the power supply voltage line is led out through a corresponding test pad 203. Figure 4 Each power supply voltage line is represented by Vdd + row number, such as Vdd01, which represents the power supply voltage line in the first row. Figure 4 The CCP shows the eight power supply voltage lines, namely Vdd01, Vdd02, and so on up to Vdd08.

[0093] The selected bit line ends of each of the SRAM cells 201 in the same column are connected to the bit lines in the same column, and the bit lines are led out through a corresponding test pad 203. Figure 4 Each bit line is represented by BL + column number, such as BL01, which represents the bit line in the first column. Figure 4 The CCP displayed the eight bit lines mentioned above, namely BL01, BL02, up to BL08.

[0094] The N-well leads NW of each SRAM cell 201 are connected together and led out through a corresponding test pad 203. Figure 4 In this configuration, the N-well leads NW of each SRAM cell 201 are all connected to a common N-well. Figure 4 The common N-well terminal in the middle is also represented by Common NW; Figure 5 In the middle, the common N-well end is connected to the 21st test pad 203. Figure 5 In the text, the 21st test pad 203 is also designated as Pad 21. Figure 4 The image also shows Pad 21.

[0095] The P-well leads PW of each SRAM cell 201 are connected together and led out through a corresponding test pad 203. Figure 4 In this configuration, the P-well leads PW of each SRAM cell 201 are all connected to a common P-well. Figure 4 The common P-well terminal in the middle also uses Common PW representation; Figure 5 In the middle, the common P-well end is connected to the 22nd test pad 203. Figure 5 In the text, the 22nd test pad 203 is also designated as Pad 22. Figure 4 The image also shows Pad 22.

[0096] The ground terminals Vss of each SRAM cell 201 are connected together and led out through a corresponding test pad 203. Figure 4 In this configuration, the ground terminal Vss of each SRAM cell 201 is connected to a common ground terminal. Figure 4 The common ground terminal is also represented by Common Vss; Figure 5 In the middle, the common ground terminal is connected to the 20th test pad 203. Figure 5 In the text, the 20th test pad 203 is also referred to as Pad 20.

[0097] like Figure 6A As shown, the SRAM cell 201 includes a first inverter 202a and a second inverter 202b. The output terminal of the first inverter 202a and the input terminal of the second inverter 202b are connected to the first storage node n1, and the output terminal of the second inverter 202b and the input terminal of the first inverter 202a are connected to the second storage node n2.

[0098] The first source and drain of the first select transistor PG1, which is composed of NMOS transistors, are connected to the first bit line terminal BLa, the second source and drain are connected to the first memory node n1, and the gate is connected to the word line terminal WL.

[0099] The first source and drain of the second select transistor, which is composed of NMOS transistors, are connected to the second bit line terminal BLb, the second source and drain are connected to the second memory node n2, and the gate is connected to the word line terminal WL.

[0100] like Figure 6B The diagram shown is a circuit diagram of the SRAM cell 201 of the SRAM write boundary variation extraction structure in an embodiment of the present invention when the first line terminal BLa is selected as the line terminal; the first inverter 202a includes a first pull-up transistor PU1 composed of PMOS transistors and a first pull-down transistor PD1 composed of NMOS transistors.

[0101] The source of the first pull-up transistor PU1 is connected to the power supply voltage terminal Vdd, the drain of the first pull-down transistor PD1 and the drain of the first pull-up transistor PU1 are connected to the first memory node n1, the source of the first pull-down transistor PD1 is connected to the ground terminal Vss, and the gate of the first pull-up transistor PU1 and the gate of the first pull-down transistor PD1 are connected to the second memory node n2.

[0102] The second inverter 202b includes a second pull-up transistor PU2 composed of PMOS transistors and a second pull-down transistor PD2 composed of NMOS transistors.

[0103] The source of the second pull-up transistor PU2 is connected to the power supply voltage terminal Vdd, the drain of the second pull-down transistor PD2 and the drain of the second pull-up transistor PU2 are connected to the second memory node n2, the source of the second pull-down transistor PD2 is connected to the ground terminal Vss, and the gate of the second pull-up transistor PU2 and the gate of the second pull-down transistor PD2 are connected to the first memory node n1.

[0104] This invention provides an embodiment that uses a test array to obtain multiple SRAM cells 201 for testing write boundaries. SRAM cells 201 in the same row can share a power supply voltage line and a test pad 203, and SRAM cells 201 in the same column can share a bit line and a test pad 203. The word line terminal WL and the unselected bit line terminal of each SRAM cell 201 are connected to the power supply voltage terminal Vdd. The N-well leads NW of all SRAM cells 201 are connected together and share a test pad 203. The P-well leads PW of all SRAM cells 201 are connected together and share a test pad 203. The ground terminals Vss of all SRAM cells 201 are connected together and share a test pad 203. The memory nodes of each SRAM cell 201 do not need to be led out and have corresponding test pads 203 set. Therefore, this invention can reduce the number of test pads 203, reduce the layout area of ​​the extraction structure, and finally reduce the chip area.

[0105] Furthermore, the embodiments of the present invention only require setting the layout of the photomask and the layout of the metal interconnects by using the SRAM cell 201 and the test array. Therefore, the present invention does not require an additional photomask and will not increase costs.

[0106] The embodiments of the present invention do not require changes to the structure of the SRAM cell 201 itself. Therefore, the manufacturing steps of the SRAM cell 201 will remain unchanged. Based on the change of the photomask layout, the subsequent metal interconnect process will not add any additional steps or complexity. Therefore, the present invention does not require adding process steps to generate complexity.

[0107] like Figure 8A The diagram shown is a layout diagram below the first metal layer of the SRAM cell in the SRAM write boundary variation extraction structure of an embodiment of the present invention. In this embodiment, the layout diagram below the first metal layer can be the same as the existing structure. The SRAM cell 201 includes four active regions (AA), wherein the first active region 301a is shared by the first pull-down transistor PD1 and the first select transistor PG1; the second active region 301b is shared by the second pull-down transistor PD2 and the second select transistor PG2; the third active region 301c is used to form the first pull-up transistor PU1; and the fourth active region 301d is used to form the second pull-up transistor PU2. P-wells are formed in both the first active region 301a and the second active region 301b, and N-wells are formed in both the third active region 301c and the fourth active region 301d.

[0108] The gate structure of each transistor, namely PG1, PG2, PD1, PD2, PU1, and PU2, is composed of a polysilicon strip 302 spanning the corresponding active region. Among them, PU1 and PD1 share the same polysilicon strip 302, and PU2 and PD2 share the same polysilicon strip 302.

[0109] The source and drain regions of each transistor are formed in the active regions on both sides of the corresponding polysilicon strip 302.

[0110] The source / drain regions and gate structures of each transistor are connected to the corresponding first metal layer (M1) 304 through contact holes (CT) 303 formed at the top, forming corresponding terminals. For example, the first source / drain of PG2 is connected to the bit line terminal BL2 formed by the first metal layer 304 through the contact holes 303 at the top. Figure 8A In the middle, the bit line end BL2 is... Figure 6BThe second bit line terminal BLb is shown. The contact hole 303 at the top of the source of PD2 is connected to the ground terminal Vss formed by the first metal layer 304. The second source and drain of PG2 are shared with the drain of PD2 and are connected to the first metal layer 304 corresponding to the second memory node n2 through the corresponding contact hole 303 at the top; the polysilicon strip 302 shared by PU1 and PD1 is also connected to the first metal layer 304 corresponding to the second memory node n2 through the corresponding contact hole 303 at the top.

[0111] The top of the source of PU2 is connected to the power supply voltage terminal Vdd formed by the first metal layer 304 through the contact hole 303, and the top of the drain of PU2 is connected to the first metal layer 304 corresponding to the second storage node n2 through the contact hole 303.

[0112] The polysilicon strip 302 of PG2 is connected to the word line terminal WL formed by the first metal layer 304 through the corresponding contact hole 303 at the top.

[0113] Similarly, the first source and drain of PG1 are connected to the bit line terminal BL1 formed by the first metal layer 304 through the contact hole 303 at the top. Figure 8A In the middle, the bit line terminal BL1 is... Figure 6B The first bit line terminal BLa shown is connected to the ground terminal Vss formed by the first metal layer 304 via a contact hole 303 at the top of the source of PD1. The second source and drain of PG1 are shared with the drain of PD1 and are connected to the first metal layer 304 corresponding to the first memory node n1 via a corresponding contact hole 303 at the top; the polysilicon strip 302 shared by PU2 and PD2 is also connected to the first metal layer 304 corresponding to the first memory node n1 via a corresponding contact hole 303 at the top.

[0114] The top of the source of PU1 is connected to the power supply voltage terminal Vdd formed by the first metal layer 304 through the contact hole 303, and the top of the drain of PU1 is connected to the first metal layer 304 corresponding to the first memory node n1 through the contact hole 303.

[0115] The polysilicon strip 302 of PG1 is connected to the word line terminal WL formed by the first metal layer 304 through the corresponding contact hole 303 at the top.

[0116] Figure 8A The diagram also shows the patterns corresponding to each layer: AA represents the active region pattern, POLY represents the polysilicon strip 302 pattern, CT represents the contact hole 303 pattern, and M1 represents the first metal layer 304 pattern. Figure 8A The text also shows the subsequent... Figures 8B to 8EThe added patterns include: V1 representing the pattern of the first through-hole layer, M2 representing the pattern of the second metal layer, V2 representing the pattern of the second through-hole layer, and M3 representing the pattern of the third metal layer.

[0117] like Figure 8B The diagram shown is a layout diagram below the first via (V1) layer of the SRAM cell in the SRAM write boundary variation extraction structure of the present invention. Figure 8B Is Figure 8A The layout diagram for the first through-hole layer was added based on the existing diagram. Figure 8B As shown, in the SRAM cell 201, a first via 305 is provided on the top of each of the bit line terminals BL1 and BL2, the two word line terminals WL, and the two power supply voltage terminals Vdd. The pattern of the first metal layer 304 corresponding to the two ground terminals Vss extends to the outside of the SRAM cell 201, and a corresponding first via 305 is also formed on the top of the pattern of the first metal layer 304 extending to the outside of the SRAM cell 201 at the ground terminals Vss.

[0118] like Figure 8C The diagram shown is a layout diagram below the second metal layer of the SRAM cell in the SRAM write boundary variation extraction structure of an embodiment of the present invention. Figure 8C Is Figure 8B The layout diagram with the addition of a second metal layer 306 is based on the previous one. Figure 8C As shown, the bit line terminal BL2 and the two power supply voltage terminals Vdd are respectively connected to the same pattern of the second metal layer 306 through the first through hole 305 at the top to realize the output of BL2 and Vdd; the bit line terminal BL1 is connected to the corresponding pattern of the second metal layer 306 through the first through hole 305 at the top to realize the single-end output of BL2.

[0119] A corresponding second metal layer 306 pattern is also formed on the top of the first through hole 305 corresponding to the word line end WL and the ground end Vss.

[0120] like Figure 8D The diagram shown is a layout diagram below the second via (V2) layer of the SRAM cell in the SRAM write boundary variation extraction structure of an embodiment of the present invention. Figure 8D Is Figure 8C The layout diagram with the second through-hole layer was added based on the previous one. Figure 8D As shown, in the SRAM cell 201, a second via 307 is formed on the top of the pattern of the second metal layer 306 corresponding to the bit line terminal BL2 and the two word line terminals WL, respectively; on the outside of the SRAM cell 201, a second via 307 is formed on the top of the pattern of the second metal layer 306 corresponding to the two ground terminals Vss, respectively.

[0121] like Figure 8E The diagram shown is a layout diagram below the third metal layer of the SRAM cell in the SRAM write boundary variation extraction structure of an embodiment of the present invention. Figure 8E Is Figure 8C The layout diagram with the third metal layer 308 added to the original is as follows: Figure 8E As shown, the second metal layer 306 corresponding to the bit line terminal BL2 and the second metal layer 306 corresponding to the two word line terminals WL are respectively connected to the same pattern of the third metal layer 308 through the second through hole 307 at the top, so that the word line terminal WL is connected to Vdd and BL2.

[0122] The second through hole 307 at the top of the pattern of the second metal layer 306 corresponding to the two grounding terminals Vss is connected to the pattern of the same third metal layer 308, so as to realize the grounding terminal Vss is connected.

[0123] Depend on Figures 8A to 8E As shown, in this embodiment of the invention, only the layout pattern of each layer of the photomask needs to be set, and no additional photomask is required, so the cost is low.

[0124] By setting up a test array, this embodiment of the invention can obtain a large amount of data, namely the write boundary of SRAM cell 201, through testing. The more SRAM cells 201 included in the test array, the more data is obtained, and the higher the accuracy of the obtained SRAM write boundary variation value. Therefore, by setting up a test array, this embodiment of the invention can improve the testing accuracy of SRAM write boundary variation value.

[0125] As can be seen from the above, in this embodiment of the invention, based on a test key with 22 pads, a measurable architecture with a total number of 8×8=64 bits can be designed, which can measure the electrical properties of 64 write margins.

[0126] The write margin variation can be calculated using a single SRAM cell, i.e., a bit, as the unit. The write margins corresponding to 64 bits, i.e., Bit 01 to Bit 64, can be calculated.

[0127] like Figures 9A to 9C The diagram shown is a circuit diagram illustrating the operation of a selected SRAM cell in the SRAM write boundary mutation extraction method according to an embodiment of the present invention. Taking the SRAM write boundary mutation extraction method using the previously described SRAM write boundary mutation extraction structure as an example, the SRAM write boundary mutation extraction method according to an embodiment of the present invention includes the following steps:

[0128] Step 1: Apply 1V to the test pad 203 shared by all N-well leads (NW), apply 0V to the test pad 203 shared by all P-well leads (PW), and apply 0V to the test pad 203 shared by all ground terminals (Vss). That is, for... Figure 5 Pad 21 is charged to 1V, Pad 22 to 0V, and Pad 20 to 0V.

[0129] Step 2: Extract the write boundary of the selected SRAM cell 201, assuming the selected SRAM cell 201 is located in the i-th row and j-th column, 1≤i≤m, 1≤j≤n, including the following sub-steps:

[0130] Step 2a: Apply a 1V voltage to the bit line in column j.

[0131] Figure 9A In the selected SRAM cell 201 and Figure 7B The connection structure of the SRAM cell 201 shown is the same. In other examples, the selected SRAM cell 201 can also be... Figure 6B The connection structure of the SRAM cell 201 shown is the same.

[0132] The bit line in column j is connected to the second bit line terminal BLb of the selected SRAM cell 201, so the second bit line terminal BLb of the selected SRAM cell 201 will be supplied with a voltage of 1V.

[0133] Step 2b: 0V voltage on the power supply voltage line in row i.

[0134] like Figure 9A As shown, the power supply voltage line in the i-th row is connected to the first bit line terminal BLa, the power supply voltage terminal Vdd, and the word line terminal WL of the selected SRAM cell 201. Therefore, the 0V voltage on the power supply voltage line in the i-th row is equivalent to applying a 0V voltage to the power supply voltage terminal Vdd of the selected SRAM cell 201.

[0135] Then, the voltage of the power supply line in the i-th row is switched to 1V. For example... Figure 9B As shown, the voltage of the power supply voltage terminal Vdd of the selected SRAM cell 201 is switched to 1V.

[0136] Then, the current of the bit line in the j-th column is measured. When the current of the bit line in the j-th column is detected to be 0A, the first state signal is written into the selected SRAM cell 201. Figure 9BIn the test, measuring the current of the bit line in column j is the current of the second bit line terminal BLb of the selected SRAM cell 201. When the second storage node n2 rises to 1V, the second selection transistor PG2 will be turned off, and the current of the second bit line terminal BLb will be about 0A. At this time, the writing of the first status signal is completed. The first status signal corresponds to 0V (low level) for the first storage node n1 and 1V (high level) for the second storage node n2.

[0137] Step 2c: Scan the voltage of the bit line in column j from 1V to 0V, and simultaneously detect the current of the bit line in column j. When the current of the bit line in column j suddenly jumps from a negative value to a positive value, it indicates that the storage signal of the selected SRAM cell 201 has switched from the first state signal to the inverted second state signal. At this time, the voltage of the corresponding bit line in column j is the write boundary.

[0138] Figure 9C The term Sweep 1V to 0V indicates that the voltage of the second bit line terminal BLb of the selected SRAM cell 201 is scanned from 1V to 0V.

[0139] While scanning the voltage of the second bit line terminal BLb, the current of the second bit line terminal BLb is measured. If the current of the second bit line terminal BLb suddenly jumps from a negative value to a positive value, then the voltage of the corresponding second bit line terminal BLb at this time is the write boundary.

[0140] like Figure 10 The figure shows the curves of the changes in BLa and BLb currents when performing a BLb voltage scan on a selected SRAM cell in the SRAM write boundary variation extraction method of this embodiment of the invention. Curve 401 represents the current of BLa, and curve 402 represents the current of BLb.

[0141] The second bit line terminal will be directly represented by BLb below. The sweep voltage of BLb will decrease from 1V to 0V. For example... Figure 10 As shown, when the BLb voltage is high, the second storage node n2 will stabilize at 1V, and the second select transistor PG2 will remain off, so the current of BLb is 0A. However, since the first storage node n1 is 0V, the first select transistor PG1 will be on, therefore, the first bit line current remains a large value. At this time, corresponding to... Figure 10 The voltage of BLb in the range is above 0.45V.

[0142] As the voltage of BLb decreases, such as to 0.45V, the second selection transistor PG2 will gradually turn on, but the second storage node n2 will remain at 1V. At this time, the current of BLb will flow from the power supply voltage terminal Vdd, through the second pull-up transistor PU, the second storage node n2, and the second selection transistor PG2 to BLb. Figure 10 The voltage of BLb in the medium is in the range of 0.45V to 0.3V.

[0143] When the voltage of BLb continues to decrease, such as to 0.3V, the first storage node n1 and the second storage node n2 will reverse. At this time, the voltage of the second storage node n2 is 0V, and the voltage of the first storage node n1 is 1V. The current in BLb will then flow from BLb through the second select transistor PG2, the second storage node n2, and the second pull-down transistor PD2 to the ground terminal Vss. Therefore, the direction of the BLb current has reversed. Meanwhile, the first select transistor PG2 is off, so the first bit line current is 0A.

[0144] As the voltage of BLb continues to drop, such as to 0V, the current of BLb will also decrease further, corresponding to... Figure 10 The voltage of BLb in the medium ranges from 0.25V to 0V.

[0145] Step 3: Change the values ​​of i and j, and then repeat step 2 until the write boundaries of all the SRAM cells 201 in the test array are obtained.

[0146] Step 4: Obtain the SRAM write boundary variation value based on the write boundaries of all SRAM cells 201 in the obtained test array.

[0147] In some embodiments, the initial value of i is 1, the initial value of j is 1, and step two is performed once with i=1 and j=1 before step three is performed.

[0148] In step three, each time the values ​​of i and j are changed, only one of i and j is incremented by 1, while the other remains unchanged or is changed to its initial value. The logic for changing the values ​​of i and j in step three is as follows:

[0149] When i < m, j remains unchanged and i is incremented by 1.

[0150] When i = m, when j < n, j is incremented by 1 and i is set to 1; when j = n, step three ends.

[0151] In other embodiments, other logic for changing the values ​​of i and j can also be used, as long as it is ensured that after repeating step two multiple times, all the SRAM cells 201 in the test array can be tested.

[0152] In some examples of the methods in embodiments of the present invention, the testing process includes:

[0153] First, set Vss = 0V, Pw = 0V, and Nw = 1 for the common endpoints;

[0154] Test Bit01:

[0155] Step S1: Set BL01 = 1V;

[0156] Step S2: Set Vdd01 = 0V, then set Vdd01 = 1V, and check if the current of BL01 is close to 0A, which means that the initial conditions have been written.

[0157] Step S3: Scan BL01 from 1V to 0V. When the BL01 current suddenly jumps from low to high (from negative to positive), it means that the writing is complete. At this time, the BL01 voltage is the Bit01 write margin voltage.

[0158] Test Bit02 by repeating steps S1, S2, and S3 to obtain the write margin voltage of Bit02. Test Bit03 by repeating steps S1, S2, and S3 to obtain the write margin voltage of Bit03.

[0159] Repeat steps S1, S2, and S3 until Bit 64 is tested. Repeat steps S1, S2, and S3 to obtain the Bit 64 write margin voltage.

[0160] Using these data, namely 64 write margin voltages, we can obtain the SRAM write margin variation (standard deviation), which can be used to calculate and analyze SRAM performance, evaluate yield, and observe process stability.

[0161] In the method of this embodiment of the invention, during testing, after applying a fixed voltage to the N-well lead-out terminal NW, the P-well lead-out terminal PW, and the ground terminal Vss, it is only necessary to apply the corresponding voltage to the bit lines and power supply voltage lines of the selected SRAM cell 201 and test the current of the bit lines to collect the write boundaries of each SRAM cell 201. The method of this embodiment of the invention does not require testing the voltage of the storage node. Therefore, the method of this embodiment of the invention can also reduce the number of SMUs in the test machine, simplify the test procedure, and improve the test speed. Since the test speed of each SRAM cell 201 can be improved, combined with the test array, the time required for the method of this embodiment of the invention to complete the SRAM write boundary variation value test can be greatly reduced. Therefore, the method of this embodiment of the invention can also save test time.

[0162] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. An SRAM write boundary variation extraction structure, characterized in that, include: A test array consisting of m×n SRAM cells, where m is greater than or equal to 1, n is greater than or equal to 1, and m×n is greater than or equal to 2; Each SRAM cell has the following connection ports: word line terminal, power supply voltage terminal, ground terminal, N-well lead-out terminal, P-well lead-out terminal, first bit line terminal, and second bit line terminal; either the first bit line terminal or the second bit line terminal is a selected bit line terminal and the other is an unselected bit line terminal, and the word line terminal, the power supply voltage terminal, and the unselected bit line terminal are connected together; The test array includes at least m×n+3 test pads; In the test array, the power supply voltage terminals of each SRAM cell in the same row are connected to the power supply voltage line in the same row, and the power supply voltage line is led out through a corresponding test pad. The selected bit line terminals of each SRAM cell in the same column are connected to the bit line in the same column, and the bit line is led out through a corresponding test pad. The N-well leads of each SRAM cell are connected together and led out through a corresponding test pad; The P-well leads of each SRAM cell are connected together and led out through a corresponding test pad; The ground terminals of each SRAM cell are connected together and led out through a corresponding test pad.

2. The SRAM write boundary mutation extraction structure as described in claim 1, characterized in that: The SRAM cell includes a first inverter and a second inverter. The output of the first inverter and the input of the second inverter are connected to a first storage node, and the output of the second inverter and the input of the first inverter are connected to a second storage node.

3. The SRAM write boundary variation extraction structure as described in claim 2, characterized in that: The first source and drain of the first select transistor, which is composed of NMOS transistors, are connected to the first bit line terminal, the second source and drain are connected to the first memory node, and the gate is connected to the word line terminal. The first source and drain of the second select transistor, which is composed of NMOS transistors, are connected to the second bit line terminal, the second source and drain are connected to the second memory node, and the gate is connected to the word line terminal.

4. The SRAM write boundary mutation extraction structure as described in claim 3, characterized in that: The first inverter includes a first pull-up transistor composed of PMOS transistors and a first pull-down transistor composed of NMOS transistors; The source of the first pull-up transistor is connected to the power supply voltage terminal, the drain of the first pull-down transistor and the drain of the first pull-up transistor are connected to the first memory node, the source of the first pull-down transistor is connected to the ground terminal, and the gate of the first pull-up transistor and the gate of the first pull-down transistor are connected to the second memory node.

5. The SRAM write boundary mutation extraction structure as described in claim 4, characterized in that: The second inverter includes a second pull-up transistor composed of PMOS transistors and a second pull-down transistor composed of NMOS transistors; The source of the second pull-up transistor is connected to the power supply voltage terminal, the drain of the second pull-down transistor and the drain of the second pull-up transistor are connected to the second memory node, the source of the second pull-down transistor is connected to the ground terminal, and the gate of the second pull-up transistor and the gate of the second pull-up transistor are connected to the first memory node.

6. The SRAM write boundary mutation extraction structure as described in claim 1, characterized in that: m equals 8, n equals 8, and the number of test pads is 22.

7. A method for extracting SRAM write boundary mutations using the SRAM write boundary mutation extraction structure as described in claim 1, characterized in that, This includes the following steps: Step 1: Apply 1V to the test pad shared by all N-well leads, apply 0V to the test pad shared by all P-well leads, and apply 0V to the test pad shared by all ground terminals. Step 2: Extract the write boundary of the selected SRAM cell, assuming the selected SRAM cell is located in the i-th row and j-th column, 1≤i≤m, 1≤j≤n, including the following sub-steps: Step 2a: Apply a 1V voltage to the bit line in column j; Step 2b: The voltage on the power supply line in the i-th row is 0V. Then, the voltage on the power supply line in the i-th row is switched to 1V. Then, the current of the bit line in the j-th column is measured. When the current of the bit line in the j-th column is detected to be 0A, the first state signal is written in the selected SRAM cell. Step 2c: Scan the voltage of the bit line in column j from 1V to 0V, and simultaneously detect the current of the bit line in column j. When the current of the bit line in column j suddenly jumps from a negative value to a positive value, it indicates that the storage signal of the selected SRAM cell has switched from the first state signal to the inverted second state signal. At this time, the voltage of the corresponding bit line in column j is the write boundary. Step 3: Change the values ​​of i and j, and then repeat step 2 until the write boundaries of all the SRAM cells in the test array are obtained; Step 4: Obtain the SRAM write boundary variation value based on the write boundaries of all SRAM cells in the obtained test array.

8. The SRAM write boundary mutation extraction method as described in claim 7, characterized in that: The SRAM cell includes a first inverter and a second inverter. The output of the first inverter and the input of the second inverter are connected to a first storage node, and the output of the second inverter and the input of the first inverter are connected to a second storage node.

9. The SRAM write boundary mutation extraction method as described in claim 8, characterized in that: The first source and drain of the first select transistor, which is composed of NMOS transistors, are connected to the first bit line terminal, the second source and drain are connected to the first memory node, and the gate is connected to the word line terminal. The first source and drain of the second select transistor, which is composed of NMOS transistors, are connected to the second bit line terminal, the second source and drain are connected to the second memory node, and the gate is connected to the word line terminal.

10. The SRAM write boundary mutation extraction method as described in claim 9, characterized in that: The first inverter includes a first pull-up transistor composed of PMOS transistors and a first pull-down transistor composed of NMOS transistors; The source of the first pull-up transistor is connected to the power supply voltage terminal, the drain of the first pull-down transistor and the drain of the first pull-up transistor are connected to the first memory node, the source of the first pull-down transistor is connected to the ground terminal, and the gate of the first pull-up transistor and the gate of the first pull-down transistor are connected to the second memory node.

11. The SRAM write boundary mutation extraction method as described in claim 10, characterized in that: The second inverter includes a second pull-up transistor composed of PMOS transistors and a second pull-down transistor composed of NMOS transistors; The source of the second pull-up transistor is connected to the power supply voltage terminal, the drain of the second pull-down transistor and the drain of the second pull-up transistor are connected to the second memory node, the source of the second pull-down transistor is connected to the ground terminal, and the gate of the second pull-up transistor and the gate of the second pull-up transistor are connected to the first memory node.

12. The SRAM write boundary mutation extraction method as described in claim 7, characterized in that: m equals 8, n equals 8, and the number of test pads is 22.

13. The SRAM write boundary mutation extraction method as described in claim 7, characterized in that: The initial value of i is 1, and the initial value of j is 1. In step three, each time the values ​​of i and j are changed, only one of i and j is incremented by 1, while the other remains unchanged or is changed to its initial value.

14. The SRAM write boundary mutation extraction method as described in claim 13, characterized in that: In step three, the logic for changing the values ​​of i and j each time is as follows: When i < m, j remains unchanged and i is incremented by 1; When i = m, when j < n, j is incremented by 1 and i is set to 1; when j = n, step three ends.

Images