Memory chip test socket

Abstract

The application discloses a memory chip test seat and relates to the technical field of memory chip test equipment.The memory chip test seat comprises a base support layer, a honeycomb structure layer, a test wiring layer and a surface protection layer; the test wiring layer is provided with a plurality of wirings, and the wirings are partially arranged in the honeycomb structure layer; the wirings comprise signal input ends and signal output ends; the signal input ends are connected with probes, the top ends of the probes protrude from the surface protection layer, and the probes are used for electrically connecting with the memory chips to be tested; and the signal output ends protrude from the honeycomb structure layer.The application integrates the test wirings in the interior of the test seat, discards the structure form that the traditional test wirings are arranged on a PCB as a support carrier, effectively eliminates the performance difference between the PCBs caused by the manufacturing tolerance of the PCBs, avoids the phase difference and impedance deviation caused by the manual wiring layout, and effectively solves the technical problem that the test results of different test seats are inconsistent.

Description

Technical Field

[0001] This invention relates to the field of memory chip testing equipment technology, and in particular to a memory chip testing socket. Background Technology

[0002] Existing PCB-based test socket structures have many inherent defects, which severely restrict the accuracy and efficiency of memory chip testing. Specifically, the manufacturing process of the PCB board, which serves as the support carrier and signal transmission medium for the test socket, is significantly affected by factors such as environmental temperature and humidity fluctuations and PCB manufacturing tolerances. In addition, existing test traces generally rely on manual layout, which inevitably introduces problems such as trace length differences, phase differences, and impedance deviations.

[0003] To compensate for testing errors caused by differences between PCB boards and trace deviations, the industry generally relies on gold-standard samples for manual calibration. However, this manual calibration method is cumbersome and time-consuming, severely limiting testing efficiency. More importantly, traditional manual calibration methods are no longer sufficient to meet the high-precision and high-efficiency testing requirements of high-speed memory chips such as DDR5.

[0004] Therefore, there is an urgent need to provide a memory chip test socket that can effectively eliminate differences between PCB boards and deviations in manual wiring, and does not require frequent calibration with gold samples, in order to meet the increasingly stringent testing requirements of high-speed memory chips such as DDR5. Summary of the Invention

[0005] The main objective of this invention is to provide a memory chip test socket that effectively eliminates testing errors caused by differences between PCB boards and deviations in manual wiring.

[0006] To achieve the above objectives, the present invention proposes a memory chip test socket, comprising, from bottom to top, a substrate support layer, a honeycomb structure layer, a test trace layer and a surface protective layer; The test wiring layer is provided with a number of wirings, and the wirings are partially located inside the honeycomb structure layer; The trace includes a signal input terminal and a signal output terminal; the signal input terminal is connected to a probe, and the tip of the probe protrudes from the surface protective layer, the probe being used for electrical connection with the memory chip under test; the signal output terminal protrudes from the honeycomb structure layer, the signal output terminal being used for electrical connection with the test equipment.

[0007] Preferably, the cellular structure layer includes an energy absorption layer and a rigid constraint layer arranged sequentially from bottom to top; The energy-absorbing layer has an elastic modulus of 0.1–0.5 GPa, an elongation at break of >300%, and an energy absorption efficiency of >85%. The elastic modulus of the rigid constraint layer is 5-15 GPa, and the bending strength is >80 MPa.

[0008] Preferably, the energy absorption layer has a relative density of 8-22%, a honeycomb pore size of 2-3 mm, a honeycomb wall thickness of 0.15-0.5 mm, and a thickness of 0.05-0.2 mm. The rigid constraint layer has a relative density of 40-55%, a honeycomb pore size of 0.5-1 mm, a honeycomb wall thickness of 0.55-0.9 mm, and a thickness of 0.01-0.1 mm.

[0009] Preferably, both the energy absorption layer and the rigid constraint layer have a honeycomb structure that is a topological structure.

[0010] Preferably, the trace includes a trace body and a modulus transition ring surrounding the outside of the trace body, and the elastic modulus of the modulus transition ring decreases from the inside to the outside. The thickness of the wiring body is 100-200 μm; The thickness of the modulus transition ring is 0.1–0.5 mm; A mechanical interlocking structure is provided between the rigid constraint layer and the modulus transition ring.

[0011] Preferably, the modulus transition ring includes an inner ring, a middle ring, and an outer ring arranged sequentially from the inside to the outside; The elastic modulus of the inner ring is 5–10 GPa; The elastic modulus of the middle ring is 1-5 GPa; The elastic modulus of the outer ring is 0.1 to 1 GPa.

[0012] Preferably, the trace body includes a metal layer, an adhesive layer, and a conductive silver paste layer arranged sequentially from bottom to top; The thickness of the metal layer is 50–100 μm; The thickness of the adhesive layer is 5–10 μm; The conductive silver paste layer has a thickness of 50-100 μm and includes silver powder with a content of 60-80 wt%.

[0013] Preferably, the thickness of the base support layer is 0.05-0.2 mm, the elastic modulus is 0.1-0.5 GPa, and the elongation at break is >300%.

[0014] Preferably, the thickness of the surface protective layer is 5-10 μm, and the surface protective layer comprises a silane coupling agent and cyanoacrylate.

[0015] Preferably, the probe is a conductive elastic post.

[0016] The technical solution of this invention integrates the test traces inside the test socket, abandoning the traditional structure that relies on the PCB board as a support carrier to lay the test traces. This effectively eliminates the performance differences between boards caused by PCB manufacturing tolerances, and avoids the phase difference and impedance deviation that are easily caused by manual layout of traces. Thus, it effectively solves the technical problem of inconsistent test results between different test sockets. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of the memory chip test socket provided by the present invention; Figure 2 This is a cross-sectional schematic diagram of the traces in the memory chip test socket provided by the present invention.

[0019] Substrate support layer 1, honeycomb structure layer 2, energy absorption layer 21, rigid constraint layer 22, test trace layer 3, trace body 311, metal layer 3111, adhesive layer 3112, conductive silver paste layer 3113, modulus transition ring 312, inner ring 3121, middle ring 3122, outer ring 3123, surface protection layer 4, probe 5, memory chip 6.

[0020] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0022] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0023] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0024] The present invention will be further illustrated below through specific embodiments: As a core component of computer systems, memory chips' performance and quality directly affect the stable operation of the entire electronic system. In the manufacturing process of memory chips, the testing stage is a crucial step in ensuring chip quality and filtering out defective products. Traditional memory chip testing methods require the chip under test (DUT) to be placed entirely within specialized testing equipment, with electrical connections between the chip's pins and the equipment established via test sockets. Specifically, test sockets typically use a PCB board as a support, with test traces laid out on the PCB. The test socket uses probes or terminal assemblies to electrically connect the signal pins of the DUT to the test traces on the PCB, and then the signal is transmitted to the testing equipment via the PCB.

[0025] However, existing PCB-based test socket structures have many inherent defects, which severely restrict the accuracy and efficiency of memory chip testing.

[0026] First, the PCB board, as the supporting carrier and signal transmission medium of the test socket, is significantly affected by factors such as environmental temperature and humidity fluctuations and PCB manufacturing tolerances during its manufacturing process. Different batches of PCB boards, and even different boards within the same batch, may exhibit inter-board performance differences, including fluctuations in dielectric constant, trace impedance deviations, and interlayer alignment errors. These differences directly lead to inconsistencies in the electrical performance between different test sockets, resulting in deviations in the test results for the same chip on different test sockets, affecting the repeatability and consistency of the test results.

[0027] Secondly, current test traces generally rely on manual placement, inevitably introducing issues such as trace length differences, phase differences, and impedance deviations. In high-speed signal transmission, signals are extremely sensitive to delay; even minute differences in trace length can lead to inconsistent signal arrival timing. For high-speed memory chips like DDR5, the testing requirements are even more stringent. In existing technologies, the trace lengths within a large number of PCBs need to be controlled to a difference of less than 0.1mm to ensure signal synchronization. Manual trace placement struggles to consistently achieve such stringent length matching requirements, and the resulting timing deviations further exacerbate the inconsistencies in test results between different test sockets.

[0028] To compensate for testing errors caused by differences between PCB boards and trace deviations, the industry generally relies on gold-standard calibration for manual calibration. A gold-standard calibrator is one or more reference chips confirmed to fully meet design requirements in terms of function, performance, and specifications, used as a benchmark for calibrating and verifying the test system. Each time a test socket is changed or a test batch is switched, the test system must be calibrated against the gold-standard calibrator to compensate for performance differences between different test sockets. However, this manual calibration method is cumbersome and time-consuming, severely limiting testing efficiency. More importantly, traditional manual calibration methods are no longer sufficient to meet the high-precision, high-efficiency testing requirements of high-speed memory chips such as DDR5.

[0029] Therefore, there is an urgent need to provide a memory chip test socket that can effectively eliminate differences between PCB boards and deviations in manual wiring, and does not require frequent calibration with gold samples, in order to meet the increasingly stringent testing requirements of high-speed memory chips such as DDR5.

[0030] Therefore, this technical solution proposes a memory chip test socket, which includes a base support layer 1, a honeycomb structure layer 2, a test trace layer 3 and a surface protective layer 4 arranged sequentially from bottom to top; The test wiring layer 3 is provided with a plurality of wirings 31, and the wirings 31 are partially disposed inside the honeycomb structure layer 2; The trace 31 includes a signal input terminal and a signal output terminal; the signal input terminal is connected to the probe 5, and the tip of the probe 5 protrudes from the surface protective layer 4, and the probe 5 is used to electrically connect with the memory chip 6 under test; the signal output terminal protrudes from the honeycomb structure layer 2, and the signal output terminal is used to electrically connect with the test equipment.

[0031] The memory chip test socket provided by this solution integrates the test traces inside the test socket, abandoning the traditional structure that relies on the PCB board as a support carrier for laying the test traces. This effectively eliminates the performance differences between boards caused by PCB manufacturing tolerances, and avoids the phase difference and impedance deviation that are easily caused by manual layout of traces. Thus, it effectively solves the technical problem of inconsistent test results between different test sockets.

[0032] Furthermore, such as Figure 1 As shown, the memory chip test socket of this solution includes, from bottom to top, a base support layer 1, a honeycomb structure layer 2, a test trace layer 3, and a surface protective layer 4. The base support layer 1, as the bottom layer of the test socket, provides a stable support foundation for the entire test socket, ensuring the positional accuracy and structural stability of each layer during installation and testing. When the honeycomb structure layer 2 is subjected to an impact load transmitted from the memory chip under test 6 to the test socket via probe 5, its honeycomb walls can bend and crush sequentially. This plastic deformation process efficiently converts the impact kinetic energy into the deformation energy of the material, thereby absorbing a large amount of impact energy. This energy absorption mechanism is similar to the process where the energy is consumed in the gradual crushing of a can when it is squeezed flat by an external force, effectively attenuating the impact stress transmitted to the test trace layer and protecting the internal traces from damage. The surface protective layer 4 covers the top layer of the test socket, effectively isolating the test socket from the influence of external environmental temperature and humidity fluctuations on the internal structure and electrical performance of the test socket. It is a key measure to suppress performance drift during long-term use of the test socket and solve the long-term source of inter-board differences, helping to ensure the performance consistency of the test socket across different test batches.

[0033] To further explain, the honeycomb structure layer 2 includes an energy absorption layer 21 and a rigid constraint layer 22 arranged sequentially from bottom to top; The energy absorption layer 21 has an elastic modulus of 0.1–0.5 GPa, an elongation at break of >300%, and an energy absorption efficiency of >85%. The elastic modulus of the rigid constraint layer 22 is 5-15 GPa, and the bending strength is >80 MPa.

[0034] In a preferred embodiment of this technical solution, the honeycomb structure layer 2 includes an energy absorption layer 21 and a rigid constraint layer 22 arranged sequentially from bottom to top. These two layers synergistically enhance each other in terms of material properties and function, jointly forming a highly efficient energy dissipation and precision support system. Specifically: The elastic modulus of the energy-absorbing layer 21 is controlled between 0.1 GPa and 0.5 GPa, the elongation at break is greater than 300%, and the energy absorption efficiency is over 85%. As a unit for receiving impact energy, this layer can fully absorb and dissipate impact energy through its own deformation capacity when subjected to an impact load (up to 2000G) transmitted from the memory chip under test 6 to the test socket via probe 5. Its mechanism is similar to an elastic buffer structure, effectively intercepting most of the energy in the early stages of impact and significantly weakening the impact intensity transmitted to the upper structure. It should be noted that energy absorption efficiency refers to the ratio of the energy absorbed by the material under impact load to the corresponding stress level. It characterizes the material's ability to convert external impact kinetic energy into its own plastic deformation energy and can be calculated from the stress-strain curve of the material during compression, which will not be elaborated upon here.

[0035] The rigid constraint layer, as the direct load-bearing structure of trace 31, has an elastic modulus set between 5 GPa and 15 GPa and a bending strength greater than 80 MPa. This layer provides sufficient rigid support under impact conditions, effectively constraining the geometric deformation of the trace area, ensuring the shape and positional accuracy of trace 31, thereby ensuring the trace impedance remains consistent during impact and meeting the requirements of precision testing for signal transmission stability.

[0036] In one specific embodiment, the energy-absorbing layer 21 is printed using FDM technology with TPU (Shore 85A) material, and the rigid constraint layer 22 is printed using DLP or SLA technology with ceramic-reinforced photopolymer resin. This combined process fully leverages the material adaptability advantages of FDM technology in elastomer material molding, and the precision advantages of DLP / SLA technology in high-precision rigid structure molding, effectively avoiding the limitations of a single process on material selection and molding accuracy.

[0037] Furthermore, for printing the ceramic-reinforced photopolymer resin onto the rigid constraint layer 22, the laser power is controlled to be between 50mW and 250mW (SLA point scanning method) or the projection power density is 5mW / cm². 2 Up to 60mW / cm 2 (DLP surface exposure method), wavelength 405nm, exposure energy density 100mJ / cm² 2 Up to 300mJ / cm 2This ensures that the ceramic particles and the resin matrix are fully cured and bonded, with a curing depth reaching 1.5 to 2 times the thickness of the printed layer, thereby guaranteeing the molding quality and mechanical properties of the rigid constraint layer. It should be noted that ceramic-reinforced photocurable resin refers to a composite material formed by uniformly dispersing ceramic powders (such as silica, alumina, zirconium oxide, etc.) in a photocurable resin matrix. This material is formed using photocurable additive manufacturing processes (such as SLA or DLP). Under ultraviolet or visible light irradiation, the photoinitiator in the resin is activated, initiating a cross-linking polymerization reaction of monomers or prepolymers, thereby curing the ceramic particles and the resin matrix together. The material formulation can be designed according to the actual performance requirements of the rigid constraint layer 22, and is not limited in this case.

[0038] Furthermore, the energy absorption layer 21 has a relative density of 8-22%, a honeycomb pore size of 2-3 mm, a honeycomb wall thickness of 0.15-0.5 mm, and a thickness of 0.05-0.2 mm. The rigid constraint layer 22 has a relative density of 40-55%, a honeycomb pore size of 0.5-1 mm, a honeycomb wall thickness of 0.55-0.9 mm, and a thickness of 0.01-0.1 mm.

[0039] As a preferred embodiment of the above, this solution differentiates the energy absorption layer 21 and the rigid constraint layer 22 in the honeycomb structure layer 2 in terms of structural parameters: On one hand, the energy-absorbing layer 21 has a relative density of 8% to 22%, a honeycomb pore size of 2 mm to 3 mm, a honeycomb wall thickness of 0.15 mm to 0.5 mm, and a thickness of 0.05 mm to 0.2 mm. Under impact loads, this large-pore, thin-walled honeycomb structure allows the honeycomb walls to bend and crush sequentially, efficiently converting impact kinetic energy into material deformation energy through this plastic deformation process. This achieves excellent energy absorption and effectively attenuates the impact stress transmitted to the upper structure.

[0040] On the other hand, the rigid constraint layer 22 has a relative density of 40% to 55%, a honeycomb pore size of 0.5 mm to 1 mm, a honeycomb wall thickness of 0.55 mm to 0.9 mm, and a thickness of 0.01 mm to 0.1 mm. Compared to the large-pore, thin-walled structure of the energy absorption layer 21, the rigid constraint layer 22 adopts a small-pore, thick-walled honeycomb structure, and its structural form is more like a rigid frame. It mainly plays a role in structural support and geometric constraint, thereby providing a stable rigid bearing foundation for the test traces and ensuring that the trace area maintains geometric accuracy and impedance consistency under impact conditions.

[0041] In summary, the energy absorption layer 21 achieves efficient buffering and energy absorption through a large-aperture thin-walled honeycomb structure, while the rigid constraint layer 22 provides rigid support through a small-aperture thick-walled honeycomb structure. The two work together to meet the dual requirements of impact protection and precision testing.

[0042] It should be noted that relative density refers to the ratio of the volume of solid material to the total volume of the honeycomb structure including solid material and pore structure. That is, the relative density is 8 to 22%, which means that the volume ratio of solid material in energy absorption layer 21 is 8 to 22%.

[0043] To further clarify, both the energy absorption layer 21 and the rigid constraint layer 22 have honeycomb structures that are topological structures.

[0044] Traditional regular honeycomb structures are essentially regular geometric structures arranged in a periodic array. Their pore size, wall thickness, and density are completely consistent, and their structural configuration is relatively fixed. They can usually be mass-produced using simple molds. However, their mechanical properties are uniformly distributed in space, making it difficult to perform targeted optimization for the differentiated stress requirements of different functional areas.

[0045] This scheme preferably uses a topological structure for the honeycomb structure of the energy absorption layer 21 and the rigid constraint layer 22. This structure is a honeycomb porous structure with spatially non-uniform distribution characteristics, generated by existing topology optimization algorithms. Specifically, its pore size, wall thickness, density, orientation, and defect distribution all exhibit spatial non-uniformity, adaptively generated by the optimization algorithm based on the load transfer path and stiffness requirements. By setting both the energy absorption layer and the rigid constraint layer as topological structures, the honeycomb configuration of each functional layer is no longer limited to a regular geometric form, but can be spatially differentiated according to the actual stress state. This achieves efficient dissipation of impact energy in the energy absorption layer and high rigidity support in the precision wiring area in the rigid constraint layer.

[0046] It should be noted that topology optimization is a structural design method based on mathematical calculations in the prior art. Its basic principle is to optimize the distribution of materials in space within a given design domain, with material usage as a constraint and a certain performance index of the structure as the objective function, through finite element analysis and iterative calculations, thereby obtaining a structural configuration that meets specific performance requirements. The topology structure in this case was calculated and designed according to the actual needs of the test base using conventional topology optimization methods in this field, and will not be elaborated further here.

[0047] To further explain, the trace 31 includes a trace body 311 and a modulus transition ring 312 surrounding the outside of the trace body 311, and the elastic modulus of the modulus transition ring 312 decreases from the inside to the outside. The thickness of the wiring body 311 is 100-200 μm; The thickness of the modulus transition ring 312 is 0.1–0.5 mm; A mechanical interlock structure is provided between the rigid constraint layer 22 and the modulus transition ring 312.

[0048] The 311 trace body has a thickness of 100μm to 200μm and is made of a relatively hard material to meet the requirements of signal transmission for trace rigidity and impedance stability. While the honeycomb structure layer (especially the rigid constraint layer) has a certain degree of rigidity, its material properties differ from those of the trace body. If the trace body and the rigid constraint layer are in direct contact, a sudden "cliff-like" change in stiffness can easily occur between them. Under impact loads, stress concentration is likely to occur at the interface, leading to delamination failure and affecting the service life of the test socket and the reliability of signal transmission.

[0049] In another preferred embodiment of this technical solution, such as Figure 2 As shown, the trace 31 in this scheme further includes a trace body 311 and a modulus transition ring 312 surrounding the outside of the trace body 311. By setting the modulus transition ring 312 and making the elastic modulus of the modulus transition ring 312 gradually decrease from the inside to the outside, a stiffness gradient transition region can be constructed between the trace body 311 and the rigid constraint layer 22, eliminating the abrupt change in stiffness between the two, so that stress can be smoothly transferred and dispersed in the interface region, thereby effectively avoiding excessive shear stress on a single interface, significantly reducing the risk of delamination, and improving the structural integrity and long-term reliability of the test seat under impact conditions.

[0050] Furthermore, a mechanical interlocking structure (not shown in the figure) is provided between the rigid constraint layer 22 and the modulus transition ring 312. In one specific embodiment, the mechanical interlocking structure can be achieved by providing mutually cooperating protrusions and recesses on the contact surfaces of the rigid constraint layer 22 and the modulus transition ring 312. For example, the rigid constraint layer 22 printed using FDM technology forms micro-protrusions on its surface, and the modulus transition ring 312 printed using DLP / SLA technology forms grooves at corresponding positions. The two achieve mechanical locking through the interlocking of the protrusions and grooves. The mechanical interlocking structure can be implemented without relying on the chemical compatibility of the interlayer materials. Even when using dissimilar materials with significantly different chemical properties, a strong bond can be achieved through physical interlocking. In addition, under impact loads, the mechanical interlocking structure can further suppress interlayer slippage and separation through the shear resistance between the protrusions and recesses, enhancing the structural stability of the test fixture under dynamic load conditions.

[0051] To further explain, the modulus transition ring 312 includes an inner ring 3121, a middle ring 3122, and an outer ring 3123 arranged sequentially from the inside to the outside; The elastic modulus of the inner ring 3121 is 5-10 GPa; The elastic modulus of the middle ring 3122 is 1-5 GPa; The elastic modulus of the outer ring 3123 is 0.1 to 1 GPa.

[0052] As a preferred embodiment of the above, the modulus transition ring 312 further includes an inner ring 3121, a middle ring 3122, and an outer ring 3123 arranged sequentially from the inside to the outside. The three rings construct a continuous stiffness gradient transition region through differentiated configuration of elastic modulus. The inner ring 3121 provides rigid constraints, the middle ring 3122 realizes gradient connection, and the outer ring 3123 completes flexible buffering and residual energy absorption. The three rings work together to form a complete modulus gradient transition system, which further eliminates the risk of stress concentration and delamination failure caused by stiffness mismatch between the wiring body 311 and the honeycomb structure layer 2 (especially the rigid constraint layer 22), and significantly improves the structural stability and test reliability of the test fixture under high-speed signal transmission and complex load conditions.

[0053] In one specific embodiment, the inner ring 3121 is set close to the trace body 311 and can be made of ceramic-reinforced resin material by 3D printing. It provides high rigidity constraint for the trace body 311, ensuring that the trace maintains positional accuracy under impact loads and long-term use, and avoiding signal transmission path deviation that affects impedance consistency. The middle ring 3122 can use a mixture of TPU and resin as the matrix material and add 5wt% to 15wt% nano-silica particles for reinforcement. This layer serves as a transition for stiffness gradient changes in the entire modulus transition ring 312. Its elastic modulus forms a continuous transition between the inner ring 3121 and the outer ring 3123, effectively eliminating stress concentration points caused by abrupt stiffness changes and ensuring smooth stress attenuation during radial transmission. The outer ring 3123 is located close to the rigid constraint layer 22 and can be made of elastomeric material by 3D printing. It is responsible for absorbing the residual impact energy transmitted from the rigid constraint layer 22, and at the same time, it flexibly connects the modulus transition ring 312 with the upper and lower structure to further buffer the residual impact and prevent stress accumulation at the interface.

[0054] In another specific embodiment, the inner ring 3121, the middle ring 3122, and the outer ring 3123 can be integrally formed using a 3D printing multi-material extrusion system. The material switching speed is controlled within 0.5 seconds to ensure a continuous and uninterrupted modulus gradient between the three layers, avoiding interface defects caused by material switching delays. With the above configuration, the overall interfacial shear strength of the modulus transition ring can reach over 20 MPa, ensuring the bonding reliability of each layer interface under impact conditions.

[0055] To further explain, the trace body 311 includes a metal layer 3111, an adhesive layer 3112, and a conductive silver paste layer 3113 arranged sequentially from bottom to top; The thickness of the metal layer 3111 is 50-100 μm, and the material of the metal layer 3111 is copper or nickel; The thickness of the adhesive layer 3112 is 5-10 μm, and the material of the adhesive layer 3112 is conductive adhesive; The conductive silver paste layer 3113 has a thickness of 50-100 μm and includes silver powder, the content of which is 60-80 wt%.

[0056] As another preferred embodiment, the trace body 311 further includes a metal layer 3111, an adhesive layer 3112, and a conductive silver paste layer 3113 arranged sequentially from bottom to top. The metal layer 3111 acts as a rigid skeleton to constrain displacement and ensure impedance stability. The adhesive layer 3112 achieves strong interlayer bonding and shear stress transfer. The conductive silver paste layer 3113 maintains conductive continuity under deformation conditions due to its ductility. The three-layer structure is rigid-flexible and functionally complementary, effectively balancing the contradictory requirements of conductivity and positional stability within the same trace through a multi-layered heterogeneous structure, thus ensuring both structural stability and signal transmission reliability under impact conditions.

[0057] Specifically, the metal layer 3111 is made of copper or nickel. This layer serves as the underlying framework of the trace body 311, utilizing its high rigidity to constrain the displacement and deformation of the entire trace under impact conditions, ensuring that the geometric position of the trace does not significantly shift, thereby guaranteeing impedance stability. The adhesive layer 3112 can be made of conductive adhesive. This layer is responsible for firmly bonding the metal layer 3111 and the conductive silver paste layer 3113 together, and effectively transmitting the shear stress between them under impact loads, preventing interlayer slippage and separation. The conductive silver paste layer 3113, as the conductive functional layer for signal transmission, utilizes the inherent ductility and strain tolerance of silver paste (greater than 50%) to deform along with the underlying structure without breaking when microscopic deformation occurs due to impact, ensuring the continuity of the conductive path under dynamic conditions and guaranteeing stable transmission of high-speed signals.

[0058] In one specific embodiment, the metal purity in the metal layer 3111 is preferably 99.9% or higher to ensure the consistency and stability of material properties, and selective laser sintering or embedding molding is employed. The adhesive layer 3112 can be a conductive adhesive conventional in the art. The conductive silver paste layer refers to a conductive functional layer formed by using silver powder as a conductive filler and curing it after direct writing molding.

[0059] To further explain, the thickness of the base support layer 1 is 0.05-0.2 mm, the elastic modulus is 0.1-0.5 GPa, and the elongation at break is >300%.

[0060] In one specific embodiment, the substrate support layer 1 can be printed using FDM process with TPU (Shore 85A) material.

[0061] To further explain, the thickness of the surface protective layer 4 is 5 to 10 μm, and the surface protective layer 4 comprises a silane coupling agent and cyanoacrylate.

[0062] In one specific embodiment, the silane coupling agent can be γ-aminopropyltriethoxysilane, one end of which can form a chemical bond with the surface of inorganic materials (such as ceramic particles, metal traces, etc.), while the other end has good compatibility with the cyanoacrylate organic resin matrix. This achieves a strong interfacial bond between inorganic and organic materials at the molecular level, enhancing the bonding strength between the surface protective layer 4 and the underlying structural layers. Furthermore, the surface protective layer 4 can be applied to the surface of the test trace layer 3 by spraying or dip coating and cured at room temperature for 24 hours to form the desired structure.

[0063] It should be noted that cyanoacrylate refers to a class of fast-curing adhesive materials with cyanoacrylate monomers as the main component. Its molecular structure contains cyano groups (-CN) and ester groups (-COOR). It can rapidly undergo anionic polymerization and cure under the initiation of trace amounts of water or a weak alkali, exhibiting characteristics such as fast curing speed and high adhesive strength. The specific formulation of surface protective layer 4 can be configured according to actual applications, and is not limited in this case.

[0064] To further clarify, the probe 5 is a conductive elastic post.

[0065] Compared to traditional hard metal probes, probe 5 uses a conductive elastic post formed by 3D printing, which has the characteristics of flexible surface contact, short path and low impedance, which helps to further eliminate the source of test error and make the entire test seat system more precise, reliable and efficient.

[0066] In one specific embodiment, probe 5 establishes an electrical connection with the memory chip 6 under test through a solder ball at the bottom.

[0067] The above description is merely an exemplary embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention specification and drawings under the technical concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A memory chip test socket, characterized in that, It includes, from bottom to top, a base support layer, a honeycomb structure layer, a test trace layer, and a surface protective layer; The test wiring layer is provided with a number of wirings, and the wirings are partially located inside the honeycomb structure layer; The trace includes a signal input terminal and a signal output terminal; the signal input terminal is connected to a probe, and the tip of the probe protrudes from the surface protective layer, the probe being used for electrical connection with the memory chip under test; the signal output terminal protrudes from the honeycomb structure layer, the signal output terminal being used for electrical connection with the test equipment.

2. The memory chip test socket as described in claim 1, characterized in that, The cellular structure layer includes an energy absorption layer and a rigid constraint layer arranged sequentially from bottom to top; The energy-absorbing layer has an elastic modulus of 0.1–0.5 GPa, an elongation at break of >300%, and an energy absorption efficiency of >85%. The elastic modulus of the rigid constraint layer is 5-15 GPa, and the bending strength is >80 MPa.

3. The memory chip test socket as described in claim 2, characterized in that, The energy absorption layer has a relative density of 8-22%, a honeycomb pore size of 2-3 mm, a honeycomb wall thickness of 0.15-0.5 mm, and a thickness of 0.05-0.2 mm. The rigid constraint layer has a relative density of 40-55%, a honeycomb pore size of 0.5-1 mm, a honeycomb wall thickness of 0.55-0.9 mm, and a thickness of 0.01-0.1 mm.

4. The memory chip test socket as described in claim 3, characterized in that, Both the energy absorption layer and the rigid constraint layer have cellular structures that are topological structures.

5. The memory chip test socket as described in claim 2, characterized in that, The trace includes a trace body and a modulus transition ring surrounding the outside of the trace body, and the elastic modulus of the modulus transition ring decreases from the inside to the outside. The thickness of the wiring body is 100-200 μm; The thickness of the modulus transition ring is 0.1–0.5 mm; A mechanical interlocking structure is provided between the rigid constraint layer and the modulus transition ring.

6. The memory chip test socket as described in claim 5, characterized in that, The modulus transition ring includes an inner ring, a middle ring, and an outer ring arranged sequentially from the inside to the outside; The elastic modulus of the inner ring is 5–10 GPa; The elastic modulus of the middle ring is 1-5 GPa; The elastic modulus of the outer ring is 0.1 to 1 GPa.

7. The memory chip test socket as described in claim 5, characterized in that, The trace body includes a metal layer, an adhesive layer, and a conductive silver paste layer arranged sequentially from bottom to top; The thickness of the metal layer is 50–100 μm; The thickness of the adhesive layer is 5–10 μm; The conductive silver paste layer has a thickness of 50-100 μm and includes silver powder with a content of 60-80 wt%.

8. The memory chip test socket as described in claim 1, characterized in that, The thickness of the base support layer is 0.05-0.2 mm, the elastic modulus is 0.1-0.5 GPa, and the elongation at break is >300%.

9. The memory chip test socket as described in claim 1, characterized in that, The thickness of the surface protective layer is 5 to 10 μm, and the surface protective layer comprises a silane coupling agent and cyanoacrylate.

10. The memory chip test socket as described in claim 1, characterized in that, The probe is a conductive elastic column.

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