A continuous gradient doped zinc oxide varistor chip and a method for manufacturing the same

Abstract

The application relates to the field of electronic component manufacturing, and discloses a continuously gradient-doped zinc oxide pressure-sensitive resistor chip and a preparation method thereof. The chip is symmetrically distributed from inside to outside along the thickness direction and sequentially comprises a center layer, an intermediate transition layer and a surface enrichment layer. Each layer is based on a pretreated zinc oxide coated with graphene and a variety of metal oxides as a basic material, and the intermediate transition layer and the surface enrichment layer are respectively externally added with aluminum oxide and silver oxide in different proportions. Through a layered powder laying and high-temperature co-sintering process, long-range deep thermal diffusion of aluminum and silver elements occurs in the bismuth-rich liquid phase, and a continuously gradient-increasing distribution structure without a physical interface is formed in the chip. The application eliminates the interlayer thermal stress concentration problem of a traditional multilayer structure, reduces the surface contact resistance, maintains the high potential barrier characteristic of the center area, and realizes the compatibility of high pressure-sensitive voltage, large current flow capacity, excellent thermal shock resistance and excellent aging resistance.

Description

Technical Field

[0001] This invention relates to the field of electronic component manufacturing technology, and in particular to a continuously gradient doped zinc oxide varistor chip and its preparation method. Background Technology

[0002] Zinc oxide varistors, as core surge protection components, are widely used in overvoltage protection of power systems and electronic equipment. With the increasing demands for surge protection levels in modern electronic equipment, varistor chips must simultaneously possess high voltage sensitivity and large current capacity. To reduce the bulk resistance of the ceramic body and the contact resistance with external electrodes to improve surge resistance, the conventional method is to dope zinc oxide materials with donor elements such as aluminum and silver. However, in traditional homogeneous doping systems, aluminum and silver elements are uniformly distributed throughout the global crystal network, inevitably leading to an increase in electron concentration within the grains and a reduction in the overall height of the double Schottky barrier at grain boundaries. This directly causes a sharp drop in macroscopic varistor voltage and a surge in nonlinear leakage current, making it difficult to resolve the inherent physical contradiction between high voltage sensitivity and large current capacity.

[0003] To achieve spatial decoupling of electrical parameters, existing technologies attempt to employ multilayer heterogeneous structures, using a highly doped formulation on the chip surface layer while maintaining a low-doped or pure zinc oxide formulation in the central layer. However, in actual manufacturing, directly stacking, pressing, and sintering powders of different concentrations results in significant macroscopic physical step interfaces between the layers. Because zinc oxide powders with different formulations exhibit varying volume shrinkage rates during high-temperature sintering, and because the coefficients of thermal expansion and thermal conductivity of the formed layers inherently differ, the expansion and contraction deformations of different layers cannot be coordinated during the sintering cooling stage and later when subjected to high-energy thermal shocks accompanied by transient high currents. This physical mismatch at the material interfaces generates high concentrated shear stress at the interlayer boundaries. When the stress exceeds the fracture toughness limit of the ceramic grain boundary, microcracks easily develop and propagate along the parallel cross-section, leading to delamination, cracking, or even explosion of the resistor chip under alternating electrothermal conditions.

[0004] Furthermore, under long-term continuous DC bias voltage and high-temperature operating conditions, the inherent interstitial zinc ions and oxygen vacancies within the zinc oxide ceramic lattice tend to drift directionally along conventional grain boundary channels. A large amount of migrating ionic material accumulates at the grain boundary depletion layer interface, gradually neutralizing the negative charge layer at the interface. This causes a structural degradation of the double Schottky barrier height with prolonged operation, ultimately resulting in a degradation of the chip's nonlinear conductivity mechanism and an increase in leakage current, making it difficult to meet the technical requirements for accelerated aging lifespan at high temperatures in high-reliability applications. Summary of the Invention

[0005] The purpose of this invention is to provide a continuously gradient doped zinc oxide varistor chip and its fabrication method, which solves the problem that existing zinc oxide varistors are difficult to simultaneously achieve high voltage sensitivity and high current carrying capacity, and that interlayer stress delamination failure is prone to occur under electrothermal shock when using traditional multilayer heterostructures.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] In a first aspect, the present invention provides a continuously gradient-doped zinc oxide varistor chip, employing the following technical solution:

[0008] The chip is symmetrically distributed from the inside to the outside along the thickness direction, and includes a central layer, an intermediate transition layer and a surface enrichment layer in sequence.

[0009] The central layer is composed of a base zinc oxide material, which comprises, by weight, the following:

[0010] Pretreatment with 90-95 parts zinc oxide, 1.5-2.5 parts bismuth trioxide, 0.5-1.0 parts cobalt oxide, 0.3-0.6 parts manganese dioxide, and 0.5-1.2 parts antimony trioxide;

[0011] The intermediate transition layers are symmetrically disposed on both sides of the central layer, and the intermediate transition layers are composed of the basic zinc oxide material plus 0.5-1.5 parts by weight of aluminum oxide;

[0012] The surface enrichment layers are symmetrically disposed on the outside of each of the intermediate transition layers. The surface enrichment layers are composed of the base zinc oxide material plus 1.0-2.5 parts by weight of aluminum oxide and 0.2-0.5 parts by weight of silver oxide.

[0013] Within the chip, the content of aluminum and silver elements increases in a gradient from the central layer to the surface enrichment layer.

[0014] By adopting the above technical solution, the microscopic element distribution inside the material is reconstructed and the macroscopic physical interface is eliminated due to the use of multi-layer component laying combined with a high-temperature co-sintering diffusion mechanism. Therefore, it achieves the effect of simultaneously possessing high voltage sensitivity and high current capacity, as well as excellent thermal shock resistance. The specific mechanism proceeds and evolves according to the following steps:

[0015] Step 1: Liquid network construction and interface ablation. During the high-temperature sintering stage, the bismuth trioxide phase in the formulation transforms into a bismuth-rich liquid phase. This liquid phase wets and flows along the zinc oxide grain boundaries, acting as a mass transfer medium to dissolve and reconstruct the physical step interfaces between the surface enrichment layer, intermediate transition layer, and central layer left over from the powder pressing stage, forming a continuous grain boundary network channel that runs through the entire material.

[0016] Step 2: Long-range thermodynamic diffusion of doped atoms. High concentrations of aluminum and silver pre-placed in the surface enrichment layer and intermediate transition layer undergo long-range deep diffusion into the central layer, driven by both the activation energy provided by the high sintering temperature and the thermodynamic gradient generated by the concentration difference within the material, via bismuth-rich liquid phase channels and intrinsic lattice vacancies. Due to the buffering effect of the intermediate transition layer, the concentration distribution of aluminum and silver transforms from an initial step-like discontinuity into a smooth, continuous concentration decrease curve.

[0017] Step 3: Independent decoupling of micro-area electrical parameters. The surface enrichment layer retains a high concentration of aluminum and silver donor doping, forming a low-resistivity surface ohmic contact region. This reduces the contact resistance with the external electrode, minimizing Joule heat dissipation caused by transient high-current surges and improving current carrying capacity. The central layer is minimally affected by aluminum diffusion, maintaining the high double Schottky barrier characteristics of the pure zinc oxide network, ensuring macroscopic high voltage sensitivity and low leakage current.

[0018] Step 4: Thermal stress gradient dissipation mechanism. The continuous and smooth gradient distribution of aluminum and silver ensures that the coefficient of thermal expansion and thermal conductivity of the entire ceramic chip exhibit a continuous and stepless evolution along the thickness direction. When the chip is subjected to severe thermal shock generated by surge current, the volume expansion deformation of the crystal lattice remains spatially consistent, avoiding the reflection and accumulation of stress waves at the heterogeneous interface, and eliminating delamination cracking defects caused by thermal stress concentration from a physical mechanism perspective.

[0019] Preferably, the powder filling weight of the central layer accounts for 40%-60% of the total powder filling weight of the chip; the powder filling weight of the intermediate transition layers on both sides accounts for 15%-25% of the total powder filling weight of the chip; and the powder filling weight of the surface enrichment layers on both sides accounts for 5%-15% of the total powder filling weight of the chip.

[0020] By adopting the above technical solution, the geometric thickness ratio of each functional layer is limited. The surface layer thickness accounts for 5%-15%, which can provide sufficient but not excessive diffusion sources. The central layer maintains a dominant absolute thickness of 40%-60%, ensuring that the diffusion front does not penetrate and destroy the high-barrier grain boundary structure of the core region. At the same time, the thickness ratio of the transition layer ensures the smoothness of the concentration gradient and avoids local concentration abrupt changes caused by excessively short diffusion paths.

[0021] Preferably, the pretreated zinc oxide in the basic zinc oxide material is zinc oxide particles coated with a composite layer of silane coupling agent and graphene; and in the pretreated zinc oxide, the mass ratio of zinc oxide particles, silane coupling agent and graphene is 1:(0.01-0.02):(0.05-0.06).

[0022] By adopting the above technical solution, a synergistic mechanism between grain boundary steric hindrance and conductive network is introduced. During sintering, graphene is positioned at the zinc oxide grain boundaries. Its two-dimensional layered structure, under high temperature and long-term DC bias conditions, acts as a spatial physical barrier to the directional drift of interstitial zinc ions and oxygen vacancies. This steric effect suppresses the accumulation of a large number of charge carriers in the grain boundary depletion layer, delaying the decay of the double Schottky barrier height, thereby significantly improving the high-temperature accelerated aging life and nonlinear parameter stability of the varistor chip.

[0023] Secondly, the present invention provides a method for fabricating a continuously gradient-doped zinc oxide varistor chip, employing the following technical solution:

[0024] Powders were prepared and granulated independently according to the formulas of the central layer, the intermediate transition layer and the surface enrichment layer, respectively, to obtain central layer granules, transition layer granules and surface layer granules.

[0025] In a pressing mold, powder is layered and filled in the order of powder layering: surface layer granules, transition layer granules, center layer granules, transition layer granules, and surface layer granules. The green body is then formed in one pressing process.

[0026] The green body is subjected to debinding treatment to obtain a first intermediate;

[0027] The first intermediate is placed in a sintering furnace for high-temperature co-sintering, wherein the maximum temperature of the high-temperature co-sintering is controlled at 1150℃-1260℃ and the holding time is 4-5h.

[0028] After the heat preservation is completed, the resistor chip is obtained by cooling in the furnace.

[0029] By adopting the above technical solution, granulation, programmed powder spreading, and high-temperature co-sintering processes are organically combined. Independent granulation prevents disordered cross-contamination of different formulation components during the dry powder mixing stage. Specific temperature windows and holding times control the viscosity and fluidity of the bismuth trioxide liquid phase, providing aluminum and silver elements with just the right thermodynamic kinetic energy to complete grain boundary diffusion reconstruction without causing phase separation, thus achieving the regulation of the gradient distribution morphology of components inside the material.

[0030] Preferably, the pretreated zinc oxide in the base zinc oxide material is prepared by the following method:

[0031] Zinc oxide powder was dispersed in deionized water, a silane coupling agent was added and stirred at 58°C, the pH was adjusted to 5 with glacial acetic acid, and after filtration and washing, it was dispersed in an ethanol aqueous solution containing graphene. After ultrasonic dispersion and spray drying, the pretreated zinc oxide was obtained.

[0032] By employing the above technical solution, uniform composite modification of powder surfaces was achieved using chemical grafting technology. The reaction mechanism includes the following steps:

[0033] Step 1: The silane coupling agent undergoes a hydrolysis reaction in a weakly acidic aqueous environment to generate silanol.

[0034] Step 2: The generated silanol undergoes a dehydration condensation reaction with the free hydroxyl groups on the surface of zinc oxide particles, chemically bonding silane molecules to the zinc oxide surface.

[0035] Step 3: After grafting organic functional groups, the surface polarity of zinc oxide is reduced. When mixed with graphene dispersion, the graphene sheets are uniformly coated on the surface of zinc oxide particles through van der Waals forces and spatial entanglement with silane organic groups, preventing abnormal growth of zinc oxide grains during subsequent sintering.

[0036] Preferably, the independent granulation operation specifically includes: adding the prepared powders of each layer to deionized water for water-soluble ball milling, adding polyvinyl alcohol solution as a binder, mixing evenly, and then spray drying in a dryer with an outlet temperature of 90℃~110℃ to obtain the central layer granules, the transition layer granules, and the surface layer granules with a particle size between 100μm and 110μm.

[0037] By adopting the above technical solution, the particle size distribution of the granules was precisely controlled. The uniform particle size of 100μm to 110μm ensured that the flowability and packing density of each layer of powder in the mold were highly consistent, avoiding defects such as local looseness or uneven density during layer pressing, and ensuring the isotropy of the sintering shrinkage process.

[0038] Preferably, during the layered powder spreading process, the weight percentage of each layer of granules is controlled as follows: 40%-60% for the central layer; 15%-25% for the transition layer on one side; and 5%-15% for the surface layer on one side.

[0039] Furthermore, the density of the green body after pressing is controlled to be 3.25 g / cm³. 3 ~3.4g / cm 3 .

[0040] By adopting the above technical solution, the green body density was preset to 3.25 g / cm³. 3 ~3.4g / cm 3 The initial density ensures that the particles maintain an appropriate physical contact area, and the capillary force is moderate during subsequent high-temperature co-sintering. This is beneficial for liquid phase wetting and also leaves enough shrinkage and exhaust channels to prevent the formation of closed-pore air gaps inside.

[0041] Preferably, the specific temperature and time control for the glue removal process are as follows:

[0042] The temperature is increased from room temperature to 200℃ over 6-7 hours; then increased to 450℃; and then from 450℃ to 590℃-612℃.

[0043] The mixture is kept at 590℃ to 612℃ for 1.7 to 2.5 hours; finally, it is cooled down to below 100℃ and removed from the furnace to obtain the first intermediate.

[0044] By employing the above technical solution, a multi-stage, slow heating process is used to fully decompose and carbonize the binder polyvinyl alcohol and other organic residues under an oxidizing atmosphere, allowing them to be slowly discharged in gaseous form. This avoids stress delamination defects at the interfaces of multi-layered structures caused by excessively rapid heating and instantaneous gas release.

[0045] Preferably, after obtaining the resistor chip, the process further includes an annealing heat treatment: cleaning the resistor chip, placing the cleaned resistor chip in an annealing furnace, heating it to 590℃~612℃ and holding it at that temperature for 2.5~3.1h, and then slowly cooling it down before removing it from the furnace.

[0046] By employing the above technical solution, the quenching process after high-temperature sintering will leave residual thermal stress and some oxygen vacancy defects inside the material. The annealing operation provides a thermal relaxation process, which causes fine-tuning of the crystal lattice, releases residual stress, and promotes the diffusion of oxygen from the environment to the surface of the ceramic body, repairing the oxygen-deficient layer at the grain boundaries, and further improving the macroscopic nonlinear coefficient.

[0047] Preferably, after the product annealing heat treatment, the process further includes preparing an electrode: printing silver paste with a silver content of 70wt% to 80wt% on the outer surface of the surface enrichment layer on both sides of the resistor chip, and performing a heat preservation reduction treatment at a temperature of 590℃ to 610℃ in a reduction furnace to obtain a conductive electrode.

[0048] By adopting the above technical solution, the surface enrichment layer itself has a high silver doping base. After printing silver paste, a heat preservation and reduction treatment is performed, which causes the silver particles in the paste to sinter and connect at the grain boundaries, forming a metal-semiconductor dense ohmic contact network with the ceramic surface enrichment layer with a low interface barrier, thus eliminating the additional resistance dissipation caused by poor electrode contact.

[0049] In summary, the present invention has at least one of the following beneficial technical effects:

[0050] 1. This invention employs a layered powder-laying process comprising a central layer, an intermediate transition layer, and a surface enrichment layer, along with high-temperature co-sintering treatment. This process promotes long-range deep diffusion of aluminum oxide and silver oxide in the bismuth-rich liquid phase medium. Because a microstructure without physical interfaces is constructed within the resistor chip, with aluminum and silver elements distributed in a continuous gradient, the thermal expansion coefficient and thermal conductivity of the overall material along the thickness direction continue to evolve. This disperses the severe thermal stress generated during transient high-current pulse injection, ultimately achieving performance compatibility of the varistor chip in terms of high current capacity, high voltage sensitivity, and excellent mechanical thermal shock resistance.

[0051] 2. This invention grafts and coats zinc oxide particles in a basic zinc oxide material with a two-dimensional layered graphene composite layer using a silane coupling agent. Because the graphene is positioned at the microscopic zinc oxide grain boundaries, it creates a spatial physical steric hindrance effect, which blocks the directional drift of zinc ions and oxygen vacancies in the interstitial spaces within the lattice under high-temperature working environments and long-term continuous DC bias voltage conditions. This suppresses the abnormal accumulation and neutralization reaction of charge carriers in the grain boundary depletion layer, thus delaying the degradation and decay of the grain boundary double Schottky barrier height, improving the high-temperature accelerated aging life of the varistor chip and the long-term stability of macroscopic leakage parameters.

[0052] 3. This invention provides a surface enrichment layer with a high proportion of aluminum oxide and silver oxide on the outermost side of the resistor chip, and prints a high-silver-content silver paste on the outer side of the surface enrichment layer for heat treatment with heat preservation and reduction. Due to the high concentration of donor doping in the surface enrichment layer, the grain boundary barrier in the micro-region is reduced, allowing the silver particles that are sintered and connected after reduction to form a dense, low-resistance ohmic contact with the ceramic network. This reduces the contact resistance between the chip and the external metal interface, thus limiting the concentrated dissipation of Joule heat generated at the electrode interface when a large surge current passes through during a lightning strike, and avoiding thermal breakdown failure caused by local melting and penetration of the electrode. Attached Figure Description

[0053] Figure 1 This is a schematic diagram of the method flow of the present invention;

[0054] Figure 2 This is a graph showing the change in sheet resistance as a function of grinding depth according to the present invention.

[0055] Figure 3 This is a comparison diagram of the flexural strength before and after thermal shock cycling of the present invention;

[0056] Figure 4 This is a comparison diagram of leakage current before and after high-temperature accelerated aging of the present invention. Detailed Implementation

[0057] The technical solution of the present invention will be described in detail below with reference to specific embodiments. Those skilled in the art should understand that the following embodiments are only for explaining the present invention and should not be considered as limiting the scope of protection of the present invention. All equivalent or similar substitutions and modifications fall within the scope of protection of the present invention.

[0058] Preparation Example 1:

[0059] This preparation example provides a method for preparing pretreated zinc oxide, wherein the mass ratio of zinc oxide particles, silane coupling agent, and graphene is 1:0.01:0.05, and includes the following steps:

[0060] Add 1000g of zinc oxide powder to 2000mL of deionized water and disperse by mechanical stirring. Add 10g of silane coupling agent KH-560 and continue stirring for 60min under constant temperature water bath heating to 58℃.

[0061] Slowly add glacial acetic acid to precisely adjust the pH of the mixture to 5, and continue the reaction for 120 minutes;

[0062] After the reaction was completed, the product was filtered and washed three times with deionized water to obtain a modified zinc oxide wet filter cake.

[0063] Add 50g of graphene to 3000mL of a mixed solution of anhydrous ethanol and deionized water in a volume ratio of 1:1, then add the above-mentioned modified zinc oxide wet filter cake, and ultrasonically disperse at a frequency of 40kHz for 60min to form a uniform suspension.

[0064] The suspension was pumped into a spray dryer and spray dried at an inlet air temperature of 150°C and an outlet air temperature of 90°C. The dried powder was collected to obtain pretreated zinc oxide A.

[0065] Preparation Example 2:

[0066] This preparation example provides a method for preparing pretreated zinc oxide, wherein the mass ratio of zinc oxide particles, silane coupling agent, and graphene is 1:0.015:0.055, and includes the following steps:

[0067] Add 1000g of zinc oxide powder to 2000mL of deionized water and disperse by mechanical stirring. Add 15g of silane coupling agent KH-560 and continue stirring for 60min under constant temperature water bath heating to 58℃.

[0068] Slowly add glacial acetic acid to precisely adjust the pH of the mixture to 5, and continue the reaction for 120 minutes;

[0069] After the reaction was completed, the product was filtered and washed three times with deionized water to obtain a modified zinc oxide wet filter cake.

[0070] Add 55g of graphene to 3000mL of a mixed solution of anhydrous ethanol and deionized water in a volume ratio of 1:1, then add the above-mentioned modified zinc oxide wet filter cake, and ultrasonically disperse at a frequency of 40kHz for 60min to form a uniform suspension.

[0071] The suspension was pumped into a spray dryer and spray dried at an inlet air temperature of 150°C and an outlet air temperature of 90°C. The dried powder was collected to obtain pretreated zinc oxide B.

[0072] Preparation Example 3:

[0073] This preparation example provides a method for preparing pretreated zinc oxide, wherein the mass ratio of zinc oxide particles, silane coupling agent, and graphene is 1:0.02:0.06, and includes the following steps:

[0074] 1000g of zinc oxide powder was added to 2000mL of deionized water and mechanically stirred to disperse it. 20g of silane coupling agent KH-560 was added to it and stirred continuously for 60min under constant temperature water bath heating to 58℃.

[0075] Slowly add glacial acetic acid to precisely adjust the pH of the mixture to 5, and continue the reaction for 120 minutes;

[0076] After the reaction was completed, the product was filtered and washed three times with deionized water to obtain a modified zinc oxide wet filter cake.

[0077] Add 60g of graphene to 3000mL of a mixed solution of anhydrous ethanol and deionized water in a volume ratio of 1:1, then add the above-mentioned modified zinc oxide wet filter cake, and ultrasonically disperse at a frequency of 40kHz for 60min to form a uniform suspension.

[0078] The suspension was pumped into a spray dryer and spray dried at an inlet air temperature of 150°C and an outlet air temperature of 90°C. The dried powder was collected to obtain pretreated zinc oxide C.

[0079] Example 1:

[0080] See attached document Figure 1 This embodiment provides a continuously gradient doped zinc oxide varistor chip and its fabrication method, including the following steps:

[0081] Weigh out 90 parts by weight of pretreated zinc oxide A, 1.5 parts by weight of bismuth trioxide, 0.5 parts by weight of cobalt oxide, 0.3 parts by weight of manganese dioxide and 0.5 parts by weight of antimony trioxide, and mix the above raw materials evenly as the base powder of the central layer; add 0.5 parts by weight of aluminum trioxide to the raw materials in the same proportion as the base powder of the central layer and mix evenly as the transition layer powder;

[0082] Add 1.0 part of aluminum oxide and 0.2 part of silver oxide to the raw materials in the same proportion as the above-mentioned core layer base powder, and mix evenly to form the surface layer powder;

[0083] The three powders were independently subjected to water-soluble ball milling. During the ball milling process, a polyvinyl alcohol solution equivalent to 1 wt% of the total weight of each powder was added as a binder. After being mixed evenly, the slurry was pumped into a spray dryer and spray dried at an outlet temperature of 90°C to obtain central layer granules, transition layer granules and surface layer granules with particle sizes between 100 μm and 110 μm.

[0084] In a pressing mold, powder is layered and filled with the aforementioned granular material in the order of powder layering. The weight ratio of each layer of granular material is controlled as follows: lower surface layer 5%, lower transition layer 25%, central layer 40%, upper transition layer 25%, and upper surface layer 5%. A green body is obtained by pressing in one step, and the density of the green body is controlled at 3.25 g / cm³. 3 ;

[0085] The green body is debonded and heated from room temperature to 200°C for 6 hours. It is then heated to 450°C and then from 450°C to 590°C and held at 590°C for 1.7 hours. Finally, it is cooled down in the furnace to below 100°C and removed from the furnace to obtain the first intermediate.

[0086] The first intermediate was placed in a sintering furnace for high-temperature co-sintering, with the maximum temperature controlled at 1150℃ and the holding time at 4h. After the holding time was completed, the resistor chip was cooled with the furnace.

[0087] The resistor chip is cleaned and then placed in an annealing furnace, heated to 590℃ and held for 2.5 hours, and then slowly cooled down and removed from the furnace.

[0088] Silver paste with a silver content of 70wt% was printed on the outer side of the surface enrichment layer on both sides of the resistor chip, and then the chip was subjected to heat preservation reduction treatment at a temperature of 590℃ in a reduction furnace to obtain a conductive electrode.

[0089] Example 2:

[0090] This embodiment provides a continuously gradient doped zinc oxide varistor chip and its fabrication method, including the following steps:

[0091] By weight, weigh 92.5 parts of pretreated zinc oxide B, 2.0 parts of bismuth trioxide, 0.75 parts of cobalt oxide, 0.45 parts of manganese dioxide and 0.85 parts of antimony trioxide, and mix the above raw materials evenly as the base powder for the central layer.

[0092] Add 1.0 part of aluminum oxide to the raw materials in the same proportion as the above-mentioned central layer base powder and mix evenly to form the transition layer powder;

[0093] Add 1.75 parts of aluminum oxide and 0.35 parts of silver oxide to the raw materials in the same proportion as the above-mentioned core layer base powder, mix evenly to form the surface layer powder;

[0094] The three powders were independently subjected to water-soluble ball milling. During the ball milling process, a polyvinyl alcohol solution equivalent to 1.1 wt% of the total weight of each powder was added as a binder. After being mixed evenly, the slurry was pumped into a spray dryer and spray dried at an outlet temperature of 100°C to obtain central layer granules, transition layer granules and surface layer granules with particle sizes between 100 μm and 110 μm.

[0095] In a pressing mold, powder is layered and filled with the aforementioned granular material in the order of powder layering. The weight ratio of each layer of granular material is controlled as follows: lower surface layer 10%, lower transition layer 15%, central layer 50%, upper transition layer 15%, and upper surface layer 10%. A green body is obtained by pressing in one step, and the density of the green body is controlled at 3.35 g / cm³. 3 ;

[0096] The green body is debinded and heated from room temperature to 200°C for 6.5 hours. It is then heated to 450°C, then from 450°C to 600°C and held at 600°C for 2.1 hours. Finally, it is cooled down in the furnace to below 100°C and removed from the furnace to obtain the first intermediate.

[0097] The first intermediate was placed in a sintering furnace for high-temperature co-sintering, with the maximum temperature controlled at 1200℃ and the holding time at 4.5h. After the holding time was completed, the resistor chip was obtained by cooling it in the furnace.

[0098] The resistor chip is cleaned and then placed in an annealing furnace, heated to 600℃ and held for 2.8 hours, and then slowly cooled down and removed from the furnace.

[0099] Silver paste with a silver content of 75wt% was printed on the outer side of the surface enrichment layer on both sides of the resistor chip, and then the chip was subjected to a reduction treatment at a temperature of 600℃ in a reduction furnace to obtain a conductive electrode.

[0100] Example 3:

[0101] This embodiment provides a continuously gradient doped zinc oxide varistor chip and its fabrication method, including the following steps:

[0102] Weigh out 95 parts of pretreated zinc oxide C, 2.5 parts of bismuth trioxide, 1.0 parts of cobalt oxide, 0.6 parts of manganese dioxide and 1.2 parts of antimony trioxide by weight, and mix the above raw materials evenly as the base powder for the central layer.

[0103] Add 1.5 parts of aluminum oxide to the raw materials in the same proportion as the above-mentioned core layer base powder and mix evenly to form the transition layer powder;

[0104] Add 2.5 parts of aluminum oxide and 0.5 parts of silver oxide to the raw materials in the same proportion as the above-mentioned core layer base powder, mix evenly to form the surface layer powder;

[0105] The three powders were independently subjected to water-soluble ball milling. During the ball milling process, a polyvinyl alcohol solution equivalent to 1.25 wt% of the total weight of each powder was added as a binder. After being mixed evenly, the slurry was pumped into a spray dryer and spray dried at an outlet temperature of 110°C to obtain central layer granules, transition layer granules and surface layer granules with particle sizes between 100 μm and 110 μm.

[0106] In a pressing mold, powder is layered and filled with the aforementioned granular material in the order of powder layering. The weight ratio of each layer of granular material is controlled as follows: lower surface layer 5%, lower transition layer 17.5%, central layer 55%, upper transition layer 17.5%, and upper surface layer 5%. A green body is obtained by pressing in one step, and the density of the green body is controlled at 3.4 g / cm³. 3 ;

[0107] The green body is debonded and heated from room temperature to 200°C for 7 hours. It is then heated to 450°C, then from 450°C to 612°C and held at 612°C for 2.5 hours. Finally, it is cooled down in the furnace to below 100°C and removed from the furnace to obtain the first intermediate.

[0108] The first intermediate was placed in a sintering furnace for high-temperature co-sintering, with the maximum temperature controlled at 1260℃ and the holding time at 5h. After the holding time was completed, the resistor chip was obtained by cooling it in the furnace.

[0109] The resistor chip was cleaned and then placed in an annealing furnace, heated to 612℃ and held for 3.1 hours, and then slowly cooled down before being removed from the furnace.

[0110] Silver paste with a silver content of 80wt% was printed on the outer side of the surface enrichment layer on both sides of the resistor chip, and then the chip was subjected to heat preservation reduction treatment at a temperature of 610℃ in a reduction furnace to obtain a conductive electrode.

[0111] Comparative Example 1:

[0112] Compared with Example 2, the difference is that the layered formulation design and layered powder spreading operation are not carried out. Instead, all the raw materials (including all the basic powders and the added aluminum oxide and silver oxide) required to prepare the central layer, transition layer and surface layer in Example 2 are directly combined, mixed evenly and granulated, and then pressed into a single-layer green body in a pressing mold. The rest are the same.

[0113] Comparative Example 2:

[0114] Compared with Example 2, the difference is that the intermediate transition layer is eliminated, that is, no transition layer granules are prepared or laid. In the pressing mold, only the lower surface layer granules, the middle layer granules and the upper surface layer granules are laid in sequence, and the weight ratio of the powder filling material of each layer of granules is adjusted to 10% for the lower surface layer granules, 80% for the middle layer granules and 10% for the upper surface layer granules, and the rest are the same.

[0115] Comparative Example 3:

[0116] Compared to Example 2, the difference lies in the formulation of the core layer base powder, in which pretreated zinc oxide B is replaced with an equal weight of commercially available pure zinc oxide powder that has not undergone any treatment; all other aspects are the same.

[0117] Comparative Example 4:

[0118] Compared with Example 2, the difference is that the maximum temperature during high-temperature co-sintering in the sintering furnace is reduced from 1200°C to 1050°C, while the rest are the same.

[0119] Test Example 1:

[0120] Take five sintered chip samples from Example 2 and Comparative Example 4 without printed silver electrodes, measure the initial thickness of the samples using a micrometer, and mark them.

[0121] The sample is fixed parallel to the sample tray of the precision single-sided grinder, ensuring that the sample surface to be tested is in contact with the grinding tray.

[0122] The initial sheet resistance was measured at five different locations on the sample surface using a four-probe resistance meter. The test data were recorded and the arithmetic mean was calculated as the resistance value at a depth of 0 μm.

[0123] Using 1200-grit silicon carbide sandpaper, the grinding disc speed was set to 50 rpm, and a constant downward pressure of 10 N was applied. Each grinding operation removed approximately 30 μm of material.

[0124] Remove the ground sample and ultrasonically clean it in anhydrous ethanol for 3 minutes to remove surface debris. After drying with nitrogen, use a micrometer to confirm the current actual grinding depth.

[0125] The sheet resistance of the currently exposed surface was measured again using a four-probe resistance tester, and the arithmetic mean of the five test points was recorded.

[0126] Repeat the above steps of grinding, cleaning, thickness measurement, and resistance testing until the cumulative grinding depth reaches 300μm and enters the central layer region.

[0127] Table 1. Grinding Depth and Corresponding Sheet Resistance Test Data for Examples and Comparative Examples

[0128] Grinding depth (μm) Example 2: Sheet resistance (Ω / sq) Comparative example: 4 square resistances (Ω / sq) 0 4.31 6.58 30 5.86 7.12 60 9.42 9.87 90 16.74 86.41 120 31.55 102.73 150 68.21 134.16 180 145.89 158.52 210 287.43 946.85 240 512.67 1105.34 270 856.12 1267.91 300 1348.95 1312.48

[0129] in conclusion:

[0130] See attached document Figure 2 According to the data in Table 1, the sheet resistance of Example 2 shows a continuous and non-linear increasing trend with the increase of polishing depth, and no abrupt jumps occur between adjacent data nodes. The regional conductivity of the varistor is positively correlated with the local concentration of donor doping elements aluminum and silver. The continuous change in the sheet resistance value indicates that aluminum and silver elements form a continuous and smooth concentration gradient distribution inside the chip.

[0131] Under co-sintering conditions at 1200℃, bismuth trioxide melts to form a liquid phase, which wets the zinc oxide grain boundary network, providing channels for element diffusion. Driven by both high temperature and concentration gradient, aluminum and silver atoms in the surface layer undergo deep thermal diffusion to the central layer through the grain boundary liquid phase and lattice vacancies, breaking down the physical step interfaces between the granular material layers during the pressing stage and completing the transformation from a layered structure to a continuous gradient structure.

[0132] The sheet resistance of Comparative Example 4 exhibits a step-like abrupt change with depth. In the grinding depth ranges of 60 μm–90 μm and 180 μm–210 μm, the sheet resistance values ​​show leaps of orders of magnitude. These depth ranges with abrupt changes basically correspond to the physical boundaries between the surface layer, transition layer, and central layer in the initial green body.

[0133] At a sintering temperature of 1050℃, the fluidity and distribution of the bismuth trioxide liquid phase are limited, and the diffusion kinetics of aluminum and silver atoms are insufficient, preventing long-distance interlayer migration. The compositional distribution within the material is constrained by the physical layering state during granulation and powder spreading, resulting in abrupt changes in doping concentration at the interlayer interfaces and failing to form a smooth concentration gradient structure.

[0134] Test Example 2:

[0135] Take 20 resistor chips each from Examples 1-3 and Comparative Example 2 prepared by sintering, and randomly divide them into two groups of 10 chips each.

[0136] The first group of samples underwent initial state testing. An ultrasonic scanning microscope was used to perform non-destructive testing on the chip's interior, extracting data on areas with abnormal acoustic wave reflection. The area ratio of internal microcracks or delamination defects was calculated and recorded. Subsequently, the initial flexural strength of the samples was measured using the three-point bending method on a computer-controlled electronic universal testing machine. The loading rate was set to 0.5 mm / min, and the peak load at sample fracture was recorded, and the flexural strength value was calculated.

[0137] The second group of samples was placed in a liquid bath thermal shock test chamber for thermal shock cycling treatment. The low temperature liquid bath temperature was set to -40℃, the high temperature liquid bath temperature was set to 125℃, the residence time of the samples in each temperature zone was set to 30 min, the transfer time between high and low temperatures was controlled within 10 s, and the total number of cycles was 100.

[0138] After the thermal shock cycle is completed, the sample is removed, the surface of the test liquid is rinsed with deionized water, and the sample is left to stand at room temperature for 24 hours to release residual surface stress.

[0139] Using the same equipment and operating parameters as in step 2, the percentage of delamination defect area and the final flexural strength of the samples after the second set of thermal shock cycle treatments were measured and recorded.

[0140] Table 2. Defect percentage and flexural strength test data before and after thermal shock in the examples and comparative examples.

[0141] Sample Name Initial defect area percentage (%) Initial flexural strength (MPa) Percentage of defect area after thermal shock (%) Flexural strength after thermal shock (MPa) Example 1 0.12 85.43 0.35 82.16 Example 2 0.08 88.61 0.21 86.37 Example 3 0.15 83.27 0.42 79.82 Comparative Example 2 1.24 71.55 15.83 34.29

[0142] in conclusion:

[0143] See attached document Figure 3 According to the data in Table 2, after undergoing thermal shock cycling, the proportion of internal defects in Examples 1-3 remained at a low level, the flexural strength decreased only slightly, and the chip structure remained stable. The addition of an intermediate transition layer containing a moderate proportion of aluminum oxide, combined with the continuous gradient structure formed by the high-temperature liquid phase diffusion mechanism, eliminated the physical interfaces within the material. The smooth transition of compositional distribution resulted in a continuous evolution of the coefficient of thermal expansion along the chip thickness direction, dispersing the thermal stress generated within the material during drastic changes in ambient temperature. The volumetric deformation of the lattice network remained consistent during alternating heating and cooling processes, avoiding grain boundary cracking caused by stress concentration.

[0144] Comparative Example 2 exhibited a high defect area ratio and low flexural strength in its initial state. After 100 thermal shock cycles, its defect area ratio increased by an order of magnitude, and its flexural strength significantly decreased. The absence of an intermediate transition layer resulted in direct contact between the central base layer and the outer surface layer, with the two materials having different coefficients of thermal expansion due to differences in doping composition. Under sintering cooling and subsequent high and low temperature alternating conditions, the inconsistent shrinkage and expansion rates of the two layers generated enormous interlaminar shear stress at the interface. This concentrated stress exceeded the bonding strength of the ceramic grain boundaries, leading to the formation of numerous microcracks that propagated parallel to the surface, eventually evolving into macroscopic delamination and destructive behavior, thus compromising the mechanical integrity of the chip.

[0145] Test Example 3:

[0146] Twenty resistor chips each from Examples 1-3 (which have completed electrode preparation and annealing processes) and Comparative Examples 1, 3, and 4 were selected and placed in a constant temperature and humidity test chamber for 24 hours at 25°C and 50% relative humidity.

[0147] Connect the resistor chips to the test fixture of the varistor DC parameter tester to ensure that the silver electrode surface is in close contact with the test probe without any oxide layer interference.

[0148] Set the DC parameter tester to output a constant DC current test waveform of 1mA for 20ms, measure the voltage across the resistor chip, and record the value as the varistor voltage.

[0149] Based on the varistor voltage value measured in step 3, the tester automatically calculates and outputs a DC bias voltage signal of 75% of the varistor voltage.

[0150] Apply the DC bias voltage to both ends of the resistor chip. After the internal leakage current stabilizes, measure and record the current value flowing through the resistor chip as the leakage current.

[0151] Adjust the tester parameters to output constant DC currents of 1mA and 0.1mA respectively, record the voltage values ​​across the resistor chip under the corresponding conditions, and calculate the nonlinear coefficient using the relevant voltage logarithmic ratio formula.

[0152] Calculate the arithmetic mean of the test data for each group of 20 samples, and complete the statistical analysis of the DC electrical parameters for all batches of samples.

[0153] Table 3. Test Data of Basic DC Electrical Parameters for Examples and Comparative Examples

[0154] Sample Name Varistor voltage (V) Leakage current (μA) Nonlinear coefficients Example 1 482.3 0.86 58.2 Example 2 475.1 0.62 64.7 Example 3 491.5 0.91 55.4 Comparative Example 1 215.8 4.35 31.2 Comparative Example 3 468.9 8.74 28.5 Comparative Example 4 612.4 15.21 19.6

[0155] in conclusion:

[0156] According to the data in Table 3, the varistor voltages of Examples 1-3 remained in the range of 470V-495V, the leakage current was less than 1μA, and the nonlinear coefficient was greater than 50. Comparative Example 1, using a single-layer hybrid structure, saw its varistor voltage decrease to 215.8V. Aluminum elements were uniformly distributed within the bulk phase of the single-layer structure, acting as the main dopant, increasing the electron concentration within the grains and reducing the macroscopic grain boundary barrier height, thus decreasing the varistor voltage value. In these examples, the central layer, without any aluminum or silver additives, retained the high barrier characteristics of the basic zinc oxide formulation, ensuring the overall varistor voltage parameters from a structural perspective.

[0157] Comparative Example 3, using unmodified pure zinc oxide powder, showed an increase in leakage current to 8.74 μA and a decrease in nonlinear coefficient to 28.5. Silane coupling agent and graphene coating treatment suppressed zinc oxide powder agglomeration, resulting in a uniformly distributed microcrystalline network during sintering. Untreated powder agglomeration led to abnormal localized grain growth after sintering, and differences in grain size across different regions caused uneven distribution of microcrystalline boundary heights. Low-barrier grain boundaries provide conductive pathways under an electric field, generating excessive leakage current and reducing the conductivity response in the nonlinear region.

[0158] Comparative Example 4, sintered at 1050℃, showed a leakage current of 15.21 μA and a nonlinear coefficient reduced to 19.6. The sintering temperature setting limited the formation and flow distribution of the bismuth trioxide liquid phase, hindering deep thermal diffusion of elements between layers. The material retained the physical step boundaries formed by powder pressing, and numerous interface defects arose in the interface regions due to lattice dislocations and abrupt compositional changes. These interface defect states disrupted the structural integrity of the zinc oxide grain boundary double Schottky barrier, increasing the probability of electrons tunneling across the barrier and causing a comprehensive deterioration of macroscopic electrical parameters.

[0159] Test Example 4:

[0160] Fifteen resistor chips from Examples 1-3, Comparative Examples 1 and 2 were selected. The initial varistor voltage of each sample was measured using a varistor DC parameter tester, and the data were recorded and the arithmetic mean was calculated.

[0161] The tested resistor chips were installed one by one into the test fixture of the lightning surge waveform generator, and the fixture pressure was adjusted to ensure that the electrode plate was in contact with the silver layer on the surface of the resistor chip.

[0162] Set the output waveform parameters of the lightning surge waveform generator, set the current waveform to the standard 8 / 20μs lightning impulse current wave, and set the peak value of a single impulse current to 6000A.

[0163] The waveform generator is activated to perform a continuous impact test on the resistor chip connected to the test fixture. The test program is set to apply 5 positive impacts first, followed by 5 negative impacts, with a time interval of 60 seconds between adjacent impacts.

[0164] After the impact test is completed, the resistor chip is removed from the fixture and placed in a room temperature environment for 24 hours to allow the heat accumulated inside the chip due to the large current impact to dissipate fully.

[0165] The varistor voltage of the resistor chip was measured again after resting using a varistor DC parameter tester. The physical appearance of the resistor chip was observed and recorded, and the rate of change of varistor voltage before and after the impact was calculated.

[0166] Table 4. Current Capacity Impact Test Data for Examples and Comparative Examples

[0167] Sample Name Initial varistor voltage (V) Voltage of the varistor after impact (V) Varistor voltage change rate (%) Appearance condition description Example 1 481.5 462.8 -3.88 The chip surface is intact, and the silver layer has not turned black. Example 2 476.2 454.1 -4.64 The chip surface is intact and has no cracks. Example 3 490.7 468.9 -4.44 The chip structure is intact, and the silver layer is tightly adhered. Comparative Example 1 216.4 / Short circuit The silver electrode on one side of the chip has partially melted and turned black. Comparative Example 2 478.9 / Unable to measure Macroscopic cracks appeared on the side of the chip, parallel to the cross-sectional direction, with localized breakage and fragmentation.

[0168] Note: " / " means "cannot be measured" or "no data (not applicable)".

[0169] in conclusion:

[0170] According to the data in Table 4, Examples 1-3 showed no physical damage after being subjected to a standard 8 / 20μs high-current surge of 6000A peak, with the varistor voltage change rate remaining between -3% and -5%. The high proportion of alumina and silver oxide added separately to the surface layer formulation adjusted the contact barrier between the ceramic body and the silver paste interface during the reduction sintering stage, forming a low-resistance ohmic contact. During transient high current passage, the low contact resistance limited the concentrated generation of Joule heat. The continuous gradient increase in aluminum and silver elements from the surface to the interior ensured uniform diffusion of the current density as it flowed into the central layer, avoiding localized hot spot effects on the internal conductive pathways.

[0171] Comparative Example 1, employing a single-layer, unlayered formulation, exhibited breakdown short circuits and electrode edge melting during impact testing. Aluminum and silver elements were dispersed throughout the chip bulk phase, resulting in a low donor doping concentration in the surface areas in contact with the electrodes. A high contact resistance existed at the interface between the ceramic bulk and the external silver electrode. During high-current pulse injection, high instantaneous heat dissipation energy was generated at the electrode interface. Localized high temperatures caused the silver electrode to melt and penetrate inwards along the grain boundaries, forming permanent conductive channels that led to thermal breakdown failure of the chip.

[0172] Comparative Example 2 developed macroscopic cracks and fractured after the impact test. The large current surge from a lightning strike passing through the resistor chip within microseconds generates a thermal shock effect. Eliminating the intermediate transition layer leads to a step-like abrupt change in component concentration at the interface between the central and surface layers, causing a hard truncation of the material's thermal expansion coefficient and thermal conductivity at the interface. The transient high-energy heat flow generates stress wave reflection and heat accumulation at this abrupt interface, inducing severe shear deformation along the interlayer direction, exceeding the fracture toughness limit of the ceramic body itself, resulting in interlayer physical fracture failure.

[0173] Test Example 5:

[0174] Fifteen resistor chips from Examples 1-3, Comparative Examples 3 and 4 were selected. The initial leakage current and initial varistor voltage of each sample were measured using a varistor DC parameter tester. The test values ​​were recorded and the arithmetic mean was calculated.

[0175] The resistor chip that has completed the initial test is placed on a special aging rack inside the high-temperature accelerated aging test chamber, ensuring that the positive and negative electrodes of the resistor chip are securely connected to the power supply terminals of the aging rack.

[0176] The internal ambient temperature of the high-temperature accelerated aging test chamber was set to 115℃. After the temperature inside the chamber reached the set value and remained stable, a constant DC bias voltage equivalent to 85% of the initial varistor voltage value of the corresponding sample was applied to each group of resistor chips.

[0177] The resistor chip was subjected to continuous aging treatment with constant temperature and voltage parameters for 1000 hours.

[0178] After the aging time is over, the DC bias voltage output is cut off, and the resistor chip is left in the aging test chamber to cool naturally to room temperature of 25°C.

[0179] After cooling, the resistor chip was removed, and the leakage current of the sample was measured again using a varistor DC parameter tester. The leakage current value after aging was recorded, and the arithmetic mean of each batch of samples was calculated.

[0180] Table 5. High-Temperature Accelerated Aging Test Data of Examples and Comparative Examples

[0181] Sample Name Initial leakage current (μA) Leakage current (μA) after aging Leakage current change (μA) Example 1 0.89 1.15 0.26 Example 2 0.67 0.84 0.17 Example 3 0.94 1.28 0.34 Comparative Example 3 8.52 46.73 38.21 Comparative Example 4 15.36 92.18 76.82

[0182] in conclusion:

[0183] See attached document Figure 4 According to the data in Table 5, after 1000 hours of continuous biasing at 115℃ and 85% varistor voltage in Examples 1-3, the increase in leakage current remained within 0.35 μA. In the microstructure of the resistor chip, the zinc oxide powder treated with silane coupling agent and graphene surface modification formed a dense and highly uniform grain network during sintering. The distribution of graphene at the grain boundaries suppressed the directional drift of interstitial zinc ions at high temperatures. The continuous gradient doping structure formed from the central layer to the surface layer eliminated the barrier distortion at the interlayer physical interface and stabilized the double Schottky barrier structure at the zinc oxide grain boundaries. Under long-term high-temperature DC electric field stress, oxygen vacancies and ion migration within the lattice were physically blocked, and the macroscopic electrical performance remained stable.

[0184] Comparative Example 3, using unmodified pure zinc oxide powder as raw material, showed an increase in leakage current to 46.73 μA after aging. The unmodified powder agglomerated during the mixing stage, leading to localized density differences and loose grain boundary defects in the sintered ceramic body. Under the combined effects of high temperature and continuous DC bias, the interstitial zinc ions and oxygen vacancies inherent in the zinc oxide lattice migrated rapidly along the loose grain boundary channels, resulting in a large accumulation of positively charged ions at the grain boundary interface, neutralizing the negative charge layer at the interface. The double Schottky barrier height decreased with prolonged energization time, the nonlinear conductivity mechanism degraded, and the leakage current increased.

[0185] Comparative Example 4, sintered at 1050℃, showed a significant increase in leakage current to 92.18μA after aging. The relatively low sintering temperature hindered the diffusion and evolution of the high-temperature liquid phase, leaving unresolved physical step interfaces between different powder layers within the resistor chip. These physical step interfaces contain structural misalignments and void defects, with defect energy levels forming pathways for electron tunneling. The sustained high-temperature electric field stress led to an increase in the defect state density at the interfaces, accelerating the disintegration of the grain boundary barrier layer and shortening the aging resistance lifespan of the resistor chip.

Claims

1. A continuously graded doped zinc oxide varistor chip, characterized in that, The chip is symmetrically distributed from the inside to the outside along the thickness direction, and includes a central layer, an intermediate transition layer and a surface enrichment layer in sequence. The central layer is composed of a base zinc oxide material, which comprises, by weight, the following: Pretreatment with 90-95 parts zinc oxide, 1.5-2.5 parts bismuth trioxide, 0.5-1.0 parts cobalt oxide, 0.3-0.6 parts manganese dioxide, and 0.5-1.2 parts antimony trioxide; The intermediate transition layers are symmetrically disposed on both sides of the central layer, and the intermediate transition layers are composed of the basic zinc oxide material plus 0.5 to 1.5 parts by weight of aluminum oxide; The surface enrichment layers are symmetrically disposed on the outside of each of the intermediate transition layers. The surface enrichment layers are composed of the base zinc oxide material plus 1.0-2.5 parts by weight of aluminum oxide and 0.2-0.5 parts by weight of silver oxide. Within the chip, the content of aluminum and silver elements increases in a gradient from the central layer to the surface enrichment layer.

2. The continuously graded doped zinc oxide varistor chip according to claim 1, characterized in that, The powder filling weight of the central layer accounts for 40% to 60% of the total powder filling weight of the chip; The powder filling weight of the intermediate transition layer on both sides accounts for 15% to 25% of the total powder filling weight of the chip; The powder filling weight of the surface enrichment layer on both sides accounts for 5% to 15% of the total powder filling weight of the chip.

3. The continuously graded doped zinc oxide varistor chip according to claim 1, characterized in that, The pretreated zinc oxide in the basic zinc oxide material is zinc oxide particles with a silane coupling agent and graphene composite layer coated on the surface. Furthermore, in the pretreated zinc oxide, the mass ratio of zinc oxide particles, silane coupling agent, and graphene is 1:(0.01~0.02):(0.05~0.06).

4. A method for fabricating a continuously gradient-doped zinc oxide varistor chip, characterized in that, The method for fabricating a continuously gradient doped zinc oxide varistor chip as described in any one of claims 1 to 3 comprises the following steps: Powders were prepared and granulated independently according to the formulas of the central layer, the intermediate transition layer and the surface enrichment layer, respectively, to obtain central layer granules, transition layer granules and surface layer granules. In a pressing mold, powder is layered and filled in the order of powder layering: surface layer granules, transition layer granules, center layer granules, transition layer granules, and surface layer granules. The green body is then formed in one pressing process. The green body is subjected to debinding treatment to obtain a first intermediate; The first intermediate is placed in a sintering furnace for high-temperature co-sintering, wherein the maximum temperature of the high-temperature co-sintering is controlled at 1150℃~1260℃ and the holding time is 4~5h. After the heat preservation is completed, the resistor chip is obtained by cooling in the furnace.

5. The preparation method according to claim 4, characterized in that, The pretreated zinc oxide in the basic zinc oxide material is prepared by the following method: Zinc oxide powder was dispersed in deionized water, a silane coupling agent was added and stirred at 58°C, the pH was adjusted to 5 with glacial acetic acid, and after filtration and washing, it was dispersed in an ethanol aqueous solution containing graphene. After ultrasonic dispersion and spray drying, the pretreated zinc oxide was obtained.

6. The preparation method according to claim 4, characterized in that, The independent granulation operation specifically includes: The prepared powders of each layer were added to deionized water for water-soluble ball milling, and polyvinyl alcohol solution was added as a binder. After being mixed evenly, the powders were spray-dried in a dryer with an outlet temperature of 90℃~110℃ to obtain the central layer granules, the transition layer granules and the surface layer granules with a particle size between 100μm and 110μm.

7. The preparation method according to claim 4, characterized in that, During the layered powder spreading process, the weight ratio of powder filling material in each layer is controlled as follows: The central layer of granules comprises 40% to 60%; the transition layer of granules on one side comprises 15% to 25%. The surface layer particles on one side comprise 5% to 15%; Furthermore, the density of the green body after pressing is controlled to be 3.25 g / cm³ to 3.4 g / cm³.

8. The preparation method according to claim 4, characterized in that, The specific temperature and time control for the glue removal process are as follows: The temperature is raised from room temperature to 200℃ in 6–7 hours. Continue heating up to 450℃; Then raise the temperature from 450℃ to 590℃~612℃; It is then kept at 590℃~612℃ for 1.7~2.5h; Finally, the furnace temperature was lowered to below 100°C before being removed from the furnace to obtain the first intermediate.

9. The preparation method according to claim 4, characterized in that, After the resistor chip is obtained, the process also includes a product annealing heat treatment operation: The resistor chip is cleaned and then placed in an annealing furnace, heated to 590℃~612℃ and held for 2.5~3.1h, and then slowly cooled down before being removed from the furnace.

10. The preparation method according to claim 9, characterized in that, Following the product annealing heat treatment, the process also includes electrode preparation. A silver paste containing 70wt% to 80wt% silver is printed on the outer surface of the surface enrichment layer on both sides of the resistor chip, and then subjected to a heat preservation reduction treatment at a temperature of 590℃ to 610℃ in a reduction furnace to obtain a conductive electrode.

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