Semiconductor structure and method of manufacturing the same

Abstract

The present invention provides a semiconductor structure and a method of manufacturing the same. The semiconductor structure includes a three-dimensional transformer structure. The three-dimensional transformer structure includes a plurality of conductive layers. The conductive layers are arranged in parallel. The conductive layers have a plurality of U-shaped structures. The conductive layers include at least one conductive layer forming a primary circuit of the three-dimensional transformer structure and at least one conductive layer forming a secondary circuit of the three-dimensional transformer structure. The at least one conductive layer of the primary circuit and the at least one conductive layer of the secondary circuit are electrically isolated from each other.

Description

Technical Field

[0001] This invention relates to semiconductor structures and methods for manufacturing the same. More particularly, this invention relates to semiconductor structures comprising three-dimensional (3D) transformer structures and methods for manufacturing the same. Background Technology

[0002] In emerging technology fields such as 5G wireless communication, fully integrated systems using on-chip components are crucial for reducing production costs and overall device size. In this regard, integrating many passive components such as inductors, capacitors, and transformers is essential, as they are fundamental components of many integrated circuits, and their performance significantly impacts overall circuit performance. On-chip transformers are used in a variety of circuits, including low-noise amplifiers (LNAs), voltage-controlled oscillators (VCOs), impedance matching circuits, DC isolation circuits, power transmission circuits, and baluns for power conversion between single-ended and differential circuits. In most cases, on-chip transformers consist of only one or two final metal layers to reduce transformer resistance through greater metal thickness. However, such on-chip transformers typically occupy a large area on the chip. Summary of the Invention

[0003] In this invention, a semiconductor structure including a three-dimensional transformer structure and a method for manufacturing the same are provided. The three-dimensional transformer structure occupies a tiny area.

[0004] A semiconductor structure according to the present invention includes a three-dimensional transformer structure. The three-dimensional transformer structure includes a plurality of conductive layers. These conductive layers are arranged in parallel. These conductive layers have a plurality of U-shaped structures. These conductive layers include at least one conductive layer forming a primary circuit of the three-dimensional transformer structure and at least one conductive layer forming a secondary circuit of the three-dimensional transformer structure, wherein the at least one conductive layer of the primary circuit and the at least one conductive layer of the secondary circuit are electrically isolated from each other.

[0005] A method for manufacturing a semiconductor structure according to the present invention includes forming a three-dimensional transformer structure. Forming the three-dimensional transformer structure includes forming a plurality of conductive layers. These conductive layers are arranged in parallel. These conductive layers have a plurality of U-shaped structures. These conductive layers include a primary circuit of the three-dimensional transformer structure formed by at least one conductive layer and a secondary circuit of the three-dimensional transformer structure formed by at least one conductive layer, wherein the at least one conductive layer of the primary circuit and the at least one conductive layer of the secondary circuit are electrically isolated from each other.

[0006] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings: Attached Figure Description

[0007] Figures 1A-1D This is a schematic diagram of an exemplary semiconductor structure according to the present invention.

[0008] Figures 2A-2B This is a schematic diagram of an exemplary semiconductor structure according to the present invention.

[0009] Figure 3 This is a schematic diagram of an exemplary semiconductor structure according to the present invention.

[0010] Figures 4A-4D This is a schematic diagram of an exemplary semiconductor structure according to the present invention.

[0011] Figures 5A-5B This is a schematic diagram of an exemplary semiconductor structure according to the present invention.

[0012] Figure 6 This is a schematic diagram of an exemplary semiconductor structure according to the present invention.

[0013] Figures 7 to 15A - Figure 15C This is a schematic diagram of the various stages of a method for manufacturing an exemplary semiconductor structure according to the present invention.

[0014] Figures 16 to 21A - Figure 21C This is a schematic diagram of the various stages of a method for manufacturing an exemplary semiconductor structure according to the present invention.

[0015] Explanation of reference numerals in the attached figures:

[0016] 10A: Semiconductor Structure

[0017] 10B: Semiconductor Structure

[0018] 10C: Semiconductor Structure

[0019] 10D: Semiconductor Structure

[0020] 10E: Semiconductor Structure

[0021] 10F: Semiconductor Structure

[0022] 100: Three-dimensional transformer structure

[0023] 110: Conductive layer

[0024] 110-1: First conductive layer

[0025] 110-2: Second conductive layer

[0026] 110-3: Third conductive layer

[0027] 110-4: Fourth conductive layer

[0028] 200: Conductive element

[0029] 210: Conductive wire

[0030] 220: Through hole

[0031] 300: Substrate

[0032] 302: Lower surface

[0033] 304: Top surface

[0034] 310: Intermediate dielectric layer

[0035] 320: Dielectric material

[0036] 330: Dielectric material

[0037] 340: Dielectric layer

[0038] 350: Dielectric material

[0039] 360: Supporting Components

[0040] 370: Barrier Layer

[0041] 380: Dielectric layer

[0042] 382: Dielectric materials

[0043] 384: Dielectric Materials

[0044] 400: Floor

[0045] 410: First Opening

[0046] 420: Second opening

[0047] D1: First horizontal direction

[0048] D2: Second horizontal direction

[0049] P: Primary circuit

[0050] R: concave part

[0051] S: Secondary circuit

[0052] S1: Secondary circuit

[0053] S2: Secondary circuit

[0054] S3: Secondary circuit

[0055] Z: Vertical direction Detailed Implementation

[0056] The following description, in conjunction with the accompanying drawings, details various embodiments. The descriptions and drawings are provided for illustrative purposes only and are not intended to be limiting. Similar elements are indicated by similar symbols. For clarity, elements may not be drawn to scale. Furthermore, some elements and / or symbols may be omitted in some drawings. It is contemplated that elements and features in one embodiment may be advantageously incorporated into another embodiment without further explanation.

[0057] One embodiment of the present invention relates to a semiconductor structure. This semiconductor structure includes a three-dimensional transformer structure. The three-dimensional transformer structure includes a plurality of conductive layers. These conductive layers are arranged in parallel. These conductive layers have a plurality of U-shaped structures. These conductive layers include a primary circuit of the three-dimensional transformer structure formed by at least one conductive layer and a secondary circuit of the three-dimensional transformer structure formed by at least one conductive layer, wherein the at least one conductive layer of the primary circuit and the at least one conductive layer of the secondary circuit are electrically isolated from each other.

[0058] The total number of conductive layers can be three or more, such as 3, 4, 5, etc. According to some embodiments, the primary circuit may include two or more conductive layers electrically coupled to each other. According to some embodiments, the secondary circuit may include two or more conductive layers electrically coupled to each other. Two or more conductive layers belonging to the same primary circuit or the same secondary circuit can be electrically coupled to each other through one or more conductive lines disposed on the same layer and multiple vias connecting the one or more conductive lines to the two or more conductive layers. According to some embodiments, the three-dimensional transformer structure may include two or more primary circuits. According to some embodiments, the three-dimensional transformer structure may include two or more secondary circuits.

[0059] Please refer to Figures 1A-1D This is a schematic diagram of an exemplary semiconductor structure 10A according to the present invention, wherein, Figure 1A This is a top view of semiconductor structure 10A. Figure 1B For semiconductor structure 10A along Figure 1A A cross-sectional view of line B-B' in the diagram. Figure 1C For semiconductor structure 10A along Figure 1A A cross-sectional view of line C-C' in the diagram. Figure 1D This is a schematic diagram of the circuit of a three-dimensional transformer structure 100 with a semiconductor structure 10A.

[0060] Semiconductor structure 10A includes a three-dimensional transformer structure 100, a plurality of conductive elements 200 for the three-dimensional transformer structure 100, and a substrate 300. Semiconductor structure 10A has a first horizontal direction D1, a second horizontal direction D2 perpendicular to the first horizontal direction D1, and a vertical direction Z perpendicular to the first horizontal direction D1 and the second horizontal direction D2.

[0061] Specifically, substrate 300 can be any suitable substrate used in the semiconductor field. Substrate 300 has a lower surface 302 and an upper surface 304. A first horizontal direction D1 and a second horizontal direction D2 can be defined as substantially parallel to the upper surface 304, and a vertical direction Z can be defined as the normal direction of the upper surface 304. In semiconductor structure 10A, substrate 300 has a recess R extending from the upper surface 304 toward the lower surface 302.

[0062] The three-dimensional transformer structure 100 includes multiple conductive layers 110. In the semiconductor structure 10A, the conductive layers 110 are disposed in the recess R. Therefore, the conductive layers 110 are disposed below the upper surface 304 of the substrate 300. In the semiconductor structure 10A, the U-shaped structure of the conductive layers 110 is perpendicular to the substrate 300, such as... Figure 1C As shown.

[0063] The conductive layer 110 of the semiconductor structure 10A includes a first conductive layer 110-1, a second conductive layer 110-2, a third conductive layer 110-3, and a fourth conductive layer 110-4 arranged sequentially. The first conductive layer 110-1 to the fourth conductive layer 110-4 are arranged sequentially from the lower surface 302 of the substrate 300 to the upper surface 304 of the substrate 300. More specifically, each U-shaped structure of the conductive layer 110 can be composed of two ends and a central portion connecting the two ends, wherein the ends are parallel to each other, and the central portion is perpendicular to the ends. The central portion of the first conductive layer 110-1 is closer to the lower surface 302 of the substrate 300 than the central portion of the fourth conductive layer 110-4. With this configuration, the total length of the first conductive layer 110-1 is greater than the total length of the second conductive layer 110-2, the total length of the second conductive layer 110-2 is greater than the total length of the third conductive layer 110-3, and the total length of the third conductive layer 110-3 is greater than the total length of the fourth conductive layer 110-4.

[0064] In semiconductor structure 10A, the first conductive layer 110-1 belongs to a primary circuit P, the second conductive layer 110-2 belongs to a secondary circuit S1, the third conductive layer 110-3 belongs to another secondary circuit S2, and the fourth conductive layer 110-4 belongs to yet another secondary circuit S3, as shown in... Figure 1A As indicated in the text. That is to say, the first conductive layer 110-1 to the fourth conductive layer 110-4 are electrically isolated from each other.

[0065] Semiconductor structure 10A may include a plurality of intermediate dielectric layers 310 separating conductive layer 110 from each other. Similarly, these intermediate dielectric layers 310 have a plurality of U-shaped structures. Semiconductor structure 10A may also include a dielectric material 320 disposed in the recess R, above conductive layer 110 and intermediate dielectric layers 310. Semiconductor structure 10A may also include a dielectric material 330 for filling the recess R on one side of conductive layer 110, intermediate dielectric layer 310, and dielectric material 320. Semiconductor structure 10A may also include a dielectric layer 340 conformally extending from above dielectric material 330 and dielectric material 320, through the sidewall of dielectric material 320, conductive layer 110, and intermediate dielectric layer 310 on the side opposite to dielectric material 330, to the bottom of recess R. Semiconductor structure 10A may also include a dielectric material 350 disposed on dielectric layer 340. Dielectric material 350 is filled into the remaining space of the recess R.

[0066] Electrical connections to conductive layer 110 can be achieved using conductive elements 200 configured based on circuit design. Conductive elements 200 may include one or more conductive lines 210 and multiple vias 220. Conductive lines 210 are disposed in a layer on dielectric material 350. Vias 220 penetrate dielectric material 350 and dielectric layer 340, connecting conductive lines 210 to their corresponding conductive layers 110.

[0067] Please refer to Figures 2A-2B This is a schematic diagram of an exemplary semiconductor structure 10B according to the present invention, wherein, Figure 2A This is a top view of semiconductor structure 10B. Figure 2B This is a schematic diagram of the circuit of the three-dimensional transformer structure 100 of semiconductor structure 10B. Semiconductor structure 10B is configured similarly to semiconductor structure 10A. The difference lies in that, in semiconductor structure 10B, the conductive elements 200 are configured differently to connect the conductive layers 110 based on a different circuit design. In semiconductor structure 10B, the first conductive layer 110-1 and the third conductive layer 110-3 belong to the primary circuit P and are electrically coupled to each other, while the second conductive layer 110-2 and the fourth conductive layer 110-4 belong to the secondary circuit S and are electrically coupled to each other. Other details of semiconductor structure 10B are similar to those described above with reference to semiconductor structure 10A, and therefore will not be repeated here.

[0068] Please refer to Figure 3 This is a schematic diagram of an exemplary semiconductor structure 10C according to the present invention, wherein, Figure 3This is a schematic diagram of the circuit of a three-dimensional transformer structure 100 of semiconductor structure 10C. Semiconductor structure 10C is configured similarly to semiconductor structure 10A. The difference is that semiconductor structure 10C may have five conductive layers 110, connected in a suitable manner by conductive elements 200 to achieve… Figure 3 The circuit design is shown. Other details of semiconductor structure 10C are similar to those described above with reference to semiconductor structure 10A, and therefore will not be repeated here.

[0069] Please refer to Figures 4A-4D This is a schematic diagram of an exemplary semiconductor structure 10D according to the present invention, wherein, Figure 4A This is a 10D top view of a semiconductor structure. Figure 4B For semiconductor structure 10D along Figure 4A A cross-sectional view of line B-B' in the diagram. Figure 4C For semiconductor structure 10D along Figure 4A A cross-sectional view of line C-C' in the diagram. Figure 4D This is a schematic diagram of the circuit of a three-dimensional transformer structure 100 with a semiconductor structure 10D.

[0070] A conductive layer 110 of the semiconductor structure 10D is disposed on a substrate 300. More specifically, the conductive layer 110 and the intermediate dielectric layer 310 may be stacked alternately on the substrate 300. Thus, the conductive layer 110 is disposed above the upper surface 304 of the substrate 300. The U-shaped structure of the conductive layer 110 of the semiconductor structure 10D is parallel to the substrate 300. In some embodiments, up to hundreds of pairs of conductive layers 110 and intermediate dielectric layers 310 may be stacked. The stack of conductive layers 110 and intermediate dielectric layers 310 may have a stepped structure at the ends of the U-shaped structure. In this configuration, the total length of the first conductive layer 110-1 is greater than the total length of the second conductive layer 110-2, the total length of the second conductive layer 110-2 is greater than the total length of the third conductive layer 110-3, and the total length of the third conductive layer 110-3 is greater than the total length of the fourth conductive layer 110-4.

[0071] The semiconductor structure 10D may also include multiple support elements 360 extending through the stack. The semiconductor structure 10D may also include multiple barrier layers 370 located on the sidewalls of the conductive layer 110, particularly on the sidewalls of the central portion of the U-shaped structure. The semiconductor structure 10D may also include a dielectric layer 380 located on the stack.

[0072] The conductive element 200 may include one or more conductive lines 210 and multiple vias 220. The conductive lines 210 are disposed in one layer of the dielectric layer 380. The vias 220 penetrate the dielectric layer 380 and fall on the corresponding conductive layer 110 at the stepped structure, connecting the conductive lines 210 to the corresponding conductive layers 110.

[0073] In the semiconductor structure 10D, the first conductive layer 110-1 belongs to a primary circuit P, the second conductive layer 110-2 belongs to a secondary circuit S1, the third conductive layer 110-3 belongs to another secondary circuit S2, and the fourth conductive layer 110-4 belongs to yet another secondary circuit S3, as shown in... Figure 4A As indicated in the text. That is to say, the first conductive layer 110-1 to the fourth conductive layer 110-4 are electrically isolated from each other.

[0074] Other details of the semiconductor structure 10D are similar to those described above with reference to the semiconductor structure 10A, and therefore will not be repeated here.

[0075] Please refer to Figures 5A-5B This is a schematic diagram of an exemplary semiconductor structure 10E according to the present invention, wherein, Figure 5A This is a top view of semiconductor structure 10E. Figure 5B This is a schematic diagram of the circuit of a three-dimensional transformer structure 100 of semiconductor structure 10E. Semiconductor structure 10E is configured similarly to semiconductor structure 10D. The difference lies in that, in semiconductor structure 10E, the conductive elements 200 are configured differently to connect the conductive layers 110 based on a different circuit design. In semiconductor structure 10E, the first conductive layer 110-1 and the third conductive layer 110-3 belong to the primary circuit P and are electrically coupled to each other, while the second conductive layer 110-2 and the fourth conductive layer 110-4 belong to the secondary circuit S and are electrically coupled to each other. Other details of semiconductor structure 10E are similar to those described above with reference to semiconductor structure 10D, and therefore will not be repeated here.

[0076] Please refer to Figure 6 This is a schematic diagram of an exemplary semiconductor structure 10F according to the present invention, wherein, Figure 6 This is a schematic diagram of the circuit of a three-dimensional transformer structure 100 with semiconductor structure 10F. Semiconductor structure 10F is configured similarly to semiconductor structure 10D. The difference is that semiconductor structure 10F may have five conductive layers 110, connected in a suitable manner by conductive elements 200 to achieve… Figure 6 The circuit design is shown. Other details of semiconductor structure 10F are similar to those described above with reference to semiconductor structure 10D, and therefore will not be repeated here.

[0077] As described above, in the semiconductor structure according to the present invention, a "three-dimensional" transformer structure is provided by multiple U-shaped conductive layers. Compared with the conventional "two-dimensional" transformer structure, the area required for the three-dimensional transformer structure is significantly reduced. Furthermore, more conductive layers can be configured in the transformer structure.

[0078] Furthermore, in semiconductor structures configured in a manner similar to semiconductor structures 10A to 10C, the magnetic field is either in the first horizontal direction D1 or the second horizontal direction D2, and not in the vertical direction Z. Therefore, magnetic effects on devices below the transformer structure (e.g., but not limited to bottom CMOS elements) can be further reduced or prevented.

[0079] In semiconductor structures configured in a manner similar to semiconductor structures 10D to 10F, greater inductance can be achieved because many conductive layers can be formed within the transformer structure. Furthermore, such semiconductor structures can be manufactured using self-aligned processes, thus allowing for more precise and easier fabrication.

[0080] Another embodiment of the present invention relates to a method of manufacturing a semiconductor structure. This method includes forming a three-dimensional transformer structure. Forming the three-dimensional transformer structure includes forming a plurality of conductive layers. These conductive layers are arranged in parallel. These conductive layers have a plurality of U-shaped structures. These conductive layers include a primary circuit of the three-dimensional transformer structure formed by at least one conductive layer and a secondary circuit of the three-dimensional transformer structure formed by at least one conductive layer, wherein the at least one conductive layer of the primary circuit and the at least one conductive layer of the secondary circuit are electrically isolated from each other.

[0081] Please refer to Figures 7 to 15A - Figure 15C This is a schematic diagram of various stages of a method for manufacturing an exemplary semiconductor structure according to the present invention, used to manufacture semiconductor structure 10A, wherein... Figure 7 and Figure 8 For a cross-sectional view, Figures 9A-9B to Figures 15A-15C For each stage shown, the diagram labeled "A" is a top view, the diagram labeled "B" is a cross-sectional view along line B-B' in the diagram "A" with the same figure number, and the diagram labeled "C" (if any) is a cross-sectional view along line C-C' in the diagram "A" with the same figure number.

[0082] like Figure 7 As shown, a substrate 300 is provided. Any suitable substrate can be used. The substrate 300 may include a dielectric layer (not shown), such as an oxide layer, located on its upper side. That is, at least a portion of the upper surface 304 of the substrate 300 is formed by the dielectric layer. A recess R is formed in the substrate 300. More specifically, the recess R may be formed in the dielectric layer. The recess R may be formed by a reactive ion etching (RIE) process, but is not limited thereto.

[0083] like Figure 8As shown, multiple layers 400 of a sacrificial material and multiple layers of a dielectric material (i.e., intermediate dielectric layers 310) are conformally alternately formed in the recess R. The sacrificial material may be a nitride. The dielectric material may be an oxide. According to some embodiments, the thickness of each layer 400 may be 1 micrometer (μm) or more. Similarly, the thickness of each intermediate dielectric layer 310 may be 1 μm or more.

[0084] A dielectric material 320 is provided to fill the remaining space of the recess R. The dielectric material 320 can be an oxide. Next, a planarization process, such as a CMP process, can be performed, stopping at the upper surface 304, as... Figures 9A-9B As shown.

[0085] Then, the sacrificial material layer 400 and the dielectric material layer (i.e., the intermediate dielectric layer 310) are patterned into multiple U-shaped structures. Specifically, as follows: Figures 10A-10B As shown, remove one side of the recess R closest to the recess R. Figure 10A Almost half of the material (on the left side) forms a first opening 410. This can be achieved through a RIE process, but is not limited to it.

[0086] like Figures 11A-11B As shown, a dielectric material 330 is filled into the first opening 410. The dielectric material 330 may be an oxide. Deposition processes and optional planarization processes, such as CMP processes, may be performed to provide the dielectric material 330.

[0087] like Figures 12A-12C As shown, remove one opposite side of the recess R. Figure 12A Almost half of the material (on the right side) forms a second opening 420. This can be achieved through a RIE process, but is not limited to it.

[0088] like Figures 13A-13C As shown, the sacrificial material is removed. The sacrificial material can be removed by a selective etching process performed through the second opening 420, which uses, for example, H3PO4, but is not limited to, this process.

[0089] like Figures 14A-14C As shown, conductive layers 110 are formed in multiple spaces created by removing sacrificial material. According to some embodiments, conductive layers 110 may include multiple barrier layers and multiple conductive bodies. For example, a TaN thin film may be formed on top and bottom of these spaces as barrier layers. Then, Cu may be deposited or (using a Cu seed layer) electroplated to form the conductive bodies. An optional wet etching process may be performed to remove excess Cu in the second opening 420. However, the invention is not limited thereto. Since the thickness of each layer 400 can be 1 μm or more, the thickness of each conductive layer 110 can also be 1 μm or more. Therefore, the transformer resistance can be reduced.

[0090] like Figures 15A-15C As shown, a dielectric layer 340 is conformally formed on dielectric materials 330 and 320. Dielectric material 320, conductive layer 110, and intermediate dielectric layer 310 are exposed on the sidewalls and bottom of the second opening 420. The dielectric layer 340 can serve as a barrier layer to prevent Cu from diffusing from the conductive layer 110. A dielectric material 350 is formed on the dielectric layer 340. The dielectric material 350 fills the remaining space of the second opening 420. A plurality of vias 220 and one or more conductive lines 210 can then be formed to provide electrical connections for the conductive layer 110.

[0091] It is expected that semiconductor structure 10B and semiconductor structure 10C can be manufactured in a similar manner.

[0092] Please refer to Figures 16 to 21A - Figure 21C This is a schematic diagram of various stages of a method for manufacturing an exemplary semiconductor structure according to the present invention, used to manufacture a semiconductor structure 10D, wherein... Figure 16 For a cross-sectional view, Figures 17A-17B to Figures 21A-21C For each stage shown, the diagram labeled "A" is a top view, the diagram labeled "B" is a cross-sectional view along line B-B' in the diagram "A" with the same figure number, and the diagram labeled "C" (if any) is a cross-sectional view along line C-C' in the diagram "A" with the same figure number.

[0093] like Figure 16 As shown, a substrate 300 is provided. Multiple layers 400 of a sacrificial material and multiple layers of a dielectric material (i.e., intermediate dielectric layers 310) are alternately formed on the substrate 300. The sacrificial material may be a nitride. The dielectric material may be an oxide. According to some embodiments, the thickness of each layer 400 may be 1 μm or more. Similarly, the thickness of each intermediate dielectric layer 310 may be 1 μm or more. According to some embodiments, up to hundreds of pairs of layers 400 and intermediate dielectric layers 310 can be stacked.

[0094] like Figures 17A-17B As shown, a stepping process commonly used in 3D memory manufacturing can be performed to form a step structure on the substrate 300 between the sacrificial material layer 400 and the dielectric material layer (i.e., the intermediate dielectric layer 310).

[0095] Next, a stack of dielectric material 382 covering the sacrificial material layer 400 and the intermediate dielectric layer 310 is formed. The dielectric material 382 may be an oxide. A plurality of support elements 360 are formed through the dielectric material 382 and the stack to support the transformer pattern during subsequent processes and prevent the stack from collapsing. The support elements 360 can be formed by forming a plurality of holes through the dielectric material 382 and the stack and subsequently filling these holes with a dielectric material such as an oxide. However, the invention is not limited thereto.

[0096] like Figures 18A-18C As shown, the sacrificial material layer 400 and the dielectric material layer (i.e., the intermediate dielectric layer 310) are patterned into multiple U-shaped structures. Stepped structures form multiple ends of these U-shaped structures.

[0097] like Figures 19A-19C As shown, the sacrificial material is removed. The sacrificial material can be removed by a selective etching process, which may use, for example, H3PO4, but is not limited to this.

[0098] like Figures 20A-20C As shown, conductive layers 110 are formed in multiple spaces created by removing sacrificial material. According to some embodiments, conductive layers 110 may include multiple barrier layers and multiple conductive bodies. For example, a TaN thin film may be formed on top and bottom of these spaces as barrier layers. Next, Cu may be deposited or (using a Cu seed layer) electroplated to form the conductive bodies. An optional wet etching process may be performed to remove excess Cu. However, the invention is not limited thereto. Since the thickness of each layer 400 can be 1 μm or more, the thickness of each conductive layer 110 can also be 1 μm or more. Therefore, the transformer resistance can be reduced.

[0099] Optionally, multiple barrier layers 370 can be formed on the sidewalls of the conductive layer 110, particularly on the sidewalls of the central portion of the U-shaped structure. The barrier layers 370 can be formed by depositing Co, TaN, TiN, or any other suitable material. The barrier layers 370 can prevent Cu leakage.

[0100] Then, a dielectric material 384 covering structure is formed. Dielectric material 384 and dielectric material 382 together constitute dielectric layer 380.

[0101] like Figures 21A-21C As shown, multiple vias 220 and one or more conductive lines 210 can be formed to provide electrical connections for the conductive layer 110.

[0102] It is expected that semiconductor structure 10E and semiconductor structure 10F can be manufactured in a similar manner.

[0103] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A semiconductor structure, comprising: A three-dimensional transformer structure includes: Multiple conductive layers are arranged in parallel and have multiple U-shaped structures; These conductive layers include a primary circuit with at least one conductive layer forming the three-dimensional transformer structure and a secondary circuit with at least one conductive layer forming the three-dimensional transformer structure, wherein the at least one conductive layer of the primary circuit and the at least one conductive layer of the secondary circuit are electrically isolated from each other.

2. The semiconductor structure according to claim 1, wherein, The total number of these conductive layers is more than 3.

3. The semiconductor structure according to claim 1, wherein, The primary circuit includes two or more of these conductive layers, which are electrically coupled to each other.

4. The semiconductor structure according to claim 1, wherein, The secondary circuit includes two or more of these conductive layers, which are electrically coupled to each other.

5. The semiconductor structure according to claim 1, wherein, Two or more conductive layers belonging to the primary circuit or the secondary circuit are electrically coupled to each other through one or more conductive lines disposed on the same layer and multiple vias connecting the one or more conductive lines to the two or more conductive layers.

6. The semiconductor structure according to claim 1, wherein, The three-dimensional transformer structure includes two or more of these primary circuits.

7. The semiconductor structure according to claim 1, wherein, The three-dimensional transformer structure includes two or more of these secondary circuits.

8. The semiconductor structure according to claim 1, wherein, These conductive layers include a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer arranged in sequence.

9. The semiconductor structure according to claim 8, wherein, The total length of the first conductive layer is greater than the total length of the second conductive layer, the total length of the second conductive layer is greater than the total length of the third conductive layer, and the total length of the third conductive layer is greater than the total length of the fourth conductive layer.

10. The semiconductor structure according to claim 8, wherein, The first conductive layer belongs to the primary circuit, the second conductive layer belongs to the secondary circuit, the third conductive layer belongs to another secondary circuit, and the fourth conductive layer belongs to yet another secondary circuit.

11. The semiconductor structure according to claim 8, wherein, The first conductive layer and the third conductive layer belong to the primary circuit and are electrically coupled to each other, while the second conductive layer and the fourth conductive layer belong to the secondary circuit and are electrically coupled to each other.

12. The semiconductor structure according to claim 8, further comprising: A substrate; The first to the fourth conductive layers are arranged sequentially from the lower surface of the substrate to the upper surface of the substrate.

13. The semiconductor structure according to claim 12, wherein, These U-shaped structures of the conductive layers are perpendicular to the substrate.

14. The semiconductor structure according to claim 13, wherein, These conductive layers are disposed beneath the upper surface of the substrate.

15. The semiconductor structure according to claim 12, wherein, These U-shaped structures of the conductive layers are parallel to the substrate.

16. The semiconductor structure according to claim 15, wherein, These conductive layers are disposed above the upper surface of the substrate.

17. The semiconductor structure according to claim 1, further comprising: Multiple intermediate dielectric layers separate these conductive layers from each other, and these intermediate dielectric layers have multiple U-shaped structures.

18. A method for manufacturing a semiconductor structure, comprising: A three-dimensional transformer structure is formed, including: Multiple conductive layers are formed, which are arranged in parallel and have multiple U-shaped structures. These conductive layers include a primary circuit with at least one conductive layer forming the three-dimensional transformer structure and a secondary circuit with at least one conductive layer forming the three-dimensional transformer structure, wherein the at least one conductive layer of the primary circuit and the at least one conductive layer of the secondary circuit are electrically isolated from each other.

19. The method for manufacturing a semiconductor structure according to claim 18, comprising: Provide a substrate; A recess is formed in the substrate; Multiple layers of a sacrificial material and multiple layers of a dielectric material are conformally alternately formed in the recess; The layers of the sacrificial material and the layers of the dielectric material are patterned into multiple U-shaped structures; Remove the sacrificial material; as well as These conductive layers are formed in the multiple spaces created by removing the sacrificial material.

20. The method for manufacturing a semiconductor structure according to claim 18, comprising: Provide a substrate; Multiple layers of a sacrificial material and multiple layers of a dielectric material are alternately formed on the substrate, wherein the layers of the sacrificial material and the layers of the dielectric material form a stepped structure on the substrate; The layers of the sacrificial material and the layers of the dielectric material are patterned into multiple U-shaped structures, wherein the stepped structures constitute multiple ends of these U-shaped structures; Remove the sacrificial material; and These conductive layers are formed in the multiple spaces created by removing the sacrificial material.

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