Capacitor conductive layer and method for manufacturing the same, and capacitor structure

Abstract

The application discloses a capacitor conductive layer, a preparation method thereof and a capacitor structure. The capacitor conductive layer is divided into a plurality of mutually insulated conductive regions by at least two interval bands. Each interval band is configured to extend spirally from a central region of the conductive layer to an outer periphery, wherein the conductive layer is completely divided by the interval band, or the central region of the conductive layer is not divided by the interval band, and a central conductive region insulated from the conductive regions is formed. The plurality of conductive regions are respectively used as electrode regions of the capacitor. The capacitor conductive layer, the preparation method thereof and the capacitor structure can significantly reduce ESL and improve the radio frequency performance of the capacitor through innovative design of the conductive layer form.

Description

Technical Field

[0001] This invention belongs to the field of micro-nano technology, specifically relating to a capacitor conductive layer, its preparation method, and a capacitor structure containing the conductive layer. Background Technology

[0002] In the field of micro-nano technology, the RF performance of capacitors (including insertion loss and reflection characteristics) directly depends on the electrode structure design. Traditional four-terminal capacitor designs typically divide the top metal layer into four uniform squares and connect them with a thin metal segment along one diagonal. While this design reduces manufacturing costs and process complexity, it does not consider the impact of equivalent series inductance (ESL) on RF characteristics.

[0003] In the current technology, there is no electrode structure design scheme that can effectively reduce ESL and has wide bandwidth operating characteristics.

[0004] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a capacitor conductive layer and its preparation method, as well as a capacitor structure. Through innovative conductive layer morphology design, it can significantly reduce ESL and improve the RF performance of the capacitor.

[0006] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution:

[0007] A capacitor conductive layer is provided, wherein the conductive layer is divided into a plurality of mutually insulated conductive regions by at least two spacer bands, and each spacer band is configured to extend spirally from the central region of the conductive layer outward; wherein...

[0008] The conductive layer is completely divided by the spacer band, or the central region of the conductive layer has a central conductive region that is not divided by the spacer band and is insulated from the conductive region.

[0009] In one or more embodiments of the present invention, the conductive layer is constructed as an n×n two-dimensional grid array, wherein n is a positive integer and n≥2; the spacer band extends spirally along the edge of the grid cell in the grid array.

[0010] In one or more embodiments of the present invention, when n is an odd number, an undivided central conductive region is formed in the central region of the conductive layer; and / or,

[0011] When n is an even number, the conductive layer is completely divided by the spacer band.

[0012] In one or more embodiments of the present invention, the lengths of the plurality of spacer strips are equal.

[0013] In one or more embodiments of the present invention, the plurality of conductive regions include a plurality of first regions and a plurality of second regions, wherein the first regions and the second regions are arranged alternately in a circumferential direction around the central region of the conductive layer; wherein...

[0014] Multiple first regions have equal areas, and multiple second regions have equal areas.

[0015] In one or more embodiments of the present invention, a plurality of first regions are rotationally symmetric; a plurality of second regions are rotationally symmetric.

[0016] In one or more embodiments of the present invention, the areas of all conductive regions in the plurality of conductive regions are equal; or,

[0017] In multiple conductive regions, some conductive regions have equal areas; or,

[0018] The areas of all conductive regions in the multiple conductive regions are not equal.

[0019] In one or more embodiments of the present invention, all conductive regions in the plurality of conductive regions have equal areas, and all conductive regions are rotationally symmetrically distributed; or,

[0020] In the plurality of conductive regions, some conductive regions have equal areas, and the conductive regions with equal areas are distributed in a rotationally symmetrical manner.

[0021] In one or more embodiments of the invention, the spacer band is at least partially in the shape of a Parker spiral; and / or,

[0022] The spacer band is a trench structure or a filling structure formed by an insulating medium.

[0023] A method for preparing a conductive layer for a capacitor, comprising:

[0024] Provide a conductive layer;

[0025] A segmented path is formed on the conductive layer, extending in a spiral shape from the central region of the conductive layer outwards;

[0026] A spacer band is formed on the conductive layer along the segmentation path, dividing the conductive layer into multiple mutually insulated conductive regions;

[0027] in,

[0028] The conductive layer is completely divided by the spacer band, or the central region of the conductive layer has a central conductive region that is not divided by the spacer band and is insulated from the conductive region.

[0029] In one or more embodiments of the present invention, generating a segmented path on the conductive layer that extends spirally from the central region of the conductive layer to the outer periphery includes:

[0030] A two-dimensional grid array is constructed on the conductive layer;

[0031] Based on the two-dimensional grid array, a segmented path is formed on the conductive layer, extending in a spiral shape along the edge of the grid cell in the grid array.

[0032] A capacitor structure includes the conductive layer described above.

[0033] Compared with the prior art, the capacitor conductive layer and its preparation method and capacitor structure of the present invention, by introducing a spirally extending spacer band, divide the conductive layer into multiple conductive regions with specific geometric distribution, thereby significantly enhancing the mutual coupling effect between the electrodes subsequently disposed in the conductive regions, while reducing the influence of mutual inductance, and effectively improving the radio frequency performance of the capacitor (including insertion loss and reflection characteristics). Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of the design structure of the capacitor conductive layer in Embodiment 1 of the present invention;

[0036] Figure 2 This is a schematic diagram of the design structure of the capacitor conductive layer in Embodiment 2 of the present invention;

[0037] Figure 3 This is a schematic diagram of the design structure of the capacitor conductive layer in Embodiment 3 of the present invention;

[0038] Figure 4 This is a simulation test diagram of the capacitance of the capacitor conductive layer in Embodiment 3 of the present invention;

[0039] Figure 5 This is a schematic diagram of the design structure of the capacitor conductive layer in Embodiment 4 of the present invention;

[0040] Figure 6 This is a simulation test diagram of the capacitance of the capacitor conductive layer in Embodiment 4 of the present invention;

[0041] Figure 7This is a schematic diagram of the design structure of the capacitor conductive layer in Embodiment 5 of the present invention;

[0042] Figure 8 This is a schematic diagram of the design structure of the capacitor conductive layer in Embodiment 6 of the present invention;

[0043] Figure 9 This is a flowchart of a method for preparing a capacitor conductive layer in one embodiment of the present invention. Detailed Implementation

[0044] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0045] As mentioned in the background section, in the field of micro-nano technology, capacitors are indispensable passive components in radio frequency integrated circuits (RFICs), microwave and millimeter-wave circuits, and system-on-a-chip (SoCs). The RF performance of capacitors, including insertion loss and reflection characteristics, directly determines the operating bandwidth, signal integrity, and overall performance of the circuit in which they are located.

[0046] Traditional multi-terminal capacitors (such as four-terminal capacitors) typically employ the following design: the top metal layer is divided into four uniform square regions, and a thin metal wire segment connects the corresponding two regions along one diagonal to form a multi-terminal structure. The main advantages of this design are its simple manufacturing process and low cost, and it can still meet basic performance requirements in low-frequency applications.

[0047] However, with the rapid development of wireless communication technology towards higher frequencies and wider bandwidths (such as 5G and 6G communication bands), the inherent defects of traditional designs are becoming increasingly apparent. First, the equivalent series inductance (ESL) is relatively large. The shape and connection method of the metal electrodes in traditional four-terminal capacitors cannot effectively reduce ESL. Under high-frequency conditions, ESL causes the capacitor's resonant frequency to drop, causing the capacitor's impedance characteristics to deviate from the ideal capacitance at high frequencies, resulting in significant insertion loss and reflection, severely impacting the performance of the RF system. Second, the operating bandwidth is limited. Due to the limitations of ESL and parasitic parameters, traditional designs struggle to maintain stable RF performance over a wide bandwidth. Finally, symmetry is insufficient. Traditional designs often cannot guarantee strict geometric and electrical symmetry between the four electrodes, leading to an imbalance of parasitic parameters, which in turn affects the performance of differential or balanced circuits.

[0048] To address the aforementioned technical problems, this invention introduces spirally extending spacer bands to divide the conductive layer into multiple conductive regions with specific geometric distributions. This significantly enhances the mutual coupling effect between electrodes subsequently placed in the conductive regions, while reducing mutual inductance and effectively improving the RF performance of the capacitor (including insertion loss and reflection characteristics).

[0049] A first aspect of the present invention provides a conductive layer for a capacitor. The conductive layer is divided into a plurality of mutually insulated conductive regions by at least two spacers. Each spacer is configured to extend spirally outward from a central region of the conductive layer. In one embodiment, the conductive layer is completely divided by the spacers. In another embodiment, the central region of the conductive layer is not divided by the spacers and forms a central conductive region insulated from the conductive regions. The plurality of conductive regions respectively serve as electrode regions of the capacitor.

[0050] The spiral extension of the spacer bands refers to the path of the spacer bands starting from the central region of the conductive layer and gradually rotating outward around the central region, forming a geometric shape similar to a spiral. This path can be a stepped broken line (when the conductive layer is constructed as a grid array) or a smooth curve (when the grid density is high enough).

[0051] In traditional designs, current often travels a long path when flowing through the electrode region, resulting in significant self-inductance and mutual inductance. The spiral spacer of this invention divides the conductive layer into multiple conductive regions extending along the spiral direction, confining the current path within a narrow, spiral region. This spiral path causes the currents in adjacent electrode regions to form a spatially coupled spiral shape, with the current direction alternating between adjacent paths. This causes the mutual inductance effect to cancel each other out or weaken, thus reducing the overall equivalent series inductance (ESL).

[0052] In a preferred embodiment of the present invention, the inherent characteristic of the spiral path extending outward from the center results in a compact and uniformly distributed conductive region. When the number of spacers is four, the four regions are rotationally symmetrically distributed around the center, ensuring a high degree of consistency in electrical parameters among the four electrodes. This symmetry is crucial for the performance of differential and balanced circuits.

[0053] In other embodiments, when the number of spacers is four or more, two or more regions may be rotationally symmetrically distributed around the center among the four regions or all regions; or, the areas of the four regions or all regions may be unequal.

[0054] In this invention, by adjusting the extension length of the spiral path (i.e., the length of the spacer), the geometric dimensions of the conductive region and the total length of the current path can be changed, thereby flexibly adjusting the impedance matching characteristics of the capacitor and achieving wideband operation.

[0055] For example, in a preferred embodiment, some or all of the paths of the multiple spacer bands are formed according to the geometric principle of the Parker spiral, and different derivative forms of spacer bands can be formed by adjusting the extension length of the spacer bands, thereby effectively reducing parasitic inductance and further optimizing ESL.

[0056] It should be noted that, in this invention, the Parker spiral refers to a geometric construction method for dividing a planar region (such as a square) into several congruent or symmetrical sub-regions using multiple dividing lines of uniform length. Its core feature is that the dividing lines originate from the center of the planar region and extend outwards in a spiral shape along a pre-defined path (which can be stepped or a smooth curve), ultimately dividing the entire planar region into several compact and regularly distributed sub-regions. Although the Parker spiral is used in magnetohydrodynamics to describe the magnetic field structure of the solar wind, in this invention, its geometric construction principle is creatively applied to the design of conductive layer electrodes for micro / nano capacitors.

[0057] The spacer can be a trench structure (formed by etching) or an insulating dielectric filling structure.

[0058] When using a trench structure, a physical recessed region can be formed between multiple conductive areas through photolithography and etching on the conductive layer. This trench effectively cuts off the metal path, achieving electrical isolation, while suppressing lateral coupling and cross-region interference of surface currents in high-frequency operating environments. Since the trench itself is a cavity structure, its impact on the overall parasitic capacitance of the capacitor is relatively small, contributing to improved Q-value and frequency response characteristics of the device. Furthermore, the trench structure is relatively simple to manufacture, can be directly achieved through standard microelectronic etching processes, is suitable for most metal materials and conventional substrate systems, and exhibits good compatibility and stability.

[0059] When an insulating dielectric-filled structure is used, it exists as a solid insulating material within the conductive layer. Common materials include SiO2, Si3N4, polyimide (PI), or epoxy resin. Compared to trench structures, this structure offers greater dielectric control, not only blocking conductive paths but also redistributing and regulating the local electric field by adjusting the dielectric constant of the insulating material, thereby improving the overall electromagnetic field uniformity of the capacitor. The insulating dielectric-filled structure exhibits superior encapsulation reliability, effectively preventing short-circuit risks caused by environmental pollution, humidity erosion, or particulate contamination in the spaced areas. It is suitable for applications requiring high insulation performance and long-term stability.

[0060] A second aspect of the present invention provides a capacitor including the conductive layer described above.

[0061] A third aspect of the present invention provides a method for preparing a conductive layer for a capacitor. The method includes: providing a conductive layer; defining a segmentation path extending spirally from a central portion of the conductive layer outwards on the conductive layer; and forming a spacer band along the segmentation path on the conductive layer to divide the conductive layer into multiple mutually insulated conductive regions.

[0062] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0063] Example 1:

[0064] like Figure 1 As shown, this embodiment provides a conductive layer for a four-terminal capacitor. The conductive layer is constructed as an n×n two-dimensional grid array, where n is a positive integer and equals 6. Each grid cell represents a tiny conductive region (such as a micrometer-scale metal cube). In its undivided state, the entire conductive layer is a complete, continuous metal layer.

[0065] Based on a spiral spacer design, four spacer bands 20 (i.e., dividing lines) are formed on the conductive layer. Each spacer band 20 extends along the edge of the grid cell in the two-dimensional grid array, forming a stepped spiral path. Specifically, the four spacer bands 20 start from the four edges of the central region of the conductive layer and spiral outward around the central region, ultimately completely dividing the conductive layer into four conductive regions 10 of equal area and congruent rotation. These four conductive regions 10 serve as the four electrode regions of a four-terminal capacitor.

[0066] Because the spacer band 20 extends spirally outward from the central region, the four divided conductive regions 10 exhibit a highly symmetrical rotationally congruent structure. This symmetry ensures that the four electrode regions maintain a high degree of consistency in electrical performance, effectively reducing the imbalance of parasitic parameters.

[0067] In this embodiment, four spiral spacers originate from the four edges of the central region and extend outwards in a spiral pattern. This "four-way symmetrical" spiral path ensures that the four conductive regions are geometrically perfectly rotationally congruent. Rotational congruence means that rotating any conductive region 90° around the center will cause it to coincide with an adjacent conductive region. This high degree of geometric symmetry ensures that the four electrode regions maintain strict consistency in electrical parameters such as current path length, parasitic capacitance, and parasitic inductance, thereby ensuring performance matching of the four-terminal capacitor in differential or balanced applications and eliminating performance deviations caused by electrode asymmetry in traditional designs. The spiral path causes the current directions of adjacent electrodes to alternate spatially, resulting in mutual inductance cancellation and achieving a low overall ESL.

[0068] Example 2:

[0069] like Figure 2As shown, this embodiment provides a conductive layer for a four-terminal capacitor. The conductive layer is constructed as an n×n two-dimensional grid array, where n is a positive integer and equals 7. Each grid cell represents a tiny conductive region (such as a micrometer-scale metal cube). In its undivided state, the entire conductive layer is a complete, continuous metal layer.

[0070] The difference between this embodiment and Embodiment 1 is that in this embodiment, an undivided grid cell (i.e., central conductive 30) is formed in the central region of the conductive layer, but the four spacer bands 20 still completely divide the outer region of the conductive layer into four conductive regions 10. The undivided grid cell in the central region can be used as a connection point for the corresponding conductive regions in the four conductive regions 10 or as a filler chip identifier.

[0071] In other embodiments, the helical spacer bands can be designed based on the geometry of the Parker spiral, and can also form a shape similar to... Figure 1 and Figure 2 The spacer extends along the path, but the geometry of the Parker spiral is not limited to this. Figure 1 and Figure 2 The specific path shown is illustrated. In fact, by adjusting the starting point, number of spiral turns, extension direction, and step size of the Parker spiral, various spiral intervals can be generated.

[0072] Example 3:

[0073] like Figure 3 As shown in the figure, this embodiment demonstrates three derivative forms of spiral spacers in a 7×7 two-dimensional grid array. A is the basic form with a shorter spacer length; B is a form where the spacers are extended a short distance from A; and C is a form where the spacers are further extended to the outer corner of the conductive layer from B.

[0074] Figure 4 The simulation results for the three configurations described above are presented. The simulation conditions were set as a four-terminal capacitor, with a frequency sweep range from 0.1 GHz to 100 GHz. In the figure, the vertical axis represents the equivalent series inductance - ESL (in pH), and the horizontal axis represents the frequency (in GHz). The simulation results show that as the spacer length increases (from A to B to C), at a frequency of 17.715 GHz, the capacitor's ESL decreases from 99.63 pH to 81.45 pH, a decrease of approximately 18%. At other frequencies, the capacitor's ESL decreases to some extent with increasing spacer length. This indicates that by adjusting the extension length of the spiral spacer, the capacitor's ESL performance can be effectively controlled, thereby improving its high-frequency performance.

[0075] This embodiment demonstrates the effect of helical path length on ESL. In the basic configuration (A), the spacer path is short, and the current path is relatively concentrated. When the spacer path is extended (configurations B and C), the number of helical turns increases, the conductive region is further elongated, and the current path is forced to flow along the longer helical direction. This longer current path results in more complete current coupling between adjacent conductive regions and a stronger mutual inductance cancellation effect, thus further reducing ESL.

[0076] In this embodiment, by designing different spiral path lengths, precise control of ESL can be achieved to meet the specific requirements of ESL in different application scenarios.

[0077] Example 4:

[0078] like Figure 5 As shown, this embodiment provides a conductive layer for a two-terminal capacitor. In this embodiment, the number of spiral spacers 20 is two, dividing the conductive layer into two conductive regions 10. These two conductive regions 10 are centrally symmetrically distributed around the center of the conductive layer (i.e., a distribution similar to a yin-yang symbol), and the areas of the two conductive regions 10 are equal. The two conductive regions 10 serve as the two electrode regions of the two-terminal capacitor.

[0079] Experiments have verified that the two-terminal capacitor formed in this embodiment has excellent radio frequency performance. For example... Figure 6 As shown, the dual-terminal capacitor formed in this embodiment has an insertion loss m1 better than -0.5dB and a reflection loss m2 better than -25dB in a frequency range up to 70GHz, which is significantly better than that of traditional dual-terminal capacitors.

[0080] In this embodiment, only two spiral spacers are used to divide the conductive layer into two conductive regions. These two regions are centrally symmetrically distributed around the center of the conductive layer. This distribution causes the current paths in the two electrode regions to form a "complementary spiral" shape—the current in one region flows clockwise, and the current in the other region flows counterclockwise. This reverse current flow creates mutual inductance cancellation in space, thereby effectively reducing the overall ESL of the two-terminal capacitor.

[0081] Example 5:

[0082] like Figure 7As shown, this embodiment also provides a conductive layer for a four-terminal capacitor. The difference between this embodiment and Embodiment 2 is that in this embodiment, the conductive layer is constructed as an n×n two-dimensional grid array, where n is a positive integer and n equals 13. The central region of the conductive layer still forms an undivided grid cell (i.e., the central conductive layer 30), and the four spacer bands 20 still completely divide the outer region of the conductive layer into four conductive regions 10. This undivided grid cell in the central region can also be used as a connection point for the corresponding conductive region among the four conductive regions 10 or as a filler chip identifier.

[0083] Example 6:

[0084] like Figure 8 As shown, this embodiment provides a conductive layer for a nine-terminal capacitor. In this embodiment, there are eight spiral spacers 20, dividing the conductive layer into eight peripheral conductive regions 10 and one central conductive region 30. The eight peripheral conductive regions 10 serve as the eight electrode regions of the capacitor, while the central conductive region 30 is not divided by the spacers 20 and is insulated from the peripheral conductive regions 10. The central conductive region 30 can serve as a connection point to connect diagonal electrodes or as an independent area to fill a chip identifier (ID). This design allows the nine-terminal capacitor to provide more electrical connection options while also integrating chip identification functionality.

[0085] In this embodiment, due to the wrapping characteristics of the spiral path, although the areas of these eight conductive regions are not exactly equal, each region has a narrow spiral shape that radiates outward from the center. This shape allows the current path in the electrode region to flow along the spiral direction, effectively suppressing parasitic inductance. At the same time, the undivided area in the center provides additional flexibility for circuit design.

[0086] In other embodiments, the spiral spacers can also be designed based on the Parker spiral geometry. Thus, the resulting eight peripheral conductive regions are divided into two groups: a first region and a second region. The first and second regions are arranged circumferentially alternately around the center of the conductive layer, i.e., sequentially, along the circumference, they are: first region, second region, first region, second region, first region, second region, first region, second region. The first regions have equal areas and are rotationally symmetrically distributed among themselves. The second regions have equal areas and are rotationally symmetrically distributed among themselves.

[0087] The first and second regions may differ in geometry (e.g., the first region is wider and the second region is narrower), but their respective sets of interiors maintain equal areas and rotational symmetry. In this embodiment, since the helical path based on the Parker spiral extends outward from the center, the alternating distribution of the first and second regions remains consistent in each turn of the helical path, thereby ensuring overall helical symmetry.

[0088] This embodiment divides the eight regions into two groups (four in each group) and ensures symmetry within each group, maintaining overall helical symmetry and electrical performance balance without requiring all eight regions to be completely identical. This design is particularly suitable for applications that require differentiation between two groups of electrodes (e.g., input and output groups).

[0089] Example 7:

[0090] As the density of the two-dimensional grid array increases significantly (i.e., the grid cell size decreases), the path accuracy of the stepped spacing band 20 improves, and its geometry gradually approaches a smooth spiral curve. A continuous spiral curve has a shorter path length (compared to a stepped path) and a smoother current distribution, which can further reduce current path discontinuities and radiation losses, reduce current concentration effects at corners, and further reduce equivalent series resistance (ESR) and ESL. This means that the present invention is also applicable to smooth spiral segmentation structures implemented using high-precision photolithography processes (such as electron beam lithography), enabling the achievement of higher-performance capacitors.

[0091] like Figure 9 As shown, the present invention also provides a method for preparing a conductive layer for a capacitor, specifically including the following steps:

[0092] S1 provides a conductive layer.

[0093] On a substrate, such as a silicon wafer, glass sheet, or ceramic substrate, or on an existing capacitor structure (electrode layer-dielectric layer-electrode layer stacked structure, with a conductive layer used for electrical lead-out of the top electrode layer), a conductive material (such as metals or alloys like copper, aluminum, gold, or silver) is deposited using methods such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or electroplating to form a conductive layer.

[0094] S2, a two-dimensional grid array is constructed on the conductive layer.

[0095] To improve the accuracy of the segmentation path, an n×n two-dimensional grid array pattern is constructed on the conductive layer using photolithography through CAD or other design software. n is a positive integer and n≥2, forming a reference frame that provides the basic coordinates for the subsequent construction of the spiral spacer.

[0096] S3, determine the spiral segmentation path.

[0097] Based on a two-dimensional grid array, fractal curves with strong space-occupying capacity and good path continuity, such as the Parker spiral or its variants, are used to define a segmented path on the conductive layer that extends spirally outward from the edge of the grid cell in the grid array, starting from the center of the conductive layer. By adjusting the extension length of the Parker spiral path (i.e., the length of the spacer), the geometric dimensions of the conductive region and the total length of the current path can be changed, thereby flexibly adjusting the impedance matching characteristics of the capacitor and achieving wideband operation.

[0098] S4 forms a spacer zone.

[0099] Spacer bands are formed on the conductive layer along the dividing path determined in step S3. The spacer bands can be formed by etching or by filling with an insulating dielectric.

[0100] For example, a mask is formed on the surface of the conductive layer using photolithography, and the exposed conductive material is removed by dry etching or wet etching to form spacer bands in a trench structure. Further, insulating dielectric materials (such as silicon dioxide, silicon nitride, polyimide, etc.) are filled into the trenches to form spacer bands in an insulating dielectric-filled structure.

[0101] Compared with the prior art, the beneficial effects of the present invention are as follows.

[0102] This invention can significantly reduce equivalent series inductance (ESL). By using a spiral spacer design, this invention optimizes the distribution of current paths, causing the current paths in adjacent electrode regions to form a spiral mutual coupling effect, thereby effectively canceling out self-inductance and mutual inductance, and achieving a significant reduction in ESL (up to 18% or more).

[0103] This invention features wideband operation. By adjusting the extension length of the helical path and the geometric parameters of the conductive region, this invention can flexibly optimize the impedance matching of the capacitor, enabling it to maintain good RF performance over a wide bandwidth.

[0104] This invention improves electrode symmetry. The geometric characteristics of the spiral path in this invention ensure that the segmented conductive regions have a high degree of structural and electrical symmetry (e.g., rotational congruence), which is crucial for improving the performance of differential and balanced circuits.

[0105] This invention offers high design flexibility. The design method of this invention is applicable to various multi-terminal capacitor structures, including two-terminal, four-terminal, and nine-terminal capacitors, and can be extended to any number of terminals. Furthermore, it is suitable for square grid arrays and allows for differences in the area of ​​the conductive regions.

[0106] The present invention has strong process compatibility. The spacer structure of the present invention can be realized by standard semiconductor manufacturing processes such as photolithography, etching, and insulating dielectric filling, and has good compatibility with existing micro-nano manufacturing technologies.

[0107] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0108] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A conductive layer for a capacitor, characterized in that, The conductive layer is divided into multiple mutually insulated conductive regions by at least two spacer bands, each of the spacer bands being configured to extend spirally outward from the central region of the conductive layer; wherein... The conductive layer is completely divided by the spacer band, or the central region of the conductive layer has a central conductive region that is not divided by the spacer band and is insulated from the conductive region.

2. The capacitor conductive layer according to claim 1, characterized in that, The conductive layer is constructed as an n×n two-dimensional grid array, where n is a positive integer and n≥2; the spacer band extends spirally along the edge of the grid cell in the grid array.

3. The capacitor conductive layer according to claim 2, characterized in that, When n is odd, the central region of the conductive layer forms an undivided central conductive region; and / or, When n is an even number, the conductive layer is completely divided by the spacer band.

4. The capacitor conductive layer according to claim 1 or 2, characterized in that, The lengths of the multiple spacer bands are equal.

5. The capacitor conductive layer according to claim 1 or 2, characterized in that, The plurality of conductive regions include a plurality of first regions and a plurality of second regions, wherein the first regions and the second regions are arranged alternately in a circumferential direction around the central region of the conductive layer; wherein, Multiple first regions have equal areas, and multiple second regions have equal areas.

6. The capacitor conductive layer according to claim 5, characterized in that, Multiple first regions are rotationally symmetric; multiple second regions are rotationally symmetric.

7. The capacitor conductive layer according to claim 1 or 2, characterized in that, All conductive regions in the plurality of conductive regions have the same area; or, In multiple conductive regions, some conductive regions have equal areas; or, The areas of all conductive regions in the multiple conductive regions are not equal.

8. The capacitor conductive layer according to claim 7, characterized in that, All conductive regions in the plurality of conductive regions have the same area, and all conductive regions are rotationally symmetrically distributed; or, In the plurality of conductive regions, some conductive regions have equal areas, and the conductive regions with equal areas are distributed in a rotationally symmetrical manner.

9. The capacitor conductive layer according to claim 1 or 2, characterized in that, The spacer band is at least partially in the shape of a Parker spiral; and / or, The spacer band is a trench structure or a filling structure formed by an insulating medium.

10. A method for preparing a conductive layer for a capacitor, characterized in that, include: Provide a conductive layer; A segmented path is formed on the conductive layer, extending in a spiral shape from the central region of the conductive layer outwards; A spacer band is formed on the conductive layer along the segmentation path, dividing the conductive layer into multiple mutually insulated conductive regions; in, The conductive layer is completely divided by the spacer band, or the central region of the conductive layer has a central conductive region that is not divided by the spacer band and is insulated from the conductive region.

11. The conductive layer according to claim 10, characterized in that, Creating segmented paths on the conductive layer that extend spirally from the central region of the conductive layer outwards, including: A two-dimensional grid array is constructed on the conductive layer; Based on the two-dimensional grid array, a segmented path is formed on the conductive layer, extending in a spiral shape along the edge of the grid cell in the grid array.

12. A capacitor structure, characterized in that, Includes the conductive layer as described in any one of claims 1 to 9.

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