Chip multilayer ceramic capacitor, method of manufacturing the same, and electronic device

Abstract

The application belongs to the field of capacitors, and particularly discloses a chip multilayer ceramic capacitor, a preparation method thereof and electronic equipment. The chip multilayer ceramic capacitor comprises a laminated body and end electrodes arranged at both ends of the laminated body, and is characterized in that: the laminated body comprises composite dielectric layers and internal electrodes arranged in layers; the composite dielectric layer comprises a ceramic dielectric layer and a sealing hole self-repairing layer arranged on the ceramic dielectric layer; the sealing hole self-repairing layer contains an insulating phase; the insulating phase comprises at least one of SiO x , TiO x , ZrO x , AlO y , SiOC and SiCN. The chip multilayer ceramic capacitor has reduced leakage rate, improved breakdown consistency, reduced electrode edge breakdown probability, reduced composite dielectric layer peak and impact stress defects, and enhanced interlayer interface stability.

Description

Technical Field

[0001] This invention relates to the field of capacitor technology, and in particular to a chip multilayer ceramic capacitor, its preparation method, and an electronic device thereof. Background Technology

[0002] Multilayer ceramic capacitors (MLCCs) consist of multiple alternating layers of internal electrodes and ceramic dielectric. Their capacitance is directly proportional to the number of layers; increasing the number of layers can increase the capacitance without changing the volume. However, with the continuous reduction in the thickness of the dielectric layer and the significant increase in the number of layers in MLCCs, the fabrication process faces severe technical challenges. (1) Thin dielectric layer is sensitive to defects: pinholes, microcracks, inclusions and local weak areas in the dielectric layer are prone to become leakage channels and breakdown sources, and they have a cumulative amplification effect with the increase of the number of stacked layers, which seriously degrades the breakdown field strength and reliability of the device. (2) Electric field concentration at the electrode edge: The geometrical abrupt change of the internal electrode causes local electric field distortion and peak value increase, which increases the breakdown probability and makes it difficult to control the breakdown voltage dispersion; (3) Poor interlayer interface adaptation: Microscopic peaks on the surface of the dielectric layer and thermal / stress mismatch during the stacking process generate cumulative stress, which induces structural failures such as electrode delamination and dielectric cracking. (4) Lack of online repair mechanism: The existing process relies too much on end-of-line electrical screening and lacks in-situ suppression or self-repair methods for internal defects in the stacking process, resulting in a significant reduction in the yield of high-layer products.

[0003] To address the aforementioned technical challenges, the industry has explored the introduction of aerosol deposition (AD / ADM) technology into the fabrication of MLCC stacks. However, existing methods still have significant drawbacks: on the one hand, when using droplet drying to prepare the dielectric layer, solvent evaporation and particle accumulation processes easily introduce structural defects such as pores and pinholes, resulting in insufficient dielectric density; on the other hand, although aerosol deposition can produce dielectric layers with high density, high-speed particle impacts introduce residual stress and surface spikes, and the lack of online suppression and repair mechanisms leads to significant yield fluctuations as the number of stacks increases. Furthermore, the aforementioned approaches mostly rely on increasing the thermal budget or local high-temperature annealing to improve dielectric performance; however, high-temperature processes are limited by the thermal compatibility and thermal stress issues between the electrodes and the ceramic dielectric, making it difficult to achieve simultaneous improvements in performance and reliability in high-layer stack structures.

[0004] Therefore, it is necessary to provide a new type of capacitor and a corresponding stacking manufacturing process to achieve dielectric densification, electrode pattern precision control and online defect suppression in the layer-by-layer stacking process, so as to meet the needs of large-scale manufacturing of high-layer-number and high-reliability MLCCs. Summary of the Invention

[0005] In order to overcome at least one of the technical problems existing in the prior art, one of the objectives of the present invention is to provide a chip multilayer ceramic capacitor.

[0006] The second objective of this invention is to provide a method for preparing a chip-type multilayer ceramic capacitor.

[0007] The third objective of this invention is to provide an electronic device.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A first aspect of the present invention provides a chip-type multilayer ceramic capacitor, comprising a laminate and end electrodes disposed at both ends of the laminate, wherein the laminate comprises a composite dielectric layer and an inner electrode stacked thereon; the composite dielectric layer comprises a ceramic dielectric layer and a self-healing sealing layer disposed on the ceramic dielectric layer; The self-healing sealing layer contains an insulating phase; the insulating phase includes at least one of SiOx, TiOx, ZrOx, AlOy, SiOC, and SiCN, wherein each x in SiOx, TiOx, and ZrOx is independently 0 < x ≤ 2; and y in AlOy is 0 < y ≤ 1.5.

[0009] In some embodiments of the present invention, the raw materials for preparing the pore-sealing self-healing layer include a pore-sealing precursor; the pore-sealing precursor includes at least one of a sol-gel inorganic precursor, a pre-ceramic polymer precursor, and an inorganic-organic hybrid precursor.

[0010] In some embodiments of the present invention, the sol-gel inorganic precursor includes at least one of a silane precursor and a metal source precursor.

[0011] In some embodiments of the present invention, the silane precursor includes at least one of tetraethyl orthosilicate (TEOS), tetramethyl orthosilicate (TMOS), methyltriethoxysilane (MTES), and glycidyl etheroxypropyltrimethoxysilane (GPTMS).

[0012] In some embodiments of the present invention, the metal source precursor includes at least one of a titanium source, a zirconium source, and an aluminum source.

[0013] In some embodiments of the present invention, the titanium source includes at least one of tetraisopropyl titanate (TTIP) and tetrabutyl titanate (TBOT); in some embodiments of the present invention, the zirconium source includes tetraalkoxyzirconium, with the general formula Zr(OR)4, wherein each R is independently C. 1-5The alkyl group, for example, each R is independently selected from methyl, ethyl, propyl, isopropyl, n-butyl, sec-butyl, isobutyl, tert-butyl, n-pentyl, sec-pentyl, 3-pentyl, 3-methylbutyl, 1,1-dimethylpropyl, 2,2-dimethylpropyl, 2-methylbutyl, 3-methylbut-2-yl; in some embodiments of the invention, the aluminum source includes aluminum isopropoxide, i.e., Al(O-iPr)3.

[0014] In some embodiments of the present invention, the pre-ceramic polymer precursor includes at least one of polysiloxane, polysilazane (PHPS), and polycarbosilane (PCS).

[0015] In some embodiments of the present invention, the inorganic-organic hybrid precursor may be an organic modified silicate (ORMOSIL) system. For example, it may be a cross-linked network formed by tetraethyl orthosilicate (TEOS) and γ-glycidoxypropyltrimethoxysilane (GPTMS), TEOS and methyltriethoxysilane (MTES), or silane coupling agent KH590 (MPTMS). To further improve dielectric strength, a small amount of nano-SiO2 or nano-Al2O3 may also be incorporated into the precursor. It is understood that after curing or transformation, the final phases of different precursors may be the same or different, but all should form a continuous, high-resistivity insulating phase compatible with the ceramic dielectric layer. The insulating phase may be SiO2. x TiO x ZrO x AlO y The insulating phase comprises SiOC, SiCN, or their composite oxides and / or hybrid networks. The insulating phase at least partially fills the pores of the ceramic dielectric layer.

[0016] In this invention, after hydrolysis, condensation, heat treatment, or oxidation treatment, the sealing precursor can form a corresponding oxide network structure, including SiO2. x TiO x ZrO x and AlO y One or more of the following. Among them, SiO x The value of x in TiO2 is in the range of 0 < x ≤ 2, preferably 1.8-2, and more preferably 1.9-2; x The value of x in ZrO is in the range of 0 < x ≤ 2, preferably 1.8-2, and more preferably 1.9-2; x The value of x in the equation is 0 < x ≤ 2, preferably 1.8-2, and more preferably 1.9-2; AlO y The value of y in the equation is in the range of 0 < y ≤ 1.5, preferably 1.3-1.5, and more preferably 1.4-1.5. More preferably, the SiO... x TiO x ZrOx and AlO y These correspond to SiO2, TiO2, ZrO2, and Al2O3, respectively.

[0017] More specifically, after the sealing precursor undergoes a sol-gel reaction, it forms a network layer containing various inorganic oxide bonding structures: on the one hand, it includes oxygen bridges between the same metal or metalloid elements such as Si—O—Si, Ti—O—Ti, Zr—O—Zr, and Al—O—Al; on the other hand, it also includes cross-linked oxygen bridges between dissimilar atoms such as Si—O—Ti, Si—O—Zr, Si—O—Al, Ti—O—Zr, Ti—O—Al, and Zr—O—Al. The resulting continuous and dense inorganic oxide network layer can significantly improve the material's density, insulation, heat resistance, moisture resistance, and interfacial bonding strength.

[0018] In some embodiments of the present invention, the edge of the inner electrode is provided with a field strength homogenization structure; the field strength homogenization structure includes at least one of electrode edge rounding, electrode edge thinning region, and electrode edge retreat region.

[0019] In some embodiments of the present invention, the edges of the inner electrode are rounded.

[0020] A second aspect of the present invention provides a method for preparing the multilayer ceramic chip capacitor described in the first aspect of the present invention, comprising the following steps: S1: A seed layer and a dense layer are sequentially deposited on the activated substrate using an aerosol deposition method to obtain a ceramic dielectric layer; S2: The sealing precursor is sprayed onto the ceramic dielectric layer using an aerosol jet printing method. After curing, a self-healing sealing layer is obtained. S3: Metal is deposited on the self-healing sealing layer using aerosol jet printing, followed by densification treatment to obtain the inner electrode; S4: Repeat steps S1-S3, repeating ≥2 times, to obtain a stacked body; S5: Prepare terminal electrodes on the laminate to obtain the chip multilayer ceramic capacitor.

[0021] In some embodiments of the present invention, the substrate is an alumina ceramic substrate, an aluminum nitride ceramic substrate, a glass substrate, a silicon wafer, or a metal substrate.

[0022] In some embodiments of the present invention, the activated substrate refers to the substrate having undergone an activation treatment, wherein the activation treatment is selected from at least one of UV-ozone treatment, oxygen plasma treatment, argon plasma treatment, and chemical activation treatment.

[0023] Furthermore, when the substrate is a metal substrate, after the activation treatment is completed, an insulating layer needs to be formed on the substrate surface to achieve electrical isolation and enhance the adhesion stability of the first dielectric layer.

[0024] In some embodiments of the present invention, the insulating layer is an inorganic insulating layer, which is selected from at least one of oxide ceramic insulating materials, Si3N4, AlN, and BN; in some embodiments of the present invention, the oxide ceramic insulating material is selected from Al2O3, SiO2, ZrO2, TiO2, MgO, Y2O3, and H2O. f At least one of O2.

[0025] In some embodiments of the present invention, the thickness of the insulating layer is 0.1-5 μm.

[0026] In some embodiments of the present invention, the preparation method further includes the step of setting a hard sacrificial layer on the surface of the activated substrate; this step is located between step S1 and step S2.

[0027] In some embodiments of the present invention, the thickness of the hard sacrificial layer is preferably 0.1-10 μm.

[0028] In this invention, the hard sacrificial layer is not necessary. For embodiments that require separating the stacked structure from the carrier substrate after stacking to obtain an independent MLCC stacked blank, the hard sacrificial layer may be provided; for embodiments that directly retain the carrier substrate in an integrated or embedded capacitor structure, the hard sacrificial layer may be omitted.

[0029] In some embodiments of the present invention, the preparation method further includes a step of performing online detection and defect determination, which is located between step S2 and step S3.

[0030] In some embodiments of the present invention, the online detection is performed using at least one of the following methods: optical reflection / scattering detection, online measurement of surface morphology or roughness, local leakage current scanning, and local capacitance response scanning detection.

[0031] In some embodiments of the present invention, the preparation method further includes online detection of the self-healing sealing layer, followed by defect determination based on the online detection results. When the defect determination result exceeds a threshold, a rework operation is triggered. The rework operation includes: repeatedly forming the self-healing sealing layer and performing online detection again, determining defects based on the online detection results; or, performing local deposition of a ceramic dielectric layer on the defective area in the self-healing sealing layer, forming the self-healing sealing layer again, performing online detection again, and determining defects based on the online detection results. Online detection and rework operations can eliminate defects in the self-healing sealing layer, thereby improving the yield of high-layer stacks. The present invention employs online detection and defect determination steps, triggering a rework operation when the defect determination exceeds a threshold, performing repair or local re-deposition before the defect enters the next stack, thereby improving the manufacturing yield of capacitors.

[0032] In some embodiments of the present invention, the substrate needs to be cleaned before activation treatment.

[0033] In some embodiments of the present invention, the cleaning includes organic solvent cleaning and water rinsing. Specifically, the organic solvent is selected from acetone or isopropanol. Further, the cleaning is followed by a drying process. Optionally, the cleaning time for each cleaning medium is 3-10 minutes.

[0034] In some embodiments of the present invention, the drying is performed at 60-120°C for 5-30 minutes to remove particulate contaminants, oil stains and residual organic matter.

[0035] In some embodiments of the present invention, the activation treatment time is 0.1s-25min; optionally, the activation treatment time is 30s-20min. More optionally, the activation treatment time is 3min-10min. By controlling the activation treatment time within the above range, the surface energy and surface activity of the substrate can be effectively improved, enhancing the adhesion between the substrate and the first dielectric layer, thereby reducing the risks of delamination, voids, and interface instability during the dielectric layer deposition process.

[0036] The present invention sets up a substrate layer to provide a continuous and stable bearing surface for the aerosol deposition of the first ceramic dielectric layer, and to provide a flat reference surface and mechanical support for the subsequent formation of the self-healing sealing layer and the preparation of the internal electrodes, thereby ensuring that the laminate can be stably constructed layer by layer.

[0037] In some embodiments of the present invention, the thicknesses of the dense layer and the seed layer are 0.2-7 μm, respectively; optionally, the thicknesses of the dense layer and the seed layer are 0.5-5 μm, respectively; optionally, the thicknesses of the dense layer and the seed layer are 0.8-3 μm, respectively; further optionally, the thicknesses of the dense layer and the seed layer are 1-2 μm, respectively.

[0038] In some embodiments of the present invention, the seed layer is formed by depositing raw material powder onto a substrate using an aerosol deposition method. In some embodiments of the present invention, the seed layer is formed by spraying a mixed gas stream of raw material powder and carrier gas onto the substrate surface through a nozzle.

[0039] In some embodiments of the present invention, the raw material powder of the seed layer is selected from at least one of barium titanate and modified barium titanate.

[0040] In some embodiments of the present invention, the modified barium titanate in the seed layer includes Sr-doped barium titanate powder, namely Ba(Sr)TiO3.

[0041] In some embodiments of the present invention, when preparing the seed layer, the carrier gas includes at least one of nitrogen, argon, and helium.

[0042] In some embodiments of the present invention, when preparing the seed layer, the D of the raw material powder 50 The particle size is 0.05-1 μm; optionally, the D of the raw material powder is... 50 The particle size is 0.05-0.50 μm; further optionally, the D of the raw material powder is... 50 It is 0.1-0.3μm.

[0043] In some embodiments of the present invention, when preparing the seed layer, the carrier gas flow rate is 0.3-8 L / min; optionally, the carrier gas flow rate is 1-6 L / min; further optionally, the carrier gas flow rate is 2-4 L / min.

[0044] In some embodiments of the present invention, the distance between the nozzle and the substrate is 1-15 mm when preparing the seed layer.

[0045] In some embodiments, the scanning speed during the preparation of the seed layer is 1-110 mm / s, preferably 5-100 mm / s, and more preferably 20-60 mm / s.

[0046] In some embodiments of the present invention, the overlap rate between scan tracks is 30%-70% when the seed layer is prepared.

[0047] In some embodiments of the present invention, when preparing the seed layer, the thickness of the seed layer formed in a single step is 0.05-0.50 μm.

[0048] In some embodiments of the present invention, when preparing the seed layer, the thickness of the seed layer formed in a single step accounts for 2-35% of the total thickness of the seed layer; optionally, the thickness of the seed layer formed in a single step accounts for 5-30% of the total thickness of the seed layer; further optionally, the thickness of the seed layer formed in a single step accounts for 10-20% of the total thickness of the seed layer.

[0049] In some embodiments of the present invention, the dense layer is formed by depositing raw material powder onto the seed layer using an aerosol deposition method. In some embodiments of the present invention, the dense layer is formed by spraying a mixed gas flow of raw material powder and carrier gas onto the surface of the seed layer through a nozzle.

[0050] In some embodiments of the present invention, the raw material powder of the dense layer is selected from at least one of barium titanate and modified barium titanate.

[0051] In some embodiments of the present invention, the modified barium titanate in the dense matrix includes Sr-doped barium titanate powder, namely Ba(Sr)TiO3.

[0052] In some embodiments of the present invention, when preparing the dense layer, the raw material powder D 50 The particle size is 0.10-3.0 μm; optionally, the raw material powder D 50 The particle size is 0.10-1.0 μm; further optionally, the raw material powder D 50 The thickness is 0.20-0.6 μm.

[0053] In some embodiments of the present invention, when preparing the dense layer, the carrier gas flow rate is 1-12 L / min; optionally, the carrier gas flow rate is 2-10 L / min; further optionally, the carrier gas flow rate is 3-6 L / min.

[0054] In some embodiments of the present invention, the distance between the nozzle and the substrate is 1-20 mm when the dense layer is prepared.

[0055] In some embodiments of the present invention, the scanning speed during the preparation of the dense layer is 0.3-85 mm / s; preferably, the scanning speed is 1-80 mm / s; more preferably, the scanning speed is 10-40 mm / s.

[0056] In some embodiments of the present invention, the overlap rate between scanning channels is 40%-80% when the dense layer is prepared.

[0057] In some embodiments of the present invention, when preparing the dense layer, the thickness of the dense layer formed in a single step accounts for 20%-80% of the total thickness of the dense layer; optionally, the thickness of the dense layer formed in a single step accounts for 30%-70% of the total thickness of the dense layer; more preferably, the thickness of the dense layer formed in a single step accounts for 35%-60% of the total thickness of the dense layer. The final scan deposition is used to supplement the target thickness and improve the thickness uniformity and surface density of the dense layer.

[0058] In some embodiments of the present invention, the dense layer and the seed layer are preferably made of the same family of host medium materials.

[0059] In this invention, each composite dielectric layer adopts a two-stage deposition process, which includes a seed layer deposition stage and a compaction layer deposition stage. The seed layer is used to correct the lower surface morphology, suppress the formation of spikes and reduce the risk of impact-induced microcracks, while the compaction layer is used to achieve the target thickness and high density.

[0060] This invention employs aerosol jet printing (AJP) to deposit a low-viscosity, penetrating pore-sealing precursor onto the surface of the ceramic dielectric layer through precursor atomization, sheath gas focusing, and nozzle scanning deposition. This allows the precursor to penetrate into pinholes, microcracks, or micropores, and is then cured at low temperature to form a pore-sealing self-healing layer. This pore-sealing self-healing layer and the ceramic dielectric layer together constitute a composite dielectric layer.

[0061] In some embodiments of the present invention, the chip multilayer ceramic capacitor contains at least one composite dielectric layer, which is composed of a ceramic dielectric layer formed by AD / ADM and a self-healing sealing layer formed by AJP, wherein the self-healing sealing layer penetrates into the defects of the ceramic dielectric layer.

[0062] The composite dielectric layer fabrication of this invention aims at "density and controllable defects": MLCC failure is usually triggered by extreme defects in the ceramic dielectric layer. AD / ADM densification through particle impact is beneficial for obtaining a highly dense ceramic dielectric layer, but the surface peaks and impact stress generated during its deposition process need to be suppressed. Therefore, this invention employs a two-stage deposition process, first constructing a seed layer, and then thickening it to form a dense layer.

[0063] In some embodiments of the present invention, when preparing the self-healing sealing layer, the viscosity of the sealing precursor is 0.5-22 mPa·s; optionally, the viscosity of the sealing precursor is 1-20 mPa·s; further optionally, the viscosity of the sealing precursor is 3-10 mPa·s. When the viscosity of the sealing precursor is within the range defined by the present invention, multiple requirements for capillary penetration, surface leveling, and stable AJP printing can be simultaneously met.

[0064] For thin dielectric laminates, failure is usually caused by a small number of pinholes or microcracks forming conductive channels. Therefore, the key to their fabrication lies in 'defect channel sealing' and 'in-process repair'. The sealing precursor, after infiltration and curing, can form a continuous insulating phase within the defect channel, cutting off the conductive path. Further combining online detection and triggered rework allows repair to be completed before defects progress to the next layer, thereby significantly improving the manufacturing yield of high-layer laminates.

[0065] In some embodiments of the present invention, when preparing the self-healing sealing layer, the nozzle orifice diameter is 80-300 μm.

[0066] In some embodiments of the present invention, when preparing the self-healing sealing layer, the distance between the nozzle and the substrate is 1-5 mm.

[0067] In some embodiments of the present invention, when preparing the sealing self-healing layer, the flow rate ratio of the atomizing gas to the sheath gas is 1:(1-6).

[0068] In some embodiments of the present invention, the curing method of the self-healing sealing layer is selected from at least one of ultraviolet curing, photon pulse curing, heat treatment and annealing.

[0069] In some embodiments of the present invention, the curing temperature of the self-healing sealing layer is 60-270°C; optionally, the curing temperature is 80-250°C; further optionally, the curing temperature is 120-200°C.

[0070] In some embodiments of the present invention, the curing time of the self-healing sealing layer is 0.5-70 min; optionally, the curing time is 1-60 min; further optionally, the curing time is 5-30 min.

[0071] In some embodiments of the present invention, after the self-healing sealing layer is formed, the visible defect density of the composite dielectric layer is ≤0.1 defects / m². 2 .

[0072] The present invention uses AJP to deposit metal electrode patterns on the surface of the composite dielectric layer, and then densifies them to form conductive and continuous inner electrodes; the inner electrodes are provided with field strength homogenization structures at their edges.

[0073] In some embodiments of the present invention, the field strength homogenization structure refers to the rounding of the edges of the inner electrode. The field strength homogenization structure can reduce local electric field concentration at the edges of the inner electrode and reduce the risk of edge breakdown. The field strength homogenization structure may include at least one of electrode edge rounding, electrode edge thinning regions, and / or electrode edge recess regions.

[0074] In this invention, the internal electrode is preferably prepared using AJP process parameters that are different from those used for the self-healing sealing layer.

[0075] In some embodiments of the present invention, the nozzle aperture during the fabrication of the internal electrode is 30-150 μm.

[0076] In some embodiments of the present invention, the distance between the nozzle and the substrate is 1-5 mm during the fabrication of the internal electrode.

[0077] In some embodiments of the present invention, the scanning speed during the fabrication of the internal electrode is 5-100 mm / s.

[0078] In some embodiments of the present invention, the densification treatment during the fabrication of the internal electrode is selected from at least one of heat treatment, photon pulse sintering, and laser local densification. The densification treatment is used to remove organic components, enhance the contact continuity between conductive particles, and reduce electrode resistance.

[0079] In some embodiments of the present invention, the densification temperature during the fabrication of the internal electrode is 60-320°C; optionally, the densification temperature is 80-300°C; further optionally, the densification temperature is 120-250°C.

[0080] In some embodiments of the present invention, the densification treatment time during the fabrication of the internal electrode is 0.5-65 min; optionally, the densification treatment time is 1-60 min; further optionally, the densification treatment time is 5-30 min.

[0081] In some embodiments of the present invention, the material of the internal electrode is at least one selected from Ni, Cu, and Ag.

[0082] The fabrication of internal electrode patterns needs to balance high resolution and edge manipulation capabilities. AJP has programmable pattern deposition capabilities, making it suitable for constructing internal electrodes on the surface of composite dielectric layers and achieving electric field homogenization through edge geometry or material transitions, thereby reducing the risk of edge breakdown.

[0083] A third aspect of the present invention provides an electronic device including the chip multilayer ceramic capacitor described in the first aspect of the present invention.

[0084] In some embodiments of the present invention, the electronic device includes an imaging device, a computer, a personal digital assistant (PDA), or a mobile phone; the imaging device includes a liquid crystal display, a plasma display panel, etc.

[0085] The beneficial effects of the present invention are: the leakage rate of the chip multilayer ceramic capacitor of the present invention is reduced, the breakdown consistency is improved, the breakdown probability of the electrode edge is reduced, the peak and impact stress defects of the composite dielectric layer are reduced, and the interlayer interface stability is enhanced.

[0086] The multilayer ceramic chip capacitor of this invention has an intralayer thickness variation coefficient CVt ≤ 10%, an interlayer thickness deviation ≤ 15%, a surface roughness Ra ≤ 0.20 μm, and a visible defect density per unit area ≤ 0.1 defects / m². 2 Steady-state leakage current density ≤ 1×10 -7 A / cm 2 Average breakdown field strength E bd ≥150 V / μm; breakdown field strength variation coefficient ≤15%, which can meet the requirements of high-performance capacitors.

[0087] This invention utilizes aerosol deposition / aerosol fusion deposition (AD / ADM) to prepare the ceramic dielectric layer and aerosol jet printing (AJP) to prepare the internal electrode, thereby improving the stacking consistency and yield of the multilayer ceramic capacitor. Specifically, a two-stage AD / ADM process is used to prepare the ceramic dielectric layer on the substrate or the previous internal electrode to reduce surface spike defects and impact-induced microcracks. Subsequently, an AJP process is used to apply a permeable sealing precursor and then cured at low temperature to form a self-healing sealing layer to seal pinholes, microcracks, and micropore channels. Finally, AJP is used to form the internal electrode pattern, and a field strength homogenization structure is set at the edge of the internal electrode to reduce edge electric field peaks. Through the synergistic effect of the above processes, breakdown consistency can be improved under the condition of a high number of stacked layers of composite dielectric layer and internal electrode. Simultaneously, increasing the number of stacked layers without changing the volume can significantly increase the capacitance. This method is applicable to the fabrication of different models of chip multilayer ceramic capacitors, such as 0603, 0402, and 0201. Detailed Implementation

[0088] The following examples provide a more detailed description of the specific implementation of the present invention, but the implementation and protection of the present invention are not limited thereto. It should be noted that any processes not specifically described below are methods that can be implemented or understood by those skilled in the art by referring to existing technology. Reagents or instruments whose manufacturers are not specified are all commercially available conventional products.

[0089] Example 1 This example provides a method for fabricating a multilayer ceramic chip capacitor, with the following specific steps: (1) Substrate preparation: The surface of the alumina ceramic substrate is cleaned and activated; The sample was ultrasonically cleaned sequentially with acetone and deionized water, with each medium taking 7 minutes to clean; then dried at 100°C for 20 minutes.

[0090] After ultrasonic cleaning, the alumina ceramic substrate was activated using a UV-Ozone cleaner for 7 minutes.

[0091] (2) Formation of the medium layer: A ceramic medium layer is deposited on the activated alumina ceramic substrate by aerosol deposition (AD / ADM). The ceramic medium layer is deposited in two stages, namely, seed layer deposition and compact layer deposition are performed sequentially. The total thickness of the dielectric layer is 4μm. The dielectric layer consists of a seed layer and a dense layer, both of which are 2μm thick (i.e., the thickness of a single dielectric layer is 2μm, and a single dielectric layer refers to either the seed layer or the dense layer).

[0092] In seed layer deposition, BaTiO3 powder D 50 (i.e. powder D 50 The thickness of the seed layer is 0.2 μm; the flow rate of the carrier gas (i.e., nitrogen) is 3 L / min; the distance between the nozzle and the alumina ceramic substrate is 10 mm; the scanning speed is 40 mm / s; the overlap rate between scanning channels is 50%; the thickness of the seed layer formed in a single deposition is 0.3 μm, accounting for 15% of the total thickness of the seed layer (i.e., the percentage of the thickness of a single deposition). The last deposition is mainly to make the thickness of the seed layer reach the set thickness.

[0093] In dense layer deposition, BaTiO3 powder D 50 The thickness is 0.4 μm; the carrier gas (nitrogen) flow rate is 4 L / min; the distance between the nozzle and the alumina ceramic substrate is 12 mm; the scanning speed is 25 mm / s; the overlap rate between scanning channels is 60%; the thickness of the dense layer formed in a single deposition accounts for 40% of the total thickness of the dense layer (i.e., the proportion of the thickness of a single deposition). The last deposition is mainly to make the thickness of the dense layer reach the set thickness.

[0094] (3) Formation of self-healing sealing layer: A low-viscosity, penetrating sealing precursor is deposited on the surface of the ceramic dielectric layer using aerosol jet printing (AJP). The AJP operation includes precursor atomization, sheath gas focusing, and nozzle scanning deposition on the substrate, so that the low-viscosity, penetrating sealing precursor preferentially penetrates into pinholes, microcracks, or micropores in the ceramic dielectric layer, and is then cured at low temperature to form a self-healing sealing layer, which together with the ceramic dielectric layer constitutes a composite dielectric layer.

[0095] In this embodiment, a multilayer ceramic capacitor is provided with 40 composite dielectric layers.

[0096] The sealing precursor is a tetraethyl orthosilicate / γ-glycidyl etheroxypropyltrimethoxysilane (TEOS / GPTMS, with a mass ratio of TEOS to GPTMS of 1:1) sol-gel precursor, which transforms into SiO2. x For the sealing insulation phase, x is 2.

[0097] The viscosity of the sealing precursor (i.e., precursor viscosity) was 7 mPa·s. The AJP nozzle orifice diameter was 200 μm, the distance between the nozzle and the ceramic dielectric layer was 3 mm, and the atomizing gas to sheath gas flow ratio was 1:4. Low-temperature curing was performed using ultraviolet light, with a curing temperature of 170℃ and a curing time of 20 min.

[0098] (4) Formation of internal electrode layer: AJP is used to deposit metal electrode patterns on the surface of composite dielectric layer, and the metal electrode patterns are densified to form a conductive and continuous internal electrode layer; field strength homogenization structure is set at the edge of the internal electrode layer. The internal electrode was fabricated using different AJP process parameters than the self-healing sealing layer. The nozzle orifice diameter was 100 μm, the distance between the nozzle and the substrate was 3 mm, and the scanning speed was 50 mm / s. The densification process is a low-temperature heat treatment, with a densification temperature of 180℃ and a treatment time of 20 minutes.

[0099] The internal electrode layer material is Ni; An electric field homogenization structure is incorporated at the edges of the internal electrode layer to reduce local electric field concentration at the edges and minimize the risk of edge breakdown. This electric field homogenization structure involves rounding the electrode edges.

[0100] (5) Stacking repetition: Repeat steps (2) to (4) 40 times to form a 40-layer "composite dielectric layer / electrode layer" alternating stacked structure.

[0101] (6) End electrode formation: End electrodes are formed at both ends of the alternating stacked structure and external electrical connections are completed to obtain the chip multilayer ceramic capacitor in this example.

[0102] The parameters used in the preparation method in this example are shown in Tables 1 and 2 below.

[0103] Example 2-3 The only difference between the preparation method of the chip multilayer ceramic capacitor in Examples 2-3 and Example 1 is that the substrate activation treatment time in step (1) is different. The specific parameters are shown in Table 1 below.

[0104] Examples 4-7 The only difference between the preparation method of the chip multilayer ceramic capacitor in Examples 4-7 and Example 1 is that the thickness of the single dielectric layer in step (2) is different. The specific parameters are shown in Table 1 below.

[0105] Examples 8-11 The difference between the preparation method of the chip multilayer ceramic capacitor in Examples 8-11 and Example 1 is only that: in the seed layer deposition step of step (2), the powder (i.e., barium titanate powder) D 50The specific parameters are different and are shown in Table 2 below.

[0106] Examples 12-15 The only difference between the preparation method of the chip multilayer ceramic capacitor in Examples 12-15 and Example 1 is that the thickness of the seed layer formed in a single step (2) is different from the total thickness of the seed layer. The specific parameters are shown in Table 2 below.

[0107] Examples 16-19 The difference between the preparation method of the chip multilayer ceramic capacitors in Examples 16-19 and Example 1 is only that: in the dense layer deposition step of step (2), the powder (i.e., barium titanate powder) D 50 The specific parameters are different and are shown in Table 2 below.

[0108] Examples 20-23 The only difference between the preparation method of the chip multilayer ceramic capacitor in Examples 20-23 and Example 1 is that the percentage of the thickness of the dense layer formed in a single step to the total thickness of the dense layer is different in the dense layer deposition step (2). The specific parameters are shown in Table 2 below.

[0109] Examples 24-27 The only difference between the preparation method of the chip multilayer ceramic capacitor in Examples 24-27 and Example 1 is that the viscosity of the precursor is different in the self-healing layer formation step (3), and the specific parameters are shown in Table 1 below.

[0110] Examples 28-31 The only difference between the preparation method of the chip multilayer ceramic capacitor in Examples 28-31 and Example 1 is that the low-temperature curing temperature is different in the self-healing layer formation step (3). The specific parameters are shown in Table 1 below.

[0111] Examples 32-35 The only difference between the preparation method of the chip multilayer ceramic capacitor in Examples 32-35 and Example 1 is that the low-temperature curing time is different in the self-healing layer formation step (3). The specific parameters are shown in Table 1 below.

[0112] Examples 36-39 The only difference between the preparation method of the chip multilayer ceramic capacitor in Examples 36-39 and Example 1 is that the densification treatment temperature is different in the internal electrode layer formation step (4). The specific parameters are shown in Table 1 below.

[0113] Examples 40-43 The only difference between the preparation method of the chip multilayer ceramic capacitor in Examples 40-43 and Example 1 is that the densification treatment time is different in the internal electrode layer formation step (4). The specific parameters are shown in Table 1 below.

[0114] Examples 44-45 The only difference between the preparation method of the chip multilayer ceramic capacitor in Examples 44-45 and Example 1 is that the substrate activation treatment time in step (1) is different. The specific parameters are shown in Table 1 below.

[0115] Examples 46-47 The only difference between the preparation method of the chip multilayer ceramic capacitor in Examples 46-47 and Example 1 is that the thickness of the single dielectric layer in step (2) is different. The specific parameters are shown in Table 1 below.

[0116] Example 48 The difference between the preparation method of the chip multilayer ceramic capacitor in this example and that in Example 1 is only that: in the seed layer deposition step of step (2), the powder (i.e., barium titanate powder) D 50 The specific parameters are different and are shown in Table 2 below.

[0117] Examples 49-50 The difference between the preparation method of the chip multilayer ceramic capacitor in Examples 49-50 and Example 1 is that the thickness of the seed layer formed in a single step and the thickness of the dense layer formed in a single step are different in the seed layer and dense layer deposition steps, respectively. The specific parameters are shown in Table 2 below.

[0118] Example 51 The only difference between the fabrication method of the chip multilayer ceramic capacitor in this example and that in Example 1 is that in the dense layer deposition step of step (2), the powder (i.e., barium titanate powder) D 50 The specific parameters are different and are shown in Table 2 below.

[0119] Examples 52-53 The only difference between the preparation method of the chip multilayer ceramic capacitor in Examples 52-53 and Example 1 is that the viscosity of the precursor is different in the self-healing layer formation step (3), and the specific parameters are shown in Table 1 below.

[0120] Examples 54-55 The only difference between the preparation method of the chip multilayer ceramic capacitor in Examples 54-55 and Example 1 is that the low-temperature curing temperature is different in the self-healing layer formation step (3). The specific parameters are shown in Table 1 below.

[0121] Examples 56-57 The only difference between the preparation method of the chip multilayer ceramic capacitor in Examples 56-57 and Example 1 is that the low-temperature curing time is different in the self-healing layer formation step (3). The specific parameters are shown in Table 1 below.

[0122] Examples 58-59 The only difference between the preparation method of the chip multilayer ceramic capacitor in Examples 58-59 and Example 1 is that the densification treatment temperature is different in the internal electrode layer formation step (4), and the specific parameters are shown in Table 1 below.

[0123] Examples 60-61 The only difference between the preparation method of the chip multilayer ceramic capacitor in Examples 60-61 and Example 1 is that the densification treatment time is different in the internal electrode layer formation step (4). The specific parameters are shown in Table 1 below.

[0124] Comparative Example 1 This example provides a method for fabricating a chip-type multilayer ceramic capacitor. The dielectric layer is fabricated using a traditional tape casting process, and the internal electrodes are fabricated using a printed internal electrode method. The specific steps are as follows: The barium titanate ceramic slurry is evenly coated onto a moving PET carrier film through the pouring port of the casting machine. Drying and curing: After the carrier film coated with slurry is dried at 60-90℃, it forms a ceramic green film sheet with a certain degree of flexibility.

[0125] Nickel conductive paste is precisely printed onto the designated positions on the film using a screen printing plate, and then dried at 60°C to obtain a dielectric layer with the internal electrode printed on it. The layers are stacked to form a 40-layer alternating "dielectric layer / electrode layer" stacked structure; Debinding and sintering yield a laminated body. End electrode formation: End electrodes are formed at both ends of the laminate and external electrical connections are completed to obtain the chip multilayer ceramic capacitor in this example.

[0126] Comparative Example 2 The only difference between the preparation method of the chip multilayer ceramic capacitor in this example and that in Example 1 is that step (3) is not included in this example, while the remaining steps and parameters are the same as in Example 1.

[0127] Comparative Example 3 The only difference between the preparation method of the chip multilayer ceramic capacitor in this example and that in Example 1 is that step (2) in this example uses the traditional casting method to prepare a single dielectric layer, while the other steps and parameters are the same as in Example 1. The specific casting process is as follows: barium titanate ceramic slurry is uniformly coated onto a moving PET carrier film through the pouring port of the casting machine; drying and curing: the carrier film coated with slurry is dried at 60-90℃ to form a ceramic green film with a certain degree of flexibility.

[0128] Comparative Example 4 The only difference between the preparation method of the chip multilayer ceramic capacitor in this example and that in Example 1 is that step (4) in this example is prepared on the dielectric layer by the traditional printing method, and the remaining steps and parameters are the same as in Example 1.

[0129] Table 1. Partial preparation parameters

[0130] In Table 1, a substrate activation time of "0" indicates that no activation treatment was performed.

[0131] Table 2. Some preparation parameters

[0132] Performance testing: The following properties of the capacitors prepared in Examples 1-61 and Comparative Examples 1-4 were tested respectively, and the specific test methods are as follows: (a) Dielectric layer thickness and thickness uniformity: Used to evaluate the improvement of thin dielectric thickness control by two-stage AD / ADM deposition. The dielectric layer thickness corresponding to the examples or comparative examples was measured.

[0133] Test method: The cross-section of the film strip was prepared by a cross-section polisher (CP) and then placed on conductive adhesive. At least three cross-sectional images were taken using FE-SEM. The average film thickness was obtained from at least 100 locations in each image to determine the final dielectric layer thickness and thickness uniformity.

[0134] Superior product standards: Intralayer thickness variation coefficient CVt≤10% (standard deviation of thickness at different locations in the same layer divided by average thickness, then multiplied by 100%), interlayer thickness deviation≤15% (percentage deviation of average thickness of each layer compared to the overall average thickness). (b) Surface roughness of composite medium layer: used to evaluate the seed layer and the leveling effect of sealing.

[0135] Test method: The prepared film strip is placed on the stage, and the surface roughness of the film strip is analyzed by white light interferometer, and a 3D morphology image of the film strip surface is obtained. The surface roughness of the film strip is obtained by measuring different positions of 30 film strips and taking the average value.

[0136] Optimal product standard: Surface roughness of the dielectric layer Ra≤0.20μm; (c) Pinhole / microcrack / micropore defect density: used to evaluate the sealing effect of the self-healing sealing layer on defect channels.

[0137] Test method: Place the film strip sample on the stage and count the number of pinholes / microcracks / micropores using a metallographic microscope. Measure the number of more than 30 film strips of the same area and take the average value to obtain the pinhole / microcrack / micropore defect density.

[0138] Optimal product standard: Visible defect density per unit area ≤ 0.1 defects / m² 2 ; (d) Leakage current density: used to evaluate the insulation performance and defect sealing effect of the composite dielectric layer.

[0139] Test method: Taking the 0603X5R226M100A capacitor as an example, a source meter is used to apply voltage to the sample's rated operating voltage for 60 seconds, and the steady-state leakage current or insulation resistance data is read. When reading the insulation resistance data, it is converted into leakage current according to the corresponding voltage conditions, and then the leakage current density is calculated in combination with the effective area of ​​the internal electrodes. It is preferable to select 200 finished samples for testing and take the average value.

[0140] Preferred product standard: Steady-state leakage current density ≤ 1×10 -7 A / cm 2 .

[0141] (e) Breakdown field strength and breakdown dispersion: used to evaluate the overall effect of dielectric layer defect control and field strength homogenization structure.

[0142] Test method: Taking the 0603X5R226M100A model capacitor as an example, the average BDV of 200 finished products was measured using a high voltage source meter, and the average breakdown field strength was obtained by dividing it by the thickness of a single dielectric layer.

[0143] First, measure the breakdown field strength of 200 finished products and calculate the average value. Then, calculate the dispersion of these data relative to the average value, which is the standard deviation. Finally, use "standard deviation ÷ average value × 100%" to obtain the coefficient of variation of the breakdown field strength. The smaller this value, the more stable and consistent the samples are.

[0144] Superior product standard: Average breakdown field strength E bd ≥150 V / μm; breakdown field strength coefficient of variation ≤15%.

[0145] The performance data obtained using the above testing method are shown in Table 3 below: Table 3 Performance Test Results

[0146] As shown in Table 3, compared with Comparative Examples 1-4, the capacitors prepared by the methods in Examples 1-61 have higher average breakdown field strength. Compared with Examples 44-61, Examples 1-43 have better overall performance, specifically: intralayer thickness variation coefficient CVt ≤ 10%, interlayer thickness deviation ≤ 15%, Ra ≤ 0.20 μm, and visible defect density per unit area ≤ 0.1 defects / m². 2 Steady-state leakage current density ≤ 1×10 -7 A / cm 2 Average breakdown field strength E bd ≥150 V / μm; breakdown field strength variation coefficient ≤15%, which can meet the requirements of high-performance capacitors.

[0147] The embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention. Furthermore, the embodiments of the present invention and the features thereof can be combined with each other unless otherwise specified.

Claims

1. A multilayer ceramic chip capacitor, comprising a laminate and end electrodes disposed at both ends of the laminate, characterized in that: The laminate includes a composite dielectric layer and an inner electrode stacked together; the composite dielectric layer includes a ceramic dielectric layer and a self-healing sealing layer disposed on the ceramic dielectric layer; The self-healing sealing layer contains an insulating phase; the insulating phase includes SiO₂. x TiO x ZrO x AlO y At least one of SiO, SiOC, and SiCN, wherein SiO x TiO x ZrO x Each x in AlO is independently 0 < x ≤ 2; y In this case, y is 0 < y ≤ 1.

5.

2. The multilayer ceramic chip capacitor according to claim 1, characterized in that: The raw materials for preparing the pore-sealing self-healing layer include a pore-sealing precursor; the pore-sealing precursor includes at least one of a sol-gel inorganic precursor, a pre-ceramic polymer precursor, and an inorganic-organic hybrid precursor. And / or, the edge of the inner electrode is provided with a field strength homogenization structure; the field strength homogenization structure includes at least one of electrode edge rounding, electrode edge thinning region, and electrode edge retreat region.

3. The method for preparing the multilayer ceramic chip capacitor according to any one of claims 1-2, characterized in that: Includes the following steps: S1: A seed layer and a dense layer are sequentially deposited on the activated substrate using an aerosol deposition method to obtain a ceramic dielectric layer; S2: The sealing precursor is sprayed onto the ceramic dielectric layer using an aerosol jet printing method. After curing, a self-healing sealing layer is obtained. S3: Metal is deposited on the self-healing sealing layer using aerosol jet printing, followed by densification treatment to obtain the inner electrode; S4: Repeat steps S1-S3, repeating ≥2 times, to obtain a stacked body; S5: Prepare terminal electrodes on the laminate to obtain the chip multilayer ceramic capacitor.

4. The method for preparing a multilayer ceramic chip capacitor according to claim 3, characterized in that: The activated substrate is obtained by activating the substrate using at least one of UV-ozone, oxygen plasma, argon plasma and chemical activation, with an activation time of 0.1s-25min.

5. The method for preparing a multilayer ceramic chip capacitor according to claim 3, characterized in that: The thicknesses of the dense layer and the seed layer are 0.2-7 μm, respectively.

6. The method for preparing a multilayer ceramic chip capacitor according to claim 3, characterized in that: The seed layer has at least one of the following parameters during preparation: (a1) D of raw material powder 50 It is 0.05-1 μm; (a2) The carrier gas flow rate is 0.3-8 L / min; (a3) The distance between the nozzle and the substrate is 1-15 mm; (a4) The scanning speed is 1-110 mm / s; (a5) The overlap rate between scan tracks is 30%-70%; (a6) The thickness of the seed layer formed in a single run is 0.05-0.50 μm; (a7) The thickness of a single seed layer is 2-35% of the total thickness of the seed layer.

7. The method for preparing a multilayer ceramic chip capacitor according to claim 3, characterized in that: The dense layer has at least one of the following parameters during its preparation: (b1) Raw material powder D 50 Its range is 0.10-3.0 μm; (b2) The carrier gas flow rate is 1-12 L / min; (b3) The distance between the nozzle and the substrate is 1-20 mm; (b4) The scanning speed is 0.3-85 mm / s; (b5) The overlap rate between scan tracks is 40%-80%; (b6) The thickness of the dense layer formed in a single step accounts for 20%-80% of the total thickness of the dense layer.

8. The method for preparing a multilayer ceramic chip capacitor according to claim 3, characterized in that: The self-healing sealing layer has at least one of the following parameters during its preparation: (c1) The viscosity of the sealing precursor is 0.5-22 mPa·s; (c2) The nozzle orifice diameter is 80-300 μm; (c3) The distance between the nozzle and the substrate is 1-5 mm; (c4) The flow rate ratio of atomizing gas to sheath gas is 1:(1-6); (c5) The curing is performed by at least one of ultraviolet curing, photon pulse curing, heat treatment or annealing; (c6) The curing temperature is 60-270℃; (c7) The curing time is 0.5-70 min.

9. The method for preparing a multilayer ceramic chip capacitor according to claim 3, characterized in that: The internal electrode has at least one of the following parameters during its fabrication: (d1) Nozzle orifice diameter is 30-150μm; (d2) The distance between the nozzle and the substrate is 1-5 mm; (d3) Scanning speed is 5-100 mm / s; (d4) The densification process is carried out by at least one of the following methods: heat treatment, photon pulse sintering, or laser local densification; (d5) The densification treatment temperature is 60-320℃; (d6) The densification process takes 0.5-65 min.

10. An electronic device, characterized in that: Including the chip multilayer ceramic capacitor as described in any one of claims 1-2.

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