Wafer carrier apparatus and ion implantation method

Abstract

The application provides a wafer carrying device and an ion implantation method. An ion beam protection layer is arranged on the surface of a support structure which can be located on the propagation path of the ion beam, and a large-angle ion implantation is performed by forming an included angle between the ion beam and the normal line of the wafer surface greater than 45° and less than 90°. On the one hand, the support structure can be protected by the ion beam protection layer, the possibility of secondary electrons generated by the direct bombardment of the ion beam on the support structure is reduced, and a structural basis for the large-angle ion implantation is provided. On the other hand, the implantation depth of the ion beam along the thickness direction of the wafer can be reduced without excessively reducing the energy of the ion beam, so that the requirements of the shallow layer ion implantation, the transmission efficiency and the beam intensity of the ion beam are considered, the ion implantation time is shortened, the ion implantation efficiency is improved, and the mass production applicability of the shallow layer ion implantation process is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a wafer carrier device and an ion implantation method. Background Technology

[0002] In semiconductor manufacturing processes, ion implantation (IMP) is commonly used to form doped regions in wafers. As the feature size of semiconductor devices continues to shrink, the requirements for ion implantation depth are becoming increasingly stringent, leading to the widespread application of shallow ion implantation in advanced processes. For example... Figure 1 As shown, existing ion implantation methods typically employ vertical implantation or small-angle tilt implantation, with the implantation angle for small-angle tilt implantation usually being less than 45°. Existing ion implantation processes typically reduce implantation depth by lowering the ion beam energy. However, during low-energy implantation, the ion beam is prone to divergence and transmission loss after deceleration, resulting in a reduced ion beam current reaching the wafer. This leads to prolonged implantation time, reduced production efficiency, and difficulty in meeting mass production requirements. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a wafer carrier device and an ion implantation method to solve the problem that it is difficult to balance the implantation depth and ion beam transmission efficiency in shallow ion implantation in the prior art.

[0004] To achieve the above and other related objectives, the present invention provides a wafer carrier device, the wafer carrier device comprising:

[0005] A tray has a bottom surface and a support surface that are arranged opposite to each other, the support surface being used to support a wafer to be implanted with ions;

[0006] A support structure includes an enclosure and a support; wherein the enclosure includes a bottom section, a side section, and an inner extension section; the bottom section is located below the bottom surface of the tray; the support section is disposed between the bottom surface of the tray and the bottom section, and the support section is used to support the tray; the side section extends from the bottom section toward the wafer and surrounds the side of the tray; the inner extension section extends from the side section toward the center of the tray, and at least a portion of the inner extension section is located below the wafer; and

[0007] An ion beam protection layer covers at least the surface of the support structure located along the ion beam propagation path during ion implantation.

[0008] Optionally, the material of the support structure includes metal, and the material of the ion beam shielding layer includes graphite.

[0009] Optionally, the ion beam protection layer covers all exposed surfaces of the support structure.

[0010] Optionally, there is a gap between the inner extension and the wafer.

[0011] The present invention also provides an ion implantation method, the ion implantation method comprising:

[0012] S1, providing a wafer to be ion implanted and a wafer carrier device as described in any of the above, and placing the wafer on a tray of the wafer carrier device; wherein, a photoresist layer is formed on the surface of the wafer away from the wafer carrier device;

[0013] S2, using the photoresist layer as a mask, ion implantation is performed on the surface of the wafer away from the wafer carrier, wherein the ion beam implanted has an angle α with the normal of the wafer surface, and 45° < α < 90°.

[0014] Optionally, the included angle α is not less than 60°.

[0015] Optionally, the ion beam accelerating voltage of the ion implantation is greater than 3kV.

[0016] Optionally, the method further includes the step of determining the parameters of the photoresist layer, wherein the photoresist layer is obtained by correcting the preset photoresist layer boundary position, and a preset implantation region is formed when a preset ion implantation perpendicular to the wafer surface is performed using the preset photoresist layer as a mask, and a target implantation region with the same position and width as the preset implantation region is formed when the ion implantation is performed using the photoresist layer as a mask and the included angle α is used.

[0017] The steps for determining the parameters of the photoresist layer include:

[0018] Determine the height t of the preset photoresist layer, the included angle α, and the ion implantation depth H;

[0019] Based on the height t of the preset photoresist layer and the included angle α, the first width L1 of the blocking injection region is determined;

[0020] Based on the included angle α and the ion implantation depth H, the second width L2 of the implantation region is determined;

[0021] Based on the first width L1 and the second width L2, the target position of the photoresist layer on the surface of the wafer away from the wafer carrier is determined.

[0022] Furthermore,

[0023] The method for determining the first width L1 of the blocking injection region based on the height t of the preset photoresist layer and the included angle α includes: calculating the product of the tangent of the included angle α and the height t, and determining the product of the tangent of the included angle α and the height t as the first width L1;

[0024] The method for determining the second width L2 of the over-implanted region based on the included angle α and the ion implantation depth H includes: calculating the product of the tangent of the included angle α and the depth H, and determining the product of the tangent of the included angle α and the depth H as the second width L2.

[0025] Further, taking the direction of the surface of the wafer away from the wafer carrier as the X-axis and the direction perpendicular to the wafer surface as the Y-axis, the preset photoresist layer has preset first coordinates (X1, 0) and preset second coordinates (X1+L0, 0) in the horizontal direction; the method for determining the target position of the photoresist layer on the surface of the wafer away from the wafer carrier based on the first width L1 and the second width L2 includes:

[0026] The first target coordinate of the photoresist layer in the horizontal direction is determined to be (X1-L2, 0);

[0027] The second target coordinate of the photoresist layer in the horizontal direction is determined as (X1+L0-L1, 0).

[0028] As described above, the wafer carrier device and ion implantation method of the present invention have the following beneficial effects:

[0029] The wafer carrier device of the present invention provides a protective portion including a bottom section, a side section, and an inner extension section, with at least a portion of the inner extension section located below the wafer. Simultaneously, an ion beam protection layer is provided on the surface of the support structure located along the ion beam propagation path during ion implantation. This protects the support structure from potential ion beam bombardment during large-angle ion implantation, reducing the likelihood of direct ion beam impact on the support structure. Furthermore, when the support structure is made of metal and the ion beam protection layer is made of graphite, it reduces secondary electrons generated by direct ion beam impact on the metal material, providing a structural basis for large-angle ion implantation.

[0030] The ion implantation method of the present invention reduces the projection depth of the ion beam in the wafer normal direction by making the angle between the ion beam and the wafer surface normal greater than 45° and less than 90°, and performing ion implantation in a large-angle tilting manner. This allows for the achievement of a shallower normal implantation depth while maintaining high ion beam energy, reducing beam divergence and transmission loss caused by lower ion beam energy. This method is beneficial for balancing the implantation depth and ion beam transmission efficiency in shallow ion implantation, thereby improving the production efficiency of the ion implantation process.

[0031] Furthermore, by determining the first width of the blocking implantation region and the second width of the over-implantation region based on the height, included angle α, and ion implantation depth of the preset photoresist layer, and correcting the position of the preset photoresist layer accordingly, the lateral obstruction and lateral offset caused by large-angle ion implantation can be compensated. This ensures that the target implantation region formed when performing large-angle ion implantation using the corrected photoresist layer has the same position and width as the preset implantation region formed when performing vertical ion implantation using the preset photoresist layer, thereby improving the positional accuracy of the implantation region under large-angle ion implantation conditions. Attached Figure Description

[0032] Figure 1 The diagram shows a schematic of ion implantation methods in the prior art.

[0033] Figure 2 The diagram shown is a schematic representation of the structure of a wafer carrier device according to an embodiment of the present invention.

[0034] Figure 3 The diagram shown is a flowchart of an ion implantation method according to an embodiment of the present invention.

[0035] Figure 4 The diagram shows the implantation depth of large-angle ion implantation in one embodiment of the present invention.

[0036] Figure 5 The diagram shown is a schematic representation of the principle for determining the first and second widths of the photoresist layer in one embodiment of the present invention.

[0037] Figure 6 This is a schematic diagram illustrating the principle of determining the target position of the photoresist layer in one embodiment of the present invention.

[0038] Component labeling: 1 Wafer, 20 Tray, 21 Support structure, 22 Support section, 23 Enclosure section, 231 Bottom section, 232 Side section, 233 Inner extension section, 3 Preset photoresist layer, 4 Photoresist layer, 5 Ion beam protection layer. Detailed Implementation

[0039] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] Please see Figures 1 to 6It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the actual number, shape, and size of components in implementation. In actual implementation, the type, quantity, and proportion of each component can be arbitrarily changed, and the component layout may also be more complex. At the same time, the directional terms such as "upper," "lower," "inner," "outer," "bottom," "side," and "horizontal" used in this specification are only for the convenience of describing the relative positional relationship between the structures in conjunction with the accompanying drawings and are not intended to limit the scope of the present invention. When the mounting posture of the wafer carrier device changes, the relative relationships represented by each directional term can be changed accordingly.

[0041] As described in the background section, during ion implantation, a photoresist layer is typically used to block areas that do not require ion implantation, allowing the ion beam to enter the wafer region not blocked by the photoresist layer. Figure 1 As shown, existing implantation methods typically employ vertical implantation or small-angle tilt implantation. Solid arrows indicate ion beams perpendicular to the wafer surface, while dashed arrows indicate ion beams with a small angle relative to the wafer surface normal. The angle for small-angle tilt implantation is typically less than 45°. For processes requiring shallow implantation depths, existing methods usually further reduce the final implantation energy of the ion beam. Lower ion beam energy reduces ion velocity, leading to significant beam current losses during shaping, deceleration, and transport. Simultaneously, the decelerated ions of the same charge repel each other, causing the ion beam to diverge and further reducing transport efficiency. Therefore, while lower energy is beneficial for forming shallower implantation regions, it also tends to reduce the ion beam current reaching the wafer and prolong implantation time, impacting production efficiency.

[0042] Based on this, such as Figure 2 As shown, this embodiment provides a wafer carrier device, which includes:

[0043] The tray 20 has a bottom surface and a support surface that are arranged opposite to each other, the support surface being used to support the wafer 1 to be ion implanted;

[0044] The support structure 21 includes an enclosure 23 and a support 22; wherein the enclosure 23 includes a bottom section 231, a side section 232, and an inner extension 233, the bottom section 231 is located below the bottom surface of the tray 20, the support 22 is disposed between the bottom surface of the tray 20 and the bottom section 231, the support 22 is used to support the tray 20, the side section 232 extends from the bottom section 231 toward the wafer 1 and surrounds the side of the tray 20, the inner extension 233 extends from the side section 232 toward the center of the tray 20, and at least a portion of the inner extension 233 is located below the wafer 1; and

[0045] The ion beam protection layer 5 covers at least the surface of the support structure 21 located in the ion beam propagation path during ion implantation.

[0046] The wafer carrier device of this embodiment provides a protective section with a bottom section, a side section, and an inner extension section below and on the outer periphery of the tray. An ion beam protection layer is provided on the surface of the support structure located on the ion beam propagation path during ion implantation. This ion beam protection layer can protect the support structure, thereby preventing the ion beam from directly bombarding the support structure. In particular, it can reduce the possibility of secondary electrons generated by the ion beam hitting the metal support structure during large-angle ion implantation. At the same time, it protects the tray and its surrounding structure, providing a corresponding structural basis for large-angle ion implantation of the wafer.

[0047] Specifically, the tray 20 can be a disk-shaped, plate-shaped, or frame-shaped support component for positioning and supporting the wafer 1. The support surface of the tray 20 faces the incident space of the ion beam, and the bottom surface of the tray 20 faces away from the support surface. The wafer 1 can be directly disposed on the support surface, or it can be disposed on the support surface through positioning members, support members, or clamping members, as long as the position of the wafer 1 can be kept stable during ion implantation. Figure 2 In the embodiment shown, the entire tray 20 is located within the space enclosed by the enclosure 23 and maintains a certain radial distance from the side enclosure 232.

[0048] The support portion 22 is disposed below the tray 20 and is used to support the tray 20 above the bottom section 231. There can be one or more support portions 22; when multiple support portions 22 are provided, they can be arranged at intervals along the circumference or radial direction of the tray 20 to ensure uniform force distribution on the tray 20. The support portion 22 can be fixedly connected to the tray 20 or form a detachable connection to facilitate replacement of the tray 20 for different sizes of wafers 1. Similarly, the support portion 22 and the bottom section 231 can also be fixedly or detachably connected. This embodiment does not limit the specific connection method, as long as it can provide stable support to the tray 20 during ion implantation.

[0049] The enclosure 23 forms a supporting and protective framework around the wafer carrier. Specifically, the bottom section 231 is located below the bottom surface of the tray 20 and extends along the outer periphery of the tray 20; the side section 232 extends from the bottom section 231 toward the side where the wafer 1 is located, thus surrounding the outer periphery of the tray 20; the inner extension section 233 connects to the upper part of the side section 232 and extends toward the center of the tray 20. Thus, in a cross-section through the central axis of the tray 20, the bottom section 231, the side section 232, and the inner extension section 233 can form an enclosure extending from below the tray 20 to the outside of the tray 20 and further bending inward. The enclosure 23 can be continuously arranged along the entire circumference of the tray 20, or it can be arranged in a partial circumferential area according to the actual incident direction of the ion beam, as long as it can cover the corresponding area that the large-angle ion beam may pass through.

[0050] The inner extension 233 extends towards the center of the tray 20, such that at least a portion of the inner extension 233 is located below the wafer 1. Since the large-angle ion beam has a large angle relative to the surface normal of the wafer 1, some ion beams that do not act on the wafer 1 may continue to propagate along the inclined direction to below the edge of the wafer 1 and the periphery of the tray 20. Therefore, by extending the inner extension 233 below the wafer 1, the enclosure 23 can form a structural cover over the ion beam propagation area at the corresponding position. The extension length of the inner extension 233 can be set according to the size of the wafer 1, the range of the angle α, and the range of the ion beam spot; this embodiment does not specifically limit this.

[0051] In this embodiment, a gap is preferably provided between the inner extension section 233 and the wafer 1. This gap prevents the inner extension section 233 from directly contacting the wafer 1, thus providing space for the support and handling of the wafer 1, and also allowing the inner extension section 233 to be positioned below the wafer 1, providing corresponding protection against the obliquely propagating ion beam. The size of the gap can be determined by considering the height of the tray 20, the mounting position of the wafer 1, and the included angle α, and can be selected while meeting the requirements for stable support of the wafer 1 and protection of the inner extension section 233.

[0052] The ion beam shielding layer 5 at least covers the surface of the support structure 21 located along the ion beam propagation path during ion implantation. Figure 2 During high-angle ion implantation, the ion beam may propagate obliquely from above the wafer 1 to the corresponding surfaces of the inner extension 233, the side section 232, or the bottom section 231. Therefore, the ion beam protection layer 5 can at least cover the areas that may be directly bombarded by the ion beam, so that the ion beam preferentially acts on the ion beam protection layer 5 rather than directly on the main material of the support structure 21. The ion beam protection layer 5 can be continuous or partitioned for different ion beam incident directions; its coverage area can be determined according to the ion beam propagation path.

[0053] As an example, the support structure 21 is made of metal, and the ion beam shielding layer 5 is made of graphite. Specifically, the use of a metal material in the support structure 21 provides the mechanical strength required for load-bearing, while the use of graphite in the ion beam shielding layer 5 forms a protective interface between the support structure 21 and the ion beam. During large-angle ion implantation, the ion beam shielding layer 5 isolates or blocks the ion beam that may be directed at the metal region, thereby reducing the possibility of the ion beam directly bombarding the metal surface and reducing secondary electrons generated by the direct impact of the ion beam on the metal material. Through the above material combination, both the support strength of the wafer carrier device and the ion beam protection requirements under large-angle ion implantation conditions can be met.

[0054] In one optional embodiment, to further expand the protection range, the ion beam protection layer 5 can cover all exposed surfaces of the support structure 21, including the surfaces of the support portion 22 and the enclosure portion 23. Thus, even if the ion beam propagation direction, beam spot range, or internal reflection and scattering conditions change, the ion beam protection layer 5 can still provide a large area of ​​protection for the support structure 21. In other optional embodiments, the ion beam protection layer 5 can be applied only to areas actually located along the possible propagation path of the ion beam, thereby reducing material usage while meeting protection requirements.

[0055] This embodiment also provides an ion implantation method, such as Figure 3 As shown, the ion implantation method includes:

[0056] S1, a wafer to be ion implanted and a wafer carrier device as described above are provided, and the wafer is placed on a tray of the wafer carrier device; wherein a photoresist layer is formed on the surface of the wafer away from the wafer carrier device;

[0057] S2, using the photoresist layer as a mask, ion implantation is performed on the surface of the wafer away from the wafer carrier, wherein the ion beam implanted has an angle α with the normal of the wafer surface, and 45° < α < 90°.

[0058] The ion implantation method of this embodiment achieves ion implantation into the wafer at a large angle by having an angle greater than 45° and less than 90° between the ion beam and the normal to the wafer surface. This reduces the component of the implantation energy in the wafer thickness direction, thereby reducing the longitudinal implantation depth of ions in the wafer while maintaining high ion beam energy. This solves the problems of reduced ion beam transmission efficiency, reduced beam current, and reduced implantation efficiency caused by the need to reduce ion beam energy in existing shallow ion implantation processes. It is beneficial to balance shallow ion implantation depth with high ion beam transmission efficiency, thereby improving the production efficiency and mass production applicability of shallow ion implantation.

[0059] refer to Figure 4 In step S1, the wafer 1 can be a semiconductor wafer that needs to form doped regions through ion implantation. The photoresist layer 4 is formed on the surface of the wafer 1 away from the wafer carrier. The photoresist layer 4 is used to shield areas that do not require ion implantation, while the areas not shielded by the photoresist layer 4 are used to receive the ion beam. The photoresist layer 4 can be patterned according to the designed position of the target doped region, and its position and width can be further determined by combining the lateral offset generated by large-angle ion implantation as described later.

[0060] In step S2, the included angle α is defined as the angle between the propagation direction of the ion beam and the normal to the surface of wafer 1. As the included angle α increases, the tilt of the ion beam relative to the surface of wafer 1 increases. In this embodiment, the included angle α is set to be greater than 45° and less than 90°, thereby distinguishing it from... Figure 1 The diagram shows vertical injection and small-angle injection, and utilizes large-angle incident light to reduce the energy component of the ion beam in the normal direction of wafer 1 and the corresponding geometric projection depth.

[0061] refer to Figure 4To illustrate the effect of large-angle implantation on the implantation depth in the normal direction, under the same ion beam energy, the reference implantation depth corresponding to perpendicular incidence is denoted as H0, and the projected depth in the normal direction of wafer 1 under large-angle incidence is denoted as H. According to the geometric relationship between the ion incident direction and the normal direction, it can be expressed as H = sin(90° - α) × H0, i.e., H = cosα × H0. When the included angle α is 60°, H is approximately half of H0; when the included angle α is approximately 84.3°, H is approximately 10% of H0. Under ideal geometric projection relationships, as the included angle α further approaches 90°, the projected depth in the normal direction can be further reduced, theoretically potentially less than 1% of the reference implantation depth. Therefore, while maintaining a relatively high ion beam energy, a shallower normal implantation effect can be obtained by changing the included angle α.

[0062] In a preferred embodiment, the included angle α is set to be no less than 60° to further reduce the projection depth of the ion beam in the normal direction of the wafer 1. The included angle α can be selected based on the target implantation depth, the surface structure of the wafer 1, the height of the photoresist layer 4, and the ion beam propagation space provided by the wafer carrier. For example, angles greater than 60°, close to 84.3°, or other angles that meet process requirements can be selected. It should be noted that the included angle α should be less than 90° so that the ion beam can enter the wafer 1 from the side of the wafer 1 away from the wafer carrier.

[0063] In one optional embodiment, the ion beam accelerating voltage is set to greater than 3kV. Compared to achieving ultra-shallow implantation by continuously reducing the ion beam energy, using a higher ion beam accelerating voltage helps maintain the beam current intensity and transmission efficiency during extraction, shaping, and transmission, and can reduce beam divergence and losses caused by excessive deceleration. Subsequently, the projection of the ion beam onto the normal direction of wafer 1 is adjusted by the included angle α, so that the high-energy ion beam can still achieve a shallow normal implantation depth. Thus, the requirements for shallow implantation and ion beam transmission efficiency can be balanced, providing conditions for improving the production efficiency of the ion implantation process.

[0064] Because the ion beam is incident at a large angle, it has a component not only in the normal direction of wafer 1 but also in a direction parallel to the surface of wafer 1. Therefore, compared to vertical implantation, the area that the ion beam can actually reach on the surface of wafer 1 after passing through the edge of the photoresist layer with a certain height will change laterally; at the same time, the ion beam will also undergo lateral displacement with the implantation depth after entering the interior of wafer 1. The preset photoresist layer 3 is used to characterize the reference photoresist position before correction under vertical implantation conditions. When the preset ion implantation perpendicular to the surface of wafer 1 is performed using the preset photoresist layer 3 as a mask, a preset implantation area is formed. If the position of the preset photoresist layer 3 is still used during large-angle ion implantation, the target area may be blocked by the photoresist and cannot be implanted, and areas that do not need to be implanted may be implanted. Therefore, it is necessary to correct the position of the preset photoresist layer 3 based on the lateral influence generated by large-angle ion implantation to form the photoresist layer 4 for step S2, so that the target implantation area formed when ion implantation is performed using the photoresist layer 4 as a mask at the included angle α has the same position and width as the preset implantation area.

[0065] Therefore, further, such as Figure 5 and Figure 6 As shown, the ion implantation method further includes a step of determining the parameters of the photoresist layer 4, which includes:

[0066] Determine the height t of the preset photoresist layer 3, the included angle α, and the ion implantation depth H;

[0067] Based on the height t of the preset photoresist layer 3 and the included angle α, the first width L1 of the blocking injection region A1 is determined;

[0068] Based on the included angle α and the ion implantation depth H, the second width L2 of the implantation region A2 is determined;

[0069] Based on the first width L1 and the second width L2, the target position of the photoresist layer 4 on the surface of the wafer 1 away from the wafer carrier is determined. Specifically, the photoresist layer 4 is obtained by correcting the boundary position of the preset photoresist layer 3. When the preset ion implantation is performed perpendicular to the surface of the wafer 1 using the preset photoresist layer 3 as a mask, the preset implantation region is formed. When the ion implantation is performed using the photoresist layer 4 as a mask at the included angle α, the target implantation region with the same position and width as the preset implantation region is formed.

[0070] Specifically, with Figure 5Taking the coordinate system shown as an example, the direction of the surface of wafer 1 away from the wafer carrier can be defined as the X-axis direction, and the direction perpendicular to the surface of wafer 1 can be defined as the Y-axis direction. The height t represents the dimension of the preset photoresist layer 3 along the Y-axis direction, the included angle α represents the angle between the ion beam propagation direction and the normal to the surface of wafer 1 corresponding to the positive Y-axis direction, and the depth H represents the ion implantation depth. In one specific embodiment, the photoresist layer 4 is modified based on the horizontal position of the preset photoresist layer 3, and the height of the photoresist layer 4 is the same as the height of the preset photoresist layer 3, both being t.

[0071] For a specific example, see Figure 5 The method for determining the first width L1 of the blocking injection region A1 based on the height t of the preset photoresist layer 3 and the included angle α includes: calculating the product of the tangent of the included angle α and the height t, and determining the product of the tangent of the included angle α and the height t as the first width L1;

[0072] The method for determining the second width L2 of the over-implanted region A2 based on the included angle α and the ion implantation depth H includes: calculating the product of the tangent of the included angle α and the depth H, and determining the product of the tangent of the included angle α and the depth H as the second width L2.

[0073] Therefore, the first width L1 can be expressed as L1 = t × tanα, and the second width L2 can be expressed as L2 = H × tanα. Here, the first width L1 reflects the lateral obstruction effect caused by the photoresist height, and the second width L2 reflects the lateral offset effect caused by the depth H after the ion beam enters the wafer 1. By simultaneously considering the first width L1 and the second width L2, the position of the preset photoresist layer 3 can be corrected according to the actual propagation geometry of the large-angle ion beam, thereby determining the position and width of the photoresist layer 4, so that the target implantation region formed after large-angle ion implantation using the photoresist layer 4 has the same position and width as the preset implantation region formed when vertical ion implantation using the preset photoresist layer 3.

[0074] Further, refer to Figure 6 The preset photoresist layer 3 has preset first coordinates (X1, 0) and preset second coordinates (X1+L0, 0) in the horizontal direction, where L0 is the preset width of the preset photoresist layer 3 in the X-axis direction. Based on the first width L1 and the second width L2, the method for determining the target position of the photoresist layer 4 on the surface of the wafer 1 away from the wafer carrier includes:

[0075] The first target coordinate of the photoresist layer 4 in the horizontal direction is determined to be (X1-L2, 0);

[0076] The second target coordinate of the photoresist layer 4 in the horizontal direction is determined to be (X1+L0-L1, 0).

[0077] Specifically, the preset photoresist layer 3 is a reference photoresist layer set to obtain the preset implantation region without considering the lateral influence of large-angle ion beams. The preset first coordinate (X1, 0) corresponds to the first boundary position of the preset photoresist layer 3 in the X-axis direction, and the preset second coordinate (X1+L0, 0) corresponds to the second boundary position of the preset photoresist layer 3 in the X-axis direction. For large-angle ion implantation, the first boundary is corrected from X1 to X1-L2 according to the second width L2, and the second boundary is corrected from X1+L0 to X1+L0-L1 according to the first width L1, thereby obtaining the target position of the photoresist layer 4 suitable for large-angle ion implantation at the included angle α.

[0078] Based on the target coordinates mentioned above, the target width of the photoresist layer 4 in the X-axis direction can be expressed as (X1+L0-L1)-(X1-L2), i.e., L0+L2-L1. Therefore, the width of the photoresist layer 4 can be different from the preset width L0 of the preset photoresist layer 3. By modifying the two boundary positions of the preset photoresist layer 3 according to the first width L1 and the second width L2 respectively, the target implantation region formed when performing large-angle ion implantation with the photoresist layer 4 as a mask can be made to have the same position and width as the preset implantation region formed when performing vertical ion implantation with the preset photoresist layer 3 as a mask. Figure 6 The diagram illustrates the position and boundary changes of the photoresist layer 4 relative to the preset photoresist layer 3. In actual manufacturing, the photoresist layer 4 can be formed according to the aforementioned first and second target coordinates, and then the photoresist layer 4 can be used as a mask for large-angle ion implantation in step S2.

[0079] The first width L1, the second width L2, and the target position of the photoresist layer 4 can be recalculated according to different process conditions. For example, when the height t of the preset photoresist layer 3 changes, the first width L1 changes accordingly; when the depth H changes, the second width L2 changes accordingly; when the included angle α changes, both the first width L1 and the second width L2 change with the tangent of the included angle α. Therefore, when performing ion implantation for different device structures, different photoresist thicknesses, or different target implantation depths, the position of the preset photoresist layer 3 can be corrected by redetermining the above parameters, so that the target position of the photoresist layer 4 obtained after correction matches the corresponding large-angle ion implantation conditions, and the position and width of the target implantation area are the same as those of the preset implantation area.

[0080] In the actual ion implantation process, the target implantation area on the wafer 1 and the height t of the preset photoresist layer 3 can be determined first based on the target device structure. The included angle α and the ion beam energy are then selected according to the required normal implantation depth. Subsequently, the first width L1 and the second width L2 are calculated based on the included angle α, the height t, and the depth H, and the target first coordinate and target second coordinate of the photoresist layer 4 are determined. After completing the patterning of the photoresist layer 4, the wafer 1 is placed on the support surface of the tray 20, and the wafer support device is adapted to the ion beam incident direction. Then, large-angle ion implantation is performed according to step S2.

[0081] When a large-angle ion beam propagates to the periphery of the wafer 1, the enclosure 23 can form a protective barrier around the tray 20 through the inner extension 233, the side enclosure 232, and the bottom enclosure 231. The ion beam protection layer 5 is located on the surface of the support structure 21, which may be bombarded by the ion beam. Therefore, a portion of the ion beam deviating from the effective implantation area of ​​the wafer 1 can preferentially act on the ion beam protection layer 5, reducing the possibility of it directly impacting the metal support area. Especially when the included angle α is large, the structure of the inner extension 233 extending downwards from the wafer 1 helps to cover areas on the sides of the traditional tray that are easily exposed to the ion beam propagation path, thus enabling the wafer carrier to cooperate with the large-angle ion implantation method.

[0082] The ion implantation method in this embodiment uses a large-angle ion beam to reduce the implantation depth in the wafer normal direction under high ion beam energy conditions. It also uses the photoresist height, implantation angle, and implantation depth to calculate the lateral obstruction and lateral offset caused by the large-angle incident beam, and adjusts the photoresist position accordingly. At the same time, the wafer carrier device provides protection for the large-angle ion beam through the outer enclosure structure and the ion beam protection layer, thereby taking into account shallow implantation, beam transmission efficiency, and the accuracy of the target implantation position.

[0083] In summary, the wafer carrier device and ion implantation method of the present invention, by setting an ion beam protection layer on the surface of the support structure that may be located in the ion beam propagation path, and forming an angle greater than 45° and less than 90° between the ion beam and the wafer surface normal for large-angle ion implantation, can, on the one hand, protect the support structure using the ion beam protection layer, reducing the possibility of secondary electrons generated by direct ion beam bombardment of the support structure, thus providing a structural basis for large-angle ion implantation; on the other hand, it can reduce the implantation depth of the ion beam along the wafer thickness direction without excessively reducing the ion beam energy, thereby balancing the needs of shallow ion implantation with ion beam transmission efficiency and beam current intensity, which is beneficial for shortening ion implantation time, improving ion implantation efficiency, and enhancing the mass production applicability of shallow ion implantation processes. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0084] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A wafer carrier device, characterized in that, The wafer carrier includes: A tray has a bottom surface and a support surface that are arranged opposite to each other, the support surface being used to support a wafer to be implanted with ions; A support structure includes an enclosure and a support; wherein the enclosure includes a bottom section, a side section, and an inner extension section; the bottom section is located below the bottom surface of the tray; the support section is disposed between the bottom surface of the tray and the bottom section, and the support section is used to support the tray; the side section extends from the bottom section toward the wafer and surrounds the side of the tray; the inner extension section extends from the side section toward the center of the tray, and at least a portion of the inner extension section is located below the wafer; and An ion beam protection layer covers at least the surface of the support structure located along the ion beam propagation path during ion implantation.

2. The wafer carrier device according to claim 1, characterized in that: The material of the support structure includes metal, and the material of the ion beam shielding layer includes graphite.

3. The wafer carrier device according to claim 1, characterized in that: The ion beam protection layer covers all exposed surfaces of the support structure.

4. The wafer carrier device according to claim 1, characterized in that: There is a gap between the inner extension section and the wafer.

5. An ion implantation method, characterized in that, The ion implantation method includes: S1, providing a wafer to be ion implanted and a wafer carrier device as described in any one of claims 1 to 4, and placing the wafer on a tray of the wafer carrier device; wherein a photoresist layer is formed on the surface of the wafer away from the wafer carrier device; S2, using the photoresist layer as a mask, ion implantation is performed on the surface of the wafer away from the wafer carrier, wherein the ion beam implanted has an angle α with the normal of the wafer surface, and 45° < α < 90°.

6. The ion implantation method according to claim 5, characterized in that: The included angle α is not less than 60°.

7. The ion implantation method according to claim 5, characterized in that: The ion beam acceleration voltage of the ion implantation is greater than 3kV.

8. The ion implantation method according to claim 5, characterized in that, It also includes the step of determining the parameters of the photoresist layer, wherein the photoresist layer is obtained based on the preset photoresist layer boundary position correction, and a preset implantation region is formed when the preset photoresist layer is used as a mask to perform preset ion implantation perpendicular to the wafer surface, and a target implantation region with the same position and width as the preset implantation region is formed when the photoresist layer is used as a mask and the included angle α is used to perform the ion implantation. The steps for determining the parameters of the photoresist layer include: Determine the height t of the preset photoresist layer, the included angle α, and the ion implantation depth H; Based on the height t of the preset photoresist layer and the included angle α, the first width L1 of the blocking injection region is determined; Based on the included angle α and the ion implantation depth H, the second width L2 of the implantation region is determined; Based on the first width L1 and the second width L2, the target position of the photoresist layer on the surface of the wafer away from the wafer carrier is determined.

9. The ion implantation method according to claim 8, characterized in that: The method for determining the first width L1 of the blocking injection region based on the height t of the preset photoresist layer and the included angle α includes: calculating the product of the tangent of the included angle α and the height t, and determining the product of the tangent of the included angle α and the height t as the first width L1; The method for determining the second width L2 of the over-implanted region based on the included angle α and the ion implantation depth H includes: calculating the product of the tangent of the included angle α and the depth H, and determining the product of the tangent of the included angle α and the depth H as the second width L2.

10. The ion implantation method according to claim 8, characterized in that, With the direction of the surface of the wafer away from the wafer carrier device as the X-axis and the direction perpendicular to the wafer surface as the Y-axis, the preset photoresist layer has a preset first coordinate (X1, 0) and a preset second coordinate (X1+L0, 0) in the horizontal direction. The method for determining the target position of the photoresist layer on the surface of the wafer away from the wafer carrier based on the first width L1 and the second width L2 includes: The first target coordinate of the photoresist layer in the horizontal direction is determined to be (X1-L2, 0); The second target coordinate of the photoresist layer in the horizontal direction is determined as (X1+L0-L1, 0).

Images