A ltcc high near-end rejection low pass filter

Abstract

The application discloses a LTCC laminated high near-end rejection low-pass filter, which comprises a ceramic dielectric base, and the side wall of the middle layer of the ceramic dielectric base is provided with an input port (P1) of the low-pass filter and an output port (P2) of the low-pass filter; the ground ports of the ceramic dielectric base are all grounded to the ground capacitor base; the ceramic dielectric base comprises 10 layers of ceramic dielectric circuit layers with a laminated structure; the ground layers of the high near-end rejection low-pass filter are arranged on the top layer, the bottom layer and the middle layer of the ceramic dielectric base of the low-pass filter, and all the ground layers are connected together through metallized vias V_G. The LTCC laminated high near-end rejection low-pass filter has the advantages of outstanding near-end out-of-band rejection, low loss, high temperature resistance, low cost, high reliability and the like, and is suitable for large-scale production.

Description

Technical Field

[0001] This invention relates to a low-pass filter with high near-end rejection based on LTCC technology, and relates to the field of microwave technology. Background Technology

[0002] A filter is a frequency-selective device whose core function is to allow signals in a specific frequency band to pass through while suppressing signals in other frequency bands. It is indispensable in the signal processing chain of fields such as communications, radar, and audio. The LTCC (Low-Temperature Ceramic) manufacturing process involves printing metal and functional structures onto several single-layer dielectric green ceramic tapes, pressing them together, and then sintering them at 800-900°C to achieve three-dimensional integration of passive components. This integration of passive components enables high-density packaging, low dielectric loss, low conductor loss, and high reliability. While LTCC low-pass filters have advantages such as small size, low insertion loss, and good stability, most low-pass filters have poor near-end out-of-band suppression. This invention provides a design method and specific preferred embodiments for a low-pass filter with high near-end suppression and low insertion loss. Summary of the Invention

[0003] The purpose of this invention is to provide a high near-end rejection low-pass filter using LTCC technology. The high near-end rejection low-pass filter includes: a ceramic dielectric substrate; an input port (P1) and an output port (P2) of the low-pass filter are provided on the outer wall of the middle layer of the ceramic substrate; a high near-end rejection low-pass filter is provided between the input port (P1) and the output port (P2) of the ceramic dielectric substrate; the grounding ports of the ceramic dielectric substrate are all grounded using grounding capacitor substrates; a metal grounding layer is provided on the top layer, bottom layer, and interior of the ceramic dielectric substrate; the ceramic dielectric substrate contains 10 layers of ceramic dielectric circuit layers with a stacked structure, wherein: The first layer consists of a metal planar conductor printed on a ceramic dielectric substrate, which serves as the grounding metal substrate 101 for the third capacitor. The second layer consists of twenty-nine mutually insulated planar metal conductors printed on a ceramic dielectric substrate. The first planar metal conductor is the common substrate 102 for the second, third, and fourth capacitors, and the second to twenty-ninth planar metal conductors are the second layer metal pads V_G-2 of the metallized vias V_G. The third layer consists of thirty-one mutually insulated planar metal conductors printed on a ceramic dielectric substrate. The first planar metal conductor is formed by the third-layer pad V1-3 of the metallized via V1 connecting the common substrate 103 of the first and second capacitors. The second planar metal conductor is formed by the third-layer pad V2-3 of the metallized via V2. The third planar metal conductor is formed by the third-layer pad V3-3 of the metallized via V3 connecting the common substrate 104 of the fourth and fifth capacitors. The fourth to thirty-first planar metal conductors are formed by the third-layer metal pad V_G-3 of the metallized via V_G. The fourth layer consists of four mutually insulated planar metal conductors printed on a ceramic dielectric substrate. The first planar metal conductor is the common substrate 105 of the first and fifth capacitors. The second planar metal conductor is the fourth layer pad V1-4 of the metallized via V1. The third planar metal conductor is the fourth layer pad V2-4 of the metallized via V2. The fourth planar metal conductor is the fourth layer pad V3-4 of the metallized via V3. The fifth layer consists of thirty-one mutually insulated planar metal conductors printed on a ceramic substrate. The first planar metal conductor is the fifth-layer pad V1-5 of the metallized via V1, the second planar metal conductor is the fifth-layer pad V2-5 of the metallized via V2, the third planar metal conductor is the fifth-layer pad V3-5 of the metallized via V3, and the fourth to thirty-first planar metal conductors are the fifth-layer metal pad V_G-5 of the metallized via V_G. The sixth layer consists of thirty-one mutually insulated planar metal conductors printed on a ceramic substrate. The first planar metal conductor is formed by connecting the input port P1 to the sixth-layer pad V1-6 of the metallized via V1, which in turn connects to the sixth-layer metal substrate L1-6 of the inductor L1. The sixth-layer metal substrate L1-6 of the inductor L1 is then connected to the sixth-layer pad V4-6 of the metallized via V4. The second planar metal conductor is the sixth-layer pad V2-6 of the metallized via V2. The third planar metal conductor is connected by connecting the output port P2 to the sixth-layer pad V3-6 of the metallized via V3, which in turn connects to the sixth-layer metal substrate L2-6 of the inductor L2. The sixth metal substrate L2-6 of inductor L2 is connected to the sixth pad V7-6 of metallized via V7; the fourth to thirty-first metal planar conductors are the sixth metal pad V_G-6 of metallized via V_G; The seventh layer consists of thirty-one mutually insulated planar metal conductors printed on the ceramic dielectric substrate. The first planar metal conductor is formed by connecting the seventh-layer pad V4-7 of the metallized via V4 to the seventh-layer metal substrate L1-7 of inductor L1, and the seventh-layer metal substrate L1-7 of inductor L1 is connected to the seventh-layer pad V5-7 of the metallized via V5. The second planar metal conductor is the sixth-layer pad V2-7 of the metallized via V2. The third planar metal conductor is formed by connecting the seventh-layer pad V7-7 of the metallized via V7 to the seventh-layer metal substrate L2-7 of inductor L2, and the seventh-layer metal substrate L2-7 of inductor L2 is connected to the seventh-layer pad V6-7 of the metallized via V6. The fourth to thirty-first planar metal conductors are the seventh-layer metal pad V_G-7 of the metallized via V_G. The eighth layer consists of twenty-nine mutually insulated planar metal conductors printed on a ceramic dielectric substrate. The first planar metal conductor is formed by connecting the eighth-layer pad V5-8 of the metallized via V5 to the eighth-layer metal substrate L1-8 of inductor L1, the eighth-layer metal substrate L1-8 of inductor L1 to the eighth-layer pad V2-8 of the metallized via V2, the eighth-layer pad V2-8 of the metallized via V2 to the eighth-layer metal substrate L2-8 of inductor L2, and the eighth-layer metal substrate L2-8 of inductor L2 to the eighth-layer pad V6-8 of the metallized via V6. The second to twenty-ninth planar metal conductors are formed by the eighth-layer metal pad V_G-8 of the metallized via V_G. The ninth layer consists of twenty-eight mutually insulated metal planar conductors printed on a ceramic dielectric substrate. The first to twenty-eighth metal planar conductors are the ninth layer metal pads V_G-9 of the metallized vias V_G. The tenth layer has a metal planar conductor printed on the ceramic dielectric substrate, which is the grounding metal substrate 106.

[0004] The beneficial effects of this invention are as follows: Based on LTCC technology, this invention achieves a low-pass filter with high near-end rejection and low insertion loss through LTCC stacked structure design. Existing ordinary LTCC low-pass filters typically have a near-end rejection of around 10-20 dB, while the LTCC high near-end rejection low-pass filter of this invention achieves an out-of-band rejection of over 35 dB. Furthermore, the return loss of the LTCC high near-end rejection low-pass filter of this invention can reach -13 dB across the entire passband frequency range. Simultaneously, this invention also includes the filtering function of suppressing high-frequency signals from passing through low-frequency signals, and possesses the advantages of LTCC low-pass filters such as low loss, resistance to high and low temperatures, low cost, and high reliability. Attached Figure Description

[0005] Figure 1 This is an equivalent circuit diagram of a specific embodiment of the present invention; Figure 2 This is a front view of the three-dimensional structure of a specific embodiment of the present invention; Figure 3 This is a top view of the three-dimensional structure of a specific embodiment of the present invention; Figure 4 This is a perspective view of a three-dimensional structure according to a specific embodiment of the present invention; Figure 5 This is a schematic diagram of the first layer circuit planar structure according to a specific embodiment of the present invention; Figure 6 This is a schematic diagram of the second-layer circuit planar structure according to a specific embodiment of the present invention; Figure 7 This is a schematic diagram of the third-layer circuit planar structure according to a specific embodiment of the present invention; Figure 8 This is a schematic diagram of the fourth layer circuit planar structure according to a specific embodiment of the present invention; Figure 9 This is a schematic diagram of the fifth-layer circuit planar structure according to a specific embodiment of the present invention; Figure 10 This is a schematic diagram of the sixth layer circuit planar structure according to a specific embodiment of the present invention; Figure 11 This is a schematic diagram of the seventh-layer circuit planar structure according to a specific embodiment of the present invention; Figure 12 This is a schematic diagram of the eighth layer circuit planar structure according to a specific embodiment of the present invention; Figure 13 This is a schematic diagram of the ninth layer circuit planar structure according to a specific embodiment of the present invention; Figure 14 This is a schematic diagram of the tenth layer circuit planar structure according to a specific embodiment of the present invention; Figure 15 The simulation results of the insertion loss (S21) of the S-parameters in a specific embodiment of the present invention are shown in the figure. Figure 16 The simulation results of the return loss (S11) of the S-parameters in a specific embodiment of the present invention are shown in the figure. Figure 17 The simulation results of the return loss (S22) of the S-parameters in a specific embodiment of the present invention are shown in the figure. Detailed Implementation The structure of specific embodiments of the present invention will be further described below with reference to the accompanying drawings. The following description is only used to clearly illustrate the technical solution of the present invention and should not be used to limit the scope of protection of the present invention.

[0006] like Figures 1 to 4As shown, this invention provides an LTCC high near-end rejection low-pass filter. The ceramic dielectric substrate of the high near-end rejection low-pass filter has an input port P1 and an output port P2 on its sidewall. The grounding ports of the ceramic dielectric substrate are all grounded by grounding capacitor substrates. A low-pass filtering structure is provided between the input port P1 and the output port P2 of the high near-end rejection low-pass filter. The grounding layers of the high near-end rejection low-pass filter are set on the top, bottom, and middle layers of the ceramic dielectric substrate of the low-pass filter, and all grounding layers are connected together through metallized vias V_G. According to the appendix Figures 5 to 14 The LTCC dielectric substrate of the present invention comprises 10 circuit layers, and the specific structure and connection relationship of the 10 circuit layers are as follows: The first layer consists of a metal planar conductor printed on a ceramic dielectric substrate, which serves as the grounding metal substrate 101 for the third capacitor. The second layer consists of twenty-nine mutually insulated planar metal conductors printed on a ceramic dielectric substrate. The first planar metal conductor is the common substrate 102 for the second, third, and fourth capacitors, and the second to twenty-ninth planar metal conductors are the second layer metal pads V_G-2 of the metallized vias V_G. The third layer consists of thirty-one mutually insulated planar metal conductors printed on a ceramic dielectric substrate. The first planar metal conductor is formed by the third-layer pad V1-3 of the metallized via V1 connecting the common substrate 103 of the first and second capacitors. The second planar metal conductor is formed by the third-layer pad V2-3 of the metallized via V2. The third planar metal conductor is formed by the third-layer pad V3-3 of the metallized via V3 connecting the common substrate 104 of the fourth and fifth capacitors. The fourth to thirty-first planar metal conductors are formed by the third-layer metal pad V_G-3 of the metallized via V_G. The fourth layer consists of four mutually insulated planar metal conductors printed on a ceramic dielectric substrate. The first planar metal conductor is the common substrate 105 of the first and fifth capacitors. The second planar metal conductor is the fourth layer pad V1-4 of the metallized via V1. The third planar metal conductor is the fourth layer pad V2-4 of the metallized via V2. The fourth planar metal conductor is the fourth layer pad V3-4 of the metallized via V3. The fifth layer consists of thirty-one mutually insulated planar metal conductors printed on a ceramic substrate. The first planar metal conductor is the fifth-layer pad V1-5 of the metallized via V1, the second planar metal conductor is the fifth-layer pad V2-5 of the metallized via V2, the third planar metal conductor is the fifth-layer pad V3-5 of the metallized via V3, and the fourth to thirty-first planar metal conductors are the fifth-layer metal pad V_G-5 of the metallized via V_G. The sixth layer consists of thirty-one mutually insulated planar metal conductors printed on a ceramic substrate. The first planar metal conductor is formed by connecting the input port P1 to the sixth-layer pad V1-6 of the metallized via V1, which in turn connects to the sixth-layer metal substrate L1-6 of the inductor L1. The sixth-layer metal substrate L1-6 of the inductor L1 is then connected to the sixth-layer pad V4-6 of the metallized via V4. The second planar metal conductor is the sixth-layer pad V2-6 of the metallized via V2. The third planar metal conductor is connected by connecting the output port P2 to the sixth-layer pad V3-6 of the metallized via V3, which in turn connects to the sixth-layer metal substrate L2-6 of the inductor L2. The sixth metal substrate L2-6 of inductor L2 is connected to the sixth pad V7-6 of metallized via V7; the fourth to thirty-first metal planar conductors are the sixth metal pad V_G-6 of metallized via V_G; The seventh layer consists of thirty-one mutually insulated planar metal conductors printed on the ceramic dielectric substrate. The first planar metal conductor is formed by connecting the seventh-layer pad V4-7 of the metallized via V4 to the seventh-layer metal substrate L1-7 of inductor L1, and the seventh-layer metal substrate L1-7 of inductor L1 is connected to the seventh-layer pad V5-7 of the metallized via V5. The second planar metal conductor is the sixth-layer pad V2-7 of the metallized via V2. The third planar metal conductor is formed by connecting the seventh-layer pad V7-7 of the metallized via V7 to the seventh-layer metal substrate L2-7 of inductor L2, and the seventh-layer metal substrate L2-7 of inductor L2 is connected to the seventh-layer pad V6-7 of the metallized via V6. The fourth to thirty-first planar metal conductors are the seventh-layer metal pad V_G-7 of the metallized via V_G. The eighth layer consists of twenty-nine mutually insulated planar metal conductors printed on a ceramic dielectric substrate. The first planar metal conductor is formed by connecting the eighth-layer pad V5-8 of the metallized via V5 to the eighth-layer metal substrate L1-8 of inductor L1, the eighth-layer metal substrate L1-8 of inductor L1 to the eighth-layer pad V2-8 of the metallized via V2, the eighth-layer pad V2-8 of the metallized via V2 to the eighth-layer metal substrate L2-8 of inductor L2, and the eighth-layer metal substrate L2-8 of inductor L2 to the eighth-layer pad V6-8 of the metallized via V6. The second to twenty-ninth planar metal conductors are formed by the eighth-layer metal pad V_G-8 of the metallized via V_G. The ninth layer consists of twenty-eight mutually insulated metal planar conductors printed on a ceramic dielectric substrate. The first to twenty-eighth metal planar conductors are the ninth layer metal pads V_G-9 of the metallized vias V_G. The tenth layer has a metal planar conductor printed on the ceramic dielectric substrate, which is the grounding metal substrate 106.

[0007] This invention relates to an LTCC (Low-End Copper Ceramic) multilayer dielectric high near-end rejection low-pass filter. It utilizes the LTCC fabrication process for multilayer filters, optimizes the design of low-pass filters based on this process, and redesigns the ideal circuit diagram and simulation model using LTCC technology. A high near-end rejection low-pass filter is thus redesigned. While typical LTCC low-pass filters have near-end out-of-band rejection of 10dB to 20dB, the low-pass filter designed in this invention achieves 35dB near-end rejection, and its in-band return loss reaches 13dB. This invention exhibits excellent in-band characteristics, low in-band insertion loss, and high near-end out-of-band rejection. Utilizing LTCC technology, it features a simple structure, high stability, and suitability for mass production.

[0008] The embodiments described above are preferred embodiments of the present invention and are not intended to limit the invention to the above-described embodiments. Based on the embodiments of the present invention, any modifications, equivalent substitutions, or improvements made by those skilled in the art without inventive effort to obtain other embodiments should be included within the scope of protection set forth in the claims.

Claims

1. A low-pass filter with high near-end rejection (LTCC), characterized in that, The LTCC low-pass filter includes a ceramic dielectric substrate, and the conductor layers of the ceramic dielectric substrate are connected through metallized vias. Specifically, the first, second, third, and fourth conductor layers are capacitor circuit layers; the fifth, sixth, seventh, eighth, and ninth conductor layers are inductor circuit layers; and the tenth conductor layer is a metal ground layer. The ceramic dielectric substrate has a total of ten internal circuit layers, as follows: The first layer consists of a metal planar conductor printed on the ceramic dielectric substrate, which serves as the grounding metal substrate 101 for the third capacitor. The second layer consists of twenty-nine mutually insulated metal planar conductors printed on the ceramic dielectric substrate. The first metal planar conductor serves as the common substrate 102 for the second, third, and fourth capacitors, while the second to twenty-ninth metal planar conductors are the second-layer metal pads V_G-2 of the metallized vias V_G. The third layer consists of thirty-one mutually insulated planar metal conductors printed on a ceramic dielectric substrate. The first planar metal conductor is formed by the third-layer pad V1-3 of the metallized via V1 connecting the common substrate 103 of the first and second capacitors. The second planar metal conductor is formed by the third-layer pad V2-3 of the metallized via V2. The third planar metal conductor is formed by the third-layer pad V3-3 of the metallized via V3 connecting the common substrate 104 of the fourth and fifth capacitors. The fourth to thirty-first planar metal conductors are formed by the third-layer metal pad V_G-3 of the metallized via V_G. The fourth layer consists of four mutually insulated planar metal conductors printed on a ceramic dielectric substrate. The first planar metal conductor is the common substrate 105 of the first and fifth capacitors. The second planar metal conductor is the fourth layer pad V1-4 of the metallized via V1. The third planar metal conductor is the fourth layer pad V2-4 of the metallized via V2. The fourth planar metal conductor is the fourth layer pad V3-4 of the metallized via V3. The fifth layer consists of thirty-one mutually insulated planar metal conductors printed on a ceramic substrate. The first planar metal conductor is the fifth-layer pad V1-5 of the metallized via V1, the second planar metal conductor is the fifth-layer pad V2-5 of the metallized via V2, the third planar metal conductor is the fifth-layer pad V3-5 of the metallized via V3, and the fourth to thirty-first planar metal conductors are the fifth-layer metal pad V_G-5 of the metallized via V_G. The sixth layer consists of thirty-one mutually insulated planar metal conductors printed on a ceramic substrate. The first planar metal conductor is formed by connecting the input port P1 to the sixth-layer pad V1-6 of the metallized via V1, which in turn connects to the sixth-layer metal substrate L1-6 of the inductor L1. The sixth-layer metal substrate L1-6 of the inductor L1 is then connected to the sixth-layer pad V4-6 of the metallized via V4. The second planar metal conductor is the sixth-layer pad V2-6 of the metallized via V2. The third planar metal conductor is connected by connecting the output port P2 to the sixth-layer pad V3-6 of the metallized via V3, which in turn connects to the sixth-layer metal substrate L2-6 of the inductor L2. The sixth metal substrate L2-6 of inductor L2 is connected to the sixth pad V7-6 of metallized via V7; the fourth to thirty-first metal planar conductors are the sixth metal pad V_G-6 of metallized via V_G; The seventh layer consists of thirty-one mutually insulated planar metal conductors printed on the ceramic substrate. The first planar metal conductor is formed by connecting the seventh-layer pad V4-7 of the metallized via V4 to the seventh-layer metal substrate L1-7 of inductor L1, and the seventh-layer metal substrate L1-7 of inductor L1 to the seventh-layer pad V5-7 of the metallized via V5. The second planar metal conductor is the sixth-layer pad V2-7 of the metallized via V2. The third planar metal conductor is formed by connecting the seventh-layer pad V7-7 of the metallized via V7 to the seventh-layer metal substrate L2-7 of inductor L2, and the seventh-layer metal substrate L2-7 of inductor L2 to the seventh-layer pad V6-7 of the metallized via V6. The fourth to thirty-first planar metal conductors are the seventh-layer metal pad V_G-7 of the metallized via V_G. The eighth layer consists of twenty-nine mutually insulated planar metal conductors printed on a ceramic dielectric substrate. The first planar metal conductor is formed by connecting the eighth-layer pad V5-8 of the metallized via V5 to the eighth-layer metal substrate L1-8 of inductor L1, the eighth-layer metal substrate L1-8 of inductor L1 to the eighth-layer pad V2-8 of the metallized via V2, the eighth-layer pad V2-8 of the metallized via V2 to the eighth-layer metal substrate L2-8 of inductor L2, and the eighth-layer metal substrate L2-8 of inductor L2 to the eighth-layer pad V6-8 of the metallized via V6. The second to twenty-ninth planar metal conductors are formed by the eighth-layer metal pad V_G-8 of the metallized via V_G. The ninth layer consists of twenty-eight mutually insulated metal planar conductors printed on a ceramic dielectric substrate. The first to twenty-eighth metal planar conductors are the ninth layer metal pads V_G-9 of the metallized vias V_G. The tenth layer has a metal planar conductor printed on the ceramic dielectric substrate, which is the grounding metal substrate 106.

2. The LTCC high near-end rejection low-pass filter according to claim 1, characterized in that, Its input port P1 and output port P2 are both located on the outer wall of the middle layer of the ceramic dielectric substrate, and the input port P1 and output port P2 are symmetrically arranged.

3. The LTCC high near-end rejection low-pass filter according to claim 1, characterized in that, From the perspective of the low-pass filter as a whole, its inductance distribution has a centrally symmetrical structure, and its capacitance distribution has an axisymmetric structure.

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