A LTCC one-to-twelve power divider

Abstract

A kind of LTCC laminated one twelfth power divider, including ceramic dielectric substrate, the input port (P1) of one twelfth power divider is equipped on the top layer of ceramic dielectric substrate, the output port (P2), (P3), (P4), (P5), (P6), (P7), (P8), (P9), (P10), (P11), (P12), (P13) of one twelfth power divider are equipped on the outer side wall of ceramic substrate;The ceramic dielectric substrate includes 12 layers of laminated structure circuit layer;The one twelfth power divider is constituted by three-stage power dividing circuit, the first-stage power dividing circuit is one one-third equal power divider, the second-stage power dividing circuit is constituted by three one-half equal power divider, and the third-stage power dividing circuit is constituted by eight one-half equal power divider;The laminated one twelfth power divider of the application is realized using LTCC technology, with the characteristics of small insertion loss, high output port isolation, good output port amplitude and phase consistency, low cost, etc., suitable for mass production.

Description

Technical Field

[0001] This invention relates to a 1-to-12 power divider based on LTCC technology, belonging to the field of microwave passive device technology. Background Technology

[0002] LTCC (Low Temperature Co-fired Ceramic) is a multilayer three-dimensional circuit manufacturing and packaging technology that combines low-temperature sintered ceramic powder with highly conductive metal paste. LTCC technology increases the isolation between individual passbands of a duplexer, enabling one-time co-firing at 850-900°C. Power dividers are fundamental passive devices in RF front-ends, antenna feed networks, transceiver components, and test equipment: they divide a single signal into multiple equal paths, requiring good matching between ports and a certain degree of isolation between output ports. With the development of 5G / 6G, Wi-Fi 6E / 7, satellite navigation, and millimeter-wave radar, the requirements for power dividers are becoming increasingly demanding. LTCC power dividers utilize low-temperature co-fired ceramic technology to achieve their function by using a lumped structure of LTCC to integrate lumped components. Summary of the Invention

[0003] The purpose of this invention is to provide a 1-to-12 power divider using LTCC technology. The LTCC 1-to-12 power divider includes: a ceramic dielectric substrate; an input port (P1) of the 1-to-12 power divider on the top layer of the ceramic substrate; output ports (P2), (P3), (P4), (P5), (P6), (P7), (P8), (P9), (P10), (P11), (P12), and (P13) of the 1-to-12 power divider on the outer wall of the ceramic substrate; the 1-to-12 power divider is composed of three power divider circuits: the first stage is a 1-to-3 power divider, the second stage is composed of three 1-to-2 power dividers, and the third stage is composed of six 1-to-2 power dividers; the second and twelfth layers of the ceramic dielectric substrate have a metal reference GND; the ceramic dielectric substrate contains 12 layers of ceramic dielectric circuits with a stacked structure, wherein: First layer: The first circuit layer has ten mutually insulated metal conductors printed on it. The first metal planar conductor is formed by connecting internal endpoint V5, metal planar conductor 107, and internal endpoint V6 in sequence; the second metal planar conductor is formed by connecting internal endpoint V7, metal planar conductor 101, and internal endpoint V2 in sequence; the third metal planar conductor is formed by connecting internal endpoint V8, metal planar conductor 108, and internal endpoint V9 in sequence; the fourth metal planar conductor is formed by connecting internal endpoint V10, metal planar conductor 109, and internal endpoint V11 in sequence; the fifth metal planar conductor is formed by connecting internal endpoint V12, metal planar conductor 107, and internal endpoint V6 in sequence. 03. The internal endpoint V3 is connected; the sixth metal planar conductor is formed by connecting internal endpoint V13, metal planar conductor 110, and internal endpoint V14 in sequence; the seventh metal planar conductor is formed by connecting internal endpoint V15, metal planar conductor 111, and internal endpoint V16 in sequence; the eighth metal planar conductor is formed by connecting internal endpoint V4, metal planar conductor 106, and internal endpoint V17 in sequence; the ninth metal planar conductor is formed by connecting internal endpoint V18, metal planar conductor 112, and internal endpoint V19 in sequence; the tenth metal planar conductor is formed by connecting internal endpoint V12 and metal planar conductor P1 in sequence. Second layer: Twenty mutually insulated metal conductors are printed on the second ceramic dielectric substrate. The first to nineteenth metal planar conductors are V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, and V19, respectively; the twentieth metal planar conductor is GND. The third layer: Nineteen mutually insulated metal conductors are printed on the third layer ceramic dielectric substrate. The first metal planar conductor is formed by connecting the internal terminal V20, the metal capacitor substrate C2, and the internal terminal V25 in sequence; the second metal planar conductor is formed by connecting the internal terminal V30, the metal capacitor substrate C3, and the internal terminal V35 in sequence; the third metal planar conductor is formed by connecting the internal terminal V40, the metal capacitor substrate C4, and the internal terminal V45 in sequence; the fourth metal planar conductor is formed by connecting the internal terminal V50, the metal capacitor substrate C5, and the internal terminal V55 in sequence; the fifth metal planar conductor is formed by connecting the internal terminal V60, the metal capacitor substrate C6, and the internal terminal V65 in sequence; the sixth metal planar conductor is formed by connecting the internal terminal V20, the metal capacitor substrate C2, and the internal terminal V25 in sequence; the seventh metal planar conductor is formed by connecting the internal terminal V20, the metal capacitor substrate C2, and the internal terminal V25 in sequence; the twentieth ... The first metal planar conductor is formed by connecting point V70, metal capacitor substrate C7, and internal endpoint V75; the second metal planar conductor is formed by connecting internal endpoint V80, metal capacitor substrate C8, and internal endpoint V85; the third metal planar conductor is formed by connecting internal endpoint V90, metal capacitor substrate C9, and internal endpoint V95; the fourth metal planar conductor is formed by connecting internal endpoint V100, metal capacitor substrate C10, and internal endpoint V105; the fifth metal planar conductor is formed by connecting internal endpoint V110, metal capacitor substrate C1, internal endpoint V115, and internal endpoint V120; the eleventh to nineteenth metal planar conductors are V2, V6, V8, V3, V11, V13, V4, V16, and V18 respectively. Fourth layer: Forty mutually insulated metal conductors are printed on the fourth layer ceramic dielectric substrate. The first to tenth metal capacitor substrates are C1, C2, C3, C4, C5, C6, C7, C8, C9, and C10, respectively; the eleventh to fortieth metal planar conductors are V2, V3, V4, V6, V8, V11, V13, V16, V18, V20, V25, V30, V35, V40, V45, V50, V55, V60, V65, V70, V75, V80, V85, V90, V95, V100, V105, V110, V115, and V120, respectively. Fifth layer: Thirty mutually insulated metal conductors are printed on the fifth layer ceramic dielectric substrate. The first metal planar conductor is formed by connecting the internal terminal V110, the metal inductor substrate L1, and the internal terminal V111 in sequence; the second metal planar conductor is formed by connecting the internal terminal V120, the metal inductor substrate L2, and the internal terminal V121 in sequence; the third metal planar conductor is formed by connecting the internal terminal V115, the metal inductor substrate L3, and the internal terminal V116 in sequence; the fourth metal planar conductor is formed by connecting the internal terminal V20, the metal inductor substrate L4, and the internal terminal V21 in sequence; the fifth metal planar conductor is formed by connecting the internal terminal V25, the metal inductor substrate L5, and the internal terminal V26 in sequence; the... Six planar metal conductors are sequentially connected by internal endpoint V30, metal inductor substrate L6, and internal endpoint V33; the seventh planar metal conductor is sequentially connected by internal endpoint V35, metal inductor substrate L7, and internal endpoint V38; the eighth planar metal conductor is sequentially connected by internal endpoint V40, metal inductor substrate L8, and internal endpoint V41; the ninth planar metal conductor is sequentially connected by internal endpoint V45, metal inductor substrate L9, and internal endpoint V46; the tenth planar metal conductor is sequentially connected by internal endpoint V50, metal inductor substrate L10, and internal endpoint V51; the eleventh planar metal conductor is sequentially connected by internal endpoint V55, metal inductor substrate L11, and internal endpoint V56. The following is a list of interconnected metal planar conductors: the twelfth metal planar conductor is formed by connecting internal endpoint V60, metal inductor substrate L12, and internal endpoint V63; the thirteenth metal planar conductor is formed by connecting internal endpoint V65, metal inductor substrate L13, and internal endpoint V68; the fourteenth metal planar conductor is formed by connecting internal endpoint V70, metal inductor substrate L14, and internal endpoint V71; the fifteenth metal planar conductor is formed by connecting internal endpoint V75, metal inductor substrate L15, and internal endpoint V76; the sixteenth metal planar conductor is formed by connecting internal endpoint V80, metal inductor substrate L16, and internal endpoint V81; the seventeenth metal planar conductor is formed by connecting internal endpoint V85, metal inductor substrate L12, and internal endpoint V63 ... thirteenth metal planar conductor is formed by connecting internal endpoint V65, metal inductor substrate L12, and internal endpoint V63; the thirteenth metal planar conductor is formed by connecting internal endpoint V65, metal inductor substrate L12, and internal endpoint V63; the thirteenth metal planar conductor is formed by connecting internal endpoint V65, metal inductor substrate L12, and internal endpoint V63; the thirteenth metal planar conductor is formed by connecting internal endpoint V65, metal inductor substrate L12, and internal endpoint V63; the thirteenth metal planar conductor is formed by connecting internal endpoint V65, metal inductor substrate L12, and internal endpoint V63; the thirteenth metal planar The substrate L17 and internal terminal V86 are connected together; the eighteenth metal planar conductor is formed by connecting internal terminal V90, metal inductor substrate L18, and internal terminal V93 in sequence; the nineteenth metal planar conductor is formed by connecting internal terminal V95, metal inductor substrate L19, and internal terminal V98 in sequence; the twentieth metal planar conductor is formed by connecting internal terminal V100, metal inductor substrate L20, and internal terminal V101 in sequence; the twenty-first metal planar conductor is formed by connecting internal terminal V105, metal inductor substrate L21, and internal terminal V106 in sequence; the twenty-second to thirtieth metal planar conductors are V2, V3, V4, V6, V8, V11, V13, V16, and V18 in sequence; Sixth layer: Thirty mutually insulated metal conductors are printed on the sixth layer ceramic dielectric substrate. The first metal planar conductor is formed by connecting the internal terminal V111, the metal inductor substrate L1, and the internal terminal V112 in sequence; the second metal planar conductor is formed by connecting the internal terminal V121, the metal inductor substrate L2, and the internal terminal V122 in sequence; the third metal planar conductor is formed by connecting the internal terminal V116, the metal inductor substrate L3, and the internal terminal V117 in sequence; the fourth metal planar conductor is formed by connecting the internal terminal V21, the metal inductor substrate L4, and the internal terminal V22 in sequence; the fifth metal planar conductor is formed by connecting the internal terminal V26, the metal inductor substrate L5, and the internal terminal V27 in sequence; the sixth... Six planar metal conductors are sequentially connected by internal endpoint V32, metal inductor substrate L6, and internal endpoint V33; the seventh planar metal conductor is sequentially connected by internal endpoint V37, metal inductor substrate L7, and internal endpoint V38; the eighth planar metal conductor is sequentially connected by internal endpoint V41, metal inductor substrate L8, and internal endpoint V42; the ninth planar metal conductor is sequentially connected by internal endpoint V46, metal inductor substrate L9, and internal endpoint V47; the tenth planar metal conductor is sequentially connected by internal endpoint V51, metal inductor substrate L10, and internal endpoint V52; the eleventh planar metal conductor is sequentially connected by internal endpoint V56, metal inductor substrate L11, and internal endpoint V57. The following is a list of interconnected metal planar conductors: the twelfth metal planar conductor is formed by connecting internal endpoint V62, metal inductor substrate L12, and internal endpoint V63 in sequence; the thirteenth metal planar conductor is formed by connecting internal endpoint V67, metal inductor substrate L13, and internal endpoint V68 in sequence; the fourteenth metal planar conductor is formed by connecting internal endpoint V71, metal inductor substrate L14, and internal endpoint V72 in sequence; the fifteenth metal planar conductor is formed by connecting internal endpoint V76, metal inductor substrate L15, and internal endpoint V77 in sequence; the sixteenth metal planar conductor is formed by connecting internal endpoint V81, metal inductor substrate L16, and internal endpoint V82 in sequence; the seventeenth metal planar conductor is formed by connecting internal endpoint V86, metal inductor substrate L14, and internal endpoint V63 in sequence; the fifteenth metal planar conductor is formed by connecting internal endpoint V76, metal inductor substrate L15, and internal endpoint V77 in sequence; the sixteenth metal planar conductor is formed by connecting internal endpoint V81, metal inductor substrate L16, and internal endpoint V82 in sequence; the seventeenth metal planar conductor is formed by connecting internal endpoint V86, metal inductor substrate L14, and internal endpoint V68 in sequence; the twelfth metal planar conductor is formed by connecting internal endpoint V62, metal inductor substrate L14, and internal endpoint V63 in sequence; the thirteenth metal planar conductor is formed by connecting internal endpoint V67, metal inductor substrate L15, and internal endpoint V77 in sequence; the sixteenth metal planar conductor is formed by connecting internal endpoint V81, metal inductor substrate L16, and internal endpoint V82 in sequence; the seventeenth metal planar conductor is formed by connecting internal endpoint V86, metal inductor substrate L14, and internal endpoint V68 in sequence; the twelfth metal planar conductor is formed by connecting internal endpoint V86, metal induct The substrate L17 and internal terminal V87 are connected together; the eighteenth metal planar conductor is formed by connecting internal terminal V92, metal inductor substrate L18, and internal terminal V93 in sequence; the nineteenth metal planar conductor is formed by connecting internal terminal V97, metal inductor substrate L19, and internal terminal V98 in sequence; the twentieth metal planar conductor is formed by connecting internal terminal V101, metal inductor substrate L20, and internal terminal V102 in sequence; the twenty-first metal planar conductor is formed by connecting internal terminal V106, metal inductor substrate L21, and internal terminal V107 in sequence; the twenty-second to thirtieth metal planar conductors are V2, V3, V4, V6, V8, V11, V13, V16, and V18 in sequence; Seventh Layer: Thirty mutually insulated metal conductors are printed on the seventh layer ceramic dielectric substrate. The first metal planar conductor is formed by connecting the internal terminal V112, the metal inductor substrate L1, and the internal terminal V113 in sequence; the second metal planar conductor is formed by connecting the internal terminal V122, the metal inductor substrate L2, and the internal terminal V123 in sequence; the third metal planar conductor is formed by connecting the internal terminal V117, the metal inductor substrate L3, and the internal terminal V118 in sequence; the fourth metal planar conductor is formed by connecting the internal terminal V22, the metal inductor substrate L4, and the internal terminal V23 in sequence; the fifth metal planar conductor is formed by connecting the internal terminal V27, the metal inductor substrate L5, and the internal terminal V28 in sequence; the sixth... Six planar metal conductors are connected sequentially from internal terminal V31, metal inductor substrate L6, and internal terminal V32; the seventh planar metal conductor is connected sequentially from internal terminal V36, metal inductor substrate L7, and internal terminal V37; the eighth planar metal conductor is connected sequentially from internal terminal V42, metal inductor substrate L8, and internal terminal V43; the ninth planar metal conductor is connected sequentially from internal terminal V47, metal inductor substrate L9, and internal terminal V48; the tenth planar metal conductor is connected sequentially from internal terminal V52, metal inductor substrate L10, and internal terminal V53; the eleventh planar metal conductor is connected sequentially from internal terminal V57, metal inductor substrate L11, and internal terminal V58. The following is a list of interconnected metal planar conductors: the twelfth metal planar conductor is formed by connecting internal endpoint V61, metal inductor substrate L12, and internal endpoint V62; the thirteenth metal planar conductor is formed by connecting internal endpoint V66, metal inductor substrate L13, and internal endpoint V67; the fourteenth metal planar conductor is formed by connecting internal endpoint V72, metal inductor substrate L14, and internal endpoint V73; the fifteenth metal planar conductor is formed by connecting internal endpoint V77, metal inductor substrate L15, and internal endpoint V78; the sixteenth metal planar conductor is formed by connecting internal endpoint V82, metal inductor substrate L16, and internal endpoint V83; the seventeenth metal planar conductor is formed by connecting internal endpoint V87, metal inductor substrate L14, and internal endpoint V62 ... thirteenth metal planar conductor is formed by connecting internal endpoint V66, metal inductor substrate L14, and internal endpoint V67; the thirteenth metal planar conductor is formed by connecting internal endpoint V87, metal inductor substrate L14, and internal endpoint V62; the thirteenth metal planar conductor is formed by connecting internal endpoint V87, metal inductor substrate L14, and internal endpoint V62; the thirteenth metal planar conductor is formed by connecting internal endpoint V87, metal inductor substrate L14, and internal endpoint V62; the thirteenth metal planar conductor is formed by connecting internal endpoint V87, metal inductor substrate L14, and internal endpoint V62; the thirteenth metal planar The first metal planar conductor is formed by connecting the substrate L17 and the internal terminal V88; the eighteenth metal planar conductor is formed by connecting the internal terminal V91, the metal inductor substrate L18, and the internal terminal V92; the nineteenth metal planar conductor is formed by connecting the internal terminal V96, the metal inductor substrate L19, and the internal terminal V97; the twentieth metal planar conductor is formed by connecting the internal terminal V102, the metal inductor substrate L20, and the internal terminal V103; the twenty-first metal planar conductor is formed by connecting the internal terminal V107, the metal inductor substrate L21, and the internal terminal V108; the twenty-second to thirtieth metal planar conductors are V2, V3, V4, V6, V8, V11, V13, V16, and V18 respectively. Eighth layer: Thirty mutually insulated metal conductors are printed on the eighth layer ceramic dielectric substrate. The first metal planar conductor is formed by connecting the internal terminal V113, the metal inductor substrate L1, and the internal terminal V114 in sequence; the second metal planar conductor is formed by connecting the internal terminal V123, the metal inductor substrate L2, and the internal terminal V124 in sequence; the third metal planar conductor is formed by connecting the internal terminal V118, the metal inductor substrate L3, and the internal terminal V119 in sequence; the fourth metal planar conductor is formed by connecting the internal terminal V23, the metal inductor substrate L4, and the internal terminal V24 in sequence; the fifth metal planar conductor is formed by connecting the internal terminal V28, the metal inductor substrate L5, and the internal terminal V29 in sequence; the sixth... Six planar metal conductors are connected sequentially from internal terminal V31, metal inductor substrate L6, and internal terminal V34; the seventh planar metal conductor is connected sequentially from internal terminal V36, metal inductor substrate L7, and internal terminal V39; the eighth planar metal conductor is connected sequentially from internal terminal V43, metal inductor substrate L8, and internal terminal V44; the ninth planar metal conductor is connected sequentially from internal terminal V48, metal inductor substrate L9, and internal terminal V49; the tenth planar metal conductor is connected sequentially from internal terminal V53, metal inductor substrate L10, and internal terminal V54; the eleventh planar metal conductor is connected sequentially from internal terminal V58, metal inductor substrate L11, and internal terminal V59. The following is a list of interconnected metal planar conductors: the twelfth metal planar conductor is formed by connecting internal endpoint V61, metal inductor substrate L12, and internal endpoint V64; the thirteenth metal planar conductor is formed by connecting internal endpoint V66, metal inductor substrate L13, and internal endpoint V69; the fourteenth metal planar conductor is formed by connecting internal endpoint V73, metal inductor substrate L14, and internal endpoint V74; the fifteenth metal planar conductor is formed by connecting internal endpoint V78, metal inductor substrate L15, and internal endpoint V79; the sixteenth metal planar conductor is formed by connecting internal endpoint V83, metal inductor substrate L16, and internal endpoint V84; the seventeenth metal planar conductor is formed by connecting internal endpoint V88, metal inductor substrate L12, and internal endpoint V64. The substrate L17 and internal terminal V89 are connected together; the eighteenth metal planar conductor is formed by connecting internal terminal V91, metal inductor substrate L18, and internal terminal V94 in sequence; the nineteenth metal planar conductor is formed by connecting internal terminal V96, metal inductor substrate L19, and internal terminal V99 in sequence; the twentieth metal planar conductor is formed by connecting internal terminal V103, metal inductor substrate L20, and internal terminal V104 in sequence; the twenty-first metal planar conductor is formed by connecting internal terminal V108, metal inductor substrate L21, and internal terminal V109 in sequence; the twenty-second to thirtieth metal planar conductors are V2, V3, V4, V6, V8, V11, V13, V16, and V18 in sequence; Ninth layer: Thirty mutually insulated metal conductors are printed on the ninth layer ceramic dielectric substrate. The first to thirtieth metal planar conductors are V2, V3, V4, V6, V8, V11, V13, V16, V18, V24, V29, V34, V39, V44, V49, V54, V59, V64, V69, V74, V79, V84, V89, V94, V99, V104, V109, V114, V119, V124. Tenth layer: Forty mutually insulated metal conductors are printed on the tenth layer ceramic dielectric substrate. The first to tenth metal capacitor substrates are CC1, CC2, CC3, CC4, CC5, CC6, CC7, CC8, CC9, and CC10, respectively; the eleventh to fortieth metal planar conductors are V2, V3, V4, V6, V8, V11, V13, V16, V18, V24, V29, V34, V39, V44, V49, V54, V59, V64, V69, V74, V79, V84, V89, V94, V99, V104, V109, V114, V119, and V124, respectively. Eleventh Layer: Ten mutually insulated metal conductors are printed on the eleventh layer ceramic dielectric substrate. The first metal planar conductor is composed of metal planar conductor P2, internal terminal V24, metal capacitor substrate C11, embedded resistor R4, metal capacitor substrate C12, internal terminal V29, and metal planar conductor P2 connected sequentially. The second metal planar conductor is composed of internal terminal V6, internal terminal V34, metal capacitor substrate C13, embedded resistor R5, metal capacitor substrate C14, internal terminal V39, and internal terminal V8 connected sequentially. The third metal planar conductor is composed of metal planar conductor P4, internal terminal V44, and metal capacitor substrate... The first metal planar conductor is composed of C15, an internal resistor R6, a metal capacitor substrate C16, an internal terminal V49, and a metal planar conductor P5; the second metal planar conductor is composed of metal planar conductor P6, an internal terminal V54, a metal capacitor substrate C17, an internal resistor R7, a metal capacitor substrate C18, an internal terminal V59, and a metal planar conductor P7; the third metal planar conductor is composed of internal terminals V11 and V64, a metal capacitor substrate C19, an internal resistor R8, a metal capacitor substrate C20, an internal terminal V69, and an internal terminal V13; the fourth metal planar conductor is composed of metal planar conductor P8, an internal resistor R6, a metal capacitor substrate C16, an internal terminal V49, and a metal planar conductor P5. The first metal planar conductor is composed of terminal V74, metal capacitor substrate C21, embedded resistor R9, metal capacitor substrate C22, internal terminal V79, and metal planar conductor P9; the second metal planar conductor is composed of metal planar conductor P10, internal terminal V84, metal capacitor substrate C23, embedded resistor R10, metal capacitor substrate C24, internal terminal V89, and metal planar conductor P11; the third metal planar conductor is composed of internal terminal V6, internal terminal V34, metal capacitor substrate C13, embedded resistor R5, metal capacitor substrate C14, internal terminal V39, and internal terminal V8; the fourth metal planar conductor is composed of... The first metal planar conductor is composed of metal planar conductor P12, internal terminal V104, metal capacitor substrate C27, embedded resistor R12, metal capacitor substrate C28, internal terminal V109, and metal planar conductor P13 connected together; the tenth metal planar conductor is composed of internal terminal V2, internal terminal V114, metal capacitor substrate C29, embedded resistor R1, metal capacitor substrate C30, internal terminal V119, internal terminal V4, metal capacitor substrate C34, embedded resistor R3, metal capacitor substrate C33, internal terminal V3, internal terminal V124, metal capacitor substrate C32, embedded resistor R2, and metal capacitor substrate C31 connected together. Twelfth layer: A metal conductor called GND is printed on the twelfth layer ceramic dielectric substrate; The beneficial effects of this invention are as follows: Based on LTCC technology, this invention implements a 1-to-12 power divider through LTCC stacked structure design. Utilizing LTCC's 3D wiring, the power divider area is minimized through interlayer striplines and vertical vias. This invention reduces mutual interference between output ports and improves consistency across multiple output ports by using grounding layers of multi-layer LTCC and surrounding vias between ports. This invention utilizes LTCC's unique feature of printing resistor paste onto green ceramic strips and then stacking and co-firing them with a multi-layer ceramic substrate to achieve embedded resistors, reducing the parasitic effects of solder joints on external resistors. The 1-to-12 LTCC power divider of this invention simultaneously features low insertion loss, high isolation between output ports, good amplitude and phase consistency of output ports, and strong resistance to external interference common to LTCC products. Attached Figure Description

[0004] Figure 1 This is an equivalent circuit diagram of a specific embodiment of the present invention; Figure 2 This is a front view of the three-dimensional structure of a specific embodiment of the present invention; Figure 3 This is a top view of the three-dimensional structure of a specific embodiment of the present invention; Figure 4 This is a perspective view of a three-dimensional structure according to a specific embodiment of the present invention; Figure 5 This is a schematic diagram of the first layer circuit planar structure according to a specific embodiment of the present invention; Figure 6 This is a schematic diagram of the second-layer circuit planar structure according to a specific embodiment of the present invention; Figure 7 This is a schematic diagram of the third-layer circuit planar structure according to a specific embodiment of the present invention; Figure 8 This is a schematic diagram of the fourth layer circuit planar structure according to a specific embodiment of the present invention; Figure 9 This is a schematic diagram of the fifth layer circuit planar structure according to a specific embodiment of the present invention; Figure 10 This is a schematic diagram of the sixth layer circuit planar structure according to a specific embodiment of the present invention; Figure 11 This is a schematic diagram of the seventh-layer circuit planar structure according to a specific embodiment of the present invention; Figure 12 This is a schematic diagram of the eighth layer circuit planar structure according to a specific embodiment of the present invention; Figure 13 This is a schematic diagram of the ninth layer circuit planar structure according to a specific embodiment of the present invention; Figure 14 This is a schematic diagram of the tenth layer circuit planar structure according to a specific embodiment of the present invention; Figure 15This is a schematic diagram of the eleventh layer circuit planar structure according to a specific embodiment of the present invention; Figure 16 This is a schematic diagram of the twelfth layer circuit planar structure according to a specific embodiment of the present invention; Figure 17 The figure shows the simulation results of the insertion loss of the S-parameters in a specific embodiment of the present invention. Figure 18 The figure shows the simulation results of the return loss of the S-parameters in a specific embodiment of the present invention. Figure 19 This is a simulation result diagram of the isolation between the output ports of the S-parameters in a specific embodiment of the present invention; Detailed Implementation The structure of specific embodiments of the present invention will be further described below with reference to the accompanying drawings. The following description is only used to clearly illustrate the technical solution of the present invention and should not be used to limit the scope of protection of the present invention.

[0005] like Figures 1 to 4 As shown, this invention provides an LTCC 1-to-12 power divider. The top layer of the 1-to-12 power divider has an input P1; the outer wall of the ceramic substrate of the 1-to-12 power divider has output ports (P2), (P3), (P4), (P5), (P6), (P7), (P8), (P9), (P10), (P11), (P12), and (P13); the second and twelfth layers of the ceramic substrate have a metal reference GND; the 1-to-12 power divider consists of one equal-power-to-1-to-3 power divider and three equal-power-to-4 power dividers; each power divider circuit of the 1-to-12 power divider is composed of chip spiral inductors, multilayer chip capacitors, embedded resistors, and interconnected microstrip lines and striplines; the ceramic substrate contains 12 layers of ceramic dielectric circuits with a stacked structure. According to the appendix Figures 5 to 16 The LTCC dielectric substrate of the present invention comprises 12 circuit layers, and the specific structure and connection relationship of the 12 circuit layers are as follows: The first layer, the first circuit layer, has ten mutually insulated metal conductors printed on it. The first metal planar conductor is formed by connecting internal endpoint V5, metal planar conductor 107, and internal endpoint V6 in sequence; the second metal planar conductor is formed by connecting internal endpoint V7, metal planar conductor 101, and internal endpoint V2 in sequence; the third metal planar conductor is formed by connecting internal endpoint V8, metal planar conductor 108, and internal endpoint V9 in sequence; the fourth metal planar conductor is formed by connecting internal endpoint V10, metal planar conductor 109, and internal endpoint V11 in sequence; the fifth metal planar conductor is formed by connecting internal endpoint V12, metal planar conductor 107, and internal endpoint V6 in sequence. 03. The internal endpoint V3 is connected; the sixth metal planar conductor is formed by connecting internal endpoint V13, metal planar conductor 110, and internal endpoint V14 in sequence; the seventh metal planar conductor is formed by connecting internal endpoint V15, metal planar conductor 111, and internal endpoint V16 in sequence; the eighth metal planar conductor is formed by connecting internal endpoint V4, metal planar conductor 106, and internal endpoint V17 in sequence; the ninth metal planar conductor is formed by connecting internal endpoint V18, metal planar conductor 112, and internal endpoint V19 in sequence; the tenth metal planar conductor is formed by connecting internal endpoint V12 and metal planar conductor P1 in sequence. The second layer consists of twenty mutually insulated metal conductors printed on the ceramic dielectric substrate. The first to nineteenth metal planar conductors are V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, and V19, respectively; the twentieth metal planar conductor is GND. The third layer consists of nineteen mutually insulated metal conductors printed on the ceramic dielectric substrate. The first metal planar conductor is formed by connecting the internal endpoint V20, the metal capacitor substrate C2, and the internal endpoint V25 sequentially; the second metal planar conductor is formed by connecting the internal endpoint V30, the metal capacitor substrate C3, and the internal endpoint V35 sequentially; the third metal planar conductor is formed by connecting the internal endpoint V40, the metal capacitor substrate C4, and the internal endpoint V45 sequentially; the fourth metal planar conductor is formed by connecting the internal endpoint V50, the metal capacitor substrate C5, and the internal endpoint V55 sequentially; the fifth metal planar conductor is formed by connecting the internal endpoint V60, the metal capacitor substrate C6, and the internal endpoint V65 sequentially; the sixth metal planar conductor is formed by connecting the internal endpoint V20, the metal capacitor substrate C2, and the internal endpoint V25 sequentially; the seventh metal planar conductor is formed by connecting the internal endpoint V20, the metal capacitor substrate C2, and the internal endpoint V25 sequentially; the twentieth ... The first metal planar conductor is formed by connecting point V70, metal capacitor substrate C7, and internal endpoint V75; the second metal planar conductor is formed by connecting internal endpoint V80, metal capacitor substrate C8, and internal endpoint V85; the third metal planar conductor is formed by connecting internal endpoint V90, metal capacitor substrate C9, and internal endpoint V95; the fourth metal planar conductor is formed by connecting internal endpoint V100, metal capacitor substrate C10, and internal endpoint V105; the fifth metal planar conductor is formed by connecting internal endpoint V110, metal capacitor substrate C1, internal endpoint V115, and internal endpoint V120; the eleventh to nineteenth metal planar conductors are V2, V6, V8, V3, V11, V13, V4, V16, and V18 respectively. The fourth layer consists of forty mutually insulated metal conductors printed on a ceramic dielectric substrate. The first to tenth metal capacitor substrates are C1, C2, C3, C4, C5, C6, C7, C8, C9, and C10, respectively; the eleventh to fortieth metal planar conductors are V2, V3, V4, V6, V8, V11, V13, V16, V18, V20, V25, V30, V35, V40, V45, V50, V55, V60, V65, V70, V75, V80, V85, V90, V95, V100, V105, V110, V115, and V120, respectively. The fifth layer consists of thirty mutually insulated metal conductors printed on the fifth-layer ceramic dielectric substrate. The first metal planar conductor is formed by connecting the internal endpoint V110, the metal inductor substrate L1, and the internal endpoint V111. The second metal planar conductor is formed by connecting the internal endpoint V120, the metal inductor substrate L2, and the internal endpoint V121. The third metal planar conductor is formed by connecting the internal endpoint V115, the metal inductor substrate L3, and the internal endpoint V116. The fourth metal planar conductor is formed by connecting the internal endpoint V20, the metal inductor substrate L4, and the internal endpoint V21. The fifth metal planar conductor is formed by connecting the internal endpoint V25, the metal inductor substrate L5, and the internal endpoint V26. Six planar metal conductors are sequentially connected by internal endpoint V30, metal inductor substrate L6, and internal endpoint V33; the seventh planar metal conductor is sequentially connected by internal endpoint V35, metal inductor substrate L7, and internal endpoint V38; the eighth planar metal conductor is sequentially connected by internal endpoint V40, metal inductor substrate L8, and internal endpoint V41; the ninth planar metal conductor is sequentially connected by internal endpoint V45, metal inductor substrate L9, and internal endpoint V46; the tenth planar metal conductor is sequentially connected by internal endpoint V50, metal inductor substrate L10, and internal endpoint V51; the eleventh planar metal conductor is sequentially connected by internal endpoint V55, metal inductor substrate L11, and internal endpoint V56. The following is a list of interconnected metal planar conductors: the twelfth metal planar conductor is formed by connecting internal endpoint V60, metal inductor substrate L12, and internal endpoint V63; the thirteenth metal planar conductor is formed by connecting internal endpoint V65, metal inductor substrate L13, and internal endpoint V68; the fourteenth metal planar conductor is formed by connecting internal endpoint V70, metal inductor substrate L14, and internal endpoint V71; the fifteenth metal planar conductor is formed by connecting internal endpoint V75, metal inductor substrate L15, and internal endpoint V76; the sixteenth metal planar conductor is formed by connecting internal endpoint V80, metal inductor substrate L16, and internal endpoint V81; the seventeenth metal planar conductor is formed by connecting internal endpoint V85, metal inductor substrate L12, and internal endpoint V63 ... thirteenth metal planar conductor is formed by connecting internal endpoint V65, metal inductor substrate L12, and internal endpoint V63; the thirteenth metal planar conductor is formed by connecting internal endpoint V65, metal inductor substrate L12, and internal endpoint V63; the thirteenth metal planar conductor is formed by connecting internal endpoint V65, metal inductor substrate L12, and internal endpoint V63; the thirteenth metal planar conductor is formed by connecting internal endpoint V65, metal inductor substrate L12, and internal endpoint V63; the thirteenth metal planar conductor is formed by connecting internal endpoint V65, metal inductor substrate L12, and internal endpoint V63; the thirteenth metal planar The substrate L17 and internal terminal V86 are connected together; the eighteenth metal planar conductor is formed by connecting internal terminal V90, metal inductor substrate L18, and internal terminal V93 in sequence; the nineteenth metal planar conductor is formed by connecting internal terminal V95, metal inductor substrate L19, and internal terminal V98 in sequence; the twentieth metal planar conductor is formed by connecting internal terminal V100, metal inductor substrate L20, and internal terminal V101 in sequence; the twenty-first metal planar conductor is formed by connecting internal terminal V105, metal inductor substrate L21, and internal terminal V106 in sequence; the twenty-second to thirtieth metal planar conductors are V2, V3, V4, V6, V8, V11, V13, V16, and V18 in sequence; The sixth layer consists of thirty mutually insulated metal conductors printed on the ceramic dielectric substrate. The first metal planar conductor is formed by connecting the internal endpoint V111, the metal inductor substrate L1, and the internal endpoint V112. The second metal planar conductor is formed by connecting the internal endpoint V121, the metal inductor substrate L2, and the internal endpoint V122. The third metal planar conductor is formed by connecting the internal endpoint V116, the metal inductor substrate L3, and the internal endpoint V117. The fourth metal planar conductor is formed by connecting the internal endpoint V21, the metal inductor substrate L4, and the internal endpoint V22. The fifth metal planar conductor is formed by connecting the internal endpoint V26, the metal inductor substrate L5, and the internal endpoint V27. Six planar metal conductors are sequentially connected by internal endpoint V32, metal inductor substrate L6, and internal endpoint V33; the seventh planar metal conductor is sequentially connected by internal endpoint V37, metal inductor substrate L7, and internal endpoint V38; the eighth planar metal conductor is sequentially connected by internal endpoint V41, metal inductor substrate L8, and internal endpoint V42; the ninth planar metal conductor is sequentially connected by internal endpoint V46, metal inductor substrate L9, and internal endpoint V47; the tenth planar metal conductor is sequentially connected by internal endpoint V51, metal inductor substrate L10, and internal endpoint V52; the eleventh planar metal conductor is sequentially connected by internal endpoint V56, metal inductor substrate L11, and internal endpoint V57. The following is a list of interconnected metal planar conductors: the twelfth metal planar conductor is formed by connecting internal endpoint V62, metal inductor substrate L12, and internal endpoint V63 in sequence; the thirteenth metal planar conductor is formed by connecting internal endpoint V67, metal inductor substrate L13, and internal endpoint V68 in sequence; the fourteenth metal planar conductor is formed by connecting internal endpoint V71, metal inductor substrate L14, and internal endpoint V72 in sequence; the fifteenth metal planar conductor is formed by connecting internal endpoint V76, metal inductor substrate L15, and internal endpoint V77 in sequence; the sixteenth metal planar conductor is formed by connecting internal endpoint V81, metal inductor substrate L16, and internal endpoint V82 in sequence; the seventeenth metal planar conductor is formed by connecting internal endpoint V86, metal inductor substrate L14, and internal endpoint V63 in sequence; the fifteenth metal planar conductor is formed by connecting internal endpoint V76, metal inductor substrate L15, and internal endpoint V77 in sequence; the sixteenth metal planar conductor is formed by connecting internal endpoint V81, metal inductor substrate L16, and internal endpoint V82 in sequence; the seventeenth metal planar conductor is formed by connecting internal endpoint V86, metal inductor substrate L14, and internal endpoint V68 in sequence; the twelfth metal planar conductor is formed by connecting internal endpoint V62, metal inductor substrate L14, and internal endpoint V63 in sequence; the thirteenth metal planar conductor is formed by connecting internal endpoint V67, metal inductor substrate L15, and internal endpoint V77 in sequence; the sixteenth metal planar conductor is formed by connecting internal endpoint V81, metal inductor substrate L16, and internal endpoint V82 in sequence; the seventeenth metal planar conductor is formed by connecting internal endpoint V86, metal inductor substrate L14, and internal endpoint V68 in sequence; the twelfth metal planar conductor is formed by connecting internal endpoint V86, metal induct The substrate L17 and internal terminal V87 are connected together; the eighteenth metal planar conductor is formed by connecting internal terminal V92, metal inductor substrate L18, and internal terminal V93 in sequence; the nineteenth metal planar conductor is formed by connecting internal terminal V97, metal inductor substrate L19, and internal terminal V98 in sequence; the twentieth metal planar conductor is formed by connecting internal terminal V101, metal inductor substrate L20, and internal terminal V102 in sequence; the twenty-first metal planar conductor is formed by connecting internal terminal V106, metal inductor substrate L21, and internal terminal V107 in sequence; the twenty-second to thirtieth metal planar conductors are V2, V3, V4, V6, V8, V11, V13, V16, and V18 in sequence; The seventh layer consists of thirty mutually insulated metal conductors printed on the ceramic dielectric substrate. The first metal planar conductor is formed by connecting internal endpoint V112, metal inductor substrate L1, and internal endpoint V113 sequentially; the second metal planar conductor is formed by connecting internal endpoint V122, metal inductor substrate L2, and internal endpoint V123 sequentially; the third metal planar conductor is formed by connecting internal endpoint V117, metal inductor substrate L3, and internal endpoint V118 sequentially; the fourth metal planar conductor is formed by connecting internal endpoint V22, metal inductor substrate L4, and internal endpoint V23 sequentially; the fifth metal planar conductor is formed by connecting internal endpoint V27, metal inductor substrate L5, and internal endpoint V28 sequentially; and so on. Six planar metal conductors are connected sequentially from internal terminal V31, metal inductor substrate L6, and internal terminal V32; the seventh planar metal conductor is connected sequentially from internal terminal V36, metal inductor substrate L7, and internal terminal V37; the eighth planar metal conductor is connected sequentially from internal terminal V42, metal inductor substrate L8, and internal terminal V43; the ninth planar metal conductor is connected sequentially from internal terminal V47, metal inductor substrate L9, and internal terminal V48; the tenth planar metal conductor is connected sequentially from internal terminal V52, metal inductor substrate L10, and internal terminal V53; the eleventh planar metal conductor is connected sequentially from internal terminal V57, metal inductor substrate L11, and internal terminal V58. The following is a list of interconnected metal planar conductors: the twelfth metal planar conductor is formed by connecting internal endpoint V61, metal inductor substrate L12, and internal endpoint V62; the thirteenth metal planar conductor is formed by connecting internal endpoint V66, metal inductor substrate L13, and internal endpoint V67; the fourteenth metal planar conductor is formed by connecting internal endpoint V72, metal inductor substrate L14, and internal endpoint V73; the fifteenth metal planar conductor is formed by connecting internal endpoint V77, metal inductor substrate L15, and internal endpoint V78; the sixteenth metal planar conductor is formed by connecting internal endpoint V82, metal inductor substrate L16, and internal endpoint V83; the seventeenth metal planar conductor is formed by connecting internal endpoint V87, metal inductor substrate L14, and internal endpoint V62 ... thirteenth metal planar conductor is formed by connecting internal endpoint V66, metal inductor substrate L14, and internal endpoint V67; the thirteenth metal planar conductor is formed by connecting internal endpoint V87, metal inductor substrate L14, and internal endpoint V62; the thirteenth metal planar conductor is formed by connecting internal endpoint V87, metal inductor substrate L14, and internal endpoint V62; the thirteenth metal planar conductor is formed by connecting internal endpoint V87, metal inductor substrate L14, and internal endpoint V62; the thirteenth metal planar conductor is formed by connecting internal endpoint V87, metal inductor substrate L14, and internal endpoint V62; the thirteenth metal planar The first metal planar conductor is formed by connecting the substrate L17 and the internal terminal V88; the eighteenth metal planar conductor is formed by connecting the internal terminal V91, the metal inductor substrate L18, and the internal terminal V92; the nineteenth metal planar conductor is formed by connecting the internal terminal V96, the metal inductor substrate L19, and the internal terminal V97; the twentieth metal planar conductor is formed by connecting the internal terminal V102, the metal inductor substrate L20, and the internal terminal V103; the twenty-first metal planar conductor is formed by connecting the internal terminal V107, the metal inductor substrate L21, and the internal terminal V108; the twenty-second to thirtieth metal planar conductors are V2, V3, V4, V6, V8, V11, V13, V16, and V18 respectively. On the eighth layer, thirty mutually insulated metal conductors are printed on the ceramic dielectric substrate. The first metal planar conductor is formed by connecting the internal terminal V113, the metal inductor substrate L1, and the internal terminal V114 in sequence; the second metal planar conductor is formed by connecting the internal terminal V123, the metal inductor substrate L2, and the internal terminal V124 in sequence; the third metal planar conductor is formed by connecting the internal terminal V118, the metal inductor substrate L3, and the internal terminal V119 in sequence; the fourth metal planar conductor is formed by connecting the internal terminal V23, the metal inductor substrate L4, and the internal terminal V24 in sequence; the fifth metal planar conductor is formed by connecting the internal terminal V28, the metal inductor substrate L5, and the internal terminal V29 in sequence; and so on. Six planar metal conductors are connected sequentially from internal terminal V31, metal inductor substrate L6, and internal terminal V34; the seventh planar metal conductor is connected sequentially from internal terminal V36, metal inductor substrate L7, and internal terminal V39; the eighth planar metal conductor is connected sequentially from internal terminal V43, metal inductor substrate L8, and internal terminal V44; the ninth planar metal conductor is connected sequentially from internal terminal V48, metal inductor substrate L9, and internal terminal V49; the tenth planar metal conductor is connected sequentially from internal terminal V53, metal inductor substrate L10, and internal terminal V54; the eleventh planar metal conductor is connected sequentially from internal terminal V58, metal inductor substrate L11, and internal terminal V59. The following is a list of interconnected metal planar conductors: the twelfth metal planar conductor is formed by connecting internal endpoint V61, metal inductor substrate L12, and internal endpoint V64; the thirteenth metal planar conductor is formed by connecting internal endpoint V66, metal inductor substrate L13, and internal endpoint V69; the fourteenth metal planar conductor is formed by connecting internal endpoint V73, metal inductor substrate L14, and internal endpoint V74; the fifteenth metal planar conductor is formed by connecting internal endpoint V78, metal inductor substrate L15, and internal endpoint V79; the sixteenth metal planar conductor is formed by connecting internal endpoint V83, metal inductor substrate L16, and internal endpoint V84; the seventeenth metal planar conductor is formed by connecting internal endpoint V88, metal inductor substrate L12, and internal endpoint V64. The substrate L17 and internal terminal V89 are connected together; the eighteenth metal planar conductor is formed by connecting internal terminal V91, metal inductor substrate L18, and internal terminal V94 in sequence; the nineteenth metal planar conductor is formed by connecting internal terminal V96, metal inductor substrate L19, and internal terminal V99 in sequence; the twentieth metal planar conductor is formed by connecting internal terminal V103, metal inductor substrate L20, and internal terminal V104 in sequence; the twenty-first metal planar conductor is formed by connecting internal terminal V108, metal inductor substrate L21, and internal terminal V109 in sequence; the twenty-second to thirtieth metal planar conductors are V2, V3, V4, V6, V8, V11, V13, V16, and V18 in sequence; The ninth layer has thirty mutually insulated metal conductors printed on it. The first to the thirtieth metal planar conductors are V2, V3, V4, V6, V8, V11, V13, V16, V18, V24, V29, V34, V39, V44, V49, V54, V59, V64, V69, V74, V79, V84, V89, V94, V99, V104, V109, V114, V119, and V124, respectively. The tenth layer consists of forty mutually insulated metal conductors printed on a ceramic dielectric substrate. The first to tenth metal capacitor substrates are CC1, CC2, CC3, CC4, CC5, CC6, CC7, CC8, CC9, and CC10, respectively; the eleventh to fortieth metal planar conductors are V2, V3, V4, V6, V8, V11, V13, V16, V18, V24, V29, V34, V39, V44, V49, V54, V59, V64, V69, V74, V79, V84, V89, V94, V99, V104, V109, V114, V119, and V124, respectively. On the eleventh layer, ten mutually insulated metal conductors are printed on the ceramic dielectric substrate. The first metal planar conductor is composed of metal planar conductor P2, internal terminal V24, metal capacitor substrate C11, embedded resistor R4, metal capacitor substrate C12, internal terminal V29, and metal planar conductor P2 connected sequentially. The second metal planar conductor is composed of internal terminal V6, internal terminal V34, metal capacitor substrate C13, embedded resistor R5, metal capacitor substrate C14, internal terminal V39, and internal terminal V8 connected sequentially. The third metal planar conductor is composed of metal planar conductor P4, internal terminal V44, and metal capacitor substrate... The first metal planar conductor is composed of C15, an internal resistor R6, a metal capacitor substrate C16, an internal terminal V49, and a metal planar conductor P5; the second metal planar conductor is composed of metal planar conductor P6, an internal terminal V54, a metal capacitor substrate C17, an internal resistor R7, a metal capacitor substrate C18, an internal terminal V59, and a metal planar conductor P7; the third metal planar conductor is composed of internal terminals V11 and V64, a metal capacitor substrate C19, an internal resistor R8, a metal capacitor substrate C20, an internal terminal V69, and an internal terminal V13; the fourth metal planar conductor is composed of metal planar conductor P8, an internal resistor R6, a metal capacitor substrate C16, an internal terminal V49, and a metal planar conductor P5. The first metal planar conductor is composed of terminal V74, metal capacitor substrate C21, embedded resistor R9, metal capacitor substrate C22, internal terminal V79, and metal planar conductor P9; the second metal planar conductor is composed of metal planar conductor P10, internal terminal V84, metal capacitor substrate C23, embedded resistor R10, metal capacitor substrate C24, internal terminal V89, and metal planar conductor P11; the third metal planar conductor is composed of internal terminal V6, internal terminal V34, metal capacitor substrate C13, embedded resistor R5, metal capacitor substrate C14, internal terminal V39, and internal terminal V8; the fourth metal planar conductor is composed of... The first metal planar conductor is composed of metal planar conductor P12, internal terminal V104, metal capacitor substrate C27, embedded resistor R12, metal capacitor substrate C28, internal terminal V109, and metal planar conductor P13 connected together; the tenth metal planar conductor is composed of internal terminal V2, internal terminal V114, metal capacitor substrate C29, embedded resistor R1, metal capacitor substrate C30, internal terminal V119, internal terminal V4, metal capacitor substrate C34, embedded resistor R3, metal capacitor substrate C33, internal terminal V3, internal terminal V124, metal capacitor substrate C32, embedded resistor R2, and metal capacitor substrate C31 connected together. The twelfth layer has a metal conductor called GND printed on it on the ceramic dielectric substrate. The LTCC multilayer chip-type 1-to-12 power divider of this invention utilizes the LTCC fabrication process for multilayer filters. By leveraging the three-dimensional interlayer wiring of LTCC to achieve power divider topology folding, the planar footprint can be significantly reduced. A quasi-closed field environment is provided by arranging numerous grounding vias around the output ports, improving port isolation and anti-interference capabilities. The isolation resistors of each power divider circuit are designed using the unique embedded resistor method of LTCC, which reduces the parasitic effects of solder joints on external resistors. This invention, implemented using LTCC technology, features a compact structure, high stability, and is suitable for mass production.

[0006] The embodiments described above are preferred embodiments of the present invention and are not intended to limit the invention to the above-described embodiments. Based on the embodiments of the present invention, any modifications, equivalent substitutions, or improvements made by those skilled in the art without inventive effort to obtain other embodiments should be included within the scope of protection set forth in the claims.

Claims

1. An LTCC stacked structure 1-to-12 power divider, the LTCC 1-to-12 power divider comprising a ceramic dielectric substrate, the top layer of the ceramic dielectric substrate having an input port (P1) for the power divider, and the outer walls of the ceramic dielectric substrate having output ports (P2), (P3), (P4), (P5), (P6), (P7), (P8), (P9), (P10), (P11), (P12), and (P13); the 1-to-12 power divider is composed of three stages of power divider circuits, the first stage being a 1-to-3 power divider, the second stage being three 1-to-2 power dividers, and the third stage being six 1-to-2 power dividers. The ceramic dielectric substrate contains circuit layers, which, from top to bottom, sequentially include a first circuit layer, a second circuit layer, a third circuit layer, a fourth circuit layer, a fifth circuit layer, a sixth circuit layer, a seventh circuit layer, an eighth circuit layer, a ninth circuit layer, a tenth circuit layer, an eleventh circuit layer, and a twelfth circuit layer.

2. A 1-to-12 power divider implementing the LTCC stacked structure as described in claim 1, characterized in that, The ceramic dielectric substrate includes one input port and twelve output ports; the ceramic dielectric substrate includes twelve circuit layers, and the stacked circuit structure includes... The first layer, the first circuit layer, has ten mutually insulated metal conductors printed on it. The first metal planar conductor is formed by connecting internal endpoint V5, metal planar conductor 107, and internal endpoint V6 in sequence; the second metal planar conductor is formed by connecting internal endpoint V7, metal planar conductor 101, and internal endpoint V2 in sequence; the third metal planar conductor is formed by connecting internal endpoint V8, metal planar conductor 108, and internal endpoint V9 in sequence; the fourth metal planar conductor is formed by connecting internal endpoint V10, metal planar conductor 109, and internal endpoint V11 in sequence; the fifth metal planar conductor is formed by connecting internal endpoint V12, metal planar conductor 107, and internal endpoint V6 in sequence.

03. The internal endpoint V3 is connected; the sixth metal planar conductor is formed by connecting internal endpoint V13, metal planar conductor 110, and internal endpoint V14 in sequence; the seventh metal planar conductor is formed by connecting internal endpoint V15, metal planar conductor 111, and internal endpoint V16 in sequence; the eighth metal planar conductor is formed by connecting internal endpoint V4, metal planar conductor 106, and internal endpoint V17 in sequence; the ninth metal planar conductor is formed by connecting internal endpoint V18, metal planar conductor 112, and internal endpoint V19 in sequence; the tenth metal planar conductor is formed by connecting internal endpoint V12 and metal planar conductor P1 in sequence. The second layer consists of twenty mutually insulated metal conductors printed on the ceramic dielectric substrate. The first to nineteenth metal planar conductors are V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, and V19, respectively; the twentieth metal planar conductor is GND. The third layer consists of nineteen mutually insulated metal conductors printed on the ceramic dielectric substrate. The first metal planar conductor is formed by connecting the internal endpoint V20, the metal capacitor substrate C2, and the internal endpoint V25 sequentially; the second metal planar conductor is formed by connecting the internal endpoint V30, the metal capacitor substrate C3, and the internal endpoint V35 sequentially; the third metal planar conductor is formed by connecting the internal endpoint V40, the metal capacitor substrate C4, and the internal endpoint V45 sequentially; the fourth metal planar conductor is formed by connecting the internal endpoint V50, the metal capacitor substrate C5, and the internal endpoint V55 sequentially; the fifth metal planar conductor is formed by connecting the internal endpoint V60, the metal capacitor substrate C6, and the internal endpoint V65 sequentially; the sixth metal planar conductor is formed by connecting the internal endpoint V20, the metal capacitor substrate C2, and the internal endpoint V25 sequentially; the seventh metal planar conductor is formed by connecting the internal endpoint V20, the metal capacitor substrate C2, and the internal endpoint V25 sequentially; the twentieth ... The first metal planar conductor is formed by connecting point V70, metal capacitor substrate C7, and internal endpoint V75; the second metal planar conductor is formed by connecting internal endpoint V80, metal capacitor substrate C8, and internal endpoint V85; the third metal planar conductor is formed by connecting internal endpoint V90, metal capacitor substrate C9, and internal endpoint V95; the fourth metal planar conductor is formed by connecting internal endpoint V100, metal capacitor substrate C10, and internal endpoint V105; the fifth metal planar conductor is formed by connecting internal endpoint V110, metal capacitor substrate C1, internal endpoint V115, and internal endpoint V120; the eleventh to nineteenth metal planar conductors are V2, V6, V8, V3, V11, V13, V4, V16, and V18 respectively. The fourth layer consists of forty mutually insulated metal conductors printed on a ceramic dielectric substrate. The first to tenth metal capacitor substrates are C1, C2, C3, C4, C5, C6, C7, C8, C9, and C10, respectively; the eleventh to fortieth metal planar conductors are V2, V3, V4, V6, V8, V11, V13, V16, V18, V20, V25, V30, V35, V40, V45, V50, V55, V60, V65, V70, V75, V80, V85, V90, V95, V100, V105, V110, V115, and V120, respectively. The fifth layer consists of thirty mutually insulated metal conductors printed on the fifth-layer ceramic dielectric substrate. The first metal planar conductor is formed by connecting the internal endpoint V110, the metal inductor substrate L1, and the internal endpoint V111. The second metal planar conductor is formed by connecting the internal endpoint V120, the metal inductor substrate L2, and the internal endpoint V121. The third metal planar conductor is formed by connecting the internal endpoint V115, the metal inductor substrate L3, and the internal endpoint V116. The fourth metal planar conductor is formed by connecting the internal endpoint V20, the metal inductor substrate L4, and the internal endpoint V21. The fifth metal planar conductor is formed by connecting the internal endpoint V25, the metal inductor substrate L5, and the internal endpoint V26. Six planar metal conductors are sequentially connected by internal endpoint V30, metal inductor substrate L6, and internal endpoint V33; the seventh planar metal conductor is sequentially connected by internal endpoint V35, metal inductor substrate L7, and internal endpoint V38; the eighth planar metal conductor is sequentially connected by internal endpoint V40, metal inductor substrate L8, and internal endpoint V41; the ninth planar metal conductor is sequentially connected by internal endpoint V45, metal inductor substrate L9, and internal endpoint V46; the tenth planar metal conductor is sequentially connected by internal endpoint V50, metal inductor substrate L10, and internal endpoint V51; the eleventh planar metal conductor is sequentially connected by internal endpoint V55, metal inductor substrate L11, and internal endpoint V56. The following is a list of interconnected metal planar conductors: the twelfth metal planar conductor is formed by connecting internal endpoint V60, metal inductor substrate L12, and internal endpoint V63; the thirteenth metal planar conductor is formed by connecting internal endpoint V65, metal inductor substrate L13, and internal endpoint V68; the fourteenth metal planar conductor is formed by connecting internal endpoint V70, metal inductor substrate L14, and internal endpoint V71; the fifteenth metal planar conductor is formed by connecting internal endpoint V75, metal inductor substrate L15, and internal endpoint V76; the sixteenth metal planar conductor is formed by connecting internal endpoint V80, metal inductor substrate L16, and internal endpoint V81; the seventeenth metal planar conductor is formed by connecting internal endpoint V85, metal inductor substrate L12, and internal endpoint V63 ... thirteenth metal planar conductor is formed by connecting internal endpoint V65, metal inductor substrate L12, and internal endpoint V63; the thirteenth metal planar conductor is formed by connecting internal endpoint V65, metal inductor substrate L12, and internal endpoint V63; the thirteenth metal planar conductor is formed by connecting internal endpoint V65, metal inductor substrate L12, and internal endpoint V63; the thirteenth metal planar conductor is formed by connecting internal endpoint V65, metal inductor substrate L12, and internal endpoint V63; the thirteenth metal planar conductor is formed by connecting internal endpoint V65, metal inductor substrate L12, and internal endpoint V63; the thirteenth metal planar The substrate L17 and internal terminal V86 are connected together; the eighteenth metal planar conductor is formed by connecting internal terminal V90, metal inductor substrate L18, and internal terminal V93 in sequence; the nineteenth metal planar conductor is formed by connecting internal terminal V95, metal inductor substrate L19, and internal terminal V98 in sequence; the twentieth metal planar conductor is formed by connecting internal terminal V100, metal inductor substrate L20, and internal terminal V101 in sequence; the twenty-first metal planar conductor is formed by connecting internal terminal V105, metal inductor substrate L21, and internal terminal V106 in sequence; the twenty-second to thirtieth metal planar conductors are V2, V3, V4, V6, V8, V11, V13, V16, and V18 in sequence; The sixth layer consists of thirty mutually insulated metal conductors printed on the ceramic dielectric substrate. The first metal planar conductor is formed by connecting the internal endpoint V111, the metal inductor substrate L1, and the internal endpoint V112. The second metal planar conductor is formed by connecting the internal endpoint V121, the metal inductor substrate L2, and the internal endpoint V122. The third metal planar conductor is formed by connecting the internal endpoint V116, the metal inductor substrate L3, and the internal endpoint V117. The fourth metal planar conductor is formed by connecting the internal endpoint V21, the metal inductor substrate L4, and the internal endpoint V22. The fifth metal planar conductor is formed by connecting the internal endpoint V26, the metal inductor substrate L5, and the internal endpoint V27. Six planar metal conductors are sequentially connected by internal endpoint V32, metal inductor substrate L6, and internal endpoint V33; the seventh planar metal conductor is sequentially connected by internal endpoint V37, metal inductor substrate L7, and internal endpoint V38; the eighth planar metal conductor is sequentially connected by internal endpoint V41, metal inductor substrate L8, and internal endpoint V42; the ninth planar metal conductor is sequentially connected by internal endpoint V46, metal inductor substrate L9, and internal endpoint V47; the tenth planar metal conductor is sequentially connected by internal endpoint V51, metal inductor substrate L10, and internal endpoint V52; the eleventh planar metal conductor is sequentially connected by internal endpoint V56, metal inductor substrate L11, and internal endpoint V57. The following is a list of interconnected metal planar conductors: the twelfth metal planar conductor is formed by connecting internal endpoint V62, metal inductor substrate L12, and internal endpoint V63 in sequence; the thirteenth metal planar conductor is formed by connecting internal endpoint V67, metal inductor substrate L13, and internal endpoint V68 in sequence; the fourteenth metal planar conductor is formed by connecting internal endpoint V71, metal inductor substrate L14, and internal endpoint V72 in sequence; the fifteenth metal planar conductor is formed by connecting internal endpoint V76, metal inductor substrate L15, and internal endpoint V77 in sequence; the sixteenth metal planar conductor is formed by connecting internal endpoint V81, metal inductor substrate L16, and internal endpoint V82 in sequence; the seventeenth metal planar conductor is formed by connecting internal endpoint V86, metal inductor substrate L14, and internal endpoint V63 in sequence; the fifteenth metal planar conductor is formed by connecting internal endpoint V76, metal inductor substrate L15, and internal endpoint V77 in sequence; the sixteenth metal planar conductor is formed by connecting internal endpoint V81, metal inductor substrate L16, and internal endpoint V82 in sequence; the seventeenth metal planar conductor is formed by connecting internal endpoint V86, metal inductor substrate L14, and internal endpoint V68 in sequence; the twelfth metal planar conductor is formed by connecting internal endpoint V62, metal inductor substrate L14, and internal endpoint V63 in sequence; the thirteenth metal planar conductor is formed by connecting internal endpoint V67, metal inductor substrate L15, and internal endpoint V77 in sequence; the sixteenth metal planar conductor is formed by connecting internal endpoint V81, metal inductor substrate L16, and internal endpoint V82 in sequence; the seventeenth metal planar conductor is formed by connecting internal endpoint V86, metal inductor substrate L14, and internal endpoint V68 in sequence; the twelfth metal planar conductor is formed by connecting internal endpoint V86, metal induct The substrate L17 and internal terminal V87 are connected together; the eighteenth metal planar conductor is formed by connecting internal terminal V92, metal inductor substrate L18, and internal terminal V93 in sequence; the nineteenth metal planar conductor is formed by connecting internal terminal V97, metal inductor substrate L19, and internal terminal V98 in sequence; the twentieth metal planar conductor is formed by connecting internal terminal V101, metal inductor substrate L20, and internal terminal V102 in sequence; the twenty-first metal planar conductor is formed by connecting internal terminal V106, metal inductor substrate L21, and internal terminal V107 in sequence; the twenty-second to thirtieth metal planar conductors are V2, V3, V4, V6, V8, V11, V13, V16, and V18 in sequence; The seventh layer consists of thirty mutually insulated metal conductors printed on the ceramic dielectric substrate. The first metal planar conductor is formed by connecting internal endpoint V112, metal inductor substrate L1, and internal endpoint V113 sequentially; the second metal planar conductor is formed by connecting internal endpoint V122, metal inductor substrate L2, and internal endpoint V123 sequentially; the third metal planar conductor is formed by connecting internal endpoint V117, metal inductor substrate L3, and internal endpoint V118 sequentially; the fourth metal planar conductor is formed by connecting internal endpoint V22, metal inductor substrate L4, and internal endpoint V23 sequentially; the fifth metal planar conductor is formed by connecting internal endpoint V27, metal inductor substrate L5, and internal endpoint V28 sequentially; and so on. Six planar metal conductors are connected sequentially from internal terminal V31, metal inductor substrate L6, and internal terminal V32; the seventh planar metal conductor is connected sequentially from internal terminal V36, metal inductor substrate L7, and internal terminal V37; the eighth planar metal conductor is connected sequentially from internal terminal V42, metal inductor substrate L8, and internal terminal V43; the ninth planar metal conductor is connected sequentially from internal terminal V47, metal inductor substrate L9, and internal terminal V48; the tenth planar metal conductor is connected sequentially from internal terminal V52, metal inductor substrate L10, and internal terminal V53; the eleventh planar metal conductor is connected sequentially from internal terminal V57, metal inductor substrate L11, and internal terminal V58. The following is a list of interconnected metal planar conductors: the twelfth metal planar conductor is formed by connecting internal endpoint V61, metal inductor substrate L12, and internal endpoint V62; the thirteenth metal planar conductor is formed by connecting internal endpoint V66, metal inductor substrate L13, and internal endpoint V67; the fourteenth metal planar conductor is formed by connecting internal endpoint V72, metal inductor substrate L14, and internal endpoint V73; the fifteenth metal planar conductor is formed by connecting internal endpoint V77, metal inductor substrate L15, and internal endpoint V78; the sixteenth metal planar conductor is formed by connecting internal endpoint V82, metal inductor substrate L16, and internal endpoint V83; the seventeenth metal planar conductor is formed by connecting internal endpoint V87, metal inductor substrate L14, and internal endpoint V62 ... thirteenth metal planar conductor is formed by connecting internal endpoint V66, metal inductor substrate L14, and internal endpoint V67; the thirteenth metal planar conductor is formed by connecting internal endpoint V87, metal inductor substrate L14, and internal endpoint V62; the thirteenth metal planar conductor is formed by connecting internal endpoint V87, metal inductor substrate L14, and internal endpoint V62; the thirteenth metal planar conductor is formed by connecting internal endpoint V87, metal inductor substrate L14, and internal endpoint V62; the thirteenth metal planar conductor is formed by connecting internal endpoint V87, metal inductor substrate L14, and internal endpoint V62; the thirteenth metal planar The first metal planar conductor is formed by connecting the substrate L17 and the internal terminal V88; the eighteenth metal planar conductor is formed by connecting the internal terminal V91, the metal inductor substrate L18, and the internal terminal V92; the nineteenth metal planar conductor is formed by connecting the internal terminal V96, the metal inductor substrate L19, and the internal terminal V97; the twentieth metal planar conductor is formed by connecting the internal terminal V102, the metal inductor substrate L20, and the internal terminal V103; the twenty-first metal planar conductor is formed by connecting the internal terminal V107, the metal inductor substrate L21, and the internal terminal V108; the twenty-second to thirtieth metal planar conductors are V2, V3, V4, V6, V8, V11, V13, V16, and V18 respectively. On the eighth layer, thirty mutually insulated metal conductors are printed on the ceramic dielectric substrate. The first metal planar conductor is formed by connecting the internal terminal V113, the metal inductor substrate L1, and the internal terminal V114 in sequence; the second metal planar conductor is formed by connecting the internal terminal V123, the metal inductor substrate L2, and the internal terminal V124 in sequence; the third metal planar conductor is formed by connecting the internal terminal V118, the metal inductor substrate L3, and the internal terminal V119 in sequence; the fourth metal planar conductor is formed by connecting the internal terminal V23, the metal inductor substrate L4, and the internal terminal V24 in sequence; the fifth metal planar conductor is formed by connecting the internal terminal V28, the metal inductor substrate L5, and the internal terminal V29 in sequence; and so on. Six planar metal conductors are connected sequentially from internal terminal V31, metal inductor substrate L6, and internal terminal V34; the seventh planar metal conductor is connected sequentially from internal terminal V36, metal inductor substrate L7, and internal terminal V39; the eighth planar metal conductor is connected sequentially from internal terminal V43, metal inductor substrate L8, and internal terminal V44; the ninth planar metal conductor is connected sequentially from internal terminal V48, metal inductor substrate L9, and internal terminal V49; the tenth planar metal conductor is connected sequentially from internal terminal V53, metal inductor substrate L10, and internal terminal V54; the eleventh planar metal conductor is connected sequentially from internal terminal V58, metal inductor substrate L11, and internal terminal V59. The following is a list of interconnected metal planar conductors: the twelfth metal planar conductor is formed by connecting internal endpoint V61, metal inductor substrate L12, and internal endpoint V64; the thirteenth metal planar conductor is formed by connecting internal endpoint V66, metal inductor substrate L13, and internal endpoint V69; the fourteenth metal planar conductor is formed by connecting internal endpoint V73, metal inductor substrate L14, and internal endpoint V74; the fifteenth metal planar conductor is formed by connecting internal endpoint V78, metal inductor substrate L15, and internal endpoint V79; the sixteenth metal planar conductor is formed by connecting internal endpoint V83, metal inductor substrate L16, and internal endpoint V84; the seventeenth metal planar conductor is formed by connecting internal endpoint V88, metal inductor substrate L12, and internal endpoint V64. The substrate L17 and internal terminal V89 are connected together; the eighteenth metal planar conductor is formed by connecting internal terminal V91, metal inductor substrate L18, and internal terminal V94 in sequence; the nineteenth metal planar conductor is formed by connecting internal terminal V96, metal inductor substrate L19, and internal terminal V99 in sequence; the twentieth metal planar conductor is formed by connecting internal terminal V103, metal inductor substrate L20, and internal terminal V104 in sequence; the twenty-first metal planar conductor is formed by connecting internal terminal V108, metal inductor substrate L21, and internal terminal V109 in sequence; the twenty-second to thirtieth metal planar conductors are V2, V3, V4, V6, V8, V11, V13, V16, and V18 in sequence; The ninth layer has thirty mutually insulated metal conductors printed on it. The first to the thirtieth metal planar conductors are V2, V3, V4, V6, V8, V11, V13, V16, V18, V24, V29, V34, V39, V44, V49, V54, V59, V64, V69, V74, V79, V84, V89, V94, V99, V104, V109, V114, V119, and V124, respectively. The tenth layer consists of forty mutually insulated metal conductors printed on a ceramic dielectric substrate. The first to tenth metal capacitor substrates are CC1, CC2, CC3, CC4, CC5, CC6, CC7, CC8, CC9, and CC10, respectively; the eleventh to fortieth metal planar conductors are V2, V3, V4, V6, V8, V11, V13, V16, V18, V24, V29, V34, V39, V44, V49, V54, V59, V64, V69, V74, V79, V84, V89, V94, V99, V104, V109, V114, V119, and V124, respectively. On the eleventh layer, ten mutually insulated metal conductors are printed on the ceramic dielectric substrate. The first metal planar conductor is formed by connecting metal planar conductor P2, internal terminal V24, metal capacitor substrate C11, embedded resistor R4, metal capacitor substrate C12, internal terminal V29, and metal planar conductor P2 in sequence. The second metal planar conductor is formed by connecting internal terminal V6, internal terminal V34, metal capacitor substrate C13, embedded resistor R5, metal capacitor substrate C14, internal terminal V39, and internal terminal V8 in sequence. The third metal planar conductor is formed by connecting metal planar conductor P4, internal terminal V44, and metal capacitor substrate C15 in sequence. The first metal planar conductor is composed of an internal resistor R6, a metal capacitor substrate C16, an internal terminal V49, and a metal planar conductor P5. The fourth metal planar conductor is composed of a metal planar conductor P6, an internal terminal V54, a metal capacitor substrate C17, an internal resistor R7, a metal capacitor substrate C18, an internal terminal V59, and a metal planar conductor P7. The fifth metal planar conductor is composed of an internal terminal V11, an internal terminal V64, a metal capacitor substrate C19, an internal resistor R8, a metal capacitor substrate C20, an internal terminal V69, and an internal terminal V13. The sixth metal planar conductor is composed of a metal planar conductor P8, an internal terminal... The seventh metal planar conductor is composed of V74, metal capacitor substrate C21, embedded resistor R9, metal capacitor substrate C22, internal terminal V79, and metal planar conductor P9 connected together; the eighth metal planar conductor is composed of metal planar conductor P10, internal terminal V84, metal capacitor substrate C23, embedded resistor R10, metal capacitor substrate C24, internal terminal V89, and metal planar conductor P11 connected together; the ninth metal planar conductor is composed of internal terminal V6, internal terminal V34, metal capacitor substrate C13, embedded resistor R5, metal capacitor substrate C14, internal terminal V39, and internal terminal V8 connected together; the ninth metal planar conductor is composed of... The first metal planar conductor is composed of metal planar conductor P12, internal terminal V104, metal capacitor substrate C27, embedded resistor R12, metal capacitor substrate C28, internal terminal V109, and metal planar conductor P13 connected together; the tenth metal planar conductor is composed of internal terminal V2, internal terminal V114, metal capacitor substrate C29, embedded resistor R1, metal capacitor substrate C30, internal terminal V119, internal terminal V4, metal capacitor substrate C34, embedded resistor R3, metal capacitor substrate C33, internal terminal V3, internal terminal V124, metal capacitor substrate C32, embedded resistor R2, and metal capacitor substrate C31 connected together. The twelfth layer has a metal conductor called GND printed on it.

3. The LTCC 1-to-12 power divider according to claim 1, characterized in that: The input port (P1) of the 1 to 12 power divider is located on the top layer of the ceramic dielectric substrate; the output ports (P2), (P3), (P4), (P5), (P6), (P7), (P8), (P9), (P10), (P11), (P12), and (P13) of the 1 to 12 power divider are located on the outer wall of the ceramic dielectric substrate.

4. The LTCC 1-to-12 power divider according to claim 1, characterized in that: The first-stage power divider circuit of the 1-to-12 power divider is a 1-to-3 power divider, the second-stage power divider circuit is a 1-to-2 power divider, and the third-stage power divider circuit is a 1-to-2 power divider.

5. The LTCC 1-to-12 power divider according to claim 2, characterized in that: The isolation resistors of the first-stage, second-stage, and third-stage power divider circuits of the 1 to 12 power divider are all controlled by embedded resistors in the LTCC circuit.

6. A 1-to-12 power divider according to claim 2, characterized in that: The inductors in the first-stage, second-stage, and third-stage power divider circuits of the 1 to 12 power divider are all multilayer spiral inductors.

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