A frequency reconfigurable filter power divider design method

Abstract

The application discloses a frequency reconfigurable filter power divider design method, and relates to the field of radio frequency and microwave technology, wherein the working frequency of a first hairpin bandpass filter is a first center frequency; the working frequency of a second hairpin bandpass filter is a second center frequency; a cross isolation resistor is connected between a first branch and a second branch; and the working frequency of the power divider is switched between the first center frequency working mode, the second center frequency working mode, and the dual-frequency working mode in which the first center frequency and the second center frequency work simultaneously. The application uses a Y-shaped junction power divider, a hairpin bandpass filter and a PIN diode to construct a single circuit, integrates power division, filtering and frequency reconfiguration, realizes single / dual-frequency mode switching, and has a simple structure and reliable control. The hairpin filter has filtering, out-of-band suppression and DC isolation functions, and the isolation resistor guarantees port matching, so that the overall volume is small, the cost is low, and the application is suitable for multi-frequency communication and radar systems.

Description

Technical Field

[0001] This invention relates to the field of radio frequency and microwave technology, and in particular to a design method for a frequency reconfigurable filter power divider. Background Technology

[0002] With the rapid development of wireless communication technologies such as 5G, IoT, WLAN, and software-defined radio, radio frequency (RF) front-end systems are facing increasingly stringent performance requirements. Modern communication equipment needs to switch flexibly between multiple frequency bands while also taking into account design goals such as miniaturization, low power consumption, and high integration. Against this backdrop, various passive devices in the RF front-end urgently need to evolve from traditional single-function, fixed-operation-mode devices to multi-functional integration and frequency reconfigurability. Power dividers and bandpass filters are two core passive devices in RF front-end circuits. Power dividers are responsible for distributing one input signal to multiple outputs according to a certain ratio and are widely used in phased array radar, wireless communication base stations and test and measurement fields. Bandpass filters are used to select signals in specific frequency bands to pass through and suppress out-of-band interference. In traditional RF front-end architectures, power dividers and filters are usually designed as independent components and then connected by cascading.

[0003] However, current common solutions have many drawbacks, including: existing frequency reconfigurable filter power divider technologies generally suffer from complex circuit structures and a large number of components. To achieve reconfigurability, multiple varactor diodes, tunable resonators, or complex bias networks are often introduced, resulting in bloated topologies, high design difficulty, and high costs. In terms of control methods, continuous tuning schemes using varactor diodes require precise and stable analog voltage sources, with stringent tuning accuracy requirements and limited frequency tuning range, making it difficult to cover the needs of large-span multi-band switching. Regarding operating modes, most existing solutions only support single-frequency continuous tuning or fixed dual-frequency designs, failing to achieve discrete switching between two independent frequency bands and freely combine various single-frequency and dual-frequency operating modes, making it difficult to flexibly adapt to the differentiated frequency band requirements of different communication standards. Furthermore, most existing designs treat filtering and reconfigurable power dividing functions as relatively independent parts, with insufficient integration depth, neglecting crosstalk suppression and DC bias isolation issues between channels. Moreover, the isolation performance between output ports often requires additional isolation networks to ensure, further increasing the circuit area, and there is still considerable room for improvement in miniaturization and integration. Summary of the Invention

[0004] To address the problems in related technologies, this invention provides a design method for a frequency reconfigurable filter power divider, thereby overcoming the aforementioned technical problems in existing related technologies.

[0005] To solve the aforementioned technical problem, the present invention is achieved through the following technical solution: In a first aspect, embodiments of the present invention provide a design method for a frequency reconfigurable filter power divider, comprising: providing a Y-junction power divider structure having one signal input port and two signal output ports; setting a first branch between a first output port and a first signal output terminal, the first branch including a first hairpin bandpass filter and a first diode switch connected in series, the operating frequency of the first hairpin bandpass filter being a first center frequency; setting a second branch between a second output port and a second signal output terminal, the second branch including a second hairpin bandpass filter and a second diode switch connected in series, the operating frequency of the second hairpin bandpass filter being a second center frequency; connecting an isolation resistor between the first branch and the second branch; applying a first DC bias voltage and a second DC bias voltage to the control terminals of the first diode switch and the second diode switch respectively, independently controlling the conduction or cutoff of the first diode switch and the second diode switch; and switching the operating frequency of the power divider between a first center frequency operating mode, a second center frequency operating mode, and a dual-frequency operating mode where the first center frequency and the second center frequency operate simultaneously, by controlling the combination of the conduction and cutoff of the first diode switch and the second diode switch.

[0006] As a preferred embodiment of the frequency reconfigurable filter power divider design method of the present invention, the first center frequency and the second center frequency correspond to two different frequency bands in the wireless communication spectrum. By selecting the first hairpin bandpass filter and the second hairpin bandpass filter with different structural parameters, the power divider can be adapted to any two preset different operating frequency bands to achieve cross-band frequency reconfiguration.

[0007] As a preferred embodiment of the frequency reconfigurable filter power divider design method of the present invention, the first diode switch and the second diode switch are both PIN diodes. The PIN diode is equivalent to a low impedance conduction state when forward biased to connect the corresponding branch, and is equivalent to a high impedance cutoff state when zero biased or reverse biased to disconnect the corresponding branch. The on / off states of the first diode switch and the second diode switch are combined to form four different switch state combinations, of which three effective states correspond to the three working modes respectively, and the remaining state is a fully cutoff state.

[0008] In a preferred embodiment of the frequency reconfigurable filter power divider design method of the present invention, the following steps are taken: by controlling the level states of the first DC bias voltage and the second DC bias voltage respectively, the first diode switch and the second diode switch can operate independently in the on or off state; when only the DC bias voltage corresponding to the first diode switch is at an effective level, the power divider operates in the first center frequency operating mode; when only the DC bias voltage corresponding to the second diode switch is at an effective level, the power divider operates in the second center frequency operating mode; when the DC bias voltages corresponding to the first diode switch and the second diode switch are simultaneously at an effective level, the power divider operates in the dual-frequency operating mode; the switching between the three operating modes is uniquely determined by the combination of the level states of the external DC bias voltage.

[0009] As a preferred embodiment of the frequency reconfigurable filter power divider design method of the present invention, wherein: the first hairpin bandpass filter is used to perform bandpass filtering on the signal transmitted in the first branch, allowing the passband signal in the first center frequency operating mode to pass through and suppressing out-of-band clutter signals deviating from the first center frequency, and forming out-of-band suppression for the signal in the corresponding frequency band of the second branch to prevent it from crosstalking to the first branch; the second hairpin bandpass filter is used to perform bandpass filtering on the signal transmitted in the second branch, allowing the passband signal in the second center frequency operating mode to pass through and suppressing out-of-band clutter signals deviating from the second center frequency, and forming out-of-band suppression for the signal in the corresponding frequency band of the first branch to prevent it from crosstalking to the second branch; the first hairpin bandpass filter and the second hairpin bandpass filter each have DC isolation function, used to block the DC bias voltage of this branch from flowing back to the other branch, and to avoid the DC bias voltage interfering with the working state of the diode switch in the other branch.

[0010] As a preferred embodiment of the frequency reconfigurable filter power divider design method of the present invention, the isolation resistor is connected across the Y-shaped junction between the first branch and the second branch. When the port impedances of the first signal output terminal and the second signal output terminal are mismatched, the signal energy reflected back by the impedance mismatch is dissipated and absorbed in the form of heat energy through the isolation resistor, thereby maintaining the isolation degree of the Y-shaped junction power divider structure between the two output ports, suppressing signal crosstalk between the output ports, and ensuring that the isolation performance between the output ports meets the preset indicators in various operating modes.

[0011] As a preferred embodiment of the frequency reconfigurable filter power divider design method of the present invention, the Y-junction power divider structure, the first branch, the second branch, and the isolation resistor are implemented using a microstrip transmission line structure. The entire circuit is arranged on the upper surface of the same dielectric substrate, and the lower surface of the dielectric substrate is a grounded metal layer. The first hairpin bandpass filter and the second hairpin bandpass filter are both composed of hairpin resonator structures formed by bending microstrip lines. The linewidth, line length, bending spacing, and coupling gap of the microstrip transmission line are determined according to the preset port impedance and the required operating frequency. The first diode switch and the second diode switch are respectively connected in series in the microstrip transmission lines of the first branch and the second branch. Their control terminals are led out to the bias pads on the surface of the dielectric substrate through metallized vias or bonding wires for connecting to an external DC bias power supply.

[0012] Secondly, to further solve the above-mentioned technical problems, the present invention provides a frequency reconfigurable filter power divider design system, comprising: a Y-junction power divider structure having one signal input port and two signal output ports for power distribution from one input signal to two output signals; a first branch connected between one output port of the Y-junction power divider structure and a first signal output terminal, the first branch including a first hairpin bandpass filter and a first diode switch connected in series, the operating frequency of the first hairpin bandpass filter being a first center frequency; and a second branch connected between the other output port of the Y-junction power divider structure and a second signal output terminal, the second branch including a second hairpin bandpass filter and a second diode switch connected in series, the second hairpin bandpass filter operating... The frequency is the second center frequency; an isolation resistor is connected between the first branch and the second branch; a first DC bias terminal is connected to the control terminal of the first diode switch to receive an externally applied first DC bias voltage to independently control the conduction or cutoff of the first diode switch; a second DC bias terminal is connected to the control terminal of the second diode switch to receive an externally applied second DC bias voltage to independently control the conduction or cutoff of the second diode switch; the first diode switch and the second diode switch form different conduction and cutoff combinations under their respective DC bias voltage control, and the operating frequency of the frequency reconfigurable filter power divider responds to the change in the conduction and cutoff combinations, switching between the first center frequency operating mode, the second center frequency operating mode, and the dual-frequency operating mode in which the first center frequency and the second center frequency operate simultaneously.

[0013] Thirdly, embodiments of the present invention provide a computer device, including a memory and a processor, wherein the memory stores a computer program, and the computer program, when executed by the processor, implements any step of the frequency reconfigurable filter power divider design method as described in the first aspect of the present invention.

[0014] Fourthly, embodiments of the present invention provide a computer-readable storage medium having a computer program stored thereon, wherein: when the computer program is executed by a processor, it implements any step of the frequency reconfigurable filter power divider design method as described in the first aspect of the present invention.

[0015] The beneficial effects of this invention are as follows: This invention utilizes a simple topology combining a Y-junction power divider with a hairpin bandpass filter and PIN diode switches to achieve deep integration of power distribution, frequency selection, and frequency reconfigurability in a single circuit. Compared to traditional solutions requiring multiple independent links, this significantly reduces the number of RF front-end components. Through the independent on / off combination of two PIN diode switches under external DC high / low level control, it can freely switch between three modes—single-frequency operation at the first center frequency, single-frequency operation at the second center frequency, and simultaneous dual-frequency operation—in a simple and reliable control method, avoiding the stringent requirements of existing varactor diode solutions on precision analog bias circuits. The hairpin bandpass filters in each branch not only perform frequency selection filtering and out-of-band clutter suppression in their respective passbands but also provide natural out-of-band suppression for signals in the corresponding frequency band of another branch to prevent inter-channel crosstalk. Their inherent DC isolation function can also block the return of the bias voltage of this branch. The current flows to another branch, ensuring that the switching states of the two diodes are independent and controllable and do not interfere with each other; the isolation resistor connected across the Y-junction can absorb the reflected signal energy to maintain good isolation between the output ports when the port impedance is mismatched, thus comprehensively ensuring the performance of the device from two aspects: crosstalk suppression between branches and reflection isolation between ports; the overall circuit adopts a microstrip transmission line structure and is laid out on the same dielectric substrate, and the bent layout of the hairpin resonator further compresses the circuit area, which has the advantages of compact structure, easy processing, good consistency and low cost. Moreover, by adjusting the structural parameters of the hairpin bandpass filter, it can be adapted to any two preset different operating frequency bands, with strong adaptability. It can be widely used in RF front-end systems such as multi-band wireless communication base stations, dual-band WLAN devices, phased array radar T / R components and software-defined radios. While ensuring excellent RF performance, it greatly reduces system complexity and manufacturing costs, and has strong engineering practical value. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a flowchart illustrating the implementation of the present invention in Example 1.

[0017] Figure 2This is a dynamic adjustment diagram of the present invention in Example 1. Detailed Implementation

[0018] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0019] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0020] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0021] Example 1 Reference Figure 1 and Figure 2 This is the first embodiment of the present invention, which provides a design method for a frequency reconfigurable filter power divider, including the following steps: S1: Provides a Y-junction power divider structure, which has one signal input port and two signal output ports.

[0022] Specifically, the Y-junction power divider structure is a Wilkinson power divider structure based on microstrip transmission lines. This structure is entirely disposed on the upper surface of a dielectric substrate, and the required microstrip line pattern is formed using standard printed circuit board manufacturing processes such as photolithography and etching. The signal input port and two signal output ports are respectively located at three different edges of the dielectric substrate. The signal input port is located on one edge of the dielectric substrate, and the two signal output ports are located on the opposite edge of the dielectric substrate. The arrangement of the three ensures that the transmission path length from the signal input port to the two signal output ports is equal, thereby ensuring that the two output signals have the same phase. The signal input port and two signal output ports are all set to 50-ohm standard impedance ports to achieve good impedance matching with external 50-ohm RF systems and minimize signal reflection and power loss. The ports are equipped with pads or microstrip line end structures to facilitate connection with external coaxial connectors or RF probes.

[0023] Furthermore, when the Y-junction power divider structure adopts an equal power distribution design, the two branch microstrip lines extending from the Y-junction to the two signal output ports have the same characteristic impedance and the same electrical length to ensure that the two output signals are of equal amplitude and in phase. The characteristic impedance of the two branch microstrip lines is designed to be √2 times the impedance of the signal input port. That is, when the signal input port is fifty ohms, the characteristic impedance of the two branch microstrip lines is seventy-seven ohms. The electrical length of the two branch microstrip lines is set to one-quarter wavelength at the corresponding operating frequency. The specific value of a quarter wavelength is related to the dielectric constant of the selected substrate and the operating frequency. In actual design, the physical length of a quarter wavelength is determined based on the actual dielectric constant of the substrate and the center frequency of the required operating band. When using an unequal power distribution design, the characteristic impedances of the two branch microstrip lines are determined according to the required power distribution ratio. For example, when the output power of one line is required to be twice that of the other, the impedances of the two branch microstrip lines are designed with different characteristic impedance values, and impedance matching with the input and output ports is achieved through a quarter-wavelength impedance transformation segment.

[0024] Specifically, the Y-shaped node is the intersection area of ​​the input microstrip line and the two branch microstrip lines. This intersection area is geometrically Y-shaped. The input microstrip line extends from one side to the intersection point, and the two branch microstrip lines extend from the intersection point in two different directions. After the radio frequency signal is transmitted from the signal input port to the Y-shaped node via the input microstrip line, it is divided into two paths at the node or proportionally distributed into two paths, which are then transmitted to the two signal output ports along the two branch microstrip lines respectively. The geometry and size of the Y-shaped node are optimized to minimize signal reflection and discontinuity effects at the node. In practical design, the Y-shaped node can be replaced with a rounded or oblique transition instead of a right-angle turn to reduce the parasitic effects and additional losses caused by the discontinuity of the microstrip line.

[0025] Furthermore, the dielectric substrate is selected from high-frequency circuit dielectric substrate materials, including but not limited to polytetrafluoroethylene glass fiber cloth copper-clad laminate, ceramic-filled polytetrafluoroethylene copper-clad laminate or liquid crystal polymer copper-clad laminate. The relative permittivity of the dielectric substrate is selected in the range of 2.2 to 10.2, and the dielectric thickness is selected in the range of 0.2 mm to 2.0 mm. The linewidth of the input microstrip line and the two branch microstrip lines is determined by impedance calculation tools or impedance calculation formulas based on the dielectric constant, dielectric thickness and required characteristic impedance of the selected substrate. In actual design, when a 50-ohm characteristic impedance is required, the linewidth decreases as the dielectric constant of the substrate increases and increases as the substrate thickness increases. The lengths of the input microstrip line and the two branch microstrip lines are determined based on the phase requirements of the signal transmission path and the spatial constraints of the circuit layout. Under the condition that the electrical lengths from the signal input port to the two signal output ports are equal, the actual physical lengths of each microstrip line segment can be adjusted by bending or detouring according to the board space.

[0026] For example, taking the design of a WLAN access point device operating in both 2.4GHz and 5.2GHz dual-band RF front-end circuit as an example, a Rogers RO4350B high-frequency dielectric substrate is selected. This substrate has a relative permittivity of 3.48 and a dielectric thickness of 0.508mm, with the overall circuit size controlled within 25mm × 30mm. A Y-junction Wilkinson power divider structure with equal power distribution is adopted. The signal input port and two signal output ports are all set to a standard impedance of 50Ω. The input port is located on the left edge of the dielectric substrate, and the two output ports are located on the right edge of the dielectric substrate and are symmetrically distributed. Based on the dielectric constant and thickness of the dielectric substrate, impedance calculation tools show that the linewidth of a 50Ω microstrip line is approximately 1.12mm, and the linewidth of a 70.7Ω microstrip line is approximately 0.62mm. Using the intermediate frequency of 3.6GHz between 2.4GHz and 5.2GHz as... Based on the quarter-wavelength design benchmark, the physical length of a quarter-wavelength on the RO4350B substrate is approximately 11.8 mm. However, in order to achieve good power divider performance in both the 2.4 GHz and 5.2 GHz frequency bands, the lengths of the two branch microstrip lines were optimized and adjusted using electromagnetic simulation software in the actual design. The final branch line length was determined to be 12.5 mm, ensuring that the return loss of the power divider is better than 15 dB in both target frequency bands. The Y-shaped node adopts an arc transition design with an arc radius of 1.5 mm to reduce signal reflection and discontinuity effects at the node. Both the input and output ports are equipped with gold-plated pads for easy soldering to SMA connectors, with a pad size of 2.5 mm × 2.5 mm.

[0027] S2: A first branch is set between the first output port and the first signal output terminal. The first branch includes a first hairpin bandpass filter and a first diode switch connected in series. The operating frequency of the first hairpin bandpass filter is the first center frequency.

[0028] Specifically, the first hairpin-type bandpass filter is a microstrip bandpass filter that adopts a hairpin-type resonator structure. The hairpin-type resonator is a half-wavelength resonator formed by bending a microstrip line into a U-shape or hairpin shape. That is, the total transmission line length of each hairpin-type resonator is about half of the waveguide wavelength corresponding to the first center frequency. Multiple hairpin resonators are arranged side by side, and energy is transferred step by step between adjacent resonators through electromagnetic field coupling, thereby forming a bandpass filter response; The input terminal of the hairpin bandpass filter is connected to the first output port of the Y-junction power divider structure, and the output terminal is connected to one end of the first diode switch. The center frequency of the passband of the hairpin bandpass filter is designed to be the first center frequency. The U-shaped structure of the hairpin resonator effectively compresses the physical length of the resonator within the plane of the dielectric substrate. Compared with the linear half-wavelength resonator, the hairpin structure occupies a smaller circuit area, which is beneficial to the miniaturization of the overall circuit. The opening direction and specific dimensions of the U-shaped bend of the hairpin resonator are designed according to the required operating frequency and coupling requirements.

[0029] Furthermore, the order of the first hairpin bandpass filter is determined based on the required out-of-band suppression performance. The order refers to the number of hairpin resonators in a filter. The higher the order, the better the frequency selectivity of the filter, the deeper the out-of-band rejection, and the steeper the transition band. However, the insertion loss will also increase accordingly, and the circuit area will also increase. In practical design, the appropriate order needs to be selected based on the system's comprehensive requirements for out-of-band suppression and insertion loss. Generally speaking, for applications that need to suppress interference in adjacent frequency bands, a third- or fourth-order hairpin bandpass filter can be selected to obtain out-of-band suppression better than 20 to 35 dB. For scenarios with higher out-of-band suppression requirements, a fifth- or higher order design can be selected. The coupling spacing between two adjacent hairpin resonators is a key parameter that determines the bandwidth of the filter. The smaller the coupling spacing, the stronger the coupling between the resonators and the wider the passband of the filter; conversely, the larger the coupling spacing, the weaker the coupling and the narrower the passband. The coupling spacing between adjacent resonators is determined by the required coupling coefficient. The specific value of the coupling coefficient is determined by the passband width and order of the filter. The coupling coefficient values ​​under different spacings can be accurately extracted using electromagnetic field simulation tools. The coupling strength between the first hairpin resonator and the input feed line, and the coupling strength between the last hairpin resonator and the output feed line, are determined by the input coupling spacing and the output coupling spacing, respectively. These two coupling spacings also affect the passband response characteristics of the filter, especially the flatness of the return loss and insertion loss in the passband. In addition to parallel coupling arranged side by side, hairpin resonators can also be coupled in different configurations, such as vertical or staggered arrangements, to achieve different coupling strengths and filtering characteristics.

[0030] Specifically, the first diode switch is connected in series between the first hairpin bandpass filter and the first signal output terminal; In the microstrip transmission line of the first branch, starting from the first output port of the Y-junction power divider structure, the first hairpin bandpass filter and the first diode switch are set in sequence, and then the first signal output terminal is reached. The anode of the first diode switch is connected to the output terminal of the first hairpin bandpass filter through the microstrip line or the pad, and the cathode of the first diode switch is connected to the first signal output terminal through the microstrip line or the pad. This series connection method makes the first diode switch the on / off control element of the first branch: when the diode is on, it is equivalent to a small resistor (usually a few ohms), and the radio frequency signal can pass through smoothly; when the diode is off, it is equivalent to a large capacitor (usually a few tenths of a picofarad) in parallel with a large resistor, and the radio frequency signal is blocked and cannot pass through. In order to reduce the insertion loss when the diode is on, a diode with a small on-resistance should be selected; in order to enhance the isolation when the diode is off, a diode with a small junction capacitance should be selected. The type and model of the first diode switch are selected according to the requirements of operating frequency, power capacity and switching speed. In the first branch, DC blocking capacitors can be set before and after the first diode switch to prevent DC bias voltage from being transmitted along the radio frequency signal path to the Y-junction power divider structure or the external circuit of the first signal output terminal.

[0031] Furthermore, the control terminal of the first diode switch is connected to an external DC bias power supply through a first bias feed network; the core function of the first bias feed network is to apply the DC bias voltage to the control terminal of the diode switch, while preventing the radio frequency signal from leaking through the DC bias path. The first bias power supply network includes a first choke inductor and a first DC blocking capacitor. One end of the first choke inductor is connected to the connection node between the control terminal of the first diode switch and the first branch microstrip transmission line, and the other end is connected to the first DC bias terminal. The choke inductor has low impedance (approximately short circuit) to DC signals and high impedance (approximately open circuit) to RF signals. Therefore, the DC bias voltage can be smoothly applied to the control terminal of the diode switch through the choke inductor, while the RF signal is blocked by the choke inductor and cannot enter the DC bias circuit. The inductance value of the first choke inductor should be selected to provide sufficiently high inductive reactance to the radio frequency signal throughout the entire operating frequency band of interest. Typically, the inductive reactance value is required to be greater than 500 ohms at the operating frequency. The first DC blocking capacitor is connected in series in the microstrip transmission line of the first branch. It is usually placed between the first diode switch and the first hairpin bandpass filter, or between the first diode switch and the first signal output terminal. The DC blocking capacitor presents a low impedance approximate short circuit to the radio frequency signal and a high impedance approximate open circuit to the DC signal. Therefore, the radio frequency signal can be transmitted smoothly through the DC blocking capacitor, while the DC bias voltage is blocked by the DC blocking capacitor and will not flow to other circuit parts along the radio frequency signal path. By using a choke inductor and a DC blocking capacitor together, the DC bias voltage and the radio frequency signal are isolated from each other, ensuring that the bias state of the diode switch is stable and controllable and is not affected by the radio frequency signal. At the same time, it also ensures that the transmission of the radio frequency signal is not affected by the DC bias circuit.

[0032] For example, continuing the design example of the RF front-end of the WLAN access point device, a third-order Chebyshev hairpin bandpass filter with an operating frequency of 2.4GHz is set in the first branch. Each hairpin resonator is a microstrip line bent into a U-shape. On the RO4350B substrate, the guided wavelength corresponding to 2.4GHz is approximately 82mm, and the half-wavelength is approximately 41mm. The total microstrip line length of each hairpin resonator is 41mm, and the actual substrate area occupied after bending into a U-shape is approximately 8mm × 6mm. The three hairpin resonators are arranged side by side. The coupling spacing between adjacent resonators is calculated based on the Chebyshev low-pass prototype parameters and 5% fractional bandwidth, and then extracted and determined by electromagnetic simulation software, and is 0.35mm and 0.38mm respectively. The input and output tap positions are set about 2mm below the center of the first and last resonators to obtain 50Ω port matching. Simulation results show that the filter has a good insertion frequency at the 2.4GHz center frequency. The input loss is approximately 1.8dB, the in-band return loss is 16dB, and the out-of-band rejection at 5.2GHz is better than 35dB. The first diode switch is a Skyworks SMP1320-079LF silicon-based PIN diode, which has an on-resistance of 1.5Ω under a 10mA forward bias current and a junction capacitance of 0.25pF under a 20V reverse bias voltage. It is connected in series between the output of the hairpin bandpass filter and the first signal output. The first choke inductor is a 47nH wire-wound RF inductor with inductive reactances of 708Ω and 1535Ω at 2.4GHz and 5.2GHz, respectively. The first DC blocking capacitor is a 100pF RF ceramic capacitor with capacitive reactances of 0.66Ω and 0.31Ω at 2.4GHz and 5.2GHz, respectively. All components are surface-mounted to the corresponding pads on the dielectric substrate. The overall area occupied by the first branch is approximately 18mm × 10mm.

[0033] S3: A second branch is set between the second output port and the second signal output terminal. The second branch includes a second hairpin bandpass filter and a second diode switch connected in series. The operating frequency of the second hairpin bandpass filter is the second center frequency.

[0034] Specifically, the first center frequency and the second center frequency correspond to two different frequency bands in the wireless communication spectrum. By selecting a first hairpin bandpass filter and a second hairpin bandpass filter with different structural parameters, the power divider can be adapted to any two preset different operating frequency bands to achieve cross-band frequency reconstruction.

[0035] Furthermore, the first hairpin-type bandpass filter is used to perform bandpass filtering on the signal transmitted in the first branch, allowing the passband signal in the first center frequency operating mode to pass through and suppressing out-of-band clutter signals that deviate from the first center frequency, and forming out-of-band suppression on the signal in the corresponding frequency band of the second branch to prevent it from crosstalking to the first branch. The second hairpin-type bandpass filter is used to perform bandpass filtering on the signal transmitted in the second branch, allowing the passband signal in the second center frequency operating mode to pass through and suppressing out-of-band clutter signals that deviate from the second center frequency, and forming out-of-band suppression on the signal in the corresponding frequency band of the first branch to prevent it from crosstalking to the second branch. The first and second hairpin bandpass filters each have DC isolation functions, which are used to block the DC bias voltage of this branch from flowing back to the other branch, so as to avoid the DC bias voltage from interfering with the working state of the diode switch in the other branch.

[0036] Specifically, the second hairpin bandpass filter also adopts a hairpin resonator structure. Its construction and working principle are the same as those of the first hairpin bandpass filter. The only difference is that its operating frequency is designed to be the second center frequency. The total transmission line length of each hairpin resonator is approximately half the wavelength of the guided wave corresponding to the second center frequency. Multiple hairpin resonators are arranged side by side, and adjacent resonators are coupled by electromagnetic fields to form a bandpass filter response. The input of the second hairpin bandpass filter is connected to the second output port of the Y-junction power divider structure, and the output is connected to one end of the second diode switch. The U-shaped structure of the hairpin resonator also achieves effective compression of the circuit area. The order, resonator size, and coupling spacing of the second hairpin bandpass filter are all designed based on the second center frequency and the required filtering performance indicators. Similar to the first hairpin bandpass filter, the higher the order of the second hairpin bandpass filter, the better the out-of-band rejection performance, but the greater the insertion loss. The specific order selection also needs to be balanced between out-of-band rejection and insertion loss.

[0037] Furthermore, the order of the second hairpin bandpass filter is determined based on the system's requirements for out-of-band suppression performance; for applications that require suppression of interference in adjacent frequency bands, the same or different order as the first hairpin bandpass filter can be selected. The fractional bandwidth of the second hairpin bandpass filter is determined based on the system's signal bandwidth requirements. The narrower the fractional bandwidth, the better the frequency selectivity, but the group delay ripple within the passband may increase; the wider the fractional bandwidth, the smaller the waveform distortion when the signal passes through, but the ability to suppress out-of-band interference decreases. In practical design, the fractional bandwidth is usually selected between three percent and ten percent. The coupling spacing between adjacent hairpin resonators is determined according to the required coupling coefficient. The precise value of the coupling spacing is obtained by electromagnetic field simulation. When a wide passband and good out-of-band rejection are required simultaneously, an asymmetrical distribution of coupling strength between different resonators can be adopted, that is, the coupling coefficients of adjacent resonator pairs are not exactly the same. This design can optimize the passband response and out-of-band rejection characteristics of the filter. In addition, the input and output feeder positions (i.e., tap positions) of the first and second hairpin bandpass filters are also important parameters affecting the impedance matching of the filter's input and output ports. The selection of tap positions needs to take into account other performance indicators of the filter while obtaining good port matching. In practical design, by adjusting the tap positions of the hairpin resonators, the input and output port impedances of the filter can be matched to fifty ohms, which facilitates direct cascading with the preceding and following circuits. The mechanism by which the first hairpin bandpass filter suppresses out-of-band signals in the corresponding frequency band of the second branch is as follows: the second center frequency is located in the stopband of the first hairpin bandpass filter, outside the passband. When the second center frequency signal transmitted in the second branch leaks to the first branch through the limited isolation of the Y-shaped node or through spatial electromagnetic coupling, the first hairpin bandpass filter, due to its bandpass filtering characteristics, presents high impedance and strong attenuation to the second center frequency signal in the stopband, preventing the signal from reaching the first signal output terminal through the first hairpin bandpass filter, thus preventing crosstalk of the second branch signal to the first output port. Similarly, when the first center frequency is located in the stopband of the second hairpin bandpass filter, and the first center frequency signal in the first branch leaks to the second branch, the second hairpin bandpass filter also presents high impedance and strong attenuation to it, preventing the signal from reaching the second signal output terminal. This design, which utilizes the out-of-band rejection characteristics of the filter itself to achieve signal isolation between branches, does not require additional isolation components, fully utilizes the inherent characteristics of the filter, and simplifies the circuit structure. The first and second hairpin bandpass filters each have DC isolation capabilities. This capability stems from the structural characteristics of the hairpin resonator itself: the hairpin resonator is an open resonant structure composed of microstrip lines. There is no direct physical electrical connection between its input end (i.e., the coupling gap between the hairpin resonator and the previous resonator or feeder) and its output end (i.e., the coupling gap between the hairpin resonator and the next resonator or feeder). Instead, signal transmission is achieved through electromagnetic field coupling. Radio frequency signals are coupled and transmitted between resonators through electromagnetic fields, while DC signals cannot cross the gap between resonators through electromagnetic coupling. Therefore, DC bias voltage cannot be transmitted from one port to another through a hairpin bandpass filter. This natural DC isolation characteristic blocks the possibility of DC bias voltage in one branch flowing back to the other branch through the Y-junction or through a spatial path, ensuring that the bias states of the diode switches in the two branches are independent of each other and will not cause malfunction of the diode switches due to crosstalk of DC bias.

[0038] Specifically, the second diode switch is connected in series between the second hairpin bandpass filter and the second signal output terminal; in the microstrip transmission line of the second branch, starting from the second output port of the Y-junction power divider structure, the second hairpin bandpass filter and the second diode switch are set in sequence, and then reach the second signal output terminal; The anode of the second diode switch is connected to the output terminal of the second hairpin bandpass filter through a microstrip line or a pad, and the cathode of the second diode switch is connected to the second signal output terminal through a microstrip line or a pad. The second diode switch serves as the on / off control element of the second branch. When it is turned on, the branch is connected, and when it is turned off, the branch is disconnected. The type and model of the second diode switch are also selected according to the requirements of operating frequency, power capacity and switching speed; a DC blocking capacitor is also provided in the second branch to prevent DC bias voltage from being transmitted along the radio frequency signal path.

[0039] Furthermore, the control terminal of the second diode switch is connected to an external DC bias power supply through a second bias feed network; the second bias feed network includes a second choke inductor and a second DC blocking capacitor, and its working principle and function are exactly the same as those of the first bias feed network. One end of the second choke inductor is connected to the connection node between the control terminal of the second diode switch and the second branch microstrip transmission line, and the other end is connected to the second DC bias terminal, which is used to apply the DC bias voltage to the diode control terminal while preventing the radio frequency signal from entering the DC bias circuit. The second DC blocking capacitor is connected in series in the microstrip transmission line of the second branch to prevent the DC bias voltage from propagating along the RF signal path; through the cooperation of the second choke inductor and the second DC blocking capacitor, the DC bias and RF signal in the second branch are mutually isolated.

[0040] For example, continuing the design example above, a third-order Chebyshev hairpin bandpass filter with an operating frequency of 5.2 GHz is set in the second branch, also implemented on an RO4350B substrate; the guided wavelength corresponding to 5.2 GHz is approximately 38 mm, and the half-wavelength is approximately 19 mm. The total microstrip line length of each hairpin resonator is 19 mm, and after being bent into a U-shape, it occupies an area of ​​approximately 5 mm × 4 mm, which is significantly smaller than the size of the 2.4 GHz filter; the three resonators are arranged side by side, with adjacent coupling spacings of 0.20 mm and 0.22 mm, respectively, and the input and output tap positions are set approximately 1.2 mm below the center of the resonators; simulation results show that the insertion loss of this 5.2 GHz filter at the center frequency is approximately 1.5 dB, and the in-band return loss is 17 dB, which is significantly lower than that at 2.4 GHz. The out-of-band rejection at point z is better than 40dB; the second diode switch uses the same SMP1320-079LF PIN diode as the first branch, connected in series between the output of the 5.2GHz hairpin bandpass filter and the second signal output. Since the hairpin filter does not have a DC conduction path, the DC bias voltage in the first branch operating at 2.4GHz will not flow back to the second branch through the Y-junction, and the DC bias voltage in the second branch operating at 5.2GHz will also not flow back to the first branch. This ensures that when only single-frequency operation is required, the diode switch in the unbiased branch will not be falsely triggered by the bias voltage of the other branch; the second choke inductor and the second DC blocking capacitor are the same 47nH inductor and 100pF capacitor as the first branch, respectively, to simplify the bill of materials.

[0041] S4: Connect the isolation resistor between the first branch and the second branch.

[0042] Specifically, the isolation resistor is connected across the Y-shaped junction between the first and second branches. When the port impedances of the first and second signal output terminals are mismatched, the signal energy reflected back by the impedance mismatch is dissipated and absorbed as heat through the isolation resistor, thereby maintaining the isolation between the two output ports of the Y-shaped junction power divider structure, suppressing signal crosstalk between the output ports, and ensuring that the isolation performance between the output ports meets the preset indicators in various operating modes.

[0043] Furthermore, the Y-junction power divider structure, the first branch, the second branch, and the isolation resistor are implemented using a microstrip transmission line structure. The entire circuit is laid out on the upper surface of the same dielectric substrate, and the lower surface of the dielectric substrate is a grounded metal layer. The first hairpin bandpass filter and the second hairpin bandpass filter are both composed of hairpin resonator structures formed by bending microstrip lines. The linewidth, line length, bending spacing, and coupling gap of the microstrip transmission line are determined according to the preset port impedance and the required operating frequency. The first diode switch and the second diode switch are connected in series in the microstrip transmission lines of the first branch and the second branch, respectively. Their control terminals are led out to the bias pads on the surface of the dielectric substrate through metallized vias or bonding leads for connecting to an external DC bias power supply.

[0044] Specifically, the isolation resistor is connected between the first branch and the second branch, specifically on the transmission line segment between the two output ports of the Y-junction power divider structure and their respective hairpin bandpass filters; In other words, after the Y-shaped node, at the microstrip line node before the first hairpin bandpass filter in the first branch and at the microstrip line node before the second hairpin bandpass filter in the second branch, an isolation resistor is connected across the microstrip line node. In the circuit layout, one end of the isolation resistor is connected to the first node in the first branch through a pad and a microstrip line, and the other end is connected to the second node in the second branch through a pad and a microstrip line. The first node is located between the first output port of the Y-junction power divider structure and the first hairpin bandpass filter, and the second node is located between the second output port of the Y-junction power divider structure and the second hairpin bandpass filter. The physical location of the isolation resistor on the circuit board is usually close to the Y-junction, bridging the two branch microstrip lines with the shortest distance, reducing the parasitic inductance and parasitic capacitance effects caused by excessively long connection leads.

[0045] Furthermore, the value of the isolation resistor is determined based on the port impedance of the Y-junction power divider structure; in a standard equal power distribution Wilkinson power divider, when the characteristic impedance of all ports is fifty ohms, the standard value of the isolation resistor connected between the two output ports is one hundred ohms. The selection of this resistance value ensures that when both output ports are matched to fifty ohms, there is no potential difference across the isolation resistor, and no power is consumed; when impedance mismatch occurs at either output port, the reflected signal forms a potential difference across the isolation resistor, and the reflected energy is dissipated by the resistor. For power dividers with unequal power distribution, the value of the isolation resistor needs to be adjusted according to the characteristic impedance of the two branch microstrip lines so that the isolation resistor can effectively absorb the reflected signal energy under various operating conditions. The resistance accuracy of the isolation resistor is usually required to be ±1% or ±5% to ensure the consistency of isolation performance. The power capacity of the isolation resistor is selected based on the maximum input power of the power divider and the maximum possible reflected power. In conventional applications, a surface-mount resistor with a rated power of one-eighth watt or one-quarter watt is sufficient. In applications that require higher input power, a resistor with a rated power of one-half watt or higher can be selected.

[0046] Specifically, when the external loads at both the first and second signal output terminals are standard impedances, the Y-junction power divider structure is in an ideal matching state. In this case, the signals transmitted on the two branch microstrip lines have the same amplitude and phase at the Y-junction. The potential difference between the two output ports of the Y-junction is zero. Therefore, there is no voltage difference across the isolation resistor connected between the two output ports, and no current flows through the resistor. The isolation resistor does not consume any RF power, and the signal is distributed from the input port to the two output ports with minimal loss.

[0047] Furthermore, when the external load at the first signal output terminal or the second signal output terminal deviates from the standard impedance, the Y-junction power divider structure is in a mismatched state. In the mismatched state, the signal reflected from the mismatched port is transmitted in reverse along the branch microstrip line where the port is located to the Y-junction, and interacts with the signal of the other branch at the Y-junction. The signal amplitude and / or phase of the two branch microstrip lines at the Y-shaped node are no longer completely consistent, a potential difference is generated across the isolation resistor, and the energy of the reflected signal is dissipated and absorbed in the form of Joule heat through the isolation resistor. In this way, the isolation resistor prevents reflected signals from interfering with each other from one output port to another, thus maintaining the isolation between the two output ports. The quality of port isolation directly affects the performance of the power divider: the higher the isolation, the less mutual interference between the two outputs, and the better the independence and integrity of the signals. In the Wilkinson power divider structure, the introduction of isolation resistors increases the isolation between ports from a few decibels to more than twenty decibels without isolation resistors. The ability of isolation resistors to absorb reflected signals is closely related to the accuracy of the resistor value, the high-frequency parasitic parameters of the resistors, and the physical layout of the resistors in the circuit.

[0048] For example, continuing the design example above, an isolation resistor is connected across the transmission line segment after the Y-junction and before the two hairpin bandpass filters; a 100Ω±1% thick film chip resistor is connected between the microstrip line node approximately 2mm from the Y-junction in the first branch and the microstrip line node approximately 2mm from the Y-junction in the second branch. The resistor has a 0603 package size and a rated power of 1 / 8W. The physical location of this resistor on the circuit board is approximately 2mm to the right of the Y-junction, bridging the two branch microstrip lines. When both output ports are connected to a 50Ω load, there is no potential difference across the isolation resistor, and it consumes no power; when one output port is open-circuited, the... The signal reflected from the port is dissipated as heat through the isolation resistor, maintaining port isolation above 12dB. In actual use cases of WLAN access points, the two output ports may be connected to the feed lines of two antennas, 2.4GHz and 5.2GHz, respectively. Since the impedance of the antennas may have slight deviations at different frequency bands, the isolation resistor ensures that even if the antenna of one frequency band has a certain degree of impedance mismatch, the reflected signal will not interfere with the output port of the other frequency band, thus ensuring that the signals of the two frequency bands are output independently and stably. In the circuit layout, the ground pad of the isolation resistor is directly connected to the microstrip line node, and the connection is achieved through the shortest possible lead to reduce parasitic effects.

[0049] S5: Apply a first DC bias voltage and a second DC bias voltage to the control terminals of the first diode switch and the second diode switch respectively, and independently control the conduction or cutoff of the first diode switch and the second diode switch.

[0050] Specifically, the first DC bias voltage is provided by an external DC power supply and is connected to the first DC bias terminal through wires or bias lines on the printed circuit board. The first DC bias terminal is the port or pad of the first choke inductor connected to the external DC power supply. When the external DC power supply outputs a positive voltage to the first DC bias terminal, the positive voltage is applied to the control terminal of the first diode switch through the first choke inductor, so that the first diode switch is in a positive bias state. When the amplitude of the first DC bias voltage exceeds the conduction threshold voltage of the first diode switch, the first diode switch is turned on. When the first DC bias terminal is floating or zero volt voltage is applied, the first diode switch has no forward bias current and is in the off state. When a reverse voltage is applied to the first DC bias terminal, the first diode switch is in the reverse bias state, which is also the off state. Reverse bias can reduce the diode junction capacitance and improve the isolation in the off state.

[0051] Furthermore, the turn-on threshold voltage of the first diode switch depends on the semiconductor material used. For silicon-based PIN diodes, since the band gap of silicon material is about 1.12 electron volts, the turn-on threshold voltage of its PN junction is about 0.7 volts. That is, when the forward bias voltage reaches or exceeds 0.7 volts, the PIN diode starts to conduct and forms a large forward current. For gallium arsenide-based PIN diodes, since the bandgap of gallium arsenide material is approximately 1.43 electron volts, its turn-on threshold voltage is approximately 0.8 to 1.0 volts. To ensure reliable diode conduction, in practical applications, a bias voltage much higher than the turn-on threshold voltage is usually applied, such as a DC voltage of +3 volts, +5 volts, or higher, to obtain a sufficiently large forward bias current and minimize the diode's on-resistance. The effective level of the first DC bias voltage refers to the voltage range that enables the first diode switch to reliably conduct, typically a forward voltage greater than or equal to 0.7 volts. The ineffective level refers to the voltage range that enables the first diode switch to reliably turn off, including zero volts, floating state, and negative voltage. The first choke inductor plays the role of isolating DC in the bias feed network; the inductor presents extremely low impedance to DC signals, so the DC bias voltage can be smoothly transmitted from the bias terminal to the diode control terminal through the choke inductor. The inductive reactance of an inductor to a radio frequency signal is proportional to the signal frequency. The higher the frequency, the greater the reactance. At the first center frequency and the second center frequency, the reactance of the first choke inductor should be much greater than the characteristic impedance of the first branch (fifty ohms). Typically, the reactance value is required to reach more than five hundred ohms to ensure that most of the radio frequency signal will not leak to the DC bias circuit through the choke inductor. The inductive reactance is proportional to the product of the inductance and the frequency. Therefore, at higher frequencies, a smaller inductance can provide sufficient inductive reactance; while at lower frequencies, a larger inductance is required to achieve the same inductive reactance requirement. In practical design, it is necessary to take into account the requirements of different operating frequencies on the inductive reactance of the choke inductor and select an inductance value that can provide sufficient inductive reactance in all operating frequency bands. The first DC blocking capacitor in the bias feed network plays the role of passing AC signals and blocking DC signals. The capacitive reactance of the capacitor to the radio frequency signal is inversely proportional to the signal frequency; the higher the frequency, the lower the capacitive reactance. At the first center frequency and the second center frequency, the capacitive reactance of the first DC blocking capacitor should be much smaller than the characteristic impedance of the first branch (fifty ohms). Typically, the capacitive reactance value is required to be less than five ohms to ensure that the radio frequency signal can pass smoothly through the DC blocking capacitor without generating significant insertion loss. The capacitive reactance value is inversely proportional to the product of the capacitance value and the frequency. Therefore, at higher frequencies, a smaller capacitance value can provide a sufficiently small capacitive reactance; while at lower frequencies, a larger capacitance value is required to achieve the same capacitive reactance requirement. In practical design, it is necessary to select a capacitor value that can provide sufficiently small capacitive reactance in all operating frequency bands. The DC blocking capacitor presents extremely high impedance to DC signals. Therefore, the DC bias voltage is blocked by the DC blocking capacitor and will not propagate along the RF signal path to the hairpin bandpass filter or output port, nor will it interfere with the diode switch of the other branch.

[0052] Specifically, the second DC bias voltage is applied to the control terminal of the second diode switch by an external DC power supply through the second DC bias terminal and the second choke inductor; when the external DC power supply outputs a positive voltage to the second DC bias terminal, the positive voltage is applied to the second diode switch through the second choke inductor, so that the second diode switch is in a forward bias state. When the amplitude of the second DC bias voltage exceeds the conduction threshold voltage of the second diode switch, the second diode switch is turned on; when the second DC bias terminal is floating or zero volt voltage is applied, the second diode switch is turned off. The control method of the second DC bias voltage is exactly the same as that of the first DC bias voltage. The two can be controlled independently and do not affect each other.

[0053] Furthermore, the functions and parameter selection principles of the second choke inductor and the second DC blocking capacitor are exactly the same as those of the first choke inductor and the first DC blocking capacitor; the second choke inductor is used to isolate the radio frequency signal from the second DC bias circuit, and its inductance value is also required to provide sufficient inductive reactance at all operating frequencies; the second DC blocking capacitor is used to isolate the DC bias voltage from the radio frequency signal path of the second branch, and its capacitance value is also required to provide sufficiently small capacitive reactance at all operating frequencies. The choke inductors and DC blocking capacitors for the two branches can use the exact same component values ​​to simplify material management, or they can be optimized separately based on the differences in the operating frequencies of the different branches. When the first center frequency and the second center frequency differ significantly, the choke inductors and DC blocking capacitors for the two branches may need to be optimized separately: in the lower frequency 2.4 GHz branch, the choke inductor needs a larger inductance value to provide sufficient low-frequency inductive reactance; in the higher frequency 5.2 GHz branch, the choke inductor can use a slightly smaller inductance value to achieve sufficient inductive reactance. However, in engineering practice, to facilitate production and material procurement, the same component values ​​are usually selected as much as possible while meeting performance requirements.

[0054] For example, continuing the design example above, the first DC bias voltage and the second DC bias voltage are provided by two general-purpose input / output ports of the baseband processor in the WLAN access point device, respectively. Each port can independently output a DC voltage signal of 0V or 3.3V. The baseband processor controls the level state of the general-purpose input / output ports through software according to the current operating frequency band requirements. When it is necessary to operate independently in the 2.4GHz frequency band, the baseband processor controls the first general-purpose input / output port to output a 3.3V voltage to the first DC bias terminal, which is applied to the control terminal of the first PIN diode through the first choke inductor. The first PIN diode receives a forward bias current of about 10mA and turns on. At the same time, it controls the second general-purpose input / output port. The output is 0V to the second DC bias terminal, and the second PIN diode is cut off due to the lack of bias current. When it needs to work alone in the 5.2GHz band, the control method is reversed. When it needs to work simultaneously in both bands, both general purpose input / output ports output 3.3V, and both PIN diodes are turned on. Since 3.3V is much greater than the 0.7V turn-on threshold voltage of silicon-based PIN diodes, the diode on-resistance is stabilized at about 1.5Ω, resulting in low insertion loss and good consistency. A one-to-one software mapping relationship is established between the level state combination of the three general purpose input / output ports and the three working modes. The baseband processor switches the output level in real time according to the frequency band scheduling instructions of the communication protocol stack, without the need for additional digital-to-analog conversion or voltage regulation circuits.

[0055] S6: By controlling the combination of the on and off states of the first diode switch and the second diode switch, the operating frequency of the power divider can be switched between the first center frequency operating mode, the second center frequency operating mode, and the dual-frequency operating mode where the first center frequency and the second center frequency operate simultaneously.

[0056] Specifically, both the first diode switch and the second diode switch are PIN diodes. When forward biased, the PIN diode is equivalent to a low-impedance conduction state to connect the corresponding branch. When zero biased or reverse biased, it is equivalent to a high-impedance cutoff state to disconnect the corresponding branch. The on / off states of the first diode switch and the second diode switch combine to form four different switch state combinations. Three of the effective states correspond to three operating modes, and the remaining state is the fully off state.

[0057] Furthermore, by controlling the levels of the first DC bias voltage and the second DC bias voltage respectively, the first diode switch and the second diode switch can operate independently in the on or off state. When only the DC bias voltage corresponding to the first diode switch is at an effective level, the power divider operates in the first center frequency operating mode. When only the DC bias voltage corresponding to the second diode switch is at an effective level, the power divider operates in the second center frequency operating mode. When the DC bias voltages corresponding to the first diode switch and the second diode switch are both at an effective level, the power divider operates in dual-frequency mode. The switching between the three operating modes is uniquely determined by the combination of the levels of the external DC bias voltage.

[0058] Specifically, the on / off state of the first diode switch and the second diode switch is independently determined by the application of the external DC bias voltage. Each diode switch has two possible states: on and off. When the two switches are combined, a total of four different switch state combinations are formed. These four combinations are: the first diode is on and the second diode is off, the first diode is off and the second diode is on, the first diode is on and the second diode is on, and the first diode is off and the second diode is off. Each combination corresponds to a specific circuit connection state, which determines which branches the radio frequency signal can be transmitted to the output port. In practical applications, external controllers (such as microcontrollers, FPGAs, or dedicated bias control chips) select the appropriate switching state combinations and output the corresponding DC bias voltage according to the system's requirements for the operating frequency band.

[0059] Furthermore, among the above four combinations of switch states, three combinations are defined as effective working states, corresponding to the three working modes of the present invention respectively. Combination 1 (first diode on, second diode off) corresponds to the first center frequency operating mode. At this time, only the first branch is connected, and the power divider outputs a signal at the first center frequency. Combination 2 (first diode off, second diode on) corresponds to the second center frequency operating mode. At this time, only the second branch is connected, and the power divider outputs a signal at the second center frequency. Combination 3 (first diode on, second diode on) corresponds to dual-frequency operating mode. At this time, both branches are connected, and the power divider outputs signals of the first center frequency and the second center frequency simultaneously. Combination 4 (first diode cut off, second diode cut off) is a fully cut-off state. At this time, both branches are disconnected. Although the radio frequency signal enters the Y-junction power divider structure from the input port, it cannot reach the output port through either branch. The power divider has no radio frequency signal output. This state is not used in normal working scenarios and can be regarded as an idle or standby state.

[0060] Specifically, in the first center frequency operating mode, the first diode switch is turned on and the second diode switch is turned off; after the radio frequency signal is input from the signal input port, it is distributed to two branch directions at the Y-shaped node. The signal entering the first branch is transmitted along the first branch, and after passing through the first hairpin bandpass filter to filter out noise signals other than the first center frequency, it reaches the first signal output terminal through the first diode switch in the on state. The signal entering the second branch can also reach the second hairpin bandpass filter and the second diode switch, but because the second diode switch is in the off state, the signal is blocked by high impedance at the second diode switch and cannot continue to be transmitted to the second signal output terminal. The blocked signal undergoes total reflection at the second diode switch, reflecting back to the direction of the Y-junction. These reflected signals are absorbed at the Y-junction through the isolation resistor and will not interfere with the normal signal transmission of the first branch. Therefore, in the first center frequency operating mode, only the first signal output terminal has a signal output, and the frequency of the output signal is the first center frequency.

[0061] Furthermore, in the second center frequency operating mode, the first diode switch is off and the second diode switch is on; After the radio frequency signal is input from the signal input port, it is distributed to two branch directions at the Y-shaped node. The signal entering the second branch is transmitted along the second branch and is filtered by the second hairpin bandpass filter to remove noise signals other than the second center frequency. Then, it passes through the second diode switch in the on state and reaches the second signal output terminal. The signal entering the first branch is blocked by the high impedance at the first diode switch because the first diode switch is in the off state, and cannot continue to be transmitted to the first signal output terminal. The blocked signal undergoes total reflection at the first diode switch, is reflected back to the Y-junction direction and is absorbed by the isolation resistor. Therefore, in the second center frequency working mode, only the second signal output terminal has a signal output, and the frequency of the output signal is the second center frequency. Both the first diode switch and the second diode switch are turned on. After the radio frequency signal is input from the signal input port, it is simultaneously distributed to two branch directions at the Y-shaped node. The signal entering the first branch is filtered by the first hairpin bandpass filter and then passes through the turned-on first diode switch to reach the first signal output terminal, and the output frequency is the first center frequency. The signal entering the second branch is filtered by the second hairpin bandpass filter and then passes through the conducting second diode switch to reach the second signal output terminal, outputting a signal with the second center frequency. Because the first hairpin bandpass filter has a natural out-of-band suppression effect on the second center frequency signal, even if a small amount of the second center frequency signal in the second branch leaks into the first branch, it cannot reach the first signal output terminal through the first hairpin bandpass filter; similarly, the first center frequency signal in the first branch cannot reach the second signal output terminal through the second hairpin bandpass filter. This allows the two output signals to maintain good frequency purity and mutual isolation in dual-frequency operating mode; therefore, in dual-frequency operating mode, both signal output terminals have signal output, with the first signal output terminal outputting the first center frequency signal and the second signal output terminal outputting the second center frequency signal. The switching between the three operating modes is uniquely determined by the combination of the levels of the external DC bias voltage. That is, by simply changing the combination of the voltage levels of the two DC bias terminals, any switching between the three operating modes can be performed. The switching process only involves changing the level of the DC voltage and does not involve mechanical movement or complex reconfiguration. Therefore, the switching speed is fast, the reliability is high, and the lifespan is long. Since the level of the bias voltage can be precisely controlled by digital circuits, the switching between the three operating modes is deterministic and repeatable, and there are no intermediate ambiguous states. The external controller can realize mode switching through simple logic control based on the one-to-one correspondence between the operating mode and the DC bias voltage state, without the need for complex feedback or calibration processes.

[0062] Specifically, when using a PIN diode as a switching element, the switching speed of the PIN diode is mainly limited by the storage and recombination time of minority carriers in the PIN diode, i.e., the carrier lifetime. When a forward bias current passes through the PIN diode, a large number of minority carriers are injected into the intrinsic layer and stored therein. When the bias voltage is rapidly switched from forward to reverse, the minority carriers stored in the intrinsic layer need a certain amount of time to be removed or recombine. This time is the switching time of the PIN diode. Switching time is usually related to the thickness and doping concentration of the intrinsic layer of a PIN diode. A thinner intrinsic layer and a higher doping concentration can result in a shorter switching time. In practical applications, the switching time of a PIN diode is usually on the order of nanoseconds to microseconds. For high-frequency RF switching applications, PIN diodes with switching times ranging from tens to hundreds of nanoseconds are common. This means that the switching speed between the three operating modes can reach millions to tens of millions of times per second, which can meet the frequency switching speed requirements of most wireless communication systems.

[0063] Furthermore, in the fully cut-off state (i.e., both the first and second diode switches are cut off), both branches are disconnected. At this time, although the radio frequency signal injected from the signal input port can be transmitted to the Y-junction and propagate from the Y-junction to the two branch microstrip lines, when the signal reaches the diode switch in the cut-off state in each branch, it is blocked by the high impedance cut-off state of the diode switch and undergoes total reflection. The signal energy reflected back to the Y-junction is absorbed by the isolation resistor. Therefore, in the fully cut-off state, there is no radio frequency signal output at either signal output terminal. This state is equivalent to the standby or silent state of the power divider. When there is no signal to be transmitted, both diode switches can be placed in the cut-off state, so that the power divider is in a safe mode with low signal leakage.

[0064] For example, continuing the design example of the WLAN access point device described above, when the access point device operates in a communication scenario of a traditional terminal device that only supports the 2.4GHz frequency band, the baseband processor controls the first general-purpose input / output port to output 3.3V and the second general-purpose input / output port to output 0V. At this time, the first PIN diode is turned on and the second PIN diode is turned off, and the power divider operates in the first center frequency operating mode. After the radio frequency signal enters the Y-junction from the input port, it is distributed to two paths. The 2.4GHz signal entering the first branch is filtered by the first hairpin bandpass filter and then passes through the turned-on diode to reach the first output port, where it is output to the 2.4GHz antenna. The signal entering the second branch is blocked by the high impedance of the turned-off state at the second PIN diode and reflected back to the Y-junction. The reflected energy is absorbed by the 100Ω isolation resistor. When the access point device operates in a communication scenario of a terminal device that only supports the 5.2GHz frequency band... In normal communication scenarios, the controller switches to output 0V from the first general-purpose input / output port and 3.3V from the second general-purpose input / output port. The power divider operates in the second center frequency mode, with only the second output port outputting a 5.2GHz signal. When the access point device needs to simultaneously serve 2.4GHz and 5.2GHz dual-band terminals, both general-purpose input / output ports output 3.3V, both PIN diodes are turned on, and the power divider operates in dual-band mode. The first output port outputs a 2.4GHz signal, and the second output port outputs a 5.2GHz signal. The two signals achieve frequency selection and mutual isolation through hairpin bandpass filters in their respective branches. The switching between the three modes is completed by the baseband processor in microseconds according to real-time communication requirements. There is no mechanical action during the switching process, resulting in high reliability and meeting the needs of WLAN access point devices for flexible switching of operating frequency bands in different communication scenarios.

[0065] In summary, this invention utilizes a simple topology combining a Y-junction power divider with a hairpin bandpass filter and PIN diode switches to achieve a deep integration of power distribution, frequency selection, and frequency reconfigurability within a single circuit. Compared to traditional solutions requiring multiple independent links, this significantly reduces the number of RF front-end components. Through the independent on / off combination of two PIN diode switches under external DC high / low level control, it can freely switch between three modes—single-frequency operation at the first center frequency, single-frequency operation at the second center frequency, and simultaneous dual-frequency operation—in a simple and reliable control manner, avoiding the stringent requirements of existing varactor diode solutions on precision analog bias circuits. The hairpin bandpass filters in each branch not only perform frequency selection filtering and out-of-band clutter suppression in their respective passbands but also provide natural out-of-band suppression for signals in the corresponding frequency band of another branch to prevent inter-channel crosstalk. Their inherent DC isolation function also prevents the bias voltage of one branch from flowing back to another. The branch circuit ensures that the switching states of the two diodes are independent and controllable, and that they do not interfere with each other. The isolation resistor connected across the Y-junction can absorb the reflected signal energy to maintain good isolation between the output ports when the port impedance is mismatched. This comprehensively protects the device performance from two aspects: crosstalk suppression between branches and reflection isolation between ports. The overall circuit adopts a microstrip transmission line structure and is laid out on the same dielectric substrate. The bent layout of the hairpin resonator further compresses the circuit area, which has the advantages of compact structure, easy processing, good consistency and low cost. Moreover, by adjusting the structural parameters of the hairpin bandpass filter, it can be adapted to any two preset different operating frequency bands. It has strong adaptability and can be widely used in RF front-end systems such as multi-band wireless communication base stations, dual-band WLAN devices, phased array radar T / R components and software-defined radios. While ensuring excellent RF performance, it greatly reduces system complexity and manufacturing costs, and has strong engineering practical value.

[0066] Example 2, an embodiment of the present invention, provides a frequency reconfigurable filter power divider design system, including: a Y-junction power divider structure, the Y-junction power divider structure having one signal input port and two signal output ports, used to realize power distribution from one input signal to two output signals; a first branch, connected between one output port of the Y-junction power divider structure and a first signal output terminal, the first branch including a first hairpin bandpass filter and a first diode switch connected in series, the operating frequency of the first hairpin bandpass filter being a first center frequency; a second branch, connected between the other output port of the Y-junction power divider structure and a second signal output terminal, the second branch including a second hairpin bandpass filter and a second diode switch connected in series, the operating frequency of the second hairpin bandpass filter being a second center frequency. Center frequency; isolation resistor, connected between the first branch and the second branch; first DC bias terminal, connected to the control terminal of the first diode switch, used to receive the externally applied first DC bias voltage to independently control the conduction or cutoff of the first diode switch; second DC bias terminal, connected to the control terminal of the second diode switch, used to receive the externally applied second DC bias voltage to independently control the conduction or cutoff of the second diode switch; the first diode switch and the second diode switch form different conduction and cutoff combinations under their respective DC bias voltage control, and the operating frequency of the frequency reconfigurable filter power divider responds to the change in conduction and cutoff combinations, switching between the first center frequency operating mode, the second center frequency operating mode, and the dual-frequency operating mode in which the first center frequency and the second center frequency operate simultaneously.

[0067] Example 3 is an embodiment of the present invention, which differs from the previous embodiment in that: If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0068] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-including system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device.

[0069] More specific examples (a non-exhaustive list) of computer-readable media include: electrical connections (electronic devices) having one or more wires, portable computer disk drives (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which programs can be printed, because programs can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0070] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0071] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A design method for a frequency reconfigurable filter power divider, characterized in that: include: A Y-junction power divider structure is provided, wherein the Y-junction power divider structure has one signal input port and two signal output ports; A first branch is provided between the first output port and the first signal output terminal. The first branch includes a first hairpin bandpass filter and a first diode switch connected in series. The operating frequency of the first hairpin bandpass filter is the first center frequency. A second branch is provided between the second output port and the second signal output terminal. The second branch includes a second hairpin bandpass filter and a second diode switch connected in series. The operating frequency of the second hairpin bandpass filter is the second center frequency. A bridging resistor is connected between the first branch and the second branch; A first DC bias voltage and a second DC bias voltage are applied to the control terminals of the first diode switch and the second diode switch respectively, so as to independently control the conduction or cutoff of the first diode switch and the second diode switch; By controlling the on / off combination of the first diode switch and the second diode switch, the operating frequency of the power divider can be switched between the first center frequency operating mode, the second center frequency operating mode, and the dual-frequency operating mode in which the first center frequency and the second center frequency operate simultaneously.

2. The design method for a frequency reconfigurable filter power divider as described in claim 1, characterized in that: The first center frequency and the second center frequency correspond to two different frequency bands in the wireless communication spectrum. By selecting the first hairpin bandpass filter and the second hairpin bandpass filter with different structural parameters, the power divider can be adapted to any two preset different operating frequency bands to achieve cross-band frequency reconstruction.

3. The design method for a frequency reconfigurable filter power divider as described in claim 1, characterized in that: Both the first diode switch and the second diode switch are PIN diodes. When forward biased, the PIN diode is equivalent to a low-impedance conduction state to connect the corresponding branch. When zero biased or reverse biased, it is equivalent to a high-impedance cutoff state to disconnect the corresponding branch. The on / off states of the first diode switch and the second diode switch can be combined to form four different switch state combinations, of which three effective states correspond to the three operating modes respectively, and the remaining state is the fully off state.

4. The design method for a frequency reconfigurable filter power divider as described in claim 1, characterized in that: By controlling the levels of the first DC bias voltage and the second DC bias voltage respectively, the first diode switch and the second diode switch can operate independently in the on or off state. When only the DC bias voltage corresponding to the first diode switch is at an effective level, the power divider operates in the first center frequency operating mode. When only the DC bias voltage corresponding to the second diode switch is at an effective level, the power divider operates in the second center frequency operating mode. When the DC bias voltages corresponding to the first diode switch and the second diode switch are simultaneously at an effective level, the power divider operates in the dual-frequency operating mode. The switching between the three operating modes is uniquely determined by the combination of the levels of the external DC bias voltage.

5. The design method for a frequency reconfigurable filter power divider as described in claim 1, characterized in that: The first hairpin bandpass filter is used to perform bandpass filtering on the signal transmitted in the first branch, so that the passband signal in the first center frequency working mode can pass through and suppress out-of-band clutter signals that deviate from the first center frequency, and form out-of-band suppression on the signal of the corresponding frequency band of the second branch to prevent it from crosstalking to the first branch. The second hairpin bandpass filter is used to perform bandpass filtering on the signal transmitted in the second branch, so that the passband signal in the second center frequency working mode can pass through and suppress out-of-band clutter signals that deviate from the second center frequency, and form out-of-band suppression for the signal in the corresponding frequency band of the first branch to prevent it from crosstalking to the second branch. The first hairpin bandpass filter and the second hairpin bandpass filter each have DC isolation function, which is used to block the DC bias voltage of this branch from flowing back to the other branch, so as to avoid the DC bias voltage from interfering with the working state of the diode switch in the other branch.

6. The design method for a frequency reconfigurable filter power divider as described in claim 1, characterized in that: The isolation resistor is connected across the Y-shaped junction between the first branch and the second branch. When the port impedances of the first signal output terminal and the second signal output terminal are mismatched, the signal energy reflected back by the impedance mismatch is dissipated and absorbed in the form of heat through the isolation resistor, thereby maintaining the isolation degree of the Y-shaped junction power divider structure between the two output ports, suppressing signal crosstalk between the output ports, and ensuring that the isolation performance between the output ports meets the preset indicators in various working modes.

7. The design method for a frequency reconfigurable filter power divider as described in claim 1, characterized in that: The Y-junction power divider structure, the first branch, the second branch, and the isolation resistor are implemented using a microstrip transmission line structure. The entire circuit is arranged on the upper surface of the same dielectric substrate, and the lower surface of the dielectric substrate is a grounded metal layer. The first hairpin bandpass filter and the second hairpin bandpass filter are both composed of hairpin resonator structures formed by bending microstrip lines. The linewidth, line length, bending spacing, and coupling gap of the microstrip transmission line are determined according to the preset port impedance and the required operating frequency. The first diode switch and the second diode switch are connected in series in the microstrip transmission lines of the first branch and the second branch, respectively. Their control terminals are led out to the bias pads on the surface of the dielectric substrate through metallized vias or bonding wires for connecting to an external DC bias power supply.

8. A frequency reconfigurable filter power divider design system, based on the frequency reconfigurable filter power divider design method according to any one of claims 1 to 7, characterized in that: include, The Y-junction power divider structure has one signal input port and two signal output ports, which are used to realize the power distribution from one input signal to two output signals. The first branch is connected between an output port of the Y-junction power divider structure and the first signal output terminal. The first branch includes a first hairpin bandpass filter and a first diode switch connected in series. The operating frequency of the first hairpin bandpass filter is the first center frequency. The second branch is connected between another output port of the Y-junction power divider structure and the second signal output terminal. The second branch includes a second hairpin bandpass filter and a second diode switch connected in series. The operating frequency of the second hairpin bandpass filter is the second center frequency. An isolation resistor is connected between the first branch and the second branch; The first DC bias terminal is connected to the control terminal of the first diode switch and is used to receive the first DC bias voltage applied externally to independently control the conduction or cutoff of the first diode switch. The second DC bias terminal is connected to the control terminal of the second diode switch and is used to receive the externally applied second DC bias voltage to independently control the conduction or cutoff of the second diode switch. The first diode switch and the second diode switch form different on and off combinations under their respective DC bias voltage control. The operating frequency of the frequency reconfigurable filter power divider responds to the change in the on and off combinations and switches between the first center frequency operating mode, the second center frequency operating mode, and the dual-frequency operating mode in which the first center frequency and the second center frequency operate simultaneously.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, it implements the steps of the design method for a frequency reconfigurable filter power divider as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, it implements the steps of the design method for a frequency reconfigurable filter power divider as described in any one of claims 1 to 7.

Images