A power feedback system for ultrafast lasers

Abstract

The application discloses a kind of power feedback systems of ultrafast laser, include: photoelectric detection module, signal attenuation module, controllable gain amplification module, pulse peak detection and fast discharge module, subtraction difference conditioning module, single-ended to difference module, high-speed analog-digital conversion module and FPGA closed-loop control module. Through the synergistic effect of module, the present application has the following beneficial effects: 1.Each femtosecond pulse can be captured with peak value, with nanosecond level time resolution, energy resolution reaches the quantization level of high-precision analog-digital conversion.2.Discharge reset time is extremely short, can support high repetition rate femtosecond laser pulse-by-pulse peak detection and feedback.3.Closed loop bandwidth is sufficient, can effectively suppress laser pump ripple, temperature drift and other low-frequency disturbances.4.The signal-to-noise ratio of weak signal is significantly improved after controllable gain amplification, and strong signal has no top distortion, wide dynamic range.

Description

Technical Field

[0001] This invention relates to the field of femtosecond laser power feedback technology, and particularly to a power feedback system for ultrafast lasers. Background Technology

[0002] Femtosecond lasers generate femtosecond-level (10^6) lasers through mode-locking technology. -15 Femtosecond lasers, characterized by high peak power, extremely narrow pulse width, and high repetition rate, have irreplaceable application value in fields such as precision micromachining, ultrafast spectroscopy, biomedical imaging, and materials science research. The stability of the output power and single-pulse energy of femtosecond lasers directly determines the accuracy, repeatability, and reliability of related applications. Therefore, achieving high-speed and high-precision feedback control of femtosecond laser power is crucial.

[0003] Currently, femtosecond laser power feedback mainly employs traditional laser feedback schemes or simple high-speed signal acquisition schemes. The publicly disclosed related technologies mainly include: 1. A photodetector is used to convert the laser light intensity into an electrical signal. The electrical signal is amplified by a fixed-gain amplifier circuit, and then the signal is acquired by a low-speed analog-to-digital converter (ADC). Feedback control is performed based on the average value of the signal. 2. A high-speed photodetector is used in conjunction with a high-speed comparator to achieve laser power threshold alarm, but it is not possible to perform quantitative feedback and closed-loop adjustment of the power. 3. The high-speed analog-to-digital converter is used to directly acquire the output signal of the photodetector. No matching circuits such as signal attenuation, controllable gain amplification, and peak detection are set, which cannot match the characteristics of femtosecond laser signals.

[0004] Defects or shortcomings of existing technology: 1. Unable to adapt to the ultrafast characteristics of femtosecond pulses: The carrier period of a femtosecond laser pulse is on the order of femtoseconds, but the rising edge of its envelope signal after conversion by a photodetector can reach the order of nanoseconds to sub-nanoseconds. Traditional mean feedback cannot reflect the true energy of a single pulse.

[0005] 2. Insufficient bandwidth and slow response: Traditional feedback bandwidth is ≤10MHz, which cannot track the transient fluctuations of femtosecond pulses, resulting in large feedback delay and poor stability.

[0006] 3. Limited dynamic range: Existing technologies mostly use fixed gain amplifier circuits, which have low signal-to-noise ratio for weak signals under low power conditions and are prone to signal saturation under high power conditions, making them unsuitable for multi-level power output of femtosecond lasers; 4. Weak anti-interference capability: Existing technologies mostly use single-ended signal transmission, and high-speed signals are easily affected by power supply ripple and electromagnetic interference, resulting in feedback signal jitter and poor power control stability. 5. Lack of closed-loop gain adjustment capability: Existing technologies do not have a controllable closed-loop gain adjustment mechanism, which cannot compensate for laser power drift and environmental interference in real time, resulting in poor long-term stability. Summary of the Invention

[0007] According to an embodiment of the present invention, a power feedback system for an ultrafast laser is provided, comprising: a photodetector module, a signal attenuation module, a controllable gain amplification module, a pulse peak detection and fast discharge module, a subtraction differential conditioning module, a single-ended to differential module, a high-speed analog-to-digital conversion module, and an FPGA closed-loop control module; The photoelectric detection module is used to receive the sampled beam from the femtosecond laser through the beam splitter and convert the optical pulses into voltage signals; The input terminal of the signal attenuation module is connected to the output terminal of the photoelectric detection module, and is used to attenuate the voltage signal; The input terminal of the controllable gain amplifier module is connected to the output terminal of the signal attenuation module, and the gain control terminal receives the gain control voltage, which is used to perform variable gain amplification on the attenuated voltage signal. The input terminal of the pulse peak detection and fast discharge module is connected to the output terminal of the controllable gain amplification module. It is used to track the input signal during the sampling phase, lock the peak voltage during the holding phase, and perform fast discharge reset when a discharge reset control signal is received. The input of the subtraction differential conditioning module is connected to the output of the pulse peak detection and fast discharge module to perform level shifting on the peak voltage signal and eliminate DC offset, and output a bipolar signal. The input of the single-ended to differential module is connected to the output of the subtraction differential conditioning module to convert bipolar signals into differential signals. The input of the high-speed analog-to-digital converter module is connected to the output of the single-ended to differential converter module to receive the ADC sampling clock and convert the differential signal into digital peak data. The FPGA closed-loop control module is connected to the controllable gain amplification module, the pulse peak detection and fast discharge module, and the high-speed analog-to-digital conversion module. It is configured to: output an outgoing light trigger signal to the femtosecond laser; output a peak hold control signal and a discharge reset control signal to the pulse peak detection and fast discharge module; output an ADC sampling clock to the high-speed analog-to-digital conversion module; receive digital peak data, calculate the single pulse energy based on the digital peak data, compare it with the set value to obtain the power deviation, output a gain control voltage to the controllable gain amplification module based on the power deviation, and output a pump source adjustment signal to the femtosecond laser pump source, forming a closed-loop feedback.

[0008] Furthermore, the photoelectric detection module includes: a photodetector, a first operational amplifier, and a feedback resistor; Photodetectors are used to receive sampled beams from femtosecond lasers extracted by a beam splitter; The inverting input of the first operational amplifier is connected to the cathode of the photodetector, the non-inverting input is grounded, the output of the first operational amplifier is connected to the input of the signal attenuation module, and the anode of the photodetector is grounded. The feedback resistor is connected between the output terminal and the inverting input terminal of the first operational amplifier.

[0009] Furthermore, the photoelectric detection module also includes an eighth capacitor, which is connected in parallel across the feedback resistor.

[0010] Furthermore, the signal attenuation module includes: a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor; One end of the fourth resistor is connected to the output terminal of the photoelectric detection module, one end of the second resistor, and one end of the third resistor. The other end of the fourth resistor is connected to the input terminal of the controllable gain amplifier module, one end of the fifth resistor, and one end of the sixth resistor. The other ends of the second, third, fifth, and sixth resistors are grounded.

[0011] Furthermore, the controllable gain amplifier module includes: an eleventh resistor, a voltage-controlled gain amplifier, a twelfth resistor, a thirteenth resistor, and a fourteenth resistor; One end of the eleventh resistor is connected to the output of the signal attenuation module; The non-inverting input of the voltage-controlled gain amplifier is connected to the other end of the eleventh resistor and one end of the twelfth resistor. The inverting input of the voltage-controlled gain amplifier is connected to one end of the thirteenth resistor. The gain control terminal of the voltage-controlled gain amplifier is connected to the FPGA closed-loop control module through the fourteenth resistor. The output terminal of the voltage-controlled gain amplifier is connected to the input terminal of the pulse peak detection and fast discharge module. The other end of the twelfth resistor and the other end of the thirteenth resistor are grounded.

[0012] Furthermore, the controllable gain amplification module also includes: a second operational amplifier, a seventh resistor, an eighth resistor, a ninth resistor, and a tenth resistor; The non-inverting input of the second operational amplifier is connected to one end of the seventh resistor and one end of the tenth resistor. The inverting input of the second operational amplifier is grounded through the eighth resistor. The output of the second operational amplifier is connected to one end of the eleventh resistor. The other end of the seventh resistor is connected to the output of the signal attenuation module, and the other end of the tenth resistor is grounded. The ninth resistor is connected between the output terminal and the inverting input terminal of the second operational amplifier.

[0013] Furthermore, the pulse peak detection and fast discharge module includes: an integrated chip, a 26th resistor, a 30th resistor, a 22nd resistor, an isolation diode, a holding capacitor, a 21st resistor, a 17th resistor, an 18th resistor, a high-speed analog switch, and a 23rd resistor; One end of the twenty-sixth resistor is connected to one end of the thirtieth resistor and the output terminal of the controllable gain amplifier module, and the other end of the twenty-sixth resistor is connected to the first pin of the integrated chip. The other end of the thirtieth resistor is grounded; The seventh pin of the integrated chip is connected to the FPGA closed-loop control module through the twenty-second resistor; the third pin of the integrated chip is connected to the second pin of the integrated chip through the seventeenth resistor; the third pin of the integrated chip is connected to the input terminal of the subtraction differential conditioning module through the eighteenth resistor; the fifth pin of the integrated chip is connected to one end of the twenty-first resistor; the sixth pin of the integrated chip is connected to the anode of the isolation diode; and the fourth pin of the integrated chip is grounded. The other end of the 21st resistor, the cathode of the isolation diode, one end of the holding capacitor, and the fourth pin of the high-speed analog switch are connected together. Keep the other end of the capacitor grounded; The sixth pin of the high-speed analog switch is connected to the FPGA closed-loop control module, and the first pin of the high-speed analog switch is grounded through the twenty-third resistor.

[0014] Furthermore, the subtraction differential conditioning module includes: a third operational amplifier, a twenty-fifth resistor, a nineteenth resistor, a twenty-seventh resistor, and a sixteenth resistor; One end of the 25th resistor is connected to the output terminal of the pulse peak detection and fast discharge module, and the other end of the 25th resistor is connected to the non-inverting input terminal of the third operational amplifier and one end of the 27th resistor. The other end of the twenty-seventh resistor is grounded; The inverting input of the third operational amplifier is connected to the reference voltage through the nineteenth resistor, and the output of the third operational amplifier is connected to the input of the single-ended to differential module. The sixteenth resistor is connected between the output and inverting input of the third operational amplifier.

[0015] Furthermore, the single-ended to differential module includes: a fully differential amplifier, a twentieth resistor, a twenty-eighth resistor, a twenty-fourth resistor, a twenty-ninth resistor, a fifteenth resistor, a thirty-first resistor, a first capacitor, and a third capacitor; The positive input terminal of the fully differential amplifier is connected to the output terminal of the subtraction differential conditioning module through the 20th resistor, the negative input terminal of the fully differential amplifier is grounded through the 28th resistor, the negative output terminal of the fully differential amplifier is connected to the input terminal of the high-speed analog-to-digital converter module through the 24th resistor, and the positive output terminal of the fully differential amplifier is connected to the input terminal of the high-speed analog-to-digital converter module through the 29th resistor. The fifteenth resistor is connected between the positive input terminal of the fully differential amplifier and one end of the twenty-fourth resistor; The first capacitor is connected between the positive input terminal and the negative output terminal of the fully differential amplifier. The thirty-first resistor is connected between the negative input terminal of the fully differential amplifier and one end of the twenty-ninth resistor; The third capacitor is connected between the negative input terminal and the positive output terminal of the fully differential amplifier.

[0016] Furthermore, the high-speed analog-to-digital conversion module includes: a passive RLC glitch filter circuit and a high-speed analog-to-digital converter; The passive RLC glitch filter circuit is connected to the output of the single-ended to differential module; The input of the high-speed analog-to-digital converter is connected to a passive RLC glitch filter circuit, and the output of the high-speed analog-to-digital converter is connected to an FPGA closed-loop control module.

[0017] Furthermore, the passive RLC glitch filter circuit includes: the thirty-third resistor, the thirty-second resistor, the first inductor, the fourth capacitor, the thirty-fourth resistor, the thirty-fifth resistor, the fifth capacitor, the sixth capacitor, the thirty-seventh resistor, the thirty-eighth resistor, the thirty-ninth resistor, the second inductor, the seventh capacitor, and the thirty-sixth resistor. One end of the thirty-third resistor is connected to the output of the single-ended to differential module, and the other end of the thirty-third resistor is connected to one end of the thirty-second resistor, one end of the first inductor, and one end of the sixth capacitor. The other end of the thirty-second resistor is connected to one end of the fifth capacitor, one end of the thirty-fourth resistor, and one end of the thirty-fifth resistor; The other end of the thirty-fifth resistor is connected to the high-speed analog-to-digital converter; The other end of the first inductor is connected to the other end of the fourth capacitor; One end of the thirty-seventh resistor is connected to the output of the single-ended to differential module, and the other end of the thirty-seventh resistor is connected to the other end of the sixth capacitor, one end of the thirty-eighth resistor, and one end of the second inductor. One end of the seventh capacitor is connected to the other end of the second inductor, and the other end of the seventh capacitor is connected to the other end of the thirty-eighth resistor, one end of the thirty-ninth resistor, and one end of the thirty-sixth resistor. The other end of the thirty-sixth resistor is connected to the high-speed analog-to-digital converter; One end of the fifth capacitor is connected to the other end of the thirty-fourth resistor and the other end of the thirty-ninth resistor, and the other end of the fifth capacitor is grounded.

[0018] A power feedback system for an ultrafast laser according to an embodiment of the present invention has the following beneficial effects: 1. It can capture the peak of each femtosecond pulse, with nanosecond-level time resolution and energy resolution reaching the quantization level of high-precision analog-to-digital conversion.

[0019] 2. The discharge reset time is extremely short, which can support pulse-by-pulse peak detection and feedback of high repetition frequency femtosecond lasers.

[0020] 3. Sufficient closed-loop bandwidth can effectively suppress low-frequency disturbances such as laser pump ripple and temperature drift.

[0021] 4. The signal-to-noise ratio of weak signals is significantly improved after being amplified by controllable gain, while strong signals have no clipping distortion and a wide dynamic range.

[0022] 5. Differential transmission allows inter-board connections to be extended over longer distances while maintaining signal integrity, facilitating system layout.

[0023] 6. Achieve real-time, high-precision closed-loop stable control of femtosecond laser output power, significantly improving the repeatability and reliability of applications such as ultrafast processing and ultrafast spectroscopy.

[0024] It should be understood that both the foregoing general description and the following detailed description are exemplary and intended to provide further illustration of the claimed technology. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the principle framework of an ultrafast laser power feedback system according to an embodiment of the present invention. Figure 2 This is a schematic diagram of a photodetector module in a power feedback system for an ultrafast laser according to an embodiment of the present invention.

[0026] Figure 3 This is a schematic diagram of a signal attenuation module in a power feedback system for an ultrafast laser according to an embodiment of the present invention.

[0027] Figure 4 This is a schematic diagram of a controllable gain amplification module in a power feedback system for an ultrafast laser according to an embodiment of the present invention.

[0028] Figure 5 This is a schematic diagram of a pulse peak detection and rapid discharge module in an ultrafast laser power feedback system according to an embodiment of the present invention.

[0029] Figure 6This is a schematic diagram of a subtraction differential conditioning module in a power feedback system for an ultrafast laser according to an embodiment of the present invention.

[0030] Figure 7 This is a schematic diagram of a single-ended to differential module in an ultrafast laser power feedback system according to an embodiment of the present invention.

[0031] Figure 8 This is a schematic diagram of a high-speed analog-to-digital conversion module and an FPGA closed-loop control module in a power feedback system for an ultrafast laser according to an embodiment of the present invention. Detailed Implementation

[0032] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, further illustrating the present invention.

[0033] First, combine Figures 1-8 This invention describes a power feedback system for an ultrafast laser, which is used in femtosecond lasers and has a wide range of applications.

[0034] like Figures 1-8 As shown, an embodiment of the present invention provides a power feedback system for an ultrafast laser, comprising a photoelectric detection module 100, a signal attenuation module 200, a controllable gain amplification module 300, a pulse peak detection and rapid discharge module 400, a subtraction differential conditioning module 500, a single-ended to differential module 600, a high-speed analog-to-digital conversion module 700, and an FPGA closed-loop control module 800.

[0035] like Figure 1 , 2 As shown, the photoelectric detection module 100 is used to receive the sampled beam from the femtosecond laser through the beam splitter and convert the light pulse into a voltage signal.

[0036] Furthermore, such as Figure 1 , 2As shown, in this embodiment, the photodetector module 100 includes: a photodetector Z1, a first operational amplifier U1, and a feedback resistor R1. The photodetector Z1 receives the sampled beam from the femtosecond laser via a beam splitter and converts the optical pulse into a weak current signal. The photodetector Z1 is preferably a PIN silicon photodiode or an avalanche photodiode (APD) with a response time <500 ps and a dark current <10 nA. The anode of the photodetector Z1 is grounded, the inverting input of the first operational amplifier U1 is connected to the cathode of the photodetector Z1, the non-inverting input is grounded, and the output of the first operational amplifier U1 is connected to the input of the signal attenuation module 200. The output of the first operational amplifier U1 serves as the output of the photodetector module 100 and must meet the requirements of a gain-bandwidth product ≥1 GHz and a slew rate ≥1000 V / μs to adapt to the amplification requirements of femtosecond-level narrow pulse signals. Preferably, U1 can be a THS4271 operational amplifier (but not limited to this; any high-speed operational amplifier with equivalent performance can be used). Feedback resistor R1 is connected between the output and inverting input of the first operational amplifier U1. The value of feedback resistor R1 is proportional to the transimpedance gain (amplification factor) of the circuit. By appropriately selecting the value of feedback resistor R1, the output voltage range can be continuously adjusted (for example, 5kΩ for an output of 0~10V when the maximum photocurrent is 2mA). The amplified 0~10V high voltage signal is transmitted to the next stage through long inter-board lines, which can effectively suppress environmental noise interference, reduce line loss, and improve the signal-to-noise ratio of the entire signal from the source.

[0037] Furthermore, such as Figure 1 , 2 As shown, the photoelectric detection module also includes: an eighth capacitor C8, which is connected in parallel across the feedback resistor R1 to compensate for the junction capacitance of the photodetector and the input capacitance of the operational amplifier, suppress high-frequency oscillations, and ensure that the pulse response is free of overshoot.

[0038] like Figure 1 , 3 As shown, the input terminal of the signal attenuation module 200 is connected to the output terminal of the photoelectric detection module 100, and is used to attenuate the voltage signal.

[0039] Furthermore, such as Figure 1 , 3As shown, in this embodiment, the signal attenuation module 200 includes: a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. One end of the fourth resistor R4 is connected to the output terminal of the photodetector module 100, one end of the second resistor R2, and one end of the third resistor R3. The other end of the fourth resistor R4 is connected to the input terminal of the controllable gain amplifier module 300, one end of the fifth resistor R5, and one end of the sixth resistor R6. The other ends of the second resistor R2, the third resistor R3, the fifth resistor R5, and the sixth resistor R6 are grounded. The second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 form a Π-type or T-type voltage divider structure to receive the wide-amplitude voltage signal output by the photodetector module 100 and proportionally compress it to an acceptable amplitude for subsequent circuits (e.g., within ±1.6V). The attenuated signal avoids the saturation and waveform clipping of subsequent chips caused by direct high-voltage input, ensuring the entire link operates in the linear region. The specific voltage division ratio of the resistor network can be adjusted according to the actual ADC input range.

[0040] like Figure 1 , 4 As shown, the input terminal of the controllable gain amplifier module 300 is connected to the output terminal of the signal attenuation module 200, and the gain control terminal receives the gain control voltage, which is used to perform variable gain amplification on the attenuated voltage signal.

[0041] Furthermore, such as Figure 1 , 4 As shown, in this embodiment, the controllable gain amplifier module 300 includes: an eleventh resistor R11, a voltage-controlled gain amplifier U3, a twelfth resistor R12, a thirteenth resistor R13, and a fourteenth resistor R14. One end of the eleventh resistor R11 is connected to the output terminal of the signal attenuation module 200; the non-inverting input terminal of the voltage-controlled gain amplifier U3 is connected to the other end of the eleventh resistor R11 and one end of the twelfth resistor R12, the inverting input terminal of the voltage-controlled gain amplifier U3 is connected to one end of the thirteenth resistor R13, the gain control terminal (VG pin) of the voltage-controlled gain amplifier U3 is connected to the FPGA closed-loop control module 800 through the fourteenth resistor R14, and the output terminal of the voltage-controlled gain amplifier U3 is connected to the input terminal of the pulse peak detection and fast discharge module 400; the other ends of the twelfth resistor R12 and the other ends of the thirteenth resistor R13 are grounded. The gain control terminal (VG pin) of the voltage-controlled gain amplifier U3 receives an analog control voltage from the FPGA. As a preferred option, the voltage-controlled gain amplifier U3 can be a VCA824 type voltage-controlled gain amplifier (not limited to this, any amplifier with voltage-controlled gain function can be used as a substitute, such as AD603, HMC641, etc.).

[0042] Furthermore, such as Figure 1 , 4As shown, in this embodiment, the controllable gain amplifier module 300 further includes: a second operational amplifier U2, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a tenth resistor R10; the non-inverting input terminal of the second operational amplifier U2 is connected to one end of the seventh resistor R7 and one end of the tenth resistor R10, the inverting input terminal of the second operational amplifier U2 is grounded through the eighth resistor R8, and the output terminal of the second operational amplifier U2 is connected to one end of the eleventh resistor R11; the other end of the seventh resistor R7 is connected to the output terminal of the signal attenuation module 200, and the other end of the tenth resistor R10 is grounded; the ninth resistor R9 is connected across the output terminal and the inverting input terminal of the second operational amplifier U2. The second operational amplifier U2 is positioned before the voltage-controlled gain amplifier U3 as a buffer or fixed gain stage. When the gain resistors are not soldered, and the eighth and tenth resistors are not soldered, and the seventh and ninth resistors are directly shorted, the second operational amplifier U2 can function as a follower in a direct pass-through manner. The second operational amplifier U2 can be a THS4271 type operational amplifier (not limited to this; any high-speed operational amplifier with equivalent performance can be used as a substitute). The FPGA outputs a 0-2V control voltage to the VG pin of the voltage-controlled gain amplifier U3, allowing continuous adjustment of the gain range from approximately -40dB to +40dB (i.e., voltage amplification from 0.01x to 100x). For weak signals, the gain is increased to improve the signal-to-noise ratio; for strong signals, the gain is decreased or cut-through is used to prevent saturation, thereby widening the power range detectable by the system.

[0043] like Figure 1 , 5 As shown, the input terminal of the pulse peak detection and fast discharge module 400 is connected to the output terminal of the controllable gain amplification module 300, which is used to track the input signal during the sampling phase, lock the peak voltage during the holding phase, and perform fast discharge reset when a discharge reset control signal is received.

[0044] Furthermore, such as Figure 1 , 5As shown, in this embodiment, the pulse peak detection and fast discharge module 400 includes: an integrated chip U4, a 26th resistor R26, a 30th resistor R30, a 22nd resistor R22, an isolation diode D1, a holding capacitor C2, a 21st resistor R21, a 17th resistor R17, an 18th resistor R18, a high-speed analog switch U5, and a 23rd resistor R23. One end of the 26th resistor R26 is connected to one end of the 30th resistor R30 and the output terminal of the controllable gain amplifier module 300, and the other end of the 26th resistor R26 is connected to the first pin of the integrated chip U4; the other end of the 30th resistor R30 is grounded; the seventh pin of the integrated chip U4 is connected to the FPGA closed-loop control module 800 through the 22nd resistor R22; the third pin of the integrated chip U4 is connected to the second pin of the integrated chip U4 through the 17th resistor R17; the third pin of the integrated chip U4 is connected to the input terminal of the subtraction differential conditioning module 500 through the 18th resistor R18; and the fifth pin of the integrated chip U4 is connected to one end of the 21st resistor R21. The sixth pin of integrated chip U4 is connected to the anode of isolation diode D1, and the fourth pin of integrated chip U4 is grounded. The other end of the twenty-first resistor R21, the cathode of isolation diode D1, one end of holding capacitor C2, and the fourth pin of high-speed analog switch U5 are connected together. The other end of holding capacitor C2 is grounded to store the peak voltage, and a value of 27pF~100pF is recommended. The sixth pin of high-speed analog switch U5 is connected to FPGA closed-loop control module 800, and the first pin of high-speed analog switch U5 is grounded through twenty-third resistor R23. The resistance of twenty-third resistor R23 is preferably less than 50Ω to ensure that the discharge time constant is less than 50ns. Integrated chip U4 internally integrates a sampling comparator (SC) and an operational transconductance amplifier (OTA), preferably OPA615 (but not limited to this; any peak hold chip with a similar integrated structure, such as LMH6517, is acceptable). The cathode of isolation diode D1 is connected to holding capacitor C2 to achieve unidirectional charging, preferably Schottky BAT54S (but not limited to this; any fast switching diode is acceptable). The high-speed analog switch U5 is preferably TS5A3159 (but not limited to this, any analog switch with a switching time of <10ns is acceptable, such as TS12A12511, MAX4644).

[0045] FPGA control signals: Hold Control → Pin 7 of integrated chip U4, switches between sample / hold modes; Discharge Reset → Control terminal of high-speed analog switch U5, controls the discharge of holding capacitor C2.

[0046] Working process (in conjunction with FPGA timing): Sampling Phase: The FPGA sets Hold Control high, and the internal switch of integrated chip U4 closes, entering sampling mode. V_out follows the input V_in. When the instantaneous voltage of V_in is higher than the voltage of holding capacitor C2, the internal comparator turns on, charging holding capacitor C2 through isolation diode D1, causing the voltage to rise rapidly.

[0047] Peak Lock-in: The FPGA estimates the peak time based on the optical path delay (approximately 20~100ns) and pulls the Hold Control low about 10ns after the peak. The internal switch of the integrated chip U4 is turned off, entering hold mode, keeping the voltage of capacitor C2 unchanged, and the peak is locked. At the same time, the isolation diode D1 is reverse-biased and cut off, blocking reverse discharge. The internal OTA of the integrated chip U4 buffers the peak voltage output with high impedance.

[0048] ADC acquisition: The FPGA immediately starts the subsequent ADC (ADC3583) and reads the digital peak value.

[0049] Discharge Reset: The FPGA outputs a high-level pulse of approximately 20ns to the control terminal of the high-speed analog switch U5. The high-speed analog switch U5 turns on, keeping capacitor C2 short-circuited, and the residual voltage is quickly discharged to below 1mV. After the pulse ends, the high-speed analog switch U5 turns off.

[0050] Next cycle: The FPGA resets Hold Control high, the circuit returns to sampling mode, keeps capacitor C2 at a low voltage, and waits for the next femtosecond pulse.

[0051] Technical effects: FPGA active control of hold control achieves nanosecond-level peak lock-up, avoiding voltage drops and uncertain delays caused by passive holding; The parallel high-speed analog switch U5 enables rapid discharge (<50ns), supports continuous pulse operation, and can handle a maximum repetition frequency of 20MHz; The overall detection and reset cycle is less than 1μs, which meets the requirements of high-speed closed-loop feedback.

[0052] When a femtosecond laser is stably mode-locked, the pulse width is constant, the single pulse energy is proportional to the peak power, and the peak voltage after photoelectric conversion is linearly related to the single pulse energy. The peak value is collected to characterize the single pulse energy.

[0053] like Figure 1 , 6 As shown, the input terminal of the subtraction differential conditioning module 500 is connected to the output terminal of the pulse peak detection and fast discharge module 400, which is used to level shift the peak voltage signal and eliminate DC offset, and output a bipolar signal.

[0054] Furthermore, such as Figure 1, 6 As shown, in this embodiment, the differential subtraction conditioning module 500 includes: a third operational amplifier U6, a twenty-fifth resistor R25, a nineteenth resistor R19, a twenty-seventh resistor R27, and a sixteenth resistor R16. One end of the twenty-fifth resistor R25 is connected to the output terminal of the pulse peak detection and fast discharge module 400, and the other end of the twenty-fifth resistor R25 is connected to the non-inverting input terminal of the third operational amplifier U6 and one end of the twenty-seventh resistor R27; the other end of the twenty-seventh resistor R27 is grounded; the inverting input terminal of the third operational amplifier U6 is connected to the reference voltage through the nineteenth resistor R19, and the output terminal of the third operational amplifier U6 is connected to the input terminal of the single-ended to differential converter module; the sixteenth resistor R16 is connected across the output terminal and the inverting input terminal of the third operational amplifier U6. The third operational amplifier U6 constitutes a differential subtraction amplifier with a closed-loop gain of 1. Its non-inverting input terminal is connected to the single-ended peak signal from the pulse peak detection and fast discharge module 400, and its inverting input terminal is connected to the reference voltage VREF (typically half of the full-scale input voltage of the subsequent ADC). As a preferred option, the third operational amplifier U6 can be a THS4271 op-amp (not limited to this, any high-speed op-amp with sufficient bandwidth is acceptable).

[0055] Working process: The single-ended peak signal (e.g., 0~3.2V) is added to VREF to output a symmetrical bipolar signal centered at 0V (e.g., -1.6V~+1.6V), while eliminating DC offset and common-mode interference, and avoiding clipping distortion in the subsequent stage.

[0056] like Figure 1 , 7 As shown, the input terminal of the single-ended to differential module 600 is connected to the output terminal of the subtraction differential conditioning module 500, and is used to convert bipolar signals into differential signals.

[0057] Furthermore, such as Figure 1 , 7As shown, in this embodiment, the single-ended to differential module includes: a fully differential amplifier U7, a twentieth resistor R20, a twenty-eighth resistor R28, a twenty-fourth resistor R24, a twenty-ninth resistor R29, a fifteenth resistor R15, a thirty-first resistor R31, a first capacitor C1, and a third capacitor C3. The positive input terminal of the fully differential amplifier U7 is connected to the output terminal of the subtraction differential conditioning module 500 through the twentieth resistor R20. The negative input terminal of the fully differential amplifier U7 is grounded through the twenty-eighth resistor R28. The negative output terminal of the fully differential amplifier U7 is connected to the input terminal of the high-speed analog-to-digital converter module 700 through the twenty-fourth resistor R24. The positive output terminal of the fully differential amplifier U7 is connected to the input terminal of the high-speed analog-to-digital converter module 700 through the twenty-ninth resistor R29. The fifteenth resistor R15 is connected between the positive input terminal of the fully differential amplifier U7 and one end of the twenty-fourth resistor R24. The first capacitor C1 is connected between the positive input terminal and the negative output terminal of the fully differential amplifier U7. The thirty-first resistor R31 is connected between the negative input terminal and one end of the twenty-ninth resistor R29. The third capacitor C3 is connected between the negative input terminal and the positive output terminal of the fully differential amplifier U7. The input of the fully differential amplifier U7 is connected to the single-ended signal output from the subtraction differential conditioning module 500, and the output is a pair of differential signals with complementary polarities. The high-speed analog-to-digital converter ADC3583 internally outputs a reference common-mode voltage VCM. This VCM signal is connected to the VOCM pin of the preceding fully differential amplifier to unify the midpoint potential of the differential signals, ensuring that the differential output common-mode potential matches the ADC input specifications. This prevents clipping distortion caused by the signal being close to the power rail on one side, reducing system differential common-mode noise. As a preferred option, the fully differential amplifier U7 can be a THS4521 type (but not limited to this; any fully differential amplifier U7 can be used, such as ADA4940, LMH6552, etc.). The differential transmission mode can significantly suppress spatial electromagnetic interference and power ripple from trace coupling, ensuring distortion-free transmission of high-frequency pulse signals over long distances (over 30cm), while also meeting the differential input requirements of the subsequent high-speed ADC.

[0058] like Figure 1 , 8 As shown, the input terminal of the high-speed analog-to-digital converter module 700 is connected to the output terminal of the single-ended to differential converter module 600, and is used to receive the ADC sampling clock and convert the differential signal into digital peak data. Furthermore, such as Figure 1 , 8As shown, in this embodiment, the high-speed analog-to-digital converter (ADC) module 700 includes a passive RLC glitch filter circuit and a high-speed ADC. The passive RLC glitch filter circuit is connected to the output of the single-ended to differential converter module to improve the signal-to-noise ratio. The input of the high-speed ADC is connected to the passive RLC glitch filter circuit, and the output of the high-speed ADC is connected to the FPGA closed-loop control module 800. Preferably, the high-speed ADC can be an ADC3583 type ADC (not limited to this; any high-speed ADC with a sampling rate ≥65MSPS and a resolution ≥12 bits is acceptable, such as ADS4249, AD9643, etc.). The high-speed ADC converts the continuous analog peak signal into a standardized digital signal at a fixed sampling rate (e.g., 65MSPS) and transmits it to the FPGA for closed-loop control.

[0059] Furthermore, such as Figure 1 , 8 As shown, in this embodiment, the passive RLC glitch filter circuit includes: a 33rd resistor R33, a 32nd resistor R32, a first inductor L1, a fourth capacitor C4, a 34th resistor R34, a 35th resistor R35, a fifth capacitor C5, a sixth capacitor C6, a 37th resistor R37, a 38th resistor R38, a 39th resistor R39, a second inductor L2, a seventh capacitor C7, and a 36th resistor R36; one end of the 33rd resistor R33 is connected to the output terminal of the single-ended to differential converter module, and the other end of the 33rd resistor R33 is connected to one end of the 32nd resistor R32, one end of the first inductor L1, and one end of the sixth capacitor C6; the other end of the 32nd resistor R32 is connected to one end of the fifth capacitor C5, one end of the 34th resistor R34, and one end of the 35th resistor; The other end of resistor R35 is connected to the high-speed analog-to-digital converter; the other end of inductor L1 is connected to the other end of capacitor C4; one end of resistor R37 is connected to the output of the single-ended to differential module, and the other end of resistor R37 is connected to the other end of capacitor C6, one end of resistor R38, and one end of inductor L2; one end of capacitor C7 is connected to the other end of inductor L2, and the other end of capacitor C7 is connected to the other end of resistor R38, one end of resistor R39, and one end of resistor R36; the other end of resistor R36 is connected to the high-speed analog-to-digital converter; one end of capacitor C5 is connected to the other end of resistor R34 and resistor R39, and the other end of capacitor C5 is grounded.

[0060] like Figure 1 , 8As shown, the FPGA closed-loop control module 800 (Field Programmable Gate Array) is connected to the controllable gain amplification module 300, the pulse peak detection and fast discharge module 400, and the high-speed analog-to-digital converter module 700. It is implemented by the FPGA and its peripheral circuits and performs the following functions: Timing control: Light emission trigger: The FPGA sends a synchronous trigger signal to the femtosecond laser.

[0061] Delay prediction: Based on the optical path transmission delay (typically 20~100ns), the Control pin of U4 is pulled high (entering sampling / tracking mode) about 20ns before the expected pulse reaches its peak.

[0062] Peak lock: About 10ns after the estimated peak value, pull the Control pin low (enter hold mode), and the hold capacitor C2 locks the peak value.

[0063] ADC Acquisition: Immediately initiate high-speed analog-to-digital converter conversion and read digital peak values.

[0064] Discharge Reset: After reading is complete, a 20ns high-level pulse is sent to the high-speed analog switch U5 to discharge and reset the holding capacitor C2.

[0065] Closed-loop calculation and adjustment: The FPGA calculates the single-pulse energy based on the peak-energy mapping relationship and compares it with the set value.

[0066] The algorithm outputs a control voltage (via DAC) to the VG pin of the voltage-controlled gain amplifier U3 to dynamically adjust the amplification gain.

[0067] Simultaneously, it outputs analog signals or PWM signals to adjust the pump source current or attenuator of the femtosecond laser, forming a high-speed closed-loop feedback.

[0068] Workflow: The laser output from the femtosecond laser is sampled by a beam splitter and then converted into a 0-10V analog voltage signal by a photodetector module 100. This signal is compressed to a ±1.6V range by a signal attenuation module 200. The controllable gain amplification module 300 (VCA824) then dynamically adjusts the gain according to the current power level. The amplified signal enters a pulse peak detection module (OPA615) to capture and hold the pulse peak. An FPGA closed-loop control module 800 controls a high-speed analog switch U5 (TS5A3159). After each acquisition, a rapid discharge reset is performed; the peak voltage is converted into a symmetrical bipolar signal by the subtraction differential conditioning module 500 (THS4271), and then output as a differential signal by the single-ended to differential module 600 (THS4521); the high-speed analog-to-digital converter module 700 (ADC3583) digitizes the differential peak signal; the FPGA closed-loop control module 800 receives the digital peak value, calculates the power and compares it with the set value, and adjusts the VCA gain and laser pump source in a closed loop to achieve real-time stable control of the femtosecond laser power.

[0069] Above, refer to Figures 1-8 A power feedback system for an ultrafast laser according to an embodiment of the present invention is described, which has the following innovations: 1. For the first time, the high-speed analog switch U5 is connected in parallel across the peak hold capacitor C2, solving the inherent problem of slow discharge and inability to work continuously pulse by pulse in OPA615 type peak hold circuits.

[0070] 2. Precise timing control of FPGA: It realizes a fully automatic pipeline-style peak detection of "light emission trigger → HOLD lock → ADC acquisition → discharge reset → next acquisition", and supports femtosecond pulse repetition frequency of up to 20MHz.

[0071] 3. High-bandwidth design across the entire chain (≥65MHz): From photoelectric detection, controllable gain amplification, peak detection to differential conditioning and high-speed ADC, the overall response speed is in the nanosecond range, which can track the transient fluctuations of femtosecond lasers.

[0072] 4. Wide dynamic range controllable gain: The VCA824 is used in conjunction with the FPGA to adjust the gain (-40dB~+40dB) in a closed loop, which takes into account both weak signal amplification and strong signal attenuation, significantly improving the signal-to-noise ratio and applicable power range.

[0073] 5. Fully differential anti-interference architecture: After peak detection, it is immediately converted into a differential signal, which is driven by THS4521 to drive ADC3583. It has a high common-mode rejection ratio and is suitable for long-distance transmission and harsh electromagnetic environments.

[0074] 6. Integrated System: It integrates attenuation, controllable gain, peak hold, discharge reset, differential conditioning, high-speed ADC acquisition and digital closed loop into a compact system, which is easy to deploy in batches in femtosecond lasers.

[0075] It should be noted that, in this specification, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0076] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A power feedback system for an ultrafast laser, characterized in that, Includes: photoelectric detection module, signal attenuation module, controllable gain amplification module, pulse peak detection and fast discharge module, subtraction differential conditioning module, single-ended to differential module, high-speed analog-to-digital conversion module, and FPGA closed-loop control module; The photoelectric detection module is used to receive the sampled beam from the femtosecond laser through the beam splitter and convert the optical pulse into a voltage signal; The input terminal of the signal attenuation module is connected to the output terminal of the photoelectric detection module, and is used to attenuate the voltage signal; The input terminal of the controllable gain amplification module is connected to the output terminal of the signal attenuation module, and the gain control terminal receives the gain control voltage, which is used to perform variable gain amplification on the attenuated voltage signal. The input terminal of the pulse peak detection and fast discharge module is connected to the output terminal of the controllable gain amplification module, and is used to track the input signal during the sampling phase, lock the peak voltage during the holding phase, and perform fast discharge reset when a discharge reset control signal is received. The input terminal of the subtraction differential conditioning module is connected to the output terminal of the pulse peak detection and fast discharge module, and is used to level shift the peak voltage signal and eliminate DC offset, and output a bipolar signal. The input terminal of the single-ended to differential module is connected to the output terminal of the subtraction differential conditioning module, and is used to convert the bipolar signal into a differential signal. The input terminal of the high-speed analog-to-digital converter module is connected to the output terminal of the single-ended to differential converter module, and is used to receive the ADC sampling clock and convert the differential signal into digital peak data. The FPGA closed-loop control module is connected to the controllable gain amplification module, the pulse peak detection and fast discharge module, and the high-speed analog-to-digital conversion module, and is configured to: output an emission trigger signal to the femtosecond laser; output a peak hold control signal and a discharge reset control signal to the pulse peak detection and fast discharge module; output an ADC sampling clock to the high-speed analog-to-digital conversion module; receive the digital peak data, calculate the single pulse energy based on the digital peak data, compare it with a set value to obtain the power deviation, output a gain control voltage to the controllable gain amplification module based on the power deviation, and output a pump source adjustment signal to the femtosecond laser pump source, forming a closed-loop feedback; The photoelectric detection module includes: a photodetector, a first operational amplifier, and a feedback resistor; The photodetector is used to receive the sampled beam extracted from the femtosecond laser by the beam splitter. The inverting input of the first operational amplifier is connected to the cathode of the photodetector, and the non-inverting input is grounded. The output of the first operational amplifier is connected to the input of the signal attenuation module, and the anode of the photodetector is grounded. The feedback resistor is connected across the output terminal and the inverting input terminal of the first operational amplifier. The controllable gain amplification module includes: an eleventh resistor, a voltage-controlled gain amplifier, a twelfth resistor, a thirteenth resistor, and a fourteenth resistor; One end of the eleventh resistor is connected to the output terminal of the signal attenuation module; The non-inverting input of the voltage-controlled gain amplifier is connected to the other end of the eleventh resistor and one end of the twelfth resistor. The inverting input of the voltage-controlled gain amplifier is connected to one end of the thirteenth resistor. The gain control terminal of the voltage-controlled gain amplifier is connected to the FPGA closed-loop control module through the fourteenth resistor. The output terminal of the voltage-controlled gain amplifier is connected to the input terminal of the pulse peak detection and fast discharge module. The other end of the twelfth resistor and the other end of the thirteenth resistor are grounded.

2. The power feedback system for ultrafast lasers as described in claim 1, characterized in that, The photoelectric detection module also includes an eighth capacitor, which is connected in parallel across the feedback resistor.

3. The power feedback system for ultrafast lasers as described in claim 1, characterized in that, The signal attenuation module includes: a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor; One end of the fourth resistor is connected to the output terminal of the photoelectric detection module, one end of the second resistor, and one end of the third resistor; the other end of the fourth resistor is connected to the input terminal of the controllable gain amplifier module, one end of the fifth resistor, and one end of the sixth resistor. The other ends of the second resistor, the third resistor, the fifth resistor, and the sixth resistor are grounded.

4. The power feedback system for ultrafast lasers as described in claim 1, characterized in that, The controllable gain amplification module further includes: a second operational amplifier, a seventh resistor, an eighth resistor, a ninth resistor, and a tenth resistor; The non-inverting input terminal of the second operational amplifier is connected to one end of the seventh resistor and one end of the tenth resistor; the inverting input terminal of the second operational amplifier is grounded through the eighth resistor; and the output terminal of the second operational amplifier is connected to one end of the eleventh resistor. The other end of the seventh resistor is connected to the output terminal of the signal attenuation module, and the other end of the tenth resistor is grounded. The ninth resistor is connected between the output terminal and the inverting input terminal of the second operational amplifier.

5. The power feedback system for ultrafast lasers as described in claim 1, characterized in that, The pulse peak detection and rapid discharge module includes: an integrated chip, a 26th resistor, a 30th resistor, a 22nd resistor, an isolation diode, a holding capacitor, a 21st resistor, a 17th resistor, an 18th resistor, a high-speed analog switch, and a 23rd resistor; One end of the 26th resistor is connected to one end of the 30th resistor and the output terminal of the controllable gain amplifier module, and the other end of the 26th resistor is connected to the first pin of the integrated chip. The other end of the thirtieth resistor is grounded; The seventh pin of the integrated chip is connected to the FPGA closed-loop control module through the twenty-second resistor; the third pin of the integrated chip is connected to the second pin of the integrated chip through the seventeenth resistor; the third pin of the integrated chip is connected to the input terminal of the subtraction differential conditioning module through the eighteenth resistor; the fifth pin of the integrated chip is connected to one end of the twenty-first resistor; the sixth pin of the integrated chip is connected to the anode of the isolation diode; and the fourth pin of the integrated chip is grounded. The other end of the 21st resistor, the cathode of the isolation diode, one end of the holding capacitor, and the fourth pin of the high-speed analog switch are connected together. The other end of the holding capacitor is grounded; The sixth pin of the high-speed analog switch is connected to the FPGA closed-loop control module, and the first pin of the high-speed analog switch is grounded through the twenty-third resistor.

6. The power feedback system for ultrafast lasers as described in claim 1, characterized in that, The subtraction differential conditioning module includes: a third operational amplifier, a twenty-fifth resistor, a nineteenth resistor, a twenty-seventh resistor, and a sixteenth resistor; One end of the 25th resistor is connected to the output terminal of the pulse peak detection and fast discharge module, and the other end of the 25th resistor is connected to the non-inverting input terminal of the third operational amplifier and one end of the 27th resistor; The other end of the 27th resistor is grounded; The inverting input terminal of the third operational amplifier is connected to the reference voltage through the nineteenth resistor, and the output terminal of the third operational amplifier is connected to the input terminal of the single-ended to differential module. The sixteenth resistor is connected between the output terminal and the inverting input terminal of the third operational amplifier.

7. The power feedback system for ultrafast lasers as described in claim 1, characterized in that, The single-ended to differential module includes: a fully differential amplifier, a twentieth resistor, a twenty-eighth resistor, a twenty-fourth resistor, a twenty-ninth resistor, a fifteenth resistor, a thirty-first resistor, a first capacitor, and a third capacitor; The positive input terminal of the fully differential amplifier is connected to the output terminal of the subtraction differential conditioning module through the twentieth resistor, the negative input terminal of the fully differential amplifier is grounded through the twenty-eighth resistor, the negative output terminal of the fully differential amplifier is connected to the input terminal of the high-speed analog-to-digital converter module through the twenty-fourth resistor, and the positive output terminal of the fully differential amplifier is connected to the input terminal of the high-speed analog-to-digital converter module through the twenty-ninth resistor. The fifteenth resistor is connected between the positive input terminal of the fully differential amplifier and one end of the twenty-fourth resistor; The first capacitor is connected between the positive input terminal and the negative output terminal of the fully differential amplifier; The thirty-first resistor is connected between the negative input terminal of the fully differential amplifier and one end of the twenty-ninth resistor; The third capacitor is connected between the negative input terminal and the positive output terminal of the fully differential amplifier.

8. The power feedback system for ultrafast lasers as described in claim 1, characterized in that, The high-speed analog-to-digital conversion module includes: a passive RLC glitch filter circuit and a high-speed analog-to-digital converter; The passive RLC glitch filter circuit is connected to the output of the single-ended to differential module. The input terminal of the high-speed analog-to-digital converter is connected to the passive RLC glitch filter circuit, and the output terminal of the high-speed analog-to-digital converter is connected to the FPGA closed-loop control module.

9. The power feedback system for ultrafast lasers as described in claim 8, characterized in that, The passive RLC glitch filter circuit includes: a 33rd resistor, a 32nd resistor, a first inductor, a fourth capacitor, a 34th resistor, a 35th resistor, a fifth capacitor, a sixth capacitor, a 37th resistor, a 38th resistor, a 39th resistor, a second inductor, a seventh capacitor, and a 36th resistor; One end of the thirty-third resistor is connected to the output terminal of the single-ended to differential module, and the other end of the thirty-third resistor is connected to one end of the thirty-second resistor, one end of the first inductor, and one end of the sixth capacitor. The other end of the thirty-second resistor is connected to one end of the fifth capacitor, one end of the thirty-fourth resistor, and one end of the thirty-fifth resistor; The other end of the thirty-fifth resistor is connected to the high-speed analog-to-digital converter; The other end of the first inductor is connected to the other end of the fourth capacitor; One end of the thirty-seventh resistor is connected to the output terminal of the single-ended to differential module, and the other end of the thirty-seventh resistor is connected to the other end of the sixth capacitor, one end of the thirty-eighth resistor, and one end of the second inductor. One end of the seventh capacitor is connected to the other end of the second inductor, and the other end of the seventh capacitor is connected to the other end of the thirty-eighth resistor, one end of the thirty-ninth resistor, and one end of the thirty-sixth resistor; The other end of the thirty-sixth resistor is connected to the high-speed analog-to-digital converter; One end of the fifth capacitor is connected to the other end of the thirty-fourth resistor and the other end of the thirty-ninth resistor, and the other end of the fifth capacitor is grounded.

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