Optoelectronic co-packaged (CPO) structure based on light-electric-thermal-reliability four-domain cooperation

Abstract

The application relates to the technical field of semiconductor lasers, in particular to an optoelectronic co-packaged CPO structure based on light-electric-thermal-reliability four-domain cooperation, which comprises the following: an optoelectronic integrated chip (OIC), which integrates a high-speed optical modulator array, a photodetector array, an on-chip SOA gain adaptive adjustment unit and an on-chip optical power monitoring array (MPD-array); a thermal isolation buffer layer (TIBL) arranged below the OIC, which is composed of a composite material with a gradient change in thermal conductivity along the thickness direction and is embedded with a directional heat sink column array (DTHA); a temperature-sensitive impedance compensation network (TS-ICN) integrated with a CPW transmission line, which comprises a BST ferroelectric film variable capacitance array and a NiFe film variable inductance array; an external laser source module (ELS) connected with an input grating coupler of the OIC through a fiber array; and a four-domain cooperation control hub based on a hardware accelerator. The application solves the suboptimal system performance problem caused by the four-domain split of light / electric / thermal / reliability in the existing CPO technology.

Description

Technical Field

[0001] This invention relates to the field of semiconductor laser technology, specifically to a photoelectric co-packaging CPO structure based on the synergy of four domains: optical, electrical, thermal, and reliability. Background Technology

[0002] With the explosive growth in computing power demands for training and inference of large artificial intelligence (AI) models, the throughput of data center switching chips is evolving towards higher speeds. Co-packaged optical (CPO) technology, by directly integrating the optical engine with the switching ASIC, has become a key solution to address the bottleneck of high-speed data transmission. Industry forecasts predict that the CPO market will grow from $46 million in 2024 to $8.1 billion in 2030, with 2025 marking its commercialization debut. Leading companies such as TSMC, Broadcom, and NVIDIA have already begun mass production.

[0003] However, existing CPO technologies suffer from three fragmented design paradigms, which prevent optimal system performance:

[0004] 1. Separation of optical and electric domains

[0005] In existing solutions, the design of the light source (ELS or on-chip laser) and the RF interconnect design are completed independently by different teams. Light source engineers focus on power and linewidth, while RF engineers focus on bandwidth and loss, resulting in a lack of collaborative optimization between the two. The result is either excessive power margin in the light source design (wasting power) or insufficient RF bandwidth (limiting data rate increases).

[0006] 2. Separation of electric and thermal domains

[0007] High-frequency interconnect designs (TSV+CPW) typically assume a constant ambient temperature and do not consider the impact of temperature fluctuations caused by dynamic power consumption changes in the ASIC on signal integrity. In actual testing, the junction temperature of the ASIC under full load can reach over 100°C, causing a 5-10% drift in the characteristic impedance of the CPW, a 3-5 dB deterioration in S11, and eye diagram closure.

[0008] 3. Separation of thermal domain and reliability domain

[0009] The current heat dissipation design only focuses on "cooling down" and does not consider the accelerating effect of temperature cycling on laser lifespan. For every 10°C increase in laser junction temperature, the MTBF is halved. Although existing microfluidic cooling can reduce the average temperature, the fatigue damage caused by temperature fluctuations (ΔT) is not quantitatively managed.

[0010] Those skilled in the art have long been limited by a "divide and conquer" engineering mindset, believing that problems in the optical, electrical, thermal, and reliability domains should be solved independently by their respective specialized teams. This technical bias stems from the following reasons:

[0011] Optical communication engineers focus on modulation formats, wavelength stability, and optical power budgets;

[0012] RF engineers focus on S-parameters, eye diagrams, and bit error rate;

[0013] Thermal management engineers focus on thermal resistance, temperature rise, and heat dissipation efficiency;

[0014] Reliability engineers focus on accelerating aging tests and life prediction.

[0015] Different professional fields use different simulation tools (OptiSystem, ADS, COMSOL, Weibull++) and different optimization objective functions, lacking a unified physical model and collaborative optimization framework. This "technical bias" has resulted in existing CPO schemes being single-domain optimizations, failing to recognize the deep coupling effects between the four domains.

[0016] Specifically, the following technical biases exist in this field:

[0017] 1. Broadcom's CPO solution (Bailly platform, integrated into the Tomahawk 5 switch chip) only optimizes the optical power output of the ELS and the integration of the silicon photonics engine, without considering its coupling with the ASIC's thermal dissipation. When the ASIC power consumption increases from 50% to 100%, thermal crosstalk between the ELS and the ASIC causes a laser wavelength drift of ±50 pm, resulting in a 2-3 order of magnitude deterioration in the bit error rate.

[0018] 2. imec's TSV solution (EP3892147A1, application date March 15, 2021) only optimizes the RF bandwidth (>110GHz) and assumes a constant ambient temperature. In actual testing, the CPW characteristic impedance drifted by 8% under full ASIC load, S11 deteriorated by 4.5dB, and the eye diagram opening decreased from 0.35UI to 0.26UI.

[0019] 3. IBM's microfluidic solution (US2020 / 0389634A1, application date June 18, 2020) only optimizes heat dissipation efficiency (>500W / cm²). 2 The effect of temperature cycling on laser lifespan was not considered. Temperature cycling ΔT = 40℃ (1 cycle / day) caused the laser MTBF to decrease from 30,000h to 15,000h.

[0020] 4. Inphi's on-chip SOA solution (US2019 / 0319130A1, application date April 10, 2019) only optimizes optical power compensation and adopts a fixed gain mode. When the RF signal quality deteriorates, the SOA cannot adaptively adjust, resulting in wasted or insufficient optical power margin.

[0021] The above solutions are all optimal within their respective domains, but they fail to recognize the coupling effects between the four domains. For example, increased ASIC power consumption → increased temperature → CPW impedance drift → decreased RF signal quality → increased bit error rate → need to increase optical power margin to maintain signal-to-noise ratio → increased SOA power consumption → further increased temperature → formation of positive feedback. This cross-domain coupling effect cannot be identified and suppressed within the single-domain optimization framework.

[0022] Therefore, a long-standing technical bias exists in this field, namely, that optics, electricity, heat, and reliability are independent engineering problems that should be optimized separately. This bias leads to a lack of motivation among engineers to seek a unified, synergistic solution. Summary of the Invention

[0023] To address the problems mentioned in the background section, the present invention provides the following technical solution.

[0024] The optoelectronic co-packaging CPO structure based on the synergy of four domains—optical, electrical, thermal, and reliability—includes:

[0025] The Optoelectronic Integrated Circuit (OIC) integrates a high-speed optical modulator array, a photodetector array, an on-chip SOA gain adaptive adjustment unit, and an on-chip optical power monitoring array (MPD-array). The MPD-array is configured to monitor the optical power of each channel in real time and feed it back to the SOA gain adaptive adjustment unit. The on-chip SOA gain adaptive adjustment unit includes an input SOA and an output SOA. The input SOA is located after the input grating coupler of the OIC, with a gain adjustable range of 0-15dB, a noise figure less than 8dB, and a response time less than 100ns. The output SOA is located after the high-speed optical modulator array, with a gain adjustable range of 0-10dB and a response time less than 100ns. The MPD-array includes M monitoring points, one at the input and one at the output of each modulator channel, with a response time less than 10ns. The SOA gain adaptive adjustment unit is configured to: when the optical power P of a certain channel... i (t) is lower than the target power P target Subtract the threshold ΔP threshold At the same time, increase the SOA gain Gᵢ of this channel, while decreasing the gain G of the adjacent channel. j j≠i, to avoid exceeding the total power consumption limit;

[0026] (Thermal Insulation Buffer Layer) TIBL, disposed below the OIC, the TIBL is composed of a composite material with thermal conductivity gradient along the thickness direction, including a low thermal conductivity polymer layer facing the ASIC side, a gradient thermal conductivity layer in the middle layer and a high thermal conductivity interface layer facing the OIC side;

[0027] (Directional Heat Sink Array) DTHA, embedded within the TIBL, the density distribution of the DTHA is configured to match the heat source distribution of the OIC, wherein the density of the DTHA directly below the SOA gain adaptive adjustment unit is greater than the density directly below the high-speed optical modulator array, and a 1-2 μm isolation gap is maintained between the top of the DTHA and the bottom of the third sublayer of the TIBL facing the OIC.

[0028] A high-frequency TSV array and a CPW transmission line, wherein the high-frequency TSV array passes through a silicon interposer, and the CPW transmission line is located on the surface of the OIC and connected to the driving electrode of the high-speed optical modulator array;

[0029] (Temperature-Sensitive Impedance Compensation Network) TS-ICN, integrated below the ground line of the CPW transmission line, the TS-ICN includes a BST ferroelectric thin film variable capacitor array and a NiFe thin film variable inductor array, the variable capacitor and variable inductor are configured to automatically adjust their reactance values ​​in response to temperature changes in order to stabilize the characteristic impedance of the CPW transmission line;

[0030] A micropump and microchannel cooling system, wherein the micropump is mounted on the edge of the silicon adapter plate and is thermally coupled to the third sublayer of the TIBL facing the OIC side through a microchannel, the depth of which is 50-150μm;

[0031] (External laser source module) ELS, the ELS is connected to the input grating coupler of the OIC through an optical fiber array, the ELS includes multiple high-power CW DFB laser chips, with a rated output power greater than 100mW and a linewidth less than 1MHz;

[0032] (Thermoelectric cooler) TEC is used to stably control the operating temperature of the CW DFB laser chip within the range of 25±0.5℃;

[0033] A wavelength division multiplexer for multiplexing the output optical signals of multiple CW DFB laser chips to a single optical fiber, and a pluggable optical fiber connector that supports hot-swappable replacement.

[0034] A four-domain collaborative control hub based on a hardware accelerator, comprising an FPGA, ASIC, or SoC, internally embeds a multivariate adaptive optimization algorithm based on model predictive control (MPC). The hardware accelerator communicates via a bus with the SOA gain adaptive adjustment unit, the TS-ICN, the micropump, and the temperature sensor array. The control logic of the MPC algorithm is implemented through the programmable logic array of the hardware accelerator, with control registers mapped to the physical pins of the hardware accelerator. The hardware accelerator is configured as follows: optical domain control employs a lookup table hard logic pass-through mechanism with a response time of less than 1 μs; electrical domain control employs rolling optimization of the MPC algorithm with an execution cycle of 10 μs; thermal domain control employs global optimization asynchronous execution of the MPC algorithm with a cycle of 1 ms; and reliability domain evaluation has a cycle of 1 s.

[0035] In some implementations, the TIBL includes:

[0036] The first sublayer, facing the ASIC side, is made of polyimide / aerogel composite material with a thermal conductivity k1 = 0.05-0.2 W / m·K and a thickness h1 = 10-30 μm;

[0037] The second sublayer, the intermediate layer, is made of a gradient SiC / AlN composite material with a thermal conductivity ranging from kJ / k ... 2bottom =0.2W / m·K gradually changed to k 2top =50 W / m·K, thickness h2=10-20μm;

[0038] The third sublayer, facing the OIC side, is made of diamond nanosheets / silver paste composite material with thermal conductivity k3 > 500 W / m·K and thickness h3 = 5-10 μm.

[0039] The DTHA includes: a heat sink material of CVD diamond (chemical vapor deposition) or VACNT (vertically aligned carbon nanotubes), with a thermal conductivity greater than 1000 W / m·K; and a heat sink diameter d. DTH =3-10μm, height h DTH The thickness is equal to the sum of the thicknesses of the first and second sub-layers, and a 1-2 μm isolation gap is maintained between the top of the heat sink column and the bottom of the third sub-layer; the heat sink column density distribution function ρ(x,y)=ρ0·exp(-r 2 / 2σ 2 ), where r is the distance from the center of the SOA, σ = 20-50 μm, and ρ0 is the peak density directly below the SOA, with the density unit being μm. -2 The density of the DTHA directly below the SOA gain adaptive adjustment unit is in the ratio of 2:1 to 5:1 to the density directly below the high-speed optical modulator array.

[0040] In some embodiments, the TS-ICN includes:

[0041] BST ferroelectric thin-film variable capacitor array, initial capacitance C0 = 0.1-2pF, temperature coefficient α C =-100 to -500 ppm / ℃, quality factor Q > 50 @ 56 GHz;

[0042] NiFe thin film variable inductor array, initial inductance L0 = 0.2-2nH, temperature coefficient α L =-50 to -200ppm / ℃, quality factor Q>30@56GHz;

[0043] A Pt thin-film temperature sensor array is integrated below the ground wire of the CPW transmission line, with a spacing of 50μm, an initial resistance R0=100Ω, a temperature coefficient TCR=3850ppm / ℃, and an accuracy of ±0.5℃.

[0044] A resonance suppression grounding via array is disposed below the ground line of the CPW transmission line, with the via spacing being 1 / 20 to 1 / 10 of the signal wavelength, in order to suppress the parasitic resonance of the BST ferroelectric thin film and the NiFe thin film in the 56GHz frequency band.

[0045] The TS-ICN is configured such that when the temperature changes by ΔT, the capacitance value of the variable capacitor changes by ΔC = α. C ·C0·ΔT, the change in inductance value of the variable inductor is ΔL=α L The changes in capacitance and inductance, denoted as L0ΔT, together compensate for the temperature drift of the characteristic impedance of the CPW transmission line, maintaining the characteristic impedance within the range of 50±2Ω.

[0046] In some implementations, the hardware accelerator-based four-domain collaborative control hub includes:

[0047] Hardware accelerators, including FPGAs, ASICs, or SoCs, integrate processor cores and programmable logic arrays;

[0048] The on-chip storage unit, including DDR memory and on-chip SRAM, is used to store the state space model and optimization parameters of the MPC algorithm;

[0049] A high-speed ADC / DAC interface with a sampling rate greater than 1GSa / s is used to acquire the MPD-array, temperature sensor array, and RF S-parameters.

[0050] The global optimization solution of the MPC algorithm is executed in parallel in the programmable logic array of the hardware accelerator. It adopts a quadratic programming solver, the solution time is less than 100μs, and the convergence accuracy objective function change rate is less than 0.01%.

[0051] In some embodiments, the present invention employs a four-domain coupled transfer function model to describe the dynamic coupling relationships between the domains, including:

[0052] Electro-thermal coupling transfer function: , where ΔZ CPW ΔP is the change in characteristic impedance of the CPW. ASIC K represents the change in ASIC power consumption. ET α is the electro-thermal coupling coefficient. T Let τ be the temperature coefficient of CPW. T The thermal time constant;

[0053] Thermo-optical coupling transfer function: , where Δλ DFB ΔT represents the wavelength shift of the DFB laser. junction K represents the change in junction temperature. TO The thermal-optical coupling coefficient, τ is the temperature tuning coefficient of the laser. λ The photothermal time constant;

[0054] Optical-electric coupling transfer function: Where ΔBER is the change in bit error rate, and ΔP optical K represents the change in optical power. OE The opto-electric coupling coefficient, τ represents the sensitivity of optical power to bit error rate. o The photoelectric response time constant;

[0055] Reliability-thermal coupling transfer function: Where RUL represents the remaining useful life, and E... a The activation energy is given by k, Boltzmann constant is given by T, and absolute temperature is given by K. RT is the reliability-thermal coupling coefficient, and m is the material fatigue index.

[0056] In some embodiments, the high-power CW DFB laser chip in the ELS adopts an InP-based material system, with an output wavelength of 1310nm or 1550nm and a single-chip output power of 200-400mW. Multiple wavelengths are multiplexed into a single optical fiber through CW-WDM or DWDM technology. The optical fiber array is aligned with the optical waveguide of the OIC through edge coupling or grating coupling, with a coupling loss of less than 1.5dB.

[0057] In some implementations, the total data transmission rate of the structure is not limited to a specific value, and is suitable for high-speed data transmission scenarios with a single channel of 100Gbps to 800Gbps and a total bandwidth of 1.6Tbps to 51.2Tbps. The high-speed optical modulator array adopts a micro-ring modulator or an electro-absorption modulator, with a single-channel modulation rate of 112Gbps or 224Gbps. The OIC and the ASIC are connected via a 2.5D silicon adapter or 3D hybrid bonding to achieve optoelectronic heterogeneous integration.

[0058] This invention also provides an adaptive management method for the optoelectronic co-packaging CPO structure based on four-domain synergy of optical-electrical-thermal-reliability, the specific steps of which are as follows:

[0059] S1. Obtain system status parameters, including the optical power P of each channel monitored by the MPD-array. i (t), the CPW temperature T monitored by the temperature sensor array CPW(t) and OIC temperature T OIC(t) and the current reactance value of the TS-ICN;

[0060] S2. Input the system state parameters into the multiphysics coupling model. The multiphysics coupling model includes an optical power transmission model, a radio frequency signal transmission model, a heat conduction model, and a laser aging model. The state space matrices A, B, and E of the multiphysics coupling model are generated in real time based on the physical parameters of the OIC and ASIC through a system identification method or a finite element simulation order reduction method, and stored in the on-chip storage unit of the hardware accelerator.

[0061] S3. Based on the multiphysics coupling model, the optimal control action is calculated by the model predictive control (MPC) algorithm embedded in the programmable logic array of the hardware accelerator. The optimal control action includes SOA gain adjustment ΔGᵢ, TS-ICN reactance adjustment ΔX, and coolant flow rate adjustment ΔQ.

[0062] S4. Execute the optimal control action and monitor the execution effect through the MPD-array and temperature sensor array to form a closed-loop feedback;

[0063] Steps S1-S4 are executed by programmable logic embedded in the hardware accelerator, which includes FPGA, ASIC or SoC. The mathematical operations of the MPC algorithm are implemented through the DSP hard core or LUT resources of the hardware accelerator. Control commands are output to the SOA gain adaptive adjustment unit, the TS-ICN and the micro pump through the physical pins of the hardware accelerator.

[0064] The optimization objective of the MPC algorithm is as follows: The constraint is: BER < 1e -12 ,P total <P max ,T max <85℃, RUL>10000h;

[0065] The MPC algorithm includes: a state-space model x(k+1) = Ax(k) + Bu(k), where the state vector... Control vector The state space matrices A and B are obtained based on the physical parameters of the OIC and ASIC through system identification methods or finite element simulation order reduction methods. The matrix elements are updated in real time as the operating states of the OIC and ASIC change, with an update cycle of every 1000 control cycles; cost function Rolling optimization: Solve the finite-time optimization problem in each control cycle, execute only the first control action, and then solve it again in the next cycle; Feedback correction: Estimate the deviation between the actual state and the model's predicted state using a Kalman filter and correct the model parameters.

[0066] The laser aging model includes: a threshold current aging model. , where Ith0 is the initial threshold current and τ1 is the aging time constant;

[0067] Slope efficiency aging model , where η0 is the initial slope efficiency and τ2 is the degradation time constant;

[0068] Remaining life prediction ,when > Timely triggering of warnings;

[0069] Cumulative thermal cycling damage model Where ΔTᵢ is the amplitude of the i-th temperature cycle, ΔT ref The reference temperature range is denoted by m, which represents the material fatigue index. Preventive maintenance is triggered when D > 0.7.

[0070] In some implementations, the adaptive management method includes an online optimization layer based on (deep reinforcement learning) DRL, which performs nonlinear fine-tuning on the output of the MPC algorithm, and the DRL online optimization layer is embedded in the programmable logic array of the hardware accelerator;

[0071] The DRL online optimization layer includes:

[0072] The Actor network takes the system state s as input and outputs the action adjustment amount Δa. The network structure is a multilayer perceptron, with the number of hidden layer neurons decreasing layer by layer. The weight parameters of the Actor network are stored in the on-chip SRAM of the hardware accelerator.

[0073] The Critic network takes state s and action a as input and outputs state-action value Q(s,a). The network structure is a multilayer perceptron with the number of hidden layer neurons decreasing layer by layer. The weight parameters of the Critic network are stored in the on-chip SRAM of the hardware accelerator.

[0074] Reward function:

[0075] ;

[0076] The training methods include offline pre-training and online fine-tuning. The offline pre-training is performed on a high-performance computing cluster outside the hardware accelerator, and the trained network weights are burned into the on-chip SRAM through the configuration interface of the hardware accelerator.

[0077] This invention also provides a method for manufacturing an optoelectronic co-packaging CPO structure based on the synergy of four domains: optoelectronic, thermal, and reliability, specifically comprising the following steps:

[0078] S1. Form a TSV via array on a silicon wafer using the (deep reactive ion etching) (DRIE) process. The via diameter is 10-20μm and the depth is 100-300μm.

[0079] S2. An insulating layer is deposited on the sidewall of the TSV via. The insulating layer material is SiO2 or SiN, and the thickness is 0.5-2μm.

[0080] S3. The TSV vias are filled with copper by electroplating and then planarized by chemical mechanical polishing (CMP).

[0081] S4. A microchannel coolant flow network is formed on the front side of the silicon wafer by photolithography and etching processes, with a flow channel depth of 50-150μm.

[0082] S5, Deposition of TIBL, including spin-coating a polyimide / aerogel composite to form a first sublayer; forming a gradient SiC / AlN composite second sublayer by chemical vapor deposition (CVD); and spin-coating a diamond nanosheet / silver paste composite to form a third sublayer.

[0083] S6. DTHA positioning holes are formed by laser drilling or photolithography etching (directional thermal sink), and the density distribution of the positioning holes follows the Gaussian function ρ(r)=ρ0·exp(-r 2 / 2σ 2 The density unit is μm. -2Then, CVD diamond or vertically aligned carbon nanotubes are filled in, with the filling height controlled to leave a 1-2 μm isolation gap between the top of the DTHA and the bottom of the third sublayer.

[0084] S7. Integrate a BST ferroelectric thin film variable capacitor and a NiFe thin film variable inductor below the ground wire of the CPW transmission line to form a (temperature-sensitive impedance compensation network) TS-ICN, and set a resonance suppression grounding via array below the ground wire of the CPW transmission line.

[0085] S8. The OIC is bonded to the thermal isolation buffer layer using a (micro-bump flip-chip) process.

[0086] S9. Bond the ASIC chip to the other side of the silicon adapter plate using a hybrid bonding or thermo-press bonding process;

[0087] S10. Align and couple the ELS to the grating coupler of the OIC via a pluggable fiber optic connector;

[0088] S11. Integrate the hardware accelerator, MPD-array, and temperature sensor array, and embed the MPC algorithm and DRL online optimization layer into the programmable logic array of the hardware accelerator;

[0089] S12. Perform hermetic sealing and aging tests.

[0090] This invention provides a photoelectric co-packaging CPO structure based on the synergy of four domains: optical, electrical, thermal, and reliability. Compared with existing technologies, it has the following significant advantages:

[0091] 1. Optoelectronic synergy: RF bandwidth increased by 40%

[0092] In traditional solutions, the RF interconnect bandwidth is designed with a fixed value (e.g., 80GHz), without considering the impact of optical power fluctuations on signal quality. This invention, through optical domain adaptive power equalization, achieves a 40% increase in equivalent RF bandwidth when the optical power drops by 3dB, with only a 5% decrease in RF eye diagram opening (compared to a 25% decrease in traditional solutions).

[0093] 2. Electro-thermal synergy: Impedance stability improved by 5 times

[0094] In traditional solutions, the characteristic impedance of the CPW (Constant Positive Voltage) drifts by 5-10% with temperature. This invention uses TS-ICN automatic compensation to control the impedance drift within ±1% (@25-100℃), with S11 change <1dB and eye diagram jitter reduced by 60%.

[0095] 3. Thermal-Reliability Synergy: Laser Lifespan Extended by 3.5 Times

[0096] In traditional solutions, the MTBF of a laser is approximately 30,000 hours. This invention extends the MTBF to >100,000 hours through predictive maintenance and thermal cycling management, and achieves zero-downtime maintenance (automatic switching + hot-swapping).

[0097] 4. Four-domain overall synergy: Energy efficiency ratio improved by 50%

[0098] Through MPC multi-objective optimization, the system satisfies BER < 1e -12 Under the premise of reducing total power consumption by 30%, extending laser life by 3.5 times, reducing maintenance costs by 90%, and improving overall energy efficiency ratio (Gbps / W) by 50%. Attached Figure Description

[0099] Figure 1 This is a diagram of the overall architecture of the four-domain collaborative CPO structure of the present invention;

[0100] Figure 2 This is a cross-sectional view of the overall structure of TS-ICN in this invention;

[0101] Figure 3 This is the equivalent circuit model of TS-ICN in this invention;

[0102] Figure 4 This is the temperature compensation characteristic curve of the present invention;

[0103] Figure 5 These are the key parameter specifications of TS-ICN in this invention;

[0104] Figure 6 This is a cross-sectional structural diagram of the thermal domain directional conduction blocking module (TIBL+DTHA) in this invention;

[0105] Figure 7 This is a top view of the density distribution of DTHA in this invention;

[0106] Figure 8 This is a simulation diagram of the temperature distribution of the present invention;

[0107] Figure 9 This is a comparative experimental data graph of eye opening in this invention;

[0108] Figure 10 This is a graph showing the experimental data of S-parameter comparison in this invention;

[0109] Figure 11 This is a graph showing the temperature distribution comparison experiment data of the present invention;

[0110] Figure 12 This is a graph showing the experimental data of RUL prediction comparison in this invention. Detailed Implementation

[0111] The following will be based on embodiments of the present invention. Figure 1 - Figure 8 The technical solutions in the embodiments of the present invention will be clearly and completely described.

[0112] The optoelectronic co-packaging CPO structure based on the synergy of four domains—optical, electrical, thermal, and reliability—includes:

[0113] 1. Optical domain adaptive power equalization module

[0114] include:

[0115] An external laser source array (ELS) contains N independent wavelength CW DFB lasers, each with a rated output power P0 > 100mW (preferably 200-400mW) and a linewidth Δν0 < 1MHz. It adopts an InP-based material system and outputs wavelengths of 1310nm or 1550nm. Multiple wavelengths are multiplexed onto a single optical fiber using CW-WDM or DWDM technology.

[0116] The on-chip optical power monitoring array (MPD-array) contains M monitoring points (one at the input and one at the output of each modulator channel) with a response time of <10ns.

[0117] The on-chip SOA gain adaptive adjustment unit includes an input SOA (gain 0-15dB, NF < 8dB) and an output SOA (gain 0-10dB), with a gain adjustment step of 0.1dB and a response time of < 100ns.

[0118] Optical domain control algorithm: When the optical power P of a certain channel is detected... i (t)<P target -ΔP threshold At the same time, increase the SOA gain G of this channel. i At the same time, reduce the gain G of adjacent channels. j (j≠i) to avoid exceeding the total power consumption limit.

[0119] The collaborative mechanism of the optical domain adaptive power equalization module:

[0120] Changes in RF interconnect bandwidth → changes in modulator drive voltage → changes in optical power → MPD detection → SOA gain adjustment → optical power recovery → improvement in RF signal quality.

[0121] 2. Dynamic Impedance Reconstruction Module in Electric Domain

[0122] include:

[0123] High-frequency TSV array, single aperture diameter d TSV =10-20μm, aspect ratio AR>10:1, copper fill rate>95%, surface gold plating 1μm, DC resistance<50mΩ;

[0124] CPW transmission line, signal line width W CPW =5-15μm, signal-to-ground distance S CPW =3-10μm, characteristic impedance Z0=50±2Ω (@25℃);

[0125] A temperature-sensitive impedance compensation network (TS-ICN), integrated below the ground line of the CPW transmission line, includes:

[0126] BST ferroelectric thin-film variable capacitor array: C0 = 0.1-2pF, α C =-100 to -500 ppm / ℃, Q>50@56GHz;

[0127] NiFe thin film variable inductor array: L0 = 0.2-2nH, α L =-50 to -200ppm / ℃, Q>30@56GHz;

[0128] Pt thin-film temperature sensor array: integrated below the CPW ground wire, with a spacing of 50μm and an accuracy of ±0.5℃;

[0129] Resonance suppression grounding via array: The via spacing is 1 / 20 to 1 / 10 of the signal wavelength (approximately 270-540 μm @ 56 GHz) to suppress parasitic resonances in BST+NiFe thin films.

[0130] The collaborative mechanism of the electric domain dynamic impedance reconstruction module:

[0131] ASIC power consumption change → temperature change → TS-ICN parameter automatic change → CPW characteristic impedance maintained at 50Ω → S11 stable → eye diagram opening maintained >0.3UI.

[0132] 3. Thermal directional conduction blocking module

[0133] include:

[0134] Thermal Insulation Buffer Layer (TIBL), total thickness h TIBL =30-80μm, composed of the following sublayers:

[0135] First sublayer (facing the ASIC): polyimide / aerogel composite, k1=0.05-0.2W / m·K, h1=10-30μm;

[0136] Second sublayer (intermediate layer): Gradient SiC / AlN composite, k 2bottom =0.2→k 2top =50W / m·K, h2=10-20μm;

[0137] Third sublayer (facing the OIC side): diamond nanosheets / silver paste composite, k3 > 500 W / m·K, h3 = 5-10 μm.

[0138] Directional heat sink array (DTHA) penetrates the first and second sublayers, with a 1-2 μm isolation gap maintained between the top and bottom of the third sublayer:

[0139] Heat sink material: CVD diamond (k>1500W / m·K) or VACNT (k>1000W / m·K);

[0140] Heat sink column size: d DTH =3-10μm, h DTH =h1+h2, spacing p DTH =10-30μm;

[0141] Density distribution function of heat sink column: ρ(x,y)=ρ0·exp(-r 2 / 2σ 2 ), where r is the distance from the center of the SOA, σ = 20-50 μm, and the density unit is μm. -2 ;

[0142] Density configuration: The ratio of the density of DTHA directly below the SOA gain adaptive adjustment unit to the density directly below the high-speed optical modulator array is 2:1 to 5:1.

[0143] The collaborative mechanism of the thermal directional conduction blocking module:

[0144] SOA heat → rapid vertical conduction in DTHA → lateral diffusion in the third sublayer → carried away by microchannels;

[0145] ASIC heat → first sublayer lateral blockage → unable to reach the OIC optical path area.

[0146] 4. Reliability Domain Predictive Maintenance Module

[0147] include:

[0148] Laser aging monitoring unit:

[0149] Threshold current aging model: ;

[0150] Slope-efficiency aging model: ;

[0151] Remaining life prediction: ;

[0152] Thermal cycling fatigue monitoring unit:

[0153] Cumulative damage model: ;

[0154] Preventive maintenance is triggered when D > 0.7;

[0155] Automatic switching unit: When RUL < 1000 hours or D > 0.7, the flow rate is automatically switched to the backup laser channel, with a switching time of < 1ms.

[0156] The collaborative mechanism of the reliability domain predictive maintenance module:

[0157] Optical power monitoring → Aging parameter extraction → RUL prediction → Thermal cycling monitoring → Fatigue assessment → Automatic switching → Maintenance notification.

[0158] 5. Four-Domain Coordinated Control Center (4D-CC)

[0159] include:

[0160] Hardware accelerators, including FPGAs, ASICs, or SoCs, integrate processor cores and programmable logic arrays;

[0161] On-chip memory units (DDR+SRAM) store the state space model and optimization parameters of the MPC algorithm;

[0162] High-speed ADC / DAC interface (>1GSa / s) for acquiring MPD-array, temperature sensor and RF S-parameters;

[0163] Multiphysics coupling model: Real-time coupling calculation of optical power P(t), radio frequency S-parameter S(f,T), temperature field T(x,y,z,t), and aging parameter A(t);

[0164] The Model Predictive Control (MPC) algorithm is embedded in the programmable logic array of the hardware accelerator:

[0165] State-space equation: x(k+1)=Ax(k)+Bu(k);

[0166] Cost function: ;

[0167] Rolling optimization: Solving a finite-time optimization problem in each control cycle;

[0168] Feedback correction: Kalman filter estimates bias and corrects the model;

[0169] Control cycle: Optical domain < 1μs (lookup table hard logic pass-through), Electrical domain 10μs (MPC rolling optimization), Thermal domain 1ms (MPC global optimization asynchronous execution), Reliability domain 1s;

[0170] The MPC global optimization solution takes less than 100μs and is accelerated by FPGA parallel computing.

[0171] Example 1: Detailed Explanation of the Four-Domain Collaborative Structure

[0172] (1) Optical domain adaptive power equalization

[0173] ELS: 8-channel CWDM4, each channel has a CW DFB output power of 200mW, a linewidth of 500kHz, a TEC temperature control of 25±0.5℃, uses an InP-based material system, and has an output wavelength of 1310nm;

[0174] MPD-array: 16 monitoring points (1 at the input and 1 at the output of each MZM channel), InGaAs PIN structure, response time <10ns;

[0175] SOA gain adjustment: Input SOA gain 0-15dB, output SOA gain 0-10dB, adjustment step 0.1dB, response time <100ns;

[0176] Control Algorithm: The optical domain adopts a lookup table hard logic pass-through mechanism with a control cycle of 1μs. The lookup table is stored in the FPGA on-chip SRAM and contains the ASIC power consumption-temperature-SOA gain mapping relationship. The control command is output directly by looking up the table through the hardware state machine, without the need for MPC real-time solution.

[0177] Coordination mechanism: When the power consumption of ASIC SerDes changes from 50% to 100%, the RF drive voltage fluctuation → MZM insertion loss change ±0.5dB → MPD detection → SOA gain adjustment ±1dB → optical power recovery → RF eye diagram opening maintained >0.3UI.

[0178] (2) Dynamic impedance reconstruction in the electric domain

[0179] TSV: Diameter 15μm, depth 200μm, copper filling rate >95%, surface gold plating 1μm, DC resistance <50mΩ;

[0180] CPW: Signal line width 10μm, signal-to-ground spacing 5μm, Z0=50±2Ω@25℃;

[0181] TS-ICN:

[0182] BST variable capacitor: C0 = 0.5pF, α C =-300ppm / ℃, Q>50@56GHz, through bias voltage V bias =0-5V adjustment;

[0183] NiFe variable inductance: L0 = 0.5nH, α L =-100ppm / ℃, Q>30@56GHz, adjustable by bias current I_bias=0-10mA;

[0184] Pt temperature sensor: R0=100Ω, TCR=3850ppm / ℃, accuracy ±0.5℃, integrated 50μm below the CPW ground wire;

[0185] Resonance suppression grounding via array: via diameter 5μm, spacing 400μm (approximately λ) g / 15@56GHz), penetrating deep through the CPW ground wire to the silicon transition board ground plane;

[0186] Coordination mechanism: When the ASIC power consumption changes from 100W to 300W, the junction temperature changes from 65℃ to 95℃, the Pt sensor detects ΔT=30℃, the BST capacitor changes ΔC=-4.5%, the NiFe inductor changes ΔL=-3%, the CPW characteristic impedance changes from 50Ω to 50.1Ω (drift <0.2%), and the S11@56GHz changes by <0.5dB.

[0187] (3) Blocking of thermal directional conduction

[0188] TIBL:

[0189] First sublayer: PI / aerogel composite (k=0.1W / m·K, h=20μm), formed by spin coating and curing process;

[0190] Second sublayer: Gradient SiC / AlN composite (k bottom =0.5→k top =30W / m·K, h=15μm), with component gradient controlled by CVD process;

[0191] The third sublayer: diamond nanosheet / silver paste composite (k=800W / m·K, h=8μm), formed by screen printing and sintering processes;

[0192] DTHA:

[0193] Material: CVD diamond (k=1800W / m·K);

[0194] Dimensions: d=5μm, h=35μm (penetrates the first and second sublayers), with a 1.5μm isolation gap between the top and the bottom of the third sublayer, p=15μm (below SOA) / 40μm (below MZM);

[0195] Density distribution: ρ(r) = 5 × 10 -3 ·exp(-r 2 / 800)μm -2 (r unit μm), positioned by laser drilling;

[0196] Density configuration: 5×10 below SOA -3 μm -2The density below MZM is 1×10 -3 Up to 2.5×10 -3 μm -2 Density ratio 2:1 to 5:1;

[0197] Synergistic mechanism: SOA power consumption 2W → heat through DTHA (thermal resistance 0.5K / W) → third sublayer (lateral diffusion) → microchannel (convective heat transfer coefficient > 5000W / m) 2 ·K) → Temperature rise < 8℃; ASIC power consumption 300W → Heat is conducted laterally through the first sublayer (thermal resistance > 100K / W) to the microchannel below the ASIC → OIC optical path area temperature rise < 2℃.

[0198] (4) Reliability domain predictive maintenance

[0199] Aging monitoring: Ith and η are sampled every 10 minutes, and an exponential model is fitted to predict RUL;

[0200] Initial state: Ith0 = 20mA, η0 = 0.3W / A;

[0201] Aging parameters: τ1=50,000h, τ2=80,000h;

[0202] Warning threshold: Ith max =40mA, T target =100,000h;

[0203] Thermal cycling monitoring: Record extreme temperature values ​​every minute and calculate cumulative damage D;

[0204] Reference temperature range: ΔT ref =20℃;

[0205] Material fatigue index: m=3 (typical value);

[0206] Warning threshold: D > 0.7;

[0207] Automatic switching: Switching time < 1ms, service interruption < 10 seconds. -9 .

[0208] (5) Four-domain coordinated control center

[0209] Hardware: FPGA (Xilinx Versal VC1902), integrating dual-core ARM Cortex-A72 and programmable logic array (>1M LUT);

[0210] Storage: DDR4-3200 8GB + on-chip SRAM 32MB;

[0211] ADC / DAC: 4-channel 16-bit ADC (1GSa / s) + 4-channel 14-bit DAC (500MSa / s);

[0212] MPC algorithm parameters:

[0213] Predicting time domain N=10;

[0214] The state weight matrix Q = diag([10,10,...,10,5,5,1,1]);

[0215] The control weight matrix R = diag([1,1,...,1,0.5,0.5,0.1]);

[0216] Terminal weight matrix P = 10·Q;

[0217] Control cycle: 1μs in optical domain (lookup table hard logic), 10μs in electrical domain (MPC rolling optimization), 1ms in thermal domain (MPC global optimization asynchronous execution), and 1s in reliability domain;

[0218] MPC global optimization solution: The quadratic programming (QP) solver is used to execute the interior point method or active set method in parallel in the FPGA programmable logic array. The solution time is <100μs and the convergence accuracy is <0.01% of the objective function change rate.

[0219] Example 2: Detailed Explanation of the MPC Algorithm

[0220] (1) Physical origin of state-space model

[0221] Matrices A, B, and E in the above state-space model are obtained based on the physical parameters of the OIC and ASIC through the following steps:

[0222] Step 1: Establish a three-dimensional multiphysics coupled finite element model

[0223] A three-dimensional thermo-electric-optical coupling model of OIC and ASIC was created using COMSOL Multiphysics software:

[0224] Thermal conductivity module: Includes the thermal conductivity and specific heat capacity of materials such as silicon substrate (k=156W / m·K), copper interconnect (k=400W / m·K), and polyimide (k=0.1W / m·K);

[0225] Electromagnetic module: includes the distributed resistance R', distributed inductance L', distributed capacitance C', and distributed conductance G' of the CPW transmission line, as well as the parasitic capacitance and inductance of the TSV;

[0226] Optical module: includes the Pockels effect of MZM, the gain saturation characteristics of SOA, and the transmission loss of waveguide;

[0227] Boundary conditions: ASIC power consumption 100W-300W (dynamically changing), ambient temperature 20℃-45℃, coolant flow rate 10-500mL / min.

[0228] Step 2: Parameter Scanning and System Identification

[0229] Perform parameter scanning at typical operating points:

[0230] ASIC power consumption: 100W, 150W, 200W, 250W, 300W;

[0231] Ambient temperature: 20℃, 25℃, 30℃, 35℃, 40℃, 45℃;

[0232] Coolant flow rate: 50, 100, 200, 300, 400, 500 mL / min;

[0233] SOA gain: 0, 5, 10, 15 dB;

[0234] TS-ICN parameters: C=0.3-0.7pF, L=0.3-0.7nH.

[0235] For each operating point, record the steady-state and transient responses:

[0236] Optical power Pᵢ (MPD-array reading);

[0237] CPW temperature T_CPW (Pt sensor reading);

[0238] OIC temperature T_OIC (integrated temperature sensor reading);

[0239] Laser threshold current Ith (reading from aging monitoring unit);

[0240] Laser slope efficiency η (reading from aging monitoring unit).

[0241] Step 3: Reduce the order of the finite element model

[0242] The intrinsic orthogonal decomposition (POD) method is used to reduce the high-dimensional finite element model to a low-dimensional state-space model:

[0243] Extract the top K dominant intrinsic modes (K=10-20, cumulative energy percentage>99%).

[0244] Project the full-order model onto the subspace spanned by the dominant mode;

[0245] Obtain the reduced state space matrix A red B red E red .

[0246] Step 4: Least Squares Fitting and Real-Time Update

[0247] By fitting the parameters of the reduced-order model using the least squares method, the mean square error between the model prediction and the finite element simulation results is minimized.

[0248] min||y_FEM y_model|| 2

[0249] Where y_FEM is the output of the finite element simulation, and y_model is the output of the state space model prediction.

[0250] The fitted state-space matrix is ​​stored in the FPGA's on-chip SRAM and updated in real time during operation using recursive least squares (RLS) or an extended Kalman filter (EKF), with an update cycle of approximately 1 second every 1000 control cycles. The matrix elements are dynamically adjusted according to the operating states of the OIC and ASIC to ensure model accuracy.

[0251] (2) Cost function design

[0252]

[0253] in:

[0254] x_ref is the reference state vector:

[0255] Optical power reference value: P ref =[0, 0, ..., 0]dBm (target output optical power of each channel);

[0256] Temperature reference value: T CPW ref =50℃, T OIC ref =45℃;

[0257] Aging parameter reference value: Ith ref =25mA, η ref =0.25W / A;

[0258] Q is the state deviation weight matrix (diagonal matrix):

[0259] Optical power weight: q P =10 (to ensure stable optical power);

[0260] Temperature weighting: q T =5 (Ensure the temperature is within a safe range);

[0261] Aging parameter weights: q A =1 (long-term reliability optimization);

[0262] R is the control action weight matrix (diagonal matrix):

[0263] SOA gain weight: r G =1 (to avoid drastic changes in gain);

[0264] TS-ICN parameter weights: r X =0.5 (to avoid drastic changes in reactance value);

[0265] Pump speed weight: r Q =0.1 (allows for relatively rapid changes in pump speed);

[0266] S is the control rate of change weight matrix (diagonal matrix):

[0267] s G =0.5, s X =0.3, s Q =0.1 (to prevent sudden changes in control actions);

[0268] P is the terminal weight matrix: P=10Q (to ensure terminal state convergence).

[0269] (3) Rolling optimization algorithm

[0270] In each control cycle t:

[0271] 1. Measure the current state x(t) (using MPD-array, temperature sensor, and aging monitoring unit);

[0272] 2. Solving finite-time optimization problems:

[0273] min J(x(t), u(t), ..., u(t+N-1))

[0274] st x(k+1) = Ax(k) + Bu(k) + Ew(k), k=t, ..., t+N-1

[0275] x_min ≤ x(k) ≤ x_max

[0276] u_min ≤ u(k) ≤ u_max

[0277] Δu_min ≤ Δu(k) ≤ Δu_max

[0278] 3. Obtain the optimal control sequence u*(t), u*(t+1), ..., u*(t+N-1);

[0279] 4. Only the first control action u*(t) is executed;

[0280] 5. In the next period t+Δt, remeasure the state and repeat steps 1-4.

[0281] The optimization problem employs a quadratic programming (QP) solver, accelerated by leveraging the parallel computing capabilities of the FPGA:

[0282] Interior point method or active set method;

[0283] Computation time < 100μs (FPGA parallel acceleration, prediction time domain N=10, state dimension M+4=12).

[0284] Convergence accuracy: rate of change of objective function < 0.01%.

[0285] (4) Feedback correction

[0286] The deviation between the actual state and the model's predicted state is estimated using a Kalman filter:

[0287] Prediction steps:

[0288] ẋ(k+1|k) = Ax(k|k) + Bu(k) + Ew(k)

[0289] P(k+1|k) = AP(k|k)Aᵀ + Q_w

[0290] Update steps:

[0291] K(k+1) = P(k+1|k)Cᵀ[CP(k+1|k)Cᵀ + Q_v] -1

[0292] x(k+1|k+1) = ẋ(k+1|k) + K(k+1)[y(k+1) Cẋ(k+1|k)]

[0293] P(k+1|k+1) = [IK(k+1)C]P(k+1|k)

[0294] in:

[0295] K is the Kalman gain matrix;

[0296] y(k+1) represents the actual measured value (MPD-array optical power and temperature sensor readings).

[0297] C is the observation matrix (selection matrix, which extracts measurable states from the state vector).

[0298] Q_w is the process noise covariance matrix;

[0299] Q_v is the measurement noise covariance matrix.

[0300] When the model bias exceeds a threshold (e.g., >5%), online model parameter identification and updating are triggered.

[0301] Recursive least squares (RLS) or extended Kalman filter (EKF) can be used.

[0302] Update the elements of matrices A, B, and E;

[0303] Update cycle: every 1000 control cycles (approximately 1 second).

[0304] Example 3: Simulation Verification Data

[0305] (1) Optical-electric synergistic verification

[0306] Conditions: Single-channel 200Gbps PAM4, fiber coupling loss 1.5dB, MZM insertion loss 7dB;

[0307] Scene Traditional solution (fixed SOA) This invention (MPC Adaptive SOA) Optical power is normal (0dB attenuation). Eye opening 0.35 UI Eye opening 0.35 UI Optical power decreased by 3dB Eye opening was 0.26 UI (a decrease of 25%). Eye opening was 0.33 UI (a decrease of 5%). Equivalent radio frequency bandwidth 80GHz 112GHz (40% improvement) Bit error rate @ optical power decrease of 3dB <![CDATA[1e -6 (Requirements not met) <![CDATA[1e -13 (Meets requirements)

[0308] (2) Electro-thermal synergistic verification

[0309] Conditions: ASIC power consumption dynamically changes from 100W to 300W, ambient temperature changes from 25℃ to 45℃;

[0310] parameter Traditional solution This invention CPW impedance drift +8% (54Ω at 100℃) +0.2% (50.1Ω at 100℃) S11@56GHz Changes +4.5dB +0.5dB Eye image jitter 0.08UI 0.03UI Bit error rate @ 100℃ <![CDATA[1e -8 ]]> <![CDATA[1e -14 ]]>

[0311] (3) Thermal-reliability co-verification

[0312] Conditions: Laser junction temperature 85℃, temperature cycling ΔT = 40℃ (20-60℃), frequency 1 time / day;

[0313] parameter Traditional solution This invention MTBF 30000h 105000h Annual failure rate 3.3% 0.95% Maintenance downtime 48h / year 0 (Automatic switching) 5-year maintenance costs $50000 $5000

[0314] (4) Four-domain overall collaborative verification

[0315] Requirements: 51.2Tbps switch, 64 x 800Gbps ports, total power consumption budget 500W;

[0316] index Traditional CPO This invention Total power consumption 480W 336W (reduced by 30%) Single-channel power consumption 7.5W 5.25W Laser MTBF 30000h 105000h Maintenance costs (5 years) $50000 $5000 (90% reduction) Energy efficiency ratio (Gbps / W) 107 160 (50% increase) Bit error rate <![CDATA[1e -12 ]]> <![CDATA[1e -14 ]]>

[0317] Example 4: Inventiveness Comparison with Existing Patents

[0318] Existing patents Technical features Differences between the present inventions Furukawa ELSFP plan ELS external laser source (CW DFB, 200-400mW) +On-chip SOA adaptive equalization +MPD-array real-time monitoring +Optic-electrode synergy UMN US9,123,456B2 TSV+CPW high-frequency interconnect (DC-110GHz) +TS-ICN temperature adaptive compensation +Pt sensor integration +Electro-thermal synergy IBM US2020 / 0389634A1 Embedded microchannel heat dissipation +TIBL gradient thermal conductivity +DTHA Gaussian distribution + thermal-reliability synergy Inphi US2019 / 0319130A1 On-chip SOA power amplifier +MPD-array real-time monitoring + adjacent channel power reallocation + adaptive optical domain equalization

[0319] The inventiveness of this invention lies not in a single physical structure (such as TIBL or DTHA), but in the first-ever construction of a unified physical model and collaborative optimization framework encompassing the four domains of optics, electronics, heat, and reliability. Physical structures such as TIBL, DTHA, and TS-ICN are specific implementation methods designed to realize this framework; their inventiveness lies in their deep coupling with the MPC algorithm, rather than in the structure itself.

[0320] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A photoelectric co-packaging CPO structure based on the synergy of four domains: optical, electrical, thermal, and reliability, characterized in that: include: The Optical Integrated Circuit (OIC) integrates a high-speed optical modulator array, a photodetector array, an on-chip SOA gain adaptive adjustment unit, and an MPD-array. The MPD-array is configured to monitor the optical power of each channel in real time and feed it back to the SOA gain adaptive adjustment unit. The on-chip SOA gain adaptive adjustment unit includes an input SOA and an output SOA. The input SOA is located after the input grating coupler of the OIC, with a gain adjustable range of 0-15dB, a noise figure less than 8dB, and a response time less than 100ns. The output SOA is located after the high-speed optical modulator array, with a gain adjustable range of 0-10dB and a response time less than 100ns. The MPD-array includes M monitoring points, one at the input and one at the output of each modulator channel, with a response time less than 10ns. The SOA gain adaptive adjustment unit is configured to: when the optical power P of a certain channel... i (t) is lower than the target power P target Subtract the threshold ΔP threshold At the same time, increase the SOA gain G of this channel. i At the same time, reduce the gain G of adjacent channels. j j≠i; The TIBL is disposed below the OIC. The TIBL is composed of a composite material whose thermal conductivity varies along the thickness direction, including a low thermal conductivity polymer layer facing the ASIC side, a gradient thermal conductivity layer in the middle layer, and a high thermal conductivity interface layer facing the OIC side. DTHA, embedded within the TIBL, has a density distribution configured to match the heat source distribution of the OIC, wherein the density of the DTHA directly below the SOA gain adaptive adjustment unit is greater than the density directly below the high-speed optical modulator array, and a 1-2 μm isolation gap is maintained between the top of the DTHA and the bottom of the third sublayer of the TIBL facing the OIC. A high-frequency TSV array and a CPW transmission line, wherein the high-frequency TSV array passes through a silicon interposer, and the CPW transmission line is located on the surface of the OIC and connected to the driving electrode of the high-speed optical modulator array; The TS-ICN, integrated below the ground line of the CPW transmission line, includes a BST ferroelectric thin-film variable capacitor array and a NiFe thin-film variable inductor array. The variable capacitors and variable inductors are configured to automatically adjust their reactance values ​​in response to temperature changes to stabilize the characteristic impedance of the CPW transmission line. A micropump and microchannel cooling system, wherein the micropump is mounted on the edge of the silicon adapter plate and is thermally coupled to the third sublayer of the TIBL facing the OIC side through a microchannel, the depth of which is 50-150μm; ELS, the ELS is connected to the input grating coupler of the OIC through an optical fiber array, the ELS includes multiple high-power CW DFB laser chips, the rated output power is greater than 100mW, and the linewidth is less than 1MHz; TEC is used to stably control the operating temperature of the CW DFB laser chip within the range of 25±0.5℃. A wavelength division multiplexer for multiplexing the output optical signals of multiple CW DFB laser chips to a single optical fiber, and a pluggable optical fiber connector. A four-domain collaborative control hub based on a hardware accelerator, comprising an FPGA, ASIC, or SoC, internally embeds a multivariate adaptive optimization algorithm based on model predictive control. The hardware accelerator communicates via a bus with the SOA gain adaptive adjustment unit, the TS-ICN, the micropump, and the temperature sensor array. The control logic of the MPC algorithm is implemented through the programmable logic array of the hardware accelerator, with control registers mapped to the physical pins of the hardware accelerator. The hardware accelerator is configured as follows: optical domain control employs a lookup table hard logic pass-through mechanism with a response time of less than 1 μs; electrical domain control employs rolling optimization of the MPC algorithm with an execution cycle of 10 μs; thermal domain control employs global optimization asynchronous execution of the MPC algorithm with a cycle of 1 ms; and reliability domain evaluation has a cycle of 1 s.

2. The optoelectronic co-packaging CPO structure based on four-domain synergy of optoelectronic-electrical-thermal-reliability as described in claim 1, characterized in that: The TIBL includes: The first sublayer, facing the ASIC side, is made of polyimide / aerogel composite material with a thermal conductivity k1 = 0.05-0.2 W / m·K and a thickness h1 = 10-30 μm; The second sublayer, the intermediate layer, is made of a gradient SiC / AlN composite material with a thermal conductivity ranging from kJ / k ... 2bottom =0.2W / m·K gradually changed to k 2top =50W / m·K, thickness h2=10-20μm; The third sublayer, facing the OIC side, is made of diamond nanosheets / silver paste composite material with thermal conductivity k3 > 500 W / m·K and thickness h3 = 5-10 μm. The DTHA includes: a heat sink material of CVD diamond or VACNT with a thermal conductivity greater than 1000 W / m·K; and a heat sink diameter d. DTH =3-10μm, height h DTH The thickness is equal to the sum of the thicknesses of the first and second sub-layers, and a 1-2 μm isolation gap is maintained between the top of the heat sink column and the bottom of the third sub-layer; the heat sink column density distribution function ρ(x,y)=ρ0·exp(-r 2 / 2σ 2 ), where r is the distance from the center of the SOA, σ = 20-50 μm, and ρ0 is the peak density directly below the SOA, with the density unit being μm. -2 The density of the DTHA directly below the SOA gain adaptive adjustment unit is in the ratio of 2:1 to 5:1 to the density directly below the high-speed optical modulator array.

3. The optoelectronic co-packaging CPO structure based on four-domain synergy of optoelectronic-electrical-thermal-reliability as described in claim 1, characterized in that: The TS-ICN includes: BST ferroelectric thin-film variable capacitor array, initial capacitance C0 = 0.1-2pF, temperature coefficient α C =-100 to -500 ppm / ℃, quality factor Q > 50 @ 56 GHz; NiFe thin film variable inductor array, initial inductance L0 = 0.2-2nH, temperature coefficient α L =-50 to -200ppm / ℃, quality factor Q>30@56GHz; A Pt thin-film temperature sensor array is integrated below the ground wire of the CPW transmission line, with a spacing of 50μm, an initial resistance R0=100Ω, a temperature coefficient TCR=3850ppm / ℃, and an accuracy of ±0.5℃. A resonance suppression grounding via array is disposed below the ground line of the CPW transmission line, with the via spacing being 1 / 20 to 1 / 10 of the signal wavelength, in order to suppress the parasitic resonance of the BST ferroelectric thin film and the NiFe thin film in the 56GHz frequency band. The TS-ICN is configured such that when the temperature changes by ΔT, the capacitance value of the variable capacitor changes by ΔC = α. C ·C0·ΔT, the change in inductance value of the variable inductor is ΔL=α L The changes in capacitance and inductance, denoted as L0ΔT, together compensate for the temperature drift of the characteristic impedance of the CPW transmission line, maintaining the characteristic impedance within the range of 50±2Ω.

4. The optoelectronic co-packaging CPO structure based on four-domain synergy of optoelectronic-electrical-thermal-reliability as described in claim 1, characterized in that: The hardware accelerator-based four-domain collaborative control center includes: Hardware accelerators, including FPGAs, ASICs, or SoCs, integrate processor cores and programmable logic arrays; The on-chip storage unit, including DDR memory and on-chip SRAM, is used to store the state space model and optimization parameters of the MPC algorithm; A high-speed ADC / DAC interface with a sampling rate greater than 1GSa / s is used to acquire the MPD-array, temperature sensor array, and RF S-parameters. The global optimization solution of the MPC algorithm is executed in parallel in the programmable logic array of the hardware accelerator. It adopts a quadratic programming solver, the solution time is less than 100μs, and the convergence accuracy objective function change rate is less than 0.01%.

5. The optoelectronic co-packaging CPO structure based on four-domain synergy of optoelectronic-electrical-thermal-reliability as described in any one of claims 1-4, characterized in that: Its adaptive management method has the following specific steps: S1. Obtain system status parameters, including the optical power P of each channel monitored by the MPD-array. i (t), the CPW temperature T monitored by the temperature sensor array CPW(t) and OIC temperature T OIC(t) and the current reactance value of the TS-ICN; S2. Input the system state parameters into the multiphysics coupling model. The multiphysics coupling model includes an optical power transmission model, a radio frequency signal transmission model, a heat conduction model, and a laser aging model. The state space matrices A, B, and E of the multiphysics coupling model are generated in real time based on the physical parameters of the OIC and ASIC through a system identification method or a finite element simulation order reduction method, and stored in the on-chip storage unit of the hardware accelerator. S3. Based on the multiphysics coupling model, the optimal control action is calculated by the model predictive control (MPC) algorithm embedded in the programmable logic array of the hardware accelerator. The optimal control action includes SOA gain adjustment ΔGᵢ, TS-ICN reactance adjustment ΔX, and coolant flow rate adjustment ΔQ. S4. Execute the optimal control action and monitor the execution effect through the MPD-array and temperature sensor array to form a closed-loop feedback; Steps S1-S4 are executed by programmable logic embedded in the hardware accelerator, which includes FPGA, ASIC or SoC. The mathematical operations of the MPC algorithm are implemented through the DSP hard core or LUT resources of the hardware accelerator. Control instructions are output to the SOA gain adaptive adjustment unit, the TS-ICN and the micro pump through the physical pins of the hardware accelerator. The optimization objective of the MPC algorithm is as follows: The constraint is: BER < 1e -12 ,P total <P max ,T max <85℃, RUL>10000h; The MPC algorithm includes: a state-space model x(k+1) = Ax(k) + Bu(k), where the state vector... Control vector The state space matrices A and B are obtained based on the physical parameters of the OIC and ASIC through system identification methods or finite element simulation order reduction methods. The matrix elements are updated in real time as the operating states of the OIC and ASIC change, with an update cycle of every 1000 control cycles; cost function Rolling optimization: Solve the finite-time optimization problem in each control cycle, execute only the first control action, and then solve it again in the next cycle; Feedback correction: Estimate the deviation between the actual state and the model's predicted state using a Kalman filter and correct the model parameters. The laser aging model includes: a threshold current aging model. , where Ith0 is the initial threshold current and τ1 is the aging time constant; Slope efficiency aging model , where η0 is the initial slope efficiency and τ2 is the degradation time constant; Remaining life prediction ,when > Time-triggered warning; cumulative thermal cycling damage model , where ΔTᵢ is the amplitude of the i-th temperature cycle, ΔT_ref is the reference temperature amplitude, m is the material fatigue index, and preventive maintenance is triggered when D>0.

7.

6. The optoelectronic co-packaging CPO structure based on four-domain synergy of optoelectronic-electrical-thermal-reliability as described in claim 5, characterized in that, The adaptive management method includes an online optimization layer based on (deep reinforcement learning) DRL, which performs nonlinear fine-tuning on the output of the MPC algorithm, and the DRL online optimization layer is embedded in the programmable logic array of the hardware accelerator; The DRL online optimization layer includes: The Actor network takes the system state s as input and outputs the action adjustment amount Δa. The network structure is a multilayer perceptron, with the number of hidden layer neurons decreasing layer by layer. The weight parameters of the Actor network are stored in the on-chip SRAM of the hardware accelerator. The Critic network takes state s and action a as input and outputs state-action value Q(s,a). The network structure is a multilayer perceptron with the number of hidden layer neurons decreasing layer by layer. The weight parameters of the Critic network are stored in the on-chip SRAM of the hardware accelerator. Reward function: ; The training methods include offline pre-training and online fine-tuning. The offline pre-training is performed on a high-performance computing cluster outside the hardware accelerator, and the trained network weights are burned into the on-chip SRAM through the configuration interface of the hardware accelerator.

7. The optoelectronic co-packaging CPO structure based on four-domain synergy of optoelectronic-electrical-thermal-reliability as described in any one of claims 1-4, characterized in that, Its manufacturing method includes the following steps: S1. Form a TSV via array on a silicon wafer using the DRIE process. The via diameter is 10-20μm and the depth is 100-300μm. S2. An insulating layer is deposited on the sidewall of the TSV via. The insulating layer material is SiO2 or SiN, and the thickness is 0.5-2μm. S3. Fill the TSV vias with copper electroplating and perform CMP planarization; S4. A microchannel coolant flow network is formed on the front side of the silicon wafer by photolithography and etching processes, with a flow channel depth of 50-150μm. S5. Deposition of TIBL, including spin-coating a polyimide / aerogel composite to form a first sublayer; forming a gradient SiC / AlN composite second sublayer by CVD; and spin-coating a diamond nanosheet / silver paste composite to form a third sublayer. S6. DTHA positioning holes are formed by laser drilling or photolithography etching, wherein the density distribution of the positioning holes follows a Gaussian function ρ(r) = ρ0·exp(-r 2 / 2σ 2 The density unit is μm. -2 Then, CVD diamond or vertically aligned carbon nanotubes are filled in, with the filling height controlled to leave a 1-2 μm isolation gap between the top of the DTHA and the bottom of the third sublayer. S7. Integrate a BST ferroelectric thin film variable capacitor and a NiFe thin film variable inductor below the ground wire of the CPW transmission line to form TS-ICN, and set a resonance suppression grounding via array below the ground wire of the CPW transmission line. S8. Bond the OIC to the TIBL using a Flip-Chip process; S9. Bond the ASIC chip to the other side of the silicon adapter plate using a hybrid bonding or thermo-press bonding process; S10. Align and couple the ELS to the grating coupler of the OIC via a pluggable fiber optic connector; S11. Integrate the hardware accelerator, MPD-array, and temperature sensor array, and embed the MPC algorithm and DRL online optimization layer into the programmable logic array of the hardware accelerator; S12. Perform hermetic sealing and aging tests.

8. The optoelectronic co-packaging CPO structure based on four-domain synergy of optoelectronic-thermal-reliability as described in any one of claims 1-4, characterized in that: A four-domain coupled transfer function model is used to describe the dynamic coupling relationships between the domains, including: Electro-thermal coupling transfer function: , where ΔZ CPW ΔP is the change in characteristic impedance of the CPW. ASIC K represents the change in ASIC power consumption. ET α is the electro-thermal coupling coefficient. T Let τ be the temperature coefficient of CPW. T The thermal time constant; Thermo-optical coupling transfer function: , where Δλ DFB ΔT represents the wavelength shift of the DFB laser. junction K represents the change in junction temperature. TO The thermal-optical coupling coefficient, τ is the temperature tuning coefficient of the laser. λ The photothermal time constant; Optical-electric coupling transfer function: Where ΔBER is the change in bit error rate, and ΔP optical K represents the change in optical power. OE The opto-electric coupling coefficient, τ represents the sensitivity of optical power to bit error rate. o The photoelectric response time constant; Reliability-thermal coupling transfer function: Where RUL represents the remaining useful life, and E... a The activation energy is given by k, Boltzmann constant is given by T, and absolute temperature is given by K. RT is the reliability-thermal coupling coefficient, and m is the material fatigue index.

9. The optoelectronic co-packaging CPO structure based on four-domain synergy of optoelectronic-thermal-reliability as described in any one of claims 1-4, characterized in that: The high-power CW DFB laser chip in the ELS uses an InP-based material system, with an output wavelength of 1310nm or 1550nm and a single-chip output power of 200-400mW. Multiple wavelengths are multiplexed into a single optical fiber using CW-WDM or DWDM technology. The optical fiber array is aligned with the optical waveguide of the OIC through edge coupling or grating coupling, with a coupling loss of less than 1.5dB.

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