Epitaxial structure, vcsel chip and manufacturing method thereof

Abstract

The application provides an epitaxial structure, a VCSEL chip and a manufacturing method thereof, wherein the epitaxial structure comprises: a substrate; an epitaxial stack arranged on the substrate, the epitaxial stack at least comprising: a second-type semiconductor layer, a first-type semiconductor layer, a first-type ohmic contact layer, a first-type DBR layer, an active region, an oxidation layer, a second-type DBR layer and a second-type ohmic contact layer; wherein the second-type semiconductor layer, the first-type semiconductor layer and the first-type ohmic contact layer can be used to form a PN junction protection area, and the second-type semiconductor layer, the first-type semiconductor layer, the first-type ohmic contact layer, the first-type DBR layer, the active region, the oxidation layer, the second-type DBR layer and the second-type ohmic contact layer can be used to form a VCSEL light-emitting area, so as to manufacture a VCSEL chip with a PN junction protection area, realize electrical over-stress (EOS) protection of the VCSEL chip, and simultaneously meet the miniaturization requirement of the device. The manufacturing method is simple, the preparation cost is low, and the method is convenient for large-scale production.

Description

Technical Field

[0001] This invention belongs to the field of optoelectronic device technology, and more specifically, relates to an epitaxial structure, a VCSEL chip, and a method for fabricating the same. Background Technology

[0002] A vertical-cavity surface-emitting laser (VCSEL) is a semiconductor laser in which the laser emission direction is perpendicular to the surface of a chip. Its internal structure includes distributed Bragg mirrors providing high reflectivity, an active region for laser generation, electrically and optically confined oxide layers, and a low-resistance ohmic contact layer. When a forward voltage is applied to the VCSEL, electrons are injected from the N-type region and holes from the P-type region. These recombine radiatively in the active region to produce photons. After multiple round trips through the Bragg mirrors on both sides, interference occurs, amplifying the number of photons exponentially, ultimately resulting in the vertically emitted laser beam.

[0003] Electrical overstress (EOS) refers to the phenomenon where electronic devices or chips are subjected to voltage or current exceeding their absolute maximum rated values. It is one of the main factors leading to field failures of integrated circuits. VCSEL chips typically have low forward operating voltages. When the applied voltage exceeds the normal operating voltage range of the VCSEL chip, the VCSEL chip will experience irreversible electrical overstress failure, resulting in complete failure and reduced product yield.

[0004] Therefore, how to design a chip structure with EOS protection function under low voltage inside a VCSEL chip has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of this, the present invention provides an epitaxial structure, a VCSEL chip, and a method for manufacturing the same, to solve the problem that when the applied voltage exceeds the normal range of the VCSEL chip's operating voltage, the VCSEL chip will experience irreversible electrical overstress failure, resulting in complete failure of the VCSEL chip and a decrease in product yield.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] An epitaxial structure, characterized in that the epitaxial structure comprises:

[0008] Substrate;

[0009] An epitaxial stack disposed on the substrate includes at least the following layers stacked from bottom to top on the substrate: a second type semiconductor layer, a first type semiconductor layer, a first type ohmic contact layer, a first type DBR layer, an active region, an oxide layer, a second type DBR layer, and a second type ohmic contact layer.

[0010] Preferably, the substrate includes an insulating material layer, and the first type semiconductor layer, the second type semiconductor layer, and the substrate are layers of the same material family, and the epitaxial stack is obtained on the substrate by a single epitaxial layer.

[0011] Preferably, one of the first type semiconductor layer and the second type semiconductor layer is an N-type semiconductor layer and the other is a P-type semiconductor layer, and the first type semiconductor layer and the second type semiconductor layer form a homogeneous PN junction.

[0012] Preferably, the thickness of both the first type semiconductor layer and the second type semiconductor layer is in the range of 10nm-1000nm, including the endpoint values.

[0013] Preferably, the first type ohmic contact layer and the second type ohmic contact layer are made of the same material family as the substrate, and both the first type ohmic contact layer and the second type ohmic contact layer are heavily doped layers.

[0014] Preferably, the first type semiconductor layer, the first type ohmic contact layer, and the first type DBR layer have the same doping type, and the substrate, the second type semiconductor layer, the oxide layer, the second type DBR layer, and the second type ohmic contact layer have the same doping type.

[0015] The present invention also provides a VCSEL chip, characterized in that the VCSEL chip comprises:

[0016] The epitaxial structure described in any of the above-mentioned methods is adopted;

[0017] The epitaxial stack includes a first region and a second region. The surface portion of the first region is a first mesa on the side of the first type ohmic contact layer facing away from the substrate, and a portion is a second mesa on the side of the second type ohmic contact layer facing away from the substrate. The surface portion of the second region is a third mesa on the side of the second type semiconductor layer facing away from the substrate, and a portion is a fourth mesa on the side of the first type ohmic contact layer facing away from the substrate.

[0018] The first electrode assembly is disposed on the first region and forms a VCSEL light-emitting region with the epitaxial stack corresponding to the first region.

[0019] The second electrode assembly is disposed on the second region and forms a PN junction protection zone with the epitaxial stack corresponding to the second region;

[0020] The VCSEL light-emitting region and the PN junction protection region are spaced apart, and the VCSEL light-emitting region and the PN junction protection region are connected in parallel.

[0021] Preferably, the substrate has an exposed surface on the side facing the epitaxial stack to form an isolation region, and the VCSEL light-emitting region and the PN junction protection region are separated by the isolation region;

[0022] The first electrode assembly includes a first electrode and a second electrode, wherein the first electrode is located on the first mesa and the second electrode is located on the second mesa;

[0023] The second electrode assembly includes a third electrode and a fourth electrode, wherein the third electrode is located on the third mesa and the fourth electrode is located on the fourth mesa;

[0024] The first electrode and the second electrode have opposite polarities, and the first electrode and the fourth electrode have the same polarity, while the second electrode and the third electrode have the same polarity.

[0025] Preferably, when the barrier height of the second type semiconductor layer remains constant, the protection voltage of the PN junction protection zone decreases as the barrier height of the first type semiconductor layer increases;

[0026] or,

[0027] When the barrier height of the first type of semiconductor layer remains constant, the protection voltage of the PN junction protection zone decreases as the barrier height of the second type of semiconductor layer increases.

[0028] Preferably, the barrier heights of both the first type semiconductor layer and the second type semiconductor layer are in the range of 1.41 eV-1.59 eV, including the endpoint values;

[0029] Alternatively, the doping concentration range of both the first type semiconductor layer and the second type semiconductor layer is 1E18cm. -3 -1E21cm -3 This includes endpoint values.

[0030] Preferably, the VCSEL chip further includes an insulating protective layer, a first metal interconnection line, and a second metal interconnection line;

[0031] The insulating protective layer covers the exposed surfaces of the VCSEL light-emitting area, the PN junction protection area, and the isolation area, and exposes the first electrode assembly and the second electrode assembly; the first metal connecting wire connects the first electrode of the VCSEL light-emitting area and the fourth electrode of the PN junction protection area through the surface of the insulating protective layer; the second metal connecting wire connects the second electrode of the VCSEL light-emitting area and the third electrode of the PN junction protection area through the surface of the insulating protective layer, and the first metal connecting wire and the second metal connecting wire are mutually insulated.

[0032] Preferably, the VCSEL light-emitting area includes multiple light-emitting units arranged in an array, and the light-emitting units are connected in parallel.

[0033] This invention also provides a method for manufacturing a VCSEL chip, characterized by comprising:

[0034] Step 1: Fabricate the epitaxial structure;

[0035] Specifically, a substrate is provided, and an epitaxial stack is formed on the substrate by an epitaxial process. The epitaxial stack includes at least a second type semiconductor layer, a first type semiconductor layer, a first type ohmic contact layer, a first type DBR layer, an active region, an oxide layer, a second type DBR layer, and a second type ohmic contact layer stacked sequentially along the growth direction.

[0036] Step 2: Etch the epitaxial stack and fabricate the first electrode assembly and the second electrode assembly to form a VCSEL chip;

[0037] Specifically, through an etching process, the epitaxial stack is made to have a first region and a second region. The surface portion of the first region is a first mesa on the side of the first type ohmic contact layer facing away from the substrate, and a portion is a second mesa on the side of the second type ohmic contact layer facing away from the substrate. The surface portion of the second region is a third mesa on the side of the second type semiconductor layer facing away from the substrate, and a portion is a fourth mesa on the side of the first type ohmic contact layer facing away from the substrate.

[0038] A first electrode assembly is fabricated in the first region, and its epitaxial stack with the first region constitutes the VCSEL light-emitting region; a second electrode assembly is fabricated in the second region, and its epitaxial stack with the second region constitutes the PN junction protection zone.

[0039] The VCSEL light-emitting region and the PN junction protection region are spaced apart, and the VCSEL light-emitting region and the PN junction protection region are connected in parallel.

[0040] By employing the above technical solution, this application provides an epitaxial structure, a VCSEL chip, and a method for fabricating the same. The epitaxial structure includes: a substrate; and an epitaxial stack disposed on the substrate, the epitaxial stack including at least: a second-type semiconductor layer, a first-type semiconductor layer, a first-type ohmic contact layer, a first-type DBR layer, an active region, an oxide layer, a second-type DBR layer, and a second-type ohmic contact layer. The second-type semiconductor layer, the first-type semiconductor layer, and the first-type ohmic contact layer can be used to form a PN junction protection zone. These layers can also be used to form the VCSEL light-emitting region, thereby fabricating a VCSEL chip with a PN junction protection zone, achieving electrical overstress (EOS) protection for the VCSEL chip, and simultaneously meeting the requirements for device miniaturization. The fabrication is simple, the preparation cost is low, and it is easy to mass-produce. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of an epitaxial structure provided in an embodiment of the present invention;

[0043] Figure 2 This is a schematic diagram of the structure of a VCSEL chip provided in an embodiment of the present invention;

[0044] Figure 3 This is a schematic diagram of another VCSEL chip provided in an embodiment of the present invention;

[0045] Figure 4 for Figure 3 A top view of the VCSEL chip;

[0046] Figure 5 This is a schematic diagram of the structure of another VCSEL chip provided in an embodiment of the present invention;

[0047] Figure 6 A flowchart illustrating a method for fabricating a VCSEL chip according to an embodiment of the present invention;

[0048] Figure 7 A flowchart illustrating another method for fabricating a VCSEL chip according to an embodiment of the present invention;

[0049] Figures 8 to 9 for Figure 7 The diagram shows the structural schematics corresponding to each step of the manufacturing process.

[0050] Explanation of symbols in the diagram:

[0051] AA', VCSEL light-emitting preset area; AA, first region; BB', PN junction protection preset area; BB, second region; CC', isolation preset area; CC, isolation area; G, channel; T1, first mesa; T2, second mesa; T3, third mesa; T4, fourth mesa;

[0052] 1. Substrate; 2. Type I DBR layer; 3. Type II DBR layer; 4. Active region; 5. First set of electrode structures; 51. First electrode; 52. Second electrode; 52a. Contact electrode; 52b. Pad electrode; 6. Second set of electrode structures; 61. Third electrode; 62. Fourth electrode; 7. Insulating protective layer; 8. First metal interconnect; 9. Second metal interconnect; 10. Light-emitting unit; 11. Type I semiconductor layer; 12. Type II semiconductor layer; 70. Type I ohmic contact layer; 80. Type II ohmic contact layer; 90. Oxide layer; 90a. Conductive channel. Detailed Implementation

[0053] To make the content of this invention clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0054] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0055] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0056] In view of this, the embodiments of this application provide an extensional structure, such as Figure 1 As shown, the epitaxial structure includes:

[0057] Substrate 1;

[0058] An epitaxial stack disposed on a substrate 1 includes at least the following layers stacked on the substrate 1 from bottom to top: a second type semiconductor layer 12, a first type semiconductor layer 11, a first type ohmic contact layer 70, a first type DBR layer 2, an active region 4, an oxide layer 90, a second type DBR layer 3, and a second type ohmic contact layer 80.

[0059] It should be noted that the epitaxial structure provided in this embodiment includes: a substrate 1, and an epitaxial stack disposed on the substrate 1. The epitaxial stack includes at least: a second type semiconductor layer 12, a first type semiconductor layer 11, a first type ohmic contact layer 70, a first type DBR layer 2, an active region 4, an oxide layer 90, a second type DBR layer 3, and a second type ohmic contact layer 80, which are sequentially stacked on the substrate 1 from bottom to top. The second type semiconductor layer 12, the first type semiconductor layer 11, and the first type ohmic contact layer 70 can be used to form a PN junction protection zone. The second type semiconductor layer 12, the first type semiconductor layer 11, the first type ohmic contact layer 70, the first type DBR layer 2, the active region 4, the oxide layer 90, the second type DBR layer 3, and the second type ohmic contact layer 80 can be used to form a VCSEL light-emitting region for fabricating a VCSEL chip with a PN junction protection zone, thereby achieving electrical overstress (EOS) protection for the VCSEL chip and simultaneously meeting the requirements for device miniaturization.

[0060] Based on the above embodiments, in an optional embodiment of this application, the substrate 1 includes an insulating material layer, and the first type semiconductor layer 11, the second type semiconductor layer 12 and the substrate 1 are material layers of the same family. An epitaxial stack is obtained on the substrate 1 by a single epitaxial layer.

[0061] It should be noted that in this embodiment, the first type semiconductor layer 11 and the second type semiconductor layer 12 are materials of the same family as the substrate 1. Materials of the same family have similar lattice constants, which can reduce the lattice mismatch between the first type semiconductor layer 11 and the second type semiconductor layer 12 and the substrate 1, reduce the dislocation density, and provide a high-quality template for subsequent multilayer growth. In addition, materials of the same family have similar coefficients of thermal expansion, which can effectively prevent thermal stress cracking during the cooling process, thereby allowing for direct epitaxial growth in a single step to obtain an epitaxial stack. Furthermore, single-step epitaxy refers to performing only one epitaxial growth on the substrate to form the required epitaxial stack. Using a single-step epitaxy method can simplify the material preparation process and lay the foundation for the monolithic integration of VCSEL chips with PN junction protected areas.

[0062] Optionally, the resistivity of substrate 1 is greater than 1×10⁻⁶. 7 Ω·cm.

[0063] Optionally, the insulating material of the substrate 1 includes, but is not limited to, one of gallium arsenide, indium phosphide, gallium nitride, and sapphire (aluminum oxide).

[0064] Optionally, the second type semiconductor layer 12 and the substrate 1 have the same doping type and doping atoms.

[0065] Based on the above embodiments, in an optional embodiment of this application, one of the first semiconductor layer 11 and the second semiconductor layer 12 is an N-type semiconductor layer and the other is a P-type semiconductor layer, and the first semiconductor layer 11 and the second semiconductor layer 12 form a homogeneous PN junction.

[0066] It should be noted that this embodiment does not limit the specific doping type of the first type semiconductor layer 11 and the second type semiconductor layer 12. The doping types of the first type semiconductor layer 11 and the second type semiconductor layer 12 are opposite. One of the first type semiconductor layer 11 and the second type semiconductor layer 12 is an N-type semiconductor layer and the other is a P-type semiconductor layer. The first type semiconductor layer 11 and the second type semiconductor layer 12 form a homogeneous PN junction. That is, the first type semiconductor layer 11 and the second type semiconductor layer 12 are PN junctions formed by the same material with opposite doping types, which provides a basis for forming a PN junction protection zone.

[0067] Based on the above embodiments, in an optional embodiment of this application, the thickness range of both the first type semiconductor layer 11 and the second type semiconductor layer 12 is 10nm-1000nm, including the endpoint values.

[0068] It should be noted that in this embodiment, by setting the thickness range of both the first type semiconductor layer 11 and the second type semiconductor layer 12 to 10nm-1000nm, including the endpoint values, dislocations can be prevented from climbing upwards, thereby further improving the crystal quality of subsequent functional layers.

[0069] Optionally, N-type doping elements include silicon, tellurium, or selenium; P-type doping elements include zinc, carbon, magnesium, or beryllium.

[0070] It should be noted that N-type doping involves adding elements that provide freely movable electrons to semiconductor materials; while P-type doping involves adding elements that provide freely movable holes to semiconductor materials.

[0071] Based on the above embodiments, in an optional embodiment of this application, the materials of the first type semiconductor layer 11 and the second type semiconductor layer 12 both include one or more of binary compound semiconductors, ternary compound semiconductors, and quaternary compound semiconductors composed of group III-V elements.

[0072] Optionally, binary compound semiconductors include, but are not limited to, one or more of GaAs, GaN, and InP.

[0073] Optionally, the ternary compound semiconductor is a semiconductor material composed of any three elements Al, Ga, As, P, In, Ga, and N in a certain proportion, including but not limited to one or more of AlGaAs and InGaAs.

[0074] Optionally, the quaternary compound semiconductor is a semiconductor material composed of any four elements Al, Ga, As, P, In, Ga, and N in a certain proportion, including but not limited to one or more of AlGaInP and AlGaAsP.

[0075] Based on the above embodiments, in an optional embodiment of this application, the first type ohmic contact layer 70 and the second type ohmic contact layer 80 are materials of the same family as the substrate 1, and both the first type ohmic contact layer 70 and the second type ohmic contact layer 80 are heavily doped layers.

[0076] It should be noted that in this embodiment, by setting both the first type ohmic contact layer 70 and the second type ohmic contact layer 80 to be heavily doped layers, the contact interface between the first type ohmic contact layer 70 and the second type ohmic contact layer 80 and the electrode structure of the subsequently formed VCSEL light-emitting region forms a low resistance, which enables the VCSEL light-emitting region to achieve efficient current injection.

[0077] In an optional embodiment of this application, the thickness range of both the first type ohmic contact layer 70 and the second type ohmic contact layer 80 is 5nm-1500nm, including the endpoint values.

[0078] In an optional embodiment of this application, the barrier heights of both the first ohmic contact layer and the second ohmic contact layer are in the range of 1.47eV-1.59eV, including the endpoint values.

[0079] In an optional embodiment of this application, the doping concentration range of both the first type ohmic contact layer 70 and the second type ohmic contact layer 80 is 1E19cm. -3 -1E21cm -3 This includes endpoint values. It avoids significant impedance phenomena at the contact interfaces of electrodes located on the first type of ohmic contact layer 70 and electrodes located on the second type of ohmic contact layer 80.

[0080] Based on the above embodiments, in an optional embodiment of this application, the first type semiconductor layer 11, the first type ohmic contact layer 70, and the first type DBR layer 2 have the same doping type, and the substrate 1, the second type semiconductor layer 12, the oxide layer 90, the second type DBR layer 3, and the second type ohmic contact layer 80 have the same doping type.

[0081] It should be noted that in this embodiment, the second type semiconductor layer 12 is formed on the upper surface of the substrate 1, and the two have the same doping type, which is more conducive to the formation of high-quality crystals.

[0082] In an optional embodiment of this application, the first type semiconductor layer 11 is an N-type semiconductor layer, the first type ohmic contact layer 70 is an N-type ohmic contact layer, and the first type DBR layer 2 is an N-type DBR layer;

[0083] Substrate 1 is a P-type substrate, second type semiconductor layer 12 is a P-type semiconductor layer, oxide layer 90 is a P-type oxide layer, second type DBR layer 3 is a P-type DBR layer, and second type ohmic contact layer 80 is a P-type ohmic contact layer.

[0084] In an optional embodiment of this application, the substrate 1 is a P-type gallium arsenide insulating substrate, and the P-type doping element is carbon; the thickness of the second type semiconductor layer 12 and the first type semiconductor layer 11 is 500 nm; the second type semiconductor layer 12 is a P-type gallium arsenide layer, and the doping element is carbon; the first type semiconductor layer 11 is an N-type gallium arsenide layer, and the doping element is silicon.

[0085] In an optional embodiment of this application, the first type ohmic contact layer 70 is an N-type gallium arsenide layer, with silicon atoms as the doping element and a doping concentration of 5E19cm⁻¹. -3 The barrier height is 1.52V and the thickness is 500nm;

[0086] The second-type ohmic contact layer 80 is a p-type gallium arsenide layer doped with carbon atoms at a doping concentration of 7E19cm⁻¹. -3 The barrier height is 1.52V and the thickness is 20nm.

[0087] In an optional embodiment of this application, the DBR structure is a periodic structure consisting of alternating stacks of two materials with different refractive indices. Both the first type DBR layer 2 and the second type DBR layer 3 have high refractive index layers comprising Al. 0.1 Ga 0.9 Both the As layer and the low refractive index layer include Al. 0.9 Ga 0.1 As layer, where (0≤x≤1);

[0088] The thicknesses of the high-refractive-index layer and the low-refractive-index layer of the first type DBR layer 2 and the second type DBR layer 3 should satisfy the formula λ / (4n), where λ is the lasing wavelength and n is the optical refractive index of the corresponding DBR material layer.

[0089] For example, the thickness of the high refractive index layer is 59.7635 nm; the thickness of the low refractive index layer is 69.8341 nm.

[0090] The doping concentration of the first type DBR layer 2 and the second type DBR layer 3 is set at 5E17cm. -3 -2E18cm -3Among them, the first type DBR layer 2 is N-type doped, using silicon atom doping, with 38 alternating stacked periods, achieving a reflectivity of 99.9%; the second type DBR layer 3 is P-type doped, using carbon atom doping, with 19 alternating stacked periods, achieving a reflectivity of 99.3%.

[0091] In one optional embodiment of this application, the active region 4 is a periodic structure composed of a barrier layer and a quantum well, and both the start layer and the end layer are barrier layers, the barrier layers including Al 0.2 Ga 0.8 As layer, quantum well includes In 0.08 Ga 0.92 The As layer has a total thickness of 5.7 nm, the quantum well layer has a total thickness of 6.2 nm, and the active region has 4 alternating stacked cycles of 3 pairs. For example, a multilayer structure of barrier layer / quantum well layer / barrier layer / quantum well layer / barrier layer / quantum well layer / barrier layer / quantum well layer / barrier layer can be formed by setting 3 quantum wells and 4 barrier layers.

[0092] In one optional embodiment of this application, the oxide layer 90 is a p-type oxide layer, and the material of the oxide layer 90 includes Al. 0.98 Ga 0.02 As, the doping element is carbon, and the doping concentration is 1E18cm. -3 The thickness is 20nm.

[0093] This application provides a VCSEL chip, such as... Figure 2 As shown, the VCSEL chip includes:

[0094] Adopting any of the above extensional structures;

[0095] The epitaxial stack includes a first region AA and a second region BB. The surface portion of the first region AA is a first mesa T1 of the first type ohmic contact layer 70 facing away from the substrate 1, and a portion is a second mesa T2 of the second type ohmic contact layer 80 facing away from the substrate 1. The surface portion of the second region BB is a third mesa T3 of the second type semiconductor layer 12 facing away from the substrate 1, and a portion is a fourth mesa T4 of the first type ohmic contact layer 70 facing away from the substrate 1.

[0096] The first set of electrode structures 5 is disposed on the first region AA and forms a VCSEL light-emitting area with the epitaxial stack corresponding to the first region AA.

[0097] The second set of electrode structures 6 is disposed on the second region BB and forms a PN junction protection zone with the epitaxial stack corresponding to the second region BB.

[0098] The VCSEL light-emitting region and the PN junction protection region are spaced apart, and the VCSEL light-emitting region and the PN junction protection region are connected in parallel.

[0099] It should be noted that the VCSEL chip provided in this embodiment adopts any of the above-mentioned epitaxial structures. In this embodiment, the epitaxial stack corresponding to the first region AA of the first group of electrode structures 5 constitutes the VCSEL light-emitting region, and the epitaxial stack corresponding to the second region BB of the second group of electrode structures 6 constitutes the PN junction protection region. The VCSEL light-emitting region and the PN junction protection region are connected in parallel. The VCSEL light-emitting region and the PN junction protection region are integrated into the same chip. In the DC forward drive application of the VCSEL chip, after the VCSEL chip is connected to the working power supply, when the working voltage is within the normal voltage range of the VCSEL chip, the PN junction protection region does not work. When the voltage exceeds the normal range of the working voltage of the VCSEL chip, the PN junction protection region will instantly become a low-impedance path, bypassing the current, that is, allowing the current to flow through the PN junction protection region, thereby protecting the VCSEL light-emitting region, so as to realize the electrical overstress (EOS) protection of the VCSEL chip, and at the same time meet the requirements of device miniaturization.

[0100] It should also be noted that the epitaxial stack corresponding to the first region AA includes: a second type semiconductor layer 12, a first type semiconductor layer 11, a first type ohmic contact layer 70, a first type DBR layer 2, an active region 4, an oxide layer 90, a second type DBR layer 3, and a second type ohmic contact layer 80; the epitaxial stack corresponding to the first region AA includes: a second type semiconductor layer 12, a first type semiconductor layer 11, and a first type ohmic contact layer 70.

[0101] Based on the above embodiments, in an optional embodiment of this application, reference is made to... Figure 2 As shown, the side of the substrate 1 facing the epitaxial stack has an exposed surface to form an isolation region CC. The VCSEL light-emitting region and the PN junction protection region are spaced apart by the isolation region CC.

[0102] The first set of electrode structures 5 includes a first electrode 51 and a second electrode 52. The first electrode 51 is located on the first mesa T1, and the second electrode 52 is located on the second mesa T2.

[0103] The second set of electrode structures 6 includes a third electrode 61 and a fourth electrode 62. The third electrode 61 is located on the third mesa T3, and the fourth electrode 62 is located on the fourth mesa T4.

[0104] The first electrode 51 and the second electrode 52 have opposite polarities, and the first electrode 51 and the fourth electrode 62 have the same polarity, while the second electrode 52 and the third electrode 62 have the same polarity.

[0105] It should be noted that in this embodiment, the isolation region CC completely isolates the VCSEL light-emitting region and the PN junction protection region, preventing short circuits caused by current flowing between the two regions. Specifically, in the VCSEL light-emitting region, the first electrode 51 is located on the first mesa T1, i.e., the first electrode 51 is formed on the first type ohmic contact layer 70 and is electrically connected to the first type DBR layer 2 through the first type ohmic contact layer 70; the second electrode 52 is located on the second mesa T2, i.e., the second electrode 52 is formed on the second type ohmic contact layer 80 and is electrically connected to the second type DBR layer 3 through the second type ohmic contact layer 80.

[0106] Optionally, in some embodiments, the substrate 1 of the isolation region CC has a groove extending away from the epitaxial stack direction.

[0107] In an optional embodiment of this application, the forward operating voltage of the VCSEL light-emitting region is 1.5V-3V, including the endpoint value; the protection voltage range of the PN junction protection region is 2.5V-5V, including the endpoint value, and the protection voltage of the PN junction protection region is greater than the forward operating voltage of the VCSEL light-emitting region.

[0108] It should be noted that the forward operating voltage of a single-junction VCSEL chip (meaning that a single light-emitting unit has only one active region) is usually between 1.5V and 3V. A PN junction protection zone is connected in parallel to the forward light-emitting region of the VCSEL. The protection voltage range of the PN junction protection zone is 2.5V to 5V, including the endpoint value. At the same time, the protection voltage of the PN junction protection zone must be greater than the forward operating voltage of the VCSEL light-emitting region.

[0109] Based on the above embodiments, in an optional embodiment of this application, when the barrier height of the second type semiconductor layer 12 remains unchanged, the protection voltage of the PN junction protection zone decreases as the barrier height of the first type semiconductor layer 11 increases.

[0110] Alternatively, when the barrier height of the first type semiconductor layer 11 remains constant, the protection voltage of the PN junction protection zone decreases as the barrier height of the second type semiconductor layer 12 increases.

[0111] It should be noted that in this embodiment, when the barrier height of the second type semiconductor layer 12 remains unchanged, the magnitude of the protection voltage of the PN junction protection zone can be adjusted by controlling the barrier height of the first type semiconductor layer 11 in the PN junction protection zone. Alternatively, when the barrier height of the first type semiconductor layer 11 remains unchanged, the magnitude of the protection voltage of the PN junction protection zone can be adjusted by controlling the barrier height of the second type semiconductor layer 11 in the PN junction protection zone. This achieves electrical overstress (EOS) protection for the VCSEL chip without affecting the luminous efficiency of the VCSEL light-emitting region.

[0112] Based on the above embodiments, in an optional embodiment of this application, the barrier height of the first type semiconductor layer 11 increases with the increase of the doping concentration of the first type semiconductor layer 11, and when the barrier height of the second type semiconductor layer 12 remains unchanged, the protection voltage of the PN junction protection zone decreases with the increase of the barrier height of the first type semiconductor layer 11.

[0113] or,

[0114] The barrier height of the second type semiconductor layer 12 increases with the increase of the doping concentration of the second type semiconductor layer 12. When the barrier height of the first type semiconductor layer 11 remains unchanged, the protection voltage of the PN junction protection zone decreases with the increase of the barrier height of the second type semiconductor layer 12.

[0115] It should be noted that in this embodiment, the barrier height of the first type semiconductor layer 11 in the PN junction protection zone can be controlled by adjusting the doping concentration of the first type semiconductor layer 11. When the barrier height of the second type semiconductor layer 12 remains unchanged, the magnitude of the protection voltage of the PN junction protection zone can be adjusted by controlling the barrier height of the first type semiconductor layer 11 in the PN junction protection zone.

[0116] Alternatively, the barrier height of the second type semiconductor layer 12 in the PN junction protection zone can be controlled by adjusting the doping concentration of the second type semiconductor layer 12. When the barrier height of the first type semiconductor layer 11 remains unchanged, the protection voltage of the PN junction protection zone can be adjusted by controlling the barrier height of the second type semiconductor layer 12 in the PN junction protection zone.

[0117] Based on the above embodiments, in an optional embodiment of this application, the barrier height range of the first type semiconductor layer 11 and the second type semiconductor layer 12 is 1.41eV-1.59eV, including the endpoint value.

[0118] In another optional embodiment of this application, the doping concentration range of both the first type semiconductor layer 11 and the second type semiconductor layer 12 is 1E18cm. -3 -1E21cm -3 This includes endpoint values;

[0119] The barrier heights of both the first type semiconductor layer 11 and the second type semiconductor layer 12 range from 1.41 eV to 1.59 eV, including the endpoint values.

[0120] It should be noted that, in this embodiment, the doping concentration range of both the first type semiconductor layer 11 and the second type semiconductor layer 12 is set to 1E18cm. -3 -1E21cm -3Including the endpoint value, a higher doping concentration is used to ensure that the first type semiconductor layer 11 and the second type semiconductor layer 12 maintain good conductivity in the PN junction protection zone, ensuring that the PN junction protection zone can quickly and with low loss conduction during overvoltage, thereby efficiently shunting the overcurrent and protecting the VCSEL light-emitting area from being burned out. At the same time, the doping concentration range is controlled to avoid tunneling leakage and dopant diffusion.

[0121] In one optional embodiment of this application, the barrier height of the first type semiconductor layer 11 in the PN junction protection zone is controlled by adjusting the doping concentration of the first type semiconductor layer 11, while the barrier height of the second type semiconductor layer 12 remains unchanged. The magnitude of the protection voltage of the PN junction protection zone is adjusted by controlling the barrier height of the first type semiconductor layer 11 in the PN junction protection zone.

[0122] Please refer to Table 1 below, which shows the barrier height of the first type semiconductor layer 11 and the protection voltage of the PN junction protection zone at different doping concentrations.

[0123] Table 1:

[0124]

[0125] The data above shows that the barrier height of the first type semiconductor layer 11 increases with the increase of the doping concentration of the first type semiconductor layer 11, while the PN junction protection zone decreases with the increase of the barrier height of the first type semiconductor layer 11. For example, the doping concentration of the first type semiconductor layer 11 is 1E20cm⁻¹. -3 With a barrier height of 1.53V, the protection voltage of the PN junction protection zone of the VCSEL chip is 2.8V. That is, when the forward voltage applied to the VCSEL chip exceeds 2.8V, no current will flow through the VCSEL light-emitting area, and the current will flow through the PN junction protection zone, thus protecting the VCSEL light-emitting area.

[0126] In one optional embodiment of this application, the first electrode 51 and the fourth electrode 62 are both N-type electrodes, and the second electrode 52 and the third electrode 61 are P-type electrodes.

[0127] In another optional embodiment of this application, the first type semiconductor layer 11 is a P-type semiconductor layer, the first type ohmic junction layer is a P-type ohmic contact layer, and the first type DBR layer 2 is a P-type DBR layer;

[0128] Substrate 1 is an N-type substrate, second type semiconductor layer 12 is an N-type semiconductor layer, oxide layer 90 is an N-type oxide layer, second type DBR layer 3 is an N-type DBR layer, and second type ohmic contact layer 80 is an N-type ohmic contact layer.

[0129] The first electrode 51 and the fourth electrode 62 are both P-type electrodes, while the second electrode 52 and the third electrode 61 are N-type electrodes.

[0130] Based on the above embodiments, in an optional embodiment of this application, the material of the N-type electrode includes, but is not limited to, one or more stacks of Ge, Ni, and Au;

[0131] The materials for P-type electrodes include, but are not limited to, one or more stacks of Ti, Pt, and Au.

[0132] Based on the above embodiments, in an optional embodiment of this application, such as Figure 3 , Figure 4 As shown, the VCSEL chip also includes an insulating protective layer 7, a first metal connection line 8, and a second metal connection line 9;

[0133] The insulating protective layer 7 covers the exposed surfaces of the VCSEL light-emitting area, PN junction protection area, and isolation area CC, and exposes the first set of electrode structures 5 and the second set of electrode structures 6; in order to protect the VCSEL chip and prevent the device from short-circuiting and the device surface from being scratched and contaminated by impurities.

[0134] The first metal connecting line 8 connects the first electrode 51 of the VCSEL light-emitting area and the fourth electrode 62 of the PN junction protection area through the surface of the insulating protective layer 7; the second metal connecting line 9 connects the second electrode 52 of the VCSEL light-emitting area and the third electrode 61 of the PN junction protection area through the surface of the insulating protective layer 7, and the first metal connecting line 8 and the second metal connecting line 9 are insulated from each other.

[0135] Based on the above embodiments, in an optional embodiment of this application, reference is made to... Figure 3 As shown, the second electrode 52 includes a contact electrode 52a and a pad electrode 52b stacked sequentially in a direction away from the epitaxial stack. The insulating protective layer 7 has a through hole that exposes the contact electrode 52a, and the pad electrode 52b is connected to the contact electrode 52a through the through hole.

[0136] Based on the above embodiments, in an optional embodiment of this application, such as Figure 5 As shown, the VCSEL light-emitting area includes multiple light-emitting units 10 arranged in an array, and the light-emitting units 10 are connected in parallel.

[0137] It should be noted that in this embodiment, the parallel connection between multiple light-emitting units 10 in the VCSEL light-emitting region will not affect the overall operating voltage of the VCSEL light-emitting region. Therefore, the protection voltage of the PN junction protection zone can still be adjusted by controlling the barrier height of the first type semiconductor layer 11 in the PN junction protection zone.

[0138] Alternatively, the barrier height of the first type semiconductor layer 11 in the PN junction protection zone can be controlled by adjusting the doping concentration of the first type semiconductor layer 11, and the protection voltage of the PN junction protection zone can be adjusted by controlling the barrier height of the first type semiconductor layer 11 in the PN junction protection zone.

[0139] Based on the above embodiments of this application, another embodiment of this application also provides a method for fabricating a VCSEL chip, referencing... Figure 6 , Figure 6 This is a flowchart illustrating a method for fabricating a VCSEL chip according to an embodiment of the present invention. The method for fabricating a VCSEL chip according to this embodiment includes:

[0140] Step 1: Fabricate the epitaxial structure;

[0141] For details, please refer to Figure 1 As shown, a substrate 1 is provided, and an epitaxial stack is formed on the substrate 1 by an epitaxial process. The epitaxial stack includes at least a second type semiconductor layer 12, a first type semiconductor layer 11, a first type ohmic contact layer 70, a first type DBR layer 2, an active region 4, an oxide layer 90, a second type DBR layer 3 and a second type ohmic contact layer 80, which are sequentially stacked along the growth direction.

[0142] Step 2: Etch the epitaxial stack and fabricate the first set of electrode structures 5 and the second set of electrode structures 6 to form a VCSEL chip;

[0143] For details, please refer to Figure 2 As shown, through an etching process, the epitaxial stack has a first region AA and a second region BB. The surface portion of the first region AA is the first mesa T1 of the surface of the first type ohmic contact layer 70 facing away from the substrate 1, and the second mesa T2 of the surface of the second type ohmic contact layer 80 facing away from the substrate 1. The surface portion of the second region BB is the third mesa T3 of the surface of the second type semiconductor layer 12 facing away from the substrate 1, and the fourth mesa T4 of the surface of the first type ohmic contact layer 70 facing away from the substrate 1.

[0144] In the first region AA, a first set of electrode structures 5 is fabricated, and the epitaxial stack corresponding to the first region AA forms the VCSEL light-emitting region; in the second region BB, a second set of electrode structures 6 is fabricated, and the epitaxial stack corresponding to the second region BB forms the PN junction protection zone.

[0145] The VCSEL light-emitting region and the PN junction protection region are spaced apart, and the VCSEL light-emitting region and the PN junction protection region are connected in parallel.

[0146] It should be noted that the VCSEL chip formed by the VCSEL chip fabrication method provided in this embodiment can achieve the beneficial effects of the VCSEL chip mentioned above. At the same time, it can directly obtain epitaxial stacks through epitaxial growth in one step, simplify the material preparation process, and realize the monolithic integrated fabrication of the VCSEL light-emitting region and the PN junction protection region on the same substrate 1. The fabrication is simple and convenient, easy to mass-produce, and does not increase the additional device fabrication cost.

[0147] Based on the above embodiments, in an optional embodiment of this application, the substrate 1 includes an insulating material layer, and the first type semiconductor layer 11, the second type semiconductor layer 12 and the substrate 1 are material layers of the same family.

[0148] Optionally, the resistivity of substrate 1 is greater than 1×10⁻⁶. 7 Ω·cm.

[0149] Optionally, the insulating material of the substrate 1 includes, but is not limited to, one of gallium arsenide, indium phosphide, gallium nitride, and sapphire (aluminum oxide).

[0150] Optionally, the second type semiconductor layer 12 and the substrate 1 have the same doping type and doping atoms.

[0151] Based on the above embodiments, in an optional embodiment of this application, one of the first semiconductor layer 11 and the second semiconductor layer 12 is an N-type semiconductor layer and the other is a P-type semiconductor layer, and the first semiconductor layer 11 and the second semiconductor layer 12 form a homogeneous PN junction.

[0152] Based on the above embodiments, in an optional embodiment of this application, the first type ohmic contact layer 70 and the second type ohmic contact layer 80 are materials of the same family as the substrate 1, and both the first type ohmic contact layer 70 and the second type ohmic contact layer 80 are heavily doped layers.

[0153] Based on the above embodiments, in an optional embodiment of this application, the first type semiconductor layer 11, the first type ohmic contact layer 70, and the first type DBR layer 2 have the same doping type, and the substrate 1, the second type semiconductor layer 12, the oxide layer 90, the second type DBR layer 3, and the second type ohmic contact layer 80 have the same doping type.

[0154] Optionally, in some embodiments, including but not limited to using MOCVD (metal-organic chemical vapor deposition) or MBE (molecular beam epitaxy) to introduce a certain proportion of compounds or chemically reactive gases into the reaction chamber, so that they react with each other at a certain temperature to generate functional layers, thereby obtaining an epitaxial stack.

[0155] Optionally, in some embodiments, after step one and before step two, the epitaxial structure is first cleaned to remove oil stains, movable impurities, etc. from the surface of the epitaxial structure to avoid contamination that may affect subsequent processes. The epitaxial structure can be cleaned using one or more chemical solvents selected from acidic, alkaline, and neutral solvents, including but not limited to one or more of acetone, isopropanol, NMP, DMSO, and deionized water.

[0156] Based on the above embodiments, in an optional embodiment of this application, such as Figure 7 As shown, step two includes the following procedures:

[0157] Step A01, as follows Figure 8 As shown, a VCSEL light-emitting preset area AA', a PN junction protection preset area BB', and an isolation preset area CC' are defined on the upper surface of the epitaxial stack. In the VCSEL light-emitting preset area AA', a portion of the epitaxial stack is formed by etching to form a light-emitting unit 10 isolated by a channel G. The channel G exposes a portion of the first type DBR layer 2. The oxide layer 90 of the light-emitting unit 10 is oxidized so that the central region of the oxide layer 90 is not oxidized to form a conductive channel 90a.

[0158] Optionally, in some embodiments, the trench G is formed by inductively coupled plasma dry etching (ICP) equipment, including but not limited to.

[0159] Optionally, in some embodiments, including but not limited to using a wet oxidation process, the oxide layer 90 in the light-emitting unit 10, except for the central region, is formed into insulating dielectric aluminum oxide through a redox reaction of high-temperature water vapor, which is used to limit the current and limit the laser to pass only from the conductive channel 90a region below the second electrode 52.

[0160] Step A02, as follows Figure 9 As shown, the epitaxial stack is further etched, and at the same time, the first region AA is formed in the VCSEL light-emitting preset region AA', the second region BB is formed in the PN junction protection preset region BB', and the isolation region CC is formed in the isolation preset region CC'.

[0161] Specifically, etching is performed along the surface of the epitaxial stack in the VCSEL light-emitting preset region AA' to expose the first type ohmic contact layer 70 to form the first mesa T1, and the surface of the second type ohmic contact layer 80 facing away from the substrate 1 is the second mesa T2; etching is performed along a portion of the surface of the epitaxial stack in the PN junction protection preset region BB' to expose the second type semiconductor layer 12 to form the third mesa T3, and etching is performed along the remaining surface of the epitaxial stack to expose the first type ohmic contact layer 70 to form the fourth mesa T4; etching is performed along the surface of the epitaxial stack in the isolation preset region CC' to expose the substrate 1 to form the isolation region CC.

[0162] Optionally, in some embodiments, the first region AA, the second region BB, and the isolation region CC are formed by inductively coupled plasma dry etching equipment (ICP).

[0163] Optionally, in some embodiments, forming the isolation region CC further includes etching a portion of the substrate 1 to give the substrate 1 of the isolation region CC a groove extending away from the epitaxial stack direction.

[0164] Step A03, Reference Figure 2 As shown, the first set of electrode structures 5 is fabricated in the first region AA, and the second set of electrode structures 6 is fabricated in the second region BB.

[0165] The first set of electrode structures 5 includes a first electrode 51 and a second electrode 52, with the first electrode 51 located on the first mesa T1 and the second electrode 52 located on the second mesa T2.

[0166] The second set of electrode structures 6 includes a third electrode 61 and a fourth electrode 62. The third electrode 61 is located on the third mesa T3, and the fourth electrode 62 is located on the fourth mesa T4.

[0167] The first electrode 51 and the second electrode 52 have opposite polarities, and the first electrode 51 and the fourth electrode 62 have the same polarity, while the second electrode 52 and the third electrode 61 have the same polarity.

[0168] Based on the above embodiments, in an optional embodiment of this application, reference is made to... Figure 3 As shown, the second electrode 52 includes a contact electrode 52a and a pad electrode 52b stacked sequentially along the growth direction.

[0169] Optionally, in some embodiments, the contact electrode 52a and the pad electrode 52b are prepared simultaneously in step A03 to obtain the second electrode 52.

[0170] In another optional embodiment, before step A01, a contact electrode 52a is first deposited on the surface of the second type ohmic contact layer 80 in the VCSEL light-emitting preset area AA', which is beneficial for the formation of a good ohmic contact between the second type ohmic contact layer 80 and the contact electrode 52a; and a first passivation layer is deposited on the surface of the epitaxial stack and the contact electrode 52a, which can be used to protect the epitaxial stack and the contact electrode 52a from scratches or contamination by impurities during subsequent fabrication; then, in step A02, the first passivation layer is simultaneously etched to make the first passivation layer have through holes, and the through holes expose the contact electrode 52a; so that in step A03, the pad electrode 52b can be connected to the contact electrode 52a through the through holes to obtain the second electrode 52.

[0171] Optionally, in some embodiments, the first electrode 51, the second electrode 52, the third electrode 61, and the fourth electrode 62 are deposited using an electron beam evaporation deposition apparatus.

[0172] Optionally, in some embodiments, the contact electrode 52a, the pad electrode 52b, and the third electrode 61 all include a Ti layer, a Pt layer, and an Au layer stacked sequentially along the growth direction; wherein the thicknesses of the Ti layer, the Pt layer, and the Au layer are 500 angstroms, 500 angstroms, and 1000 angstroms, respectively.

[0173] Both the first electrode 51 and the fourth electrode 62 include AuGeNi alloy layers and Au layers stacked sequentially along the growth direction; wherein, the AuGeNi alloy layers can be obtained by separately evaporating Au layers, Ge layers and Ni layers.

[0174] Optionally, in some embodiments, a first passivation layer is deposited using a plasma-enhanced chemical vapor deposition (PECVD) apparatus, and the material of the first passivation layer includes, but is not limited to, SiN. x The insulating dielectric film has a first passivation layer with a thickness ranging from 100 Å to 10000 Å, including endpoint values. For example, the thickness of the first passivation layer is 500 Å.

[0175] Optionally, step A04 and reference may be included after step A03. Figure 3 As shown, a second passivation layer is deposited. The first and second passivation layers constitute an insulating protective layer 7. The insulating protective layer 7 covers the exposed surfaces of the VCSEL light-emitting region and the PN junction protection region, and exposes the first set of electrode structures 5 and the second set of electrode structures 6. This protects the VCSEL chip from short circuits and prevents scratches and contamination of the device surface.

[0176] Optionally, the second passivation layer is an insulating dielectric film with a certain hardness and non-conductive properties, and the material includes, but is not limited to, one or more of silicon nitride and aluminum oxide.

[0177] Optionally, after step A04, step A05, fabricating the first metal connecting wire 8 and the second metal connecting wire 9, may be included;

[0178] For details, please refer to Figure 3 , Figure 4 As shown, the first metal connecting line 8 is connected to the first electrode 51 of the VCSEL light-emitting area and the fourth electrode 62 of the PN junction protection area via the surface of the insulating protective layer 7; the second metal connecting line 9 is connected to the second electrode 52 of the VCSEL light-emitting area and the third electrode 61 of the PN junction protection area via the surface of the insulating protective layer 7, and the first metal connecting line 8 and the second metal connecting line 9 are insulated from each other.

[0179] Based on the above embodiments, in an optional embodiment of this application, step A03 further includes forming a plurality of light-emitting units 10 isolated from each other by a channel G through an etching process, wherein the channel G exposes a portion of the first type DBR layer 2, wherein the oxide layer 90 of each light-emitting unit 10 is oxidized so that the central region of the oxide layer 90 is not oxidized to form a conductive channel 90a, as shown in the reference. Figure 6 As shown, the VCSEL light-emitting area includes multiple light-emitting units 10 arranged in an array, and each light-emitting unit 10 is connected in parallel.

[0180] Those skilled in the art should understand that, in the disclosure of this invention, the terms "lateral", "longitudinal", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting this invention.

[0181] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0182] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An epitaxial structure, characterized in that, The epitaxial structure includes: Substrate; An epitaxial stack disposed on the substrate includes at least the following layers stacked from bottom to top on the substrate: a second type semiconductor layer, a first type semiconductor layer, a first type ohmic contact layer, a first type DBR layer, an active region, an oxide layer, a second type DBR layer, and a second type ohmic contact layer.

2. The epitaxial structure according to claim 1, characterized in that: The substrate includes an insulating material layer, and the first type semiconductor layer, the second type semiconductor layer and the substrate are material layers of the same family. The epitaxial stack is obtained on the substrate by a single epitaxial layer.

3. The epitaxial structure according to claim 1, characterized in that: One of the first type semiconductor layer and the second type semiconductor layer is an N-type semiconductor layer and the other is a P-type semiconductor layer. The first type semiconductor layer and the second type semiconductor layer form a homogeneous PN junction.

4. The epitaxial structure according to claim 1, characterized in that: The thickness of both the first type semiconductor layer and the second type semiconductor layer ranges from 10nm to 1000nm, including the endpoint values.

5. The epitaxial structure according to claim 1, characterized in that: The first type ohmic contact layer and the second type ohmic contact layer are made of the same material family as the substrate, and both the first type ohmic contact layer and the second type ohmic contact layer are heavily doped layers.

6. The epitaxial structure according to claim 1, characterized in that: The first type semiconductor layer, the first type ohmic contact layer, and the first type DBR layer have the same doping type, and the substrate, the second type semiconductor layer, the oxide layer, the second type DBR layer, and the second type ohmic contact layer have the same doping type.

7. A VCSEL chip, characterized in that, The VCSEL chip includes: The epitaxial structure described in any one of claims 1-6 is adopted; The epitaxial stack includes a first region and a second region. The surface portion of the first region is a first mesa on the side of the first type ohmic contact layer facing away from the substrate, and a portion is a second mesa on the side of the second type ohmic contact layer facing away from the substrate. The surface portion of the second region is a third mesa on the side of the second type semiconductor layer facing away from the substrate, and a portion is a fourth mesa on the side of the first type ohmic contact layer facing away from the substrate. The first electrode assembly is disposed on the first region and forms a VCSEL light-emitting region with the epitaxial stack corresponding to the first region. The second electrode assembly is disposed on the second region and forms a PN junction protection zone with the epitaxial stack corresponding to the second region; The VCSEL light-emitting region and the PN junction protection region are spaced apart, and the VCSEL light-emitting region and the PN junction protection region are connected in parallel.

8. The VCSEL chip according to claim 7, characterized in that: The substrate has an exposed surface on the side facing the epitaxial stack to form an isolation region, and the VCSEL light-emitting region and the PN junction protection region are separated by the isolation region; The first electrode assembly includes a first electrode and a second electrode, wherein the first electrode is located on the first mesa and the second electrode is located on the second mesa; The second electrode assembly includes a third electrode and a fourth electrode, wherein the third electrode is located on the third mesa and the fourth electrode is located on the fourth mesa; The first electrode and the second electrode have opposite polarities, and the first electrode and the fourth electrode have the same polarity, while the second electrode and the third electrode have the same polarity.

9. The VCSEL chip according to claim 7, characterized in that: When the barrier height of the second type semiconductor layer remains constant, the protection voltage of the PN junction protection zone decreases as the barrier height of the first type semiconductor layer increases. or, When the barrier height of the first type of semiconductor layer remains constant, the protection voltage of the PN junction protection zone decreases as the barrier height of the second type of semiconductor layer increases.

10. The VCSEL chip according to claim 7, characterized in that: The barrier heights of both the first type semiconductor layer and the second type semiconductor layer range from 1.41 eV to 1.59 eV, including the endpoint values; Alternatively, the doping concentration range of both the first type semiconductor layer and the second type semiconductor layer is 1E18cm. -3 -1E21cm -3 This includes endpoint values.

11. The VCSEL chip according to claim 7, characterized in that: The VCSEL chip also includes an insulating protective layer, a first metal connection line, and a second metal connection line; The insulating protective layer covers the exposed surfaces of the VCSEL light-emitting area, the PN junction protection area, and the isolation area, and exposes the first electrode assembly and the second electrode assembly; the first metal connecting wire connects the first electrode of the VCSEL light-emitting area and the fourth electrode of the PN junction protection area through the surface of the insulating protective layer; the second metal connecting wire connects the second electrode of the VCSEL light-emitting area and the third electrode of the PN junction protection area through the surface of the insulating protective layer, and the first metal connecting wire and the second metal connecting wire are mutually insulated.

12. The VCSEL chip according to claim 7, characterized in that: The VCSEL light-emitting area includes multiple light-emitting units arranged in an array, and the light-emitting units are connected in parallel.

13. A method for fabricating a VCSEL chip, characterized in that, include: Step 1: Fabricate the epitaxial structure; Specifically, a substrate is provided, and an epitaxial stack is formed on the substrate by an epitaxial process. The epitaxial stack includes at least a second type semiconductor layer, a first type semiconductor layer, a first type ohmic contact layer, a first type DBR layer, an active region, an oxide layer, a second type DBR layer, and a second type ohmic contact layer stacked sequentially along the growth direction. Step 2: Etch the epitaxial stack and fabricate the first electrode assembly and the second electrode assembly to form a VCSEL chip; Specifically, through an etching process, the epitaxial stack is made to have a first region and a second region. The surface portion of the first region is a first mesa on the side of the first type ohmic contact layer facing away from the substrate, and a portion is a second mesa on the side of the second type ohmic contact layer facing away from the substrate. The surface portion of the second region is a third mesa on the side of the second type semiconductor layer facing away from the substrate, and a portion is a fourth mesa on the side of the first type ohmic contact layer facing away from the substrate. A first electrode assembly is fabricated in the first region, and its epitaxial stack with the first region constitutes the VCSEL light-emitting region; a second electrode assembly is fabricated in the second region, and its epitaxial stack with the second region constitutes the PN junction protection zone. The VCSEL light-emitting region and the PN junction protection region are spaced apart, and the VCSEL light-emitting region and the PN junction protection region are connected in parallel.

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