A vertical cavity surface emitting laser with low capacitance and a method of manufacturing the same

Abstract

The application relates to the technical field of lasers, in particular to a low-capacitance vertical cavity surface emitting laser and a preparation method thereof, the low-capacitance vertical cavity surface emitting laser comprises an epitaxial layer, the epitaxial layer comprises, from bottom to top, a substrate, a buffer layer, an N-type DBR, an N-type limiting layer, an active region, a P-type limiting layer, an oxidation layer, a P-type DBR and a P-type contact layer, the oxidation layer is provided with an oxidation hole in the center, the upper surface of the epitaxial layer is provided with two connecting holes, the connecting holes are provided with a dielectric layer, the dielectric layer is provided with a contact hole penetrating through the dielectric layer, and the material of the dielectric layer is porous SiCOH. The SiCOH air gap structure is applied to capacitor isolation under a VCSEL pad for the first time, so that the pad capacitance is reduced from 47-100 fF in the prior art to <5 fF, and the reduction amplitude exceeds one order of magnitude.

Description

Technical Field

[0001] This application relates to the technical field of lasers, and in particular to a low-capacitance vertical-cavity surface-emitting laser and its fabrication method. Background Technology

[0002] Vertical-cavity surface-emitting lasers (VCSELs) have become the core light source for short-distance fiber optic data communication systems due to their advantages such as low threshold current, circular beam output, ease of integration into two-dimensional arrays, and low cost. Especially in the 850nm band, VCSELs are widely used in data center interconnects, high-speed Ethernet (10GbE to 400GbE), and fiber optic channels.

[0003] In traditional VCSEL devices, the parasitic capacitance formed between the bonding pad and the semiconductor substrate is typically in the range of 80-150 fF. This large parasitic capacitance, together with the device's series resistance, forms a low-pass RC network with a cutoff frequency of only 2-5 GHz, which severely limits the high-speed modulation performance of VCSELs. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a low-capacitance vertical-cavity surface-emitting laser and its fabrication method.

[0005] One objective of this application is to provide a low-capacitance vertical-cavity surface-emitting laser, employing the following technical solution: A low-capacitance vertical-cavity surface-emitting laser includes an epitaxial layer. The epitaxial layer comprises, from bottom to top, a substrate, a buffer layer, an N-type dielectric barrier (DBR), an N-type confinement layer, an active region, a P-type confinement layer, an oxide layer, a P-type DBR, and a P-type contact layer. An oxide hole is formed at the center of the oxide layer. Two connection holes are formed on the upper surface of the epitaxial layer: an N-type connection hole and a P-type connection hole. The bottom of the N-type connection hole is located on the N-type DBR. An N-type contact layer is formed in the region directly opposite the N-type DBR and the N-type connection hole. The bottom of the P-type connection hole is located in the P-type contact layer. A dielectric layer is formed within the connection holes. Contact holes penetrating the dielectric layer are formed within the dielectric layer. These contact holes are divided into N-type contact holes directly opposite the N-type contact layer and P-type contact holes directly opposite the P-type contact layer. An N-type pad is connected above the N-type contact hole, and a P-type pad is connected above the P-type contact hole. The dielectric layer is made of porous SiCOH.

[0006] By adopting the above technical solution, the molecular structure of SiCOH (Organosilicate Glass) is based on a Si-O-Si framework network, while simultaneously introducing Si-CH3 terminal groups and nanoscale controllable pores. The polarizability of the CH3 group is 2.6 Å. 3 The value is much lower than that of Si-O bonds (5.2 Å). 3The introduction of this material disrupts the continuous Si-O network, reducing the overall polarization response of the material. The air filling the nanoscale pores (k=1.0) further reduces the effective dielectric constant.

[0007] According to the Clausius-Mossotti relation: (ε r -1) / (ε r +2) = (N / 3ε0)×(αSi-O+αC-H+fvoid×0) Where N is the molecular number density and fvoid is the porosity. As the porosity increases from 0% to 35%, the k value decreases from approximately 2.7 (dense SiCOH) to approximately 2.0 (porous SiCOH), reaching a minimum of 1.8. Compared to BCB's k value of 2.4, porous SiCOH can further reduce Pad capacitance by approximately 40-50%.

[0008] (2) The physical mechanism of Pad capacitance reduction: The VCSEL pad capacitance is determined by the parallel-plate capacitance formula: Cpad = epsilon0 * epsilon_r * A / d, where epsilon0 is the vacuum permittivity (8.85 × 10^-14 F / cm), epsilon_r is the relative permittivity of the dielectric, A is the pad area, and d is the dielectric thickness. When using an 80 × 80 square micrometer pad size and a 4-micrometer thick SiCOH air gap layer (epsilon_r = 1.6), Cpad = 8.85 × 10^-14 × 1.6 × 6400 × 10^-8 / (4 × 10^-4) = 2.27 × 10^-14 F = 22.7 fF. If selective etching is used to remove the n-GaAs semiconductor material beneath the pad to form a larger air cavity, the effective dielectric thickness increases, and the pad capacitance can be further reduced to <5 fF.

[0009] The capacitance reduction mechanism of SiCOH air gaps is based on its nanoscale porous structure. Air in the pores (k=1.0) forms a composite material with the SiCOH matrix (k=3-4), and the effective dielectric constant can be estimated using the Lichtenecker mixing formula: log(k_eff)=v1*log(k1)+v2*log(k2), where v is the volume fraction. When the porosity is approximately 40%, k_eff is approximately 2.0; by forming larger air gap cavities through a special pinch-off deposition process, k_eff can be further approached to 1.0.

[0010] (3) Relationship between RC delay and modulation bandwidth: The modulation bandwidth f_3dB of a VCSEL is limited by the parasitic RC cutoff frequency f_RC = 1 / (2*pi*R*C) and the intrinsic relaxation oscillation frequency f_r. Here, R is the equivalent series resistance (including DBR mirror resistance, contact resistance, and extension resistance), and C is the total parasitic capacitance (Cpad + Cmesa + Cj). In traditional VCSELs, f_RC is approximately 15GHz, which is the main factor limiting the modulation bandwidth. This application reduces Cpad to <5fF and R to <120 ohms, increasing f_RC to >100GHz, far exceeding the intrinsic f_r (approximately 25-30GHz), thus freeing the modulation bandwidth from parasitic effects.

[0011] Preferably, the P-type contact layer is arranged in a ring shape, with the center of the P-type contact layer directly opposite the oxide hole, and the inner diameter of the P-type contact layer is not less than the diameter of the oxide hole.

[0012] By adopting the above technical solution, the annular P-type contact layer uses a thin annular electrode tightly attached to the outer periphery of the mesa, allowing current to flow directly downwards into the P-type DBR. This shortens the path length by approximately 50% and reduces the spread resistance by 30-50%. Simultaneously, the annular symmetrical structure naturally achieves radially uniform injection, avoiding overheating problems caused by current accumulation in the center.

[0013] Preferably, the annular width of the P-type contact layer is 5-8 μm, and the inner diameter is equal to the oxide pore size plus 2-4 μm.

[0014] Another objective of this application is to provide a method for fabricating a low-capacitance vertical-cavity surface-emitting laser, employing the following technical solution: A method for fabricating a low-capacitance vertical-cavity surface-emitting laser (VCSEL), comprising the following steps: S1. Epitaxial growth: A buffer layer, an N-type DBR, an N-type confinement layer, an active region, a P-type confinement layer, an oxide layer, and a P-type DBR are sequentially grown on the substrate. S2. A P-type contact layer is deposited on a P-type DBR; S3. Etch the top platform to generate the top platform pattern; S4. Selective wet oxidation to form oxide pores in the oxide layer; S5. Deposit an N-type contact layer on an N-type DBR; S6. Etch the bottom platform to generate the bottom platform pattern; S7. Dielectric layer deposition: Using PECVD equipment, diethoxymethylsilane is used as the framework precursor, α-terpinene is used as the pore-forming agent, O2 is used as the oxidant, and He is used as the carrier gas to deposit a dielectric layer on the surface of the epitaxial layer. S8. Leveling treatment: grinding the surface of the dielectric layer; S9. Contact hole etching: The contact hole pattern is defined by photolithography. The P-type contact hole is located above the P-type contact layer, and the N-type contact hole is located above the N-type contact layer. The dielectric layer material inside the P-type contact hole and the N-type contact hole is removed by etching. S10, Electrode metal deposition: A metal layer is deposited by magnetron sputtering or electron beam evaporation, and a coplanar waveguide GSG electrode pattern is formed by photolithography + lift-off or RIE etching process.

[0015] Preferably, in step S7, the deposition temperature is 250°C, the chamber pressure is 5 Torr, the RF power is 200W, the deposition rate is 200nm / min, the total deposition time is 17-20 minutes, and the deposition thickness is 3-5μm.

[0016] Preferably, in step S7, after deposition is completed, UV curing is performed by irradiating with 365nm ultraviolet light at a temperature of 380°C for 30-60 minutes.

[0017] By employing the above technical solution, UV curing is performed after deposition, causing the pore-forming agent to decompose and volatilize, forming nanoscale pores. After curing, the film thickness shrinks by approximately 15% (from 3.5 μm to approximately 3.0 μm), and the dielectric constant decreases from 2.7 to <2.0.

[0018] Preferably, in steps S2 and S3, the outer diameter of the P-type contact layer is the same as the diameter of the top platform pattern, which is 25-35 μm, and the ring width of the P-type contact layer is 5-8 μm.

[0019] Preferably, in step S6, the diameter of the bottom platform pattern is 40-60 μm.

[0020] By adopting the above technical solution, a dual-mesa structure is formed. This step achieves complete electrical isolation between devices, while the bottom mesa pattern provides sufficient area for N-type contacts.

[0021] Preferably, in step S10, the GSG electrode pattern has the following characteristics: signal linewidth S = 20 μm, signal-to-ground gap W = 10 μm, ground linewidth 30 μm, and total GSG width 70 μm.

[0022] By adopting the above technical solution, the signal electrode of the GSG electrode is connected to the ring-shaped P-type contact through the BCB opening, and the two ground electrodes are connected to the N-type metal contact. The signal-to-ground spacing is designed to be 30 micrometers, the signal line width is 20 micrometers, and the characteristic impedance matching of about 50 ohms is achieved.

[0023] In summary, this application includes at least one of the following beneficial technical effects: 1. Extreme reduction in pad capacitance: from 80-150fF in traditional solutions to <5fF, a reduction of over 95%.

[0024] 2. Significantly improved modulation bandwidth: The 3dB bandwidth has been increased from 10-25GHz in the traditional scheme to 35-50GHz, supporting single-channel data rates of 56-112Gb / s.

[0025] 3. Minimal cost increase: The cost of a single chip increases by only about 2%, but the bandwidth is increased by 40%+, giving it a very high cost-performance advantage.

[0026] 4. Precise impedance matching: The CPW GSG electrode can achieve a characteristic impedance of 50±5Ω, which is perfectly matched with standard RF test systems and packaging substrates.

[0027] 5. Uniform current distribution: The annular P-type contact eliminates the current congestion effect, reduces the risk of local hot spots, and improves device reliability. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the overall structure of Embodiment 1.

[0029] Explanation of reference numerals in the attached figures: 1. Substrate; 2. Buffer layer; 3. N-type DBR; 4. N-type confinement layer; 5. Active region; 6. P-type confinement layer; 7. Oxide layer; 8. P-type DBR; 9. P-type contact layer; 10. Oxide via; 11. N-type connection via; 12. P-type connection via; 13. N-type contact layer; 14. Dielectric layer; 15. N-type contact via; 16. P-type contact via; 17. N-type pad; 18. P-type pad. Detailed Implementation

[0030] The present application will be further described in detail below with reference to all the accompanying drawings.

[0031] Example 1

[0032] This application discloses a low-capacitance vertical-cavity surface-emitting laser, referring to... Figure 1 The device includes an epitaxial layer, which comprises, from bottom to top, a substrate 1, a buffer layer 2, an N-type DBR 3, an N-type confinement layer 4, an active region 5, a P-type confinement layer 6, an oxide layer 7, a P-type DBR 8, and a P-type contact layer 9. The oxide layer 7 has an oxide hole 10 hollowed out at its center to limit the light-emitting aperture of the device, thereby achieving current aperture confinement.

[0033] Two connection holes are formed on the upper surface of the epitaxial layer, namely N-type connection hole 11 and P-type connection hole 12. The bottom of N-type connection hole 11 is located on N-type DBR3. N-type contact layer 13 is provided in the area directly opposite to N-type DBR3 and N-type connection hole 11. The bottom of P-type connection hole 12 is located on P-type contact layer 9.

[0034] The inner wall of the connection hole and the bottom non-contact area are covered with a dielectric layer 14, and the dielectric layer 14 is made of porous SiCOH.

[0035] The dielectric layer 14 has a contact hole that penetrates the dielectric layer 14. The contact hole is divided into an N-type contact hole 15 that is directly opposite the N-type contact layer 13 and a P-type contact hole 16 that is directly opposite the P-type contact layer 9. An N-type pad 17 is connected above the N-type contact hole 15, and a P-type pad 18 is connected above the P-type contact hole 16.

[0036] The P-type contact layer 9 adopts a ring structure. The central hollow area of ​​the ring-shaped P-type contact layer 9 is directly opposite the oxide hole 10 of the oxide layer 7, and the inner diameter of the P-type contact layer 9 is not less than the diameter of the oxide hole 10 to avoid blocking the light-emitting aperture and affecting the light extraction efficiency of the device. Further optimized parameters: the ring width of the P-type contact layer 9 is controlled at 5~8μm, and the inner diameter is 2~4μm larger than the diameter of the oxide hole 10 to achieve precise current injection and optimized heat dissipation.

[0037] Example 2

[0038] This application discloses a method for fabricating a low-capacitance vertical-cavity surface-emitting laser (VCSEL), which is used to fabricate a low-capacitance VCSEL as described in the above embodiments. The method includes the following steps: S1. Epitaxial growth: Using MOCVD epitaxial technology, a buffer layer, N-type DBR, N-type confinement layer, active region, P-type confinement layer, oxide layer and P-type DBR are continuously grown from bottom to top on the surface of a clean substrate to form a complete epitaxial stacked structure, ensuring lattice matching and low defect density of each epitaxial layer. S2. A P-type contact metal layer is deposited on the upper surface of the P-type DBR by vapor deposition process. Combined with photolithography patterning process, an annular P-type contact layer is prepared, with the outer diameter of the annular layer controlled to be 25~35μm, the width of the annular layer to be 5~8μm, and the inner diameter matched to the preset size of the oxide hole. S3. Top mesa etching: The top mesa pattern is defined by photolithography, and the top mesa structure is formed by dry etching process. The diameter of the mesa is consistent with the outer diameter of the P-type contact layer ring to ensure that the electrode and the mesa structure fit and match.

[0039] S5, N-type contact layer deposition: In the preset N-type DBR contact area, an N-type contact layer is prepared by photolithography windowing and metal deposition process to ensure that the N-type contact layer and the N-type DBR form a good ohmic contact.

[0040] S7. Porous SiCOH Dielectric Layer Deposition: A PECVD equipment was used to deposit the dielectric layer, with diethoxymethylsilane as the framework precursor, α-terpinene as the pore-forming agent, O2 as the oxidant, and He as the carrier gas. Precise control of deposition process parameters was maintained: deposition temperature 250℃, chamber pressure 5 Torr, RF power 200W, deposition rate 200nm / min, and total deposition time 17-20min, ultimately forming a 3-5μm thick SiCOH raw film. After deposition, UV curing was performed at 380℃ with 365nm ultraviolet light for 30-60min, allowing the pore-forming agent inside the film to fully decompose and volatilize, forming uniform nanoscale pores. After curing, the film thickness shrank by approximately 15%, and the dielectric constant decreased from the initial 2.7 to below 2.0, meeting the low dielectric requirement.

[0041] S8. Surface smoothing treatment: Chemical mechanical polishing (CMP) is used to smooth the surface of the cured dielectric layer, eliminating surface irregularities and step defects caused by the deposition process, and ensuring the smoothness requirements of subsequent photolithography, etching, and metal deposition processes. S9. Contact Hole Etching: The N-type and P-type contact hole patterns are precisely defined using photolithography to ensure that the P-type contact hole is aligned with the top of the annular P-type contact layer and the N-type contact hole is aligned with the top of the N-type contact layer. The dielectric layer material in the contact hole area is removed using a dry etching process to form a through-hole conductive contact hole that penetrates the dielectric layer, exposing the underlying contact metal layer.

[0042] S10 and GSG electrode fabrication: A metal layer is deposited on the surface of the dielectric layer using magnetron sputtering or electron beam evaporation, followed by photolithography + lift-off or RIE etching to fabricate a coplanar waveguide GSG electrode pattern. Electrode parameters are precisely matched to impedance requirements: signal linewidth S = 20 μm, signal-to-ground gap W = 10 μm, ground linewidth 30 μm, and total GSG electrode width 70 μm. The signal electrode is connected to an annular P-type contact layer via contact holes, and the two ground electrodes are connected to N-type contact layers, achieving precise 50Ω characteristic impedance matching to meet the requirements of high-frequency and high-speed signal transmission.

[0043] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A low-capacitance vertical-cavity surface-emitting laser, comprising an epitaxial layer, the epitaxial layer comprising, from bottom to top, a substrate (1), a buffer layer (2), an N-type DBR (3), an N-type confinement layer (4), an active region (5), a P-type confinement layer (6), an oxide layer (7), a P-type DBR (8), and a P-type contact layer (9), wherein an oxide hole (10) is formed in the center of the oxide layer (7), characterized in that: Two connection holes are formed on the upper surface of the epitaxial layer, namely an N-type connection hole (11) and a P-type connection hole (12). The bottom of the N-type connection hole (11) is located on the N-type DBR (3). An N-type contact layer (13) is provided in the area opposite to the N-type DBR (3) and the N-type connection hole (11). The bottom of the P-type connection hole (12) is located in the P-type contact layer (9). A dielectric layer (14) is provided in the connection hole. A contact hole penetrating the dielectric layer (14) is formed in the dielectric layer (14). The contact hole is divided into an N-type contact hole (15) opposite to the N-type contact layer (13) and a P-type contact hole (16) opposite to the P-type contact layer (9). An N-type pad (17) is connected above the N-type contact hole (15), and a P-type pad (18) is connected above the P-type contact hole (16). The material of the dielectric layer (14) is porous SiCOH.

2. The low-capacitance vertical-cavity surface-emitting laser according to claim 1, characterized in that: The P-type contact layer (9) is arranged in a ring shape, with the center of the P-type contact layer (9) directly opposite the oxide hole (10), and the inner diameter of the P-type contact layer (9) is not less than the diameter of the oxide hole (10).

3. A low-capacitance vertical-cavity surface-emitting laser according to claim 2, characterized in that: The annular width of the P-type contact layer (9) is 5-8 μm, and the inner diameter is equal to the diameter of the oxide pore (10) plus 2-4 μm.

4. A method for fabricating a low-capacitance vertical-cavity surface-emitting laser, characterized in that: The method for fabricating a low-capacitance vertical-cavity surface-emitting laser as described in any one of claims 1-3 includes the following steps: S1. Epitaxial growth: A buffer layer, an N-type DBR, an N-type confinement layer, an active region, a P-type confinement layer, an oxide layer, and a P-type DBR are sequentially grown on the substrate. S2. A P-type contact layer is deposited on a P-type DBR; S3. Etch the top platform to generate the top platform pattern; S4. Selective wet oxidation to form oxide pores in the oxide layer; S5. Deposit an N-type contact layer on an N-type DBR; S6. Etch the bottom platform to generate the bottom platform pattern; S7. Dielectric layer deposition: Using PECVD equipment, diethoxymethylsilane is used as the framework precursor, α-terpinene is used as the pore-forming agent, O2 is used as the oxidant, and He is used as the carrier gas to deposit a dielectric layer on the surface of the epitaxial layer. S8. Leveling treatment: grinding the surface of the dielectric layer; S9. Contact hole etching: The contact hole pattern is defined by photolithography. The P-type contact hole is located above the P-type contact layer, and the N-type contact hole is located above the N-type contact layer. The dielectric layer material inside the P-type contact hole and the N-type contact hole is removed by etching. S10, Electrode metal deposition: A metal layer is deposited by magnetron sputtering or electron beam evaporation, and a coplanar waveguide GSG electrode pattern is formed by photolithography + lift-off or RIE etching process.

5. The method for fabricating a low-capacitance vertical-cavity surface-emitting laser according to claim 4, characterized in that: In step S7, the deposition temperature is 250°C, the chamber pressure is 5 Torr, the RF power is 200W, the deposition rate is 200nm / min, the total deposition time is 17-20 minutes, and the deposition thickness is 3-5μm.

6. The method for fabricating a low-capacitance vertical-cavity surface-emitting laser according to claim 5, characterized in that: In step S7, after deposition is completed, UV curing is performed by irradiating with 365nm ultraviolet light at a temperature of 380°C for 30-60 minutes.

7. The method for fabricating a low-capacitance vertical-cavity surface-emitting laser according to claim 4, characterized in that: In steps S2 and S3, the outer diameter of the P-type contact layer is the same as the diameter of the top platform pattern, which is 25-35 μm, and the ring width of the P-type contact layer is 5-8 μm.

8. The method for fabricating a low-capacitance vertical-cavity surface-emitting laser according to claim 7, characterized in that: In step S6, the diameter of the bottom platform pattern is 40-60 μm.

9. The method for fabricating a low-capacitance vertical-cavity surface-emitting laser according to claim 4, characterized in that: In step S10, the GSG electrode pattern is as follows: signal line width S = 20 μm, signal-to-ground gap W = 10 μm, ground line width 30 μm, and total GSG width 70 μm.

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