A method for manufacturing a laser chip

Abstract

The present disclosure relates to the technical field of optical fiber communication, and provides a preparation method of a laser chip. The preparation method comprises: growing an N-InP layer and a first quantum well layer above a semi-insulating substrate; etching a preset region of the first quantum well layer and adjoiningly growing a second quantum well layer; growing a P-InP layer and an InGaAs contact layer above the first quantum well layer and the second quantum well layer in sequence; and preparing a laser, a modulator and a test device in different regions of a wafer respectively. The present disclosure synchronously prepares functional devices and test devices on a wafer, and can be used to obtain bulk resistance in the vertical wafer direction.

Description

Technical Field

[0001] This disclosure relates to the field of optical fiber communication technology, and in particular to a method for fabricating a laser chip. Background Technology

[0002] As traditional data centers gradually evolve into large-scale cloud data centers, cloud computing service providers have placed extremely high demands on the transmission capabilities of core networks. 400G and above laser chips are widely used in high-speed data exchange between servers and switches, and between switches, within data centers to meet the demand for high-density data throughput.

[0003] In applications exceeding 400G, the integrated optical chip for lasers and modulators needs a modulation bandwidth of over 78GHz. The integrated optical chip employs a graded doping process at the P-layer (P-InP layer). Different graded doping processes cause variations in the bulk resistance perpendicular to the wafer, which significantly affects the modulation bandwidth of the modulator. Summary of the Invention

[0004] This disclosure provides a method for fabricating a laser chip, which solves the problem of being unable to evaluate the bulk resistance of the modulator in the direction perpendicular to the wafer by simultaneously fabricating test devices.

[0005] In some embodiments, a method for fabricating a laser chip is provided, comprising: An N-InP layer and a first quantum well layer are grown on a semi-insulating substrate. A predetermined area of ​​the first quantum well layer is etched and a second quantum well layer is grown in connection. A P-InP layer and an InGaAs contact layer are grown sequentially on the first quantum well layer and the second quantum well layer. A SiNx mask layer is grown, and the SiNx mask layer is etched in the first, second, and third regions to obtain a SiNx mask. In the first region, both sides of the SiNx mask are etched downwards to above the first quantum well layer. The first region is located above the first quantum well layer and is used to fabricate the laser of the laser chip. The second and third regions are located above the second quantum well layer. The second region is used to fabricate the modulator of the laser chip, and the third region is used to fabricate the test device of the laser chip. Each preset sub-region is etched into the N-InP layer in the first region and the second region respectively, and in the third region, a SiNx mask is used as a mask to etch into the N-InP layer to form a columnar body; A SiO2 mask layer is grown, and the SiO2 mask layer is etched at a preset position in the second region. The SiO2 mask layer in the third sub-region is etched in the third region to obtain a second SiO2 sub-mask located at the top of the column and a first SiO2 sub-mask and a third SiO2 sub-mask located on both sides of the column. In the second and third regions, SiO2 mask layers are used as masks to etch into the semi-insulating substrate; Remove the SiO2 mask layer and the SiNx mask layer, grow a SiO2 pad layer, etch the SiO2 pad layer, so as to remove the SiO2 pad layer in the first region except at a preset location in the second region, and form a first SiO2 pad, a second SiO2 pad, a third SiO2 pad and a fourth SiO2 pad around the third sub-region, and grow a SiO2 passivation layer. SiO2 passivation layers are etched in the first and second regions to prepare P-side and N-side electrodes, and SiO2 passivation layers are etched on the top of the column to prepare the second electrode. SiO2 passivation layers are etched on both sides of the column to prepare the first and third electrodes. A first air bridge is fabricated in a second region, and a second air bridge and pads are fabricated in a third region. The pads are located on each pad. The second air bridge includes a first sub-bridge, a second sub-bridge, and a third sub-bridge. The first sub-bridge is used to connect the pads on the first SiO2 pad to the first electrode. The second sub-bridge is used to connect the pads on the second SiO2 pad, the second electrode, and the pads on the fourth SiO2 pad. The third sub-bridge is used to connect the pads on the third SiO2 pad to the third electrode.

[0006] The above technical solution has the following beneficial effects: This disclosure grows an N-InP layer and a first quantum well layer on a semi-insulating substrate, etches a predetermined area of ​​the first quantum well layer and grows a second quantum well layer, and then grows a P-InP layer and an InGaAs contact layer on the second and first quantum well layers respectively. The laser, modulator, and test device are then fabricated separately in different regions, achieving simultaneous fabrication of the laser, modulator, and test device on the same wafer. The test device and modulator have the same epitaxial structure, allowing the bulk resistance of the test device in the direction perpendicular to the wafer to reflect the bulk resistance of the modulator in the same direction. The test device includes a columnar body obtained after etching, with electrodes on the top and sides of the columnar body, and air bridges and pads connecting the electrodes are constructed. This allows the test device to be used to measure the bulk resistance in the direction perpendicular to the wafer. Because the columnar body and the areas on both sides for setting the electrodes are small, the lateral current diffusion is significantly reduced, improving the accuracy of the bulk resistance measurement.

[0007] In some embodiments, a method for fabricating a laser chip is provided, wherein the third sub-region is a SiNx mask containing the second region and the SiNx mask is located in a strip-shaped region at the center.

[0008] The above technical solution has the following beneficial effects: the third sub-region is a SiNx mask that includes the second region and the SiNx mask is located in a strip-shaped region in the center. The area is small, which can further limit the lateral diffusion of current, improve the accuracy of volume resistance measurement, and at the same time facilitate the stable connection of the air bridge.

[0009] In some embodiments, a method for fabricating a laser chip is provided, wherein the width of the third sub-region is 1.2 to 1.5 times the width of the SiNx mask of the second region, and the length of the third sub-region is 3 to 5 times the width of the SiNx mask of the second region.

[0010] The above technical solution has the following beneficial effects: the size setting of the third sub-region width being 1.2 to 1.5 times that of the SiNx mask of the second region and the length being 3 to 5 times ensures that the platform structure has sufficient mechanical stability and N-side electrode arrangement space, while avoiding the increase in lateral current diffusion caused by the excessive area of ​​the third sub-region, thus achieving an optimized balance between structural reliability and bulk resistance accuracy.

[0011] In some embodiments, a method for fabricating a laser chip is provided, wherein a first SiO2 pad, a second SiO2 pad, a third SiO2 pad, and a fourth SiO2 pad are distributed in a cross shape around a columnar body.

[0012] The above technical solution has the following beneficial effects: by distributing the pads in a cross shape around the column, the routing paths of each air bridge are minimized and do not intersect, reducing parasitic capacitance and signal crosstalk, while ensuring the symmetry of the pad layout, which is beneficial to the stable contact of subsequent test probes and the consistency of signal acquisition.

[0013] In some embodiments, a method for fabricating a laser chip is provided, which includes etching both sides of a SiNx mask downwards over a first quantum well layer in a first region, and further includes: A first mask layer is grown and etched to completely remove the first mask layer in the second and third regions, and the first mask layer within a predetermined range on both sides of the SiNx mask is removed in the first region.

[0014] The above technical solution has the following beneficial effects: by selectively removing the first mask layer, only the first mask layer outside the preset range on both sides of the SiNx mask is retained in the first region, which provides a precise patterned masking basis for subsequent etching steps and improves the accuracy of the etching area.

[0015] In some embodiments, a method for fabricating a laser chip is provided, wherein each preset sub-region is etched into an N-InP layer in a second region and a first region, respectively, and the method further includes: A second mask layer is grown and etched to remove the second mask layer in a first sub-region within a first region, to remove the second mask layer in a second sub-region within a second region, and to completely remove the second mask layer in a third region, wherein the second sub-region includes a predetermined sub-region of the second region.

[0016] The above technical solution has the following beneficial effects: by selectively removing the second mask layer in each area, it provides a precise patterned masking basis for subsequent etching steps, thereby improving the accuracy of the etching area.

[0017] In some embodiments, a method for fabricating a laser chip is provided, wherein a SiO2 mask layer is used as a mask to etch into a semi-insulating substrate in a second region and a third region, comprising: In the second and third regions, a SiO2 mask layer is used as a mask, and Cl2 and H2 are used to etch to a predetermined depth in the semi-insulating substrate.

[0018] The above technical solution has the following beneficial effects: by using a mixture of Cl2 and H2 gases for deep etching and precisely controlling the etching to a preset depth within the semi-insulating substrate, it can ensure that the platform structure containing the columnar body has sufficient height for setting the N-side electrode, thereby improving the isolation effect between the N-side electrode and the outside of the platform.

[0019] In some embodiments, a method for fabricating a laser chip is provided, which involves removing the SiO2 mask layer and the SiNx mask layer, including: The SiO2 mask layer and the SiNx mask layer are completely etched away by pre-setting the time for hydrofluoric acid etching.

[0020] The above technical solution has the following beneficial effects: by using hydrofluoric acid to remove all SiO2 mask layers and SiNx mask layers in one go, the mask residue accumulated in the previous steps can be completely removed, ensuring the interface quality of the subsequently grown SiO2 pad layer and improving the long-term reliability and electrical performance stability of the device. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of an optical module access switch according to some embodiments; Figure 2 This is a partial structural diagram of a switch according to some embodiments; Figure 3 This is a structural diagram of an optical module according to some embodiments; Figure 4 An exploded view of an optical module according to some embodiments; Figure 5 This is an exploded view of a light emitting component according to some embodiments; Figure 6 This is a structural diagram of a laser chip according to some embodiments; Figure 7 This is a schematic flowchart of a method for fabricating a laser chip according to some embodiments; Figure 8 This is a schematic diagram of the extensional structure according to some embodiments; Figure 9 This is a schematic diagram of the wafer region distribution according to some embodiments; Figure 10 This is a schematic diagram of the extensional structure of the third region according to some embodiments; Figure 11 A schematic diagram of the SiNx mask in the third region according to some embodiments; Figure 12 This is a schematic diagram of a columnar structure according to some embodiments; Figure 13 This is a schematic diagram of a SiO2 mask layer according to some embodiments; Figure 14 This is a schematic diagram of etching using a SiO2 mask layer according to some embodiments; Figure 15 This is a schematic diagram of a pad according to some embodiments; Figure 16 This is a schematic diagram of electrodes according to some embodiments; Figure 17 A schematic diagram of a pad and a second air bridge according to some embodiments; Figure 18 This is a schematic diagram of a laser according to some embodiments; Figure 19 This is a schematic diagram of the modulator according to some embodiments; Figure 20 This is a schematic diagram of the resistance distribution according to some embodiments; Figure 21 This is a schematic diagram of volume resistance measurement according to some embodiments; Figure 22 This is a schematic diagram of the wafer region distribution according to some other embodiments. Detailed Implementation

[0023] The embodiments of this disclosure will now be described clearly and in detail with reference to the accompanying drawings. However, the described embodiments are merely some, and not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0024] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and inclusive, meaning "including, but not limited to"; the terms "first" and "second" should not be construed as indicating or implying relative importance or indicating an upper limit on the number; the term "multiple" means two or more; the term "connection" should be interpreted broadly, for example, "connection" can be a fixed connection, a detachable connection, or an integral part, and can be a direct connection or an indirect connection through an intermediate medium; the use of the terms "applicable to" or "configured to" implies open and inclusive language, which does not exclude applicability to or configuration to devices performing additional tasks or steps; descriptions such as "parallel," "perpendicular," "identical," "consistent," and "aligned" are not limited to absolute mathematical theoretical relationships, but also include acceptable error ranges arising in practice, and differences based on the same design concept but due to manufacturing reasons.

[0025] In optical communication technology, information is loaded onto light waves to generate optical signals, which are then used to transmit information between information processing devices. Connections are established between these devices via optical transmission equipment. The optical power loss during transmission through this equipment is minimal, allowing for long-distance transmission with minimal power loss. Light boasts extremely high transmission speeds, and the cost of optical transmission equipment, such as fiber optic cables, is lower than that of electrical transmission equipment like copper wires. Using optical signals to transmit information offers advantages such as long-distance transmission, high speed, and low cost.

[0026] Information processing equipment typically includes switches, servers, optical network units (ONUs), optical distribution networks (ODNs), optical line terminals (OLTs), gateways, routers, mobile phones, computers, tablets, televisions, etc.; optical transmission equipment typically includes optical fibers and optical waveguides. Information processing equipment can recognize and process electrical signals, while optical transmission equipment can transmit optical signals. Therefore, optical modules are needed between the optical transmission equipment and the information processing equipment to perform the conversion between optical and electrical signals.

[0027] In some embodiments, the optical signal input and / or optical signal output of the optical module are connected to an optical fiber, and the electrical signal input and / or electrical signal output of the optical module are connected to a switch; a first optical signal from the optical fiber is transmitted to the optical module, the optical module converts the first optical signal into a first electrical signal, and transmits the first electrical signal to the switch; a second electrical signal from the switch is transmitted to the optical module, the optical module converts the second electrical signal into a second optical signal, and transmits the second optical signal to the optical fiber.

[0028] Information processing equipment connected to optical modules can also be referred to as the host computer for optical modules. In access network transmission scenarios, the host computer for optical modules is usually an ONU, ODN, or OLT; in data center transmission scenarios, the host computer for optical modules is usually a Switch or Server.

[0029] Figure 1 This is a schematic diagram of the structure of an optical module access switch according to some embodiments. For example... Figure 1 As shown, switch 100 has multiple optical module interfaces. Multiple optical modules are inserted into the switch through these interfaces, establishing electrical signal communication between the optical modules and the switch. Optical fiber 101 is connected to the optical modules, establishing optical signal communication between the optical fiber and the optical modules. One end of optical fiber 101 is connected to the optical module, and the other end of optical fiber 101 (…) Figure 1 (not shown in the image) connects to another optical module ( Figure 1 (Not shown in the image), another optical module accesses the server ( Figure 1 (not shown in the image) or another switch ( Figure 1 (Not shown in the image).

[0030] In some embodiments, the optical fiber 101 and the optical module 200 are detachably connected; in other embodiments, the optical fiber 101 and the optical module 200 are non-detachably connected.

[0031] The switch 100 is configured to provide data electrical signals to the optical module 200, or receive data electrical signals from the optical module 200, or monitor or control the operating status of the optical module 200.

[0032] In some embodiments, the optical module is a tool for converting optical signals to electrical signals. During the conversion process, the information does not change, but the encoding or decoding method of the information changes.

[0033] Figure 2 This is a partial structural diagram of a switch according to some embodiments. To clearly show the connection relationship between the optical module 200 and the switch 100, Figure 2 Only the structures related to the optical module 200 in the switch 100 are shown. For example... Figure 2As shown, in some embodiments, the switch 100 further includes a PCB circuit board 102 disposed in the receiving cavity, and a cage 103 disposed on the surface of the PCB circuit board 102; the optical module 200 is inserted into the cage 103 and fixed by the cage 103.

[0034] In some embodiments, a heat sink 104 is provided on the cage 103 to dissipate heat for the optical module; in some embodiments, the heat sink 104 has protruding structures such as fins to increase the heat dissipation area.

[0035] In some embodiments, an electrical connector is provided inside the cage 103, which is configured to access the electrical interface of the optical module 200.

[0036] In some embodiments, the optical module 200 is inserted into the cage 103 of the switch 100, and the cage 103 fixes the optical module 200. The heat generated by the optical module 200 is conducted to the cage 103 and then diffused through the heat sink 104.

[0037] In some embodiments, the optical module 200 is inserted into the cage 103 of the switch 100, and the electrical interface of the optical module 200 is connected to the electrical connector inside the cage 103, thereby establishing an electrical signal connection between the optical module 200 and the switch 100.

[0038] In some embodiments, the optical interface of the optical module 200 is connected to the optical fiber 101, thereby enabling the optical module 200 to establish an optical signal connection with the optical fiber 101.

[0039] Figure 3 This is a structural diagram of an optical module according to some embodiments. Figure 4 This is an exploded view of an optical module according to some embodiments. Figure 3 and Figure 4 As shown, the optical module 200 includes a shell, a circuit board 300 disposed within the shell, a light emitting component 400, and a light receiving component 500. However, this disclosure is not limited thereto; in some embodiments, the optical module 200 includes one of the light emitting component 400 and the light receiving component 500.

[0040] The housing includes an upper housing 201 and a lower housing 202, with the upper housing 201 covering the lower housing 202 to form the aforementioned housing having a first opening 203 and a second opening 204; the outer contour of the housing is generally square.

[0041] In some embodiments, the lower housing 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and perpendicular to the base plate 2021; the upper housing 201 includes a cover plate 2011, which covers the two lower side plates 2022 of the lower housing 202 to form the aforementioned housing.

[0042] In some embodiments, the lower housing 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and perpendicular to the base plate 2021; the upper housing 201 includes a cover plate 2011 and two upper side plates located on both sides of the cover plate 2011 and perpendicular to the cover plate 2011. The two upper side plates and the two lower side plates 2022 are combined to realize that the upper housing 201 covers the lower housing 202.

[0043] The direction of the line connecting the first opening 203 and the second opening 204 can be consistent with or inconsistent with the length direction of the optical module 200. For example, the first opening 203 is located at the end of the optical module 200. Figure 3 (Left end), the second opening 204 is located at the end of the optical module 200 ( Figure 3 (The right end). Alternatively, the first opening 203 is located at the end of the optical module 200, while the second opening 204 is located on the side of the optical module 200. The first opening 203 is an electrical port, and the end of the circuit board 300 extends from the first opening 203 and is inserted into the electrical connector of the host computer; the second opening 204 is an optical port, configured to connect to an external optical fiber 101 so that the optical fiber 101 connects the optical emitting component 400 and the optical receiving component 500 in the optical module 200.

[0044] The assembly method using an upper housing 201 and a lower housing 202 facilitates the installation of the circuit board 300, the light emitting component 400, the light receiving component 500, etc., into the aforementioned housings. The upper housing 201 and the lower housing 202 can encapsulate and protect these devices. Furthermore, the assembly of the circuit board 300, the light emitting component 400, and the light receiving component 500 facilitates the deployment of positioning components, heat dissipation components, and electromagnetic shielding components for these devices, which is beneficial for automated production.

[0045] In some embodiments, the upper housing 201 and the lower housing 202 are made of metal materials, which is beneficial for achieving electromagnetic shielding and heat dissipation.

[0046] Circuit board 300 includes circuit traces, electronic components, and chips. The circuit traces connect the electronic components and chips according to the circuit design to achieve functions such as power supply, electrical signal transmission, and grounding. Electronic components may include, for example, capacitors, resistors, transistors, and metal-oxide-semiconductor field-effect transistors (MOSFETs). Chips may include, for example, microcontroller units (MCUs), laser driver chips, transimpedance amplifiers (TIAs), limiting amplifiers (LAs), clock and data recovery chips (CDRs), power management chips, and digital signal processing (DSP) chips.

[0047] Circuit board 300 is generally a rigid circuit board. Due to its relatively hard material, the rigid circuit board can also bear loads. For example, the rigid circuit board can stably support the electronic components and chips mentioned above. The rigid circuit board can also be inserted into the electrical connector in the cage 103 of the host computer.

[0048] The circuit board 300 also includes gold fingers formed on its end surfaces, each gold finger consisting of a plurality of independent pins. The circuit board 300 is inserted into a cage 103 and is electrically connected to an electrical connector within the cage 103 by the gold fingers. The gold fingers may be located only on one side of the surface of the circuit board 300 (e.g., ...). Figure 4 The upper surface shown can also be positioned on the upper and lower surfaces of the circuit board 300 to provide a greater number of pins, thus adapting to applications with high pin count requirements. The gold fingers are configured to establish an electrical connection with the host computer to achieve power supply, grounding, and two-wire synchronous serial (Inter-Integrated Circuit, I...) 2 C) Signal transmission, data signal transmission, etc. Of course, flexible circuit boards are also used in some optical modules. Flexible circuit boards are generally used in conjunction with rigid circuit boards as a supplement to rigid circuit boards.

[0049] At least one of the light emitting component 400 or the light receiving component 500 is located on the side of the circuit board 300 away from the gold fingers.

[0050] In some embodiments, the light emitting component 400 and the light receiving component 500 are physically separated from the circuit board 300, and then electrically connected to the circuit board 300 through corresponding flexible circuit boards or electrical connectors.

[0051] In some embodiments, at least one of the light emitting component 400 or the light receiving component 500 may be directly disposed on the circuit board 300. For example, at least one of the light emitting component 400 or the light receiving component 500 may be disposed on the surface of the circuit board 300 or the side of the circuit board 300.

[0052] In some embodiments, the light emitting component 400 may include a cavity, in which an electrical device for generating emitted light signals and an optical device for transmitting emitted light signals are disposed; wherein the electrical device includes a laser, etc., and the optical device includes a collimating lens, etc.

[0053] In some embodiments, the light receiving component 500 may include a cavity, in which an optical device for transmitting received light signals and an electrical device for converting received light signals are disposed; wherein the optical device includes a converging lens, etc., and the electrical device includes a photodetector, etc.

[0054] In some embodiments, the light emitting component 400 and the light receiving component 500 may share a cavity, such as a double-layer cavity, with one layer for the light emitting component 400 and the other layer for the light receiving component 500.

[0055] In some embodiments, the light emitting component 400 and the light receiving component 500 may not share a cavity, and the light emitting component 400 and the light receiving component 500 may be independent of each other and may be disposed on the same side of the circuit board 300. Of course, in this embodiment of the present disclosure, the light emitting component 400 and the light receiving component 500 may also be disposed on different sides of the circuit board 300.

[0056] In some embodiments, the light emitting component 400 can generate light signals of multiple wavelengths. For example, the light emitting component 400 can generate light signals including four wavelengths.

[0057] Figure 5 This is an exploded view of a light emitting component according to some embodiments. Figure 5 A structure for generating optical signals of four wavelengths is shown. For example... Figure 5 As shown, in some embodiments, the light emitting component 400 includes four laser components 400a arranged in an array; wherein, each laser component 400a includes a substrate and a laser chip, and the laser chip generates a light signal of a certain wavelength, and the laser chip is disposed on the substrate.

[0058] In some embodiments, a ceramic substrate is used as the substrate, and the laser chip is eutectic bonded to the ceramic substrate. Four laser components 400a are arranged in an array, and a preset spacing must be maintained between adjacent laser components 400a, which places high demands on the assembly of the laser components 400a.

[0059] In some embodiments, to ensure the coupling efficiency of the optical signal generated by the laser component 400a, a lens is provided in the output optical path of the laser component 400a, and the assembly accuracy of the lens is required to be high. To ensure the assembly accuracy of the lens, the lens is usually placed in the output optical path of the corresponding laser component 400a by active coupling.

[0060] In some embodiments, the light emitting component 400 includes a cavity 401, and a laser assembly 400a is disposed in the cavity 401. Exemplarily, an opening is provided on one side wall of the cavity 401 for insertion of a circuit board 300; the circuit board 300 extending into the cavity is electrically connected to the laser assembly 400a.

[0061] In some embodiments, the light emitting component 400 includes a cover plate 402 that covers the connecting cavity 401.

[0062] Figure 6 This is a structural diagram of a laser chip according to some embodiments. Figure 6 In this context, the X-axis is the direction of light field transmission. For example... Figure 6 As shown, the laser chip 600 includes a light-emitting region 610, a modulation region 620, and a docking region 630. One end of the light-emitting region 610 is away from the modulation region 620, and the other end is close to the modulation region 620. One end of the modulation region 620 is close to the light-emitting region 610, and the other end is away from the light-emitting region 610. One end of the docking region 630 is connected to the other end of the light-emitting region 610, and the other end of the docking region 630 is connected to one end of the modulation region 620.

[0063] A first active layer is formed in the light-emitting region 610, which emits light without carrying a signal. A second active layer is formed in the modulation region 620, which modulates the light emitted by the light-emitting region 610 to generate an optical signal. The docking region 630 is used to couple and transmit the light generated by the light-emitting region 610 to the modulation region 620 to ensure the coupling efficiency of the light generated by the light-emitting region 610 to the modulation region 620.

[0064] In some embodiments, a light-emitting electrode 611 is disposed on the top of the light-emitting region 610. The light-emitting electrode 611 is used to electrically connect to the pins on the socket to load a bias current, thereby providing charge carriers to the first active layer of the light-emitting region 610, so that the light-emitting region 610 generates light.

[0065] In some embodiments, a modulation electrode 621 is disposed on the top of the modulation region 620. The modulation electrode 621 is used to electrically connect to the pin on the socket to load a modulation signal, thereby providing a modulation current to the second active layer of the modulation region 620, so that the modulation region 620 modulates the light generated by the light-emitting region 610.

[0066] In some embodiments, the P-InP layer (P layer for short) of the laser chip adopts a gradient doping process, and its bulk resistance in the direction perpendicular to the wafer varies depending on the gradient doping process. The bulk resistance of other epitaxial layers is not directional and is easy to obtain. Therefore, the overall resistance of the laser chip in the direction perpendicular to the wafer can be measured first, and then the bulk resistance of the P layer can be subtracted to obtain the bulk resistance of the P layer in the direction perpendicular to the wafer.

[0067] In integrated optical chips, such as those combining distributed feedback lasers (DFBs) and Mach-Zehnder modulators (MZ modulators), the bulk resistance of the P-layer of the MZ modulator in the direction perpendicular to the wafer significantly affects the modulation bandwidth. Accurately obtaining this bulk resistance is crucial for optimizing the MZ modulator. However, due to the lateral current diffusion after the integration of the DFB laser and the MZ modulator, it is difficult to accurately measure the bulk resistance of the MZ modulator in the direction perpendicular to the wafer.

[0068] To address the aforementioned technical problems, this disclosure provides a method for fabricating a laser chip. This method simultaneously fabricates a laser chip and a test device on the same substrate, with the test device and the MZ modulator sharing the same epitaxial layer. This ensures that the bulk resistance of the test device in the vertical wafer direction is the same as that of the MZ modulator in the vertical wafer direction. The resistivity can then be calculated by measuring the bulk resistance of the test device in the vertical wafer direction. Since this resistivity is identical to the bulk resistance of the MZ modulator, it reflects the resistance characteristics of the MZ modulator's bulk resistance. The test device has a small projected area in the horizontal wafer direction, thus significantly avoiding measurement errors caused by lateral current diffusion after current injection. The measured bulk resistance can approximate the bulk resistance of the test device in the vertical wafer direction.

[0069] Figure 7 This is a schematic flowchart of a laser chip fabrication method according to some embodiments, such as... Figure 7 As shown, the method may include the following steps: Step S110: An N-InP layer and a first quantum well layer are grown on a semi-insulating substrate. A preset area of ​​the first quantum well layer is etched and a second quantum well layer is grown in connection. A P-InP layer and an InGaAs contact layer are grown sequentially on the first quantum well layer and the second quantum well layer.

[0070] In some embodiments, epitaxial layers are prepared using epitaxial growth techniques in a plasma-enhanced chemical vapor deposition (PECVD) apparatus.

[0071] Figure 8 This is a schematic diagram of the extensional structure according to some embodiments, such as Figure 8 As shown, an N-InP layer 702 and a first quantum well layer 703 are sequentially grown on a substrate 701. Then, a predetermined region of the first quantum well layer 703 is etched to remove the first quantum well layer 703 in the predetermined region. Then, a second quantum well layer 703' is grown in the predetermined region using a docking growth process. A P-InP layer 704 and an InGaAs contact layer 705 can be sequentially grown on the first quantum well layer 703 and the second quantum well layer 703' to form an epitaxial structure 700.

[0072] The substrate 701 can be a semi-insulating substrate of InP-based and its multi-component compound materials, GaAs-based and its multi-component compound materials, etc. If current flows into the substrate 701, it will not diffuse laterally along the substrate 701, thereby ensuring the accuracy of resistance measurement in the direction perpendicular to the wafer.

[0073] The first quantum well layer 703 is grown according to the growth process required for quantum well layers in a DFB laser. The preset region includes the area where the quantum well layer required for growing the MZ modulator and test device needs to be grown. The second quantum well layer 703' is grown according to the growth process required for quantum well layers in an MZ modulator. For example, the proportions of Al and As in the first quantum well layer 703 and the second quantum well layer 703' are different. The first quantum well layer 703 can provide light source gain and can be used to fabricate a laser, while the second quantum well layer 703' can achieve refractive index modulation of the optical field by the electric field and can be used to fabricate a modulator and test device.

[0074] The P-InP layer 704 includes multiple sublayers with gradually varying doping concentrations. For example, the P-InP layer 704, from bottom to top, includes: a first P-InP sublayer with a thickness of 200 nm and a Zn doping concentration of 10 × 10⁻⁶. 17 cm -3 The second P-InP sublayer has a thickness of 200 nm and a Zn doping concentration of 15 × 10⁻⁶. 17 cm -3 The third P-InP sublayer has a thickness of 600 nm and a Zn doping concentration of 20 × 10⁻⁶. 17 cm -3 .

[0075] In some embodiments, a buffer layer is first grown on top of the substrate 701 using epitaxial growth technology in a PECVD device, followed by the growth of an N-InP layer 702. The buffer layer can be an InP layer with a thickness of 250 nm. The buffer layer can be used to reduce the impact of substrate defects on the quality of the epitaxial layer.

[0076] After obtaining the epitaxial structure, the test device can be fabricated simultaneously during the fabrication of the laser chip using the epitaxial structure 700. Figure 9 This is a schematic diagram of wafer region distribution according to some embodiments. For example... Figure 9 As shown, the first region, the second region, and the third region are different regions on the same epitaxial structure 700. The second region is used to fabricate the modulator of the integrated optical chip, such as the MZ modulator. The first region is used to fabricate the laser of the integrated optical chip, such as the DFB laser. The third region is used to fabricate the test device. The quantum well layer of the first region is the first quantum well layer 703, and the quantum well layers of the second region and the third region are both the second quantum well layer 703'.

[0077] Figure 10 This is a schematic diagram of the extensional structure of the third region according to some embodiments, such as Figure 10 As shown, the epitaxial structure of the third region may include a third substrate 701c, a third N-InP layer 702c, a third quantum well layer 703'c, a third P-InP layer 704c, and a third InGaAs contact layer 705c, wherein the third substrate 701c is a part of the substrate 701, the third N-InP layer 702c is a part of the N-InP layer 702, the third quantum well layer 703'c is a part of the second quantum well layer 703', the third P-InP layer 704c is a part of the P-InP layer 704, and the third InGaAs contact layer 705c is a part of the InGaAs contact layer 705.

[0078] The following steps, S120-S180, are based on... Figure 8 The process of simultaneously fabricating laser chips and test devices using the epitaxial structure shown is described.

[0079] Step S120: Grow a SiNx mask layer and etch the SiNx mask layer in the first region, the second region and the third region respectively to obtain a SiNx mask. In the first region, etch both sides of the SiNx mask downwards to above the first quantum well layer. The first region is located above the first quantum well layer and is used to fabricate the laser of the laser chip. The second region and the third region are located above the second quantum well layer. The second region is used to fabricate the modulator of the laser chip and the third region is used to fabricate the test device of the laser chip.

[0080] In some embodiments, a SiNx mask layer is grown on a substrate and etched to obtain different SiNx masks in a first region, a second region, and a third region, respectively. The SiNx mask in the third region is used to etch the epitaxial structure in the third region to obtain a partial main structure of the test device, which is called a columnar structure. The SiNx mask in the first region is used to determine the ridge waveguide position of the laser, and the SiNx mask in the second region is used to determine the ridge waveguide position of the modulator.

[0081] Figure 11 This is a schematic diagram of the SiNx mask in the third region according to some embodiments, such as Figure 11 As shown, the SiNx mask in the third region can be a mask with a smaller area, such as a square mask 706c. This square mask 706c is also called the first SiNx mask. Of course, its shape is not limited to square, and it can also be other shapes, such as circles.

[0082] In some embodiments, a PECVD device can be used at 280°C. Figure 8 A 500 nm thick SiNx mask layer is grown on the epitaxial structure 700 shown. Subsequently, using a 600 nm thick photoresist as a mask, a mixed gas of CFH3 and O2 is introduced into a reactive ion etching (RIE) device to etch away the SiNx mask layer except at the first location in the third region. The first location is the location of the aforementioned square mask, which can be 10 μm × 10 μm in size. Etching the SiNx mask layer in the first region leaves one SiNx mask for forming a 1.6 μm wide single-ridge waveguide structure. Etching the SiNx mask layer in the second region leaves two SiNx masks for forming a 1 μm wide double-ridge waveguide structure.

[0083] This disclosure embodiment, by preparing a SiNx mask and using the SiNx mask as a hard mask for subsequent semiconductor etching processes, can significantly improve the precision of the etched pattern and the perpendicularity of the sidewalls, ensuring the dimensional accuracy and consistency of the device structure in each region.

[0084] In some embodiments, for lasers, a ridge waveguide structure is further fabricated in this step to define the optical confinement structure of the laser. Specifically, etching is performed in the first region using a SiNx mask as a mask, and a mixed gas of Cl2 and H2 is used in ICP to etch the SiNx mask to the upper surface of the quantum well layer at 300°C on both sides of the mask.

[0085] In some embodiments, after obtaining the SiNx mask in the first region, before etching with a mixture of Cl2 and H2 gas by ICP, the region other than the region to be etched can be protected by setting a first mask layer.

[0086] For example, a 400 nm thick first mask layer can be grown at 280 °C using a PECVD device. The composition of this mask layer can be SiO2. Then, a 2000 nm thick photoresist is used as a mask. In the first region, a 12 μm wide area is defined by exposure. This 12 μm wide area is the area above and to both sides of the SiNx mask within a predetermined range. The SiNx mask can be located in the middle of this 12 μm wide area. The first mask layer is etched using a BOE solution, so that the first mask layer in the 12 μm wide area is removed. Subsequently, during ICP etching using a mixed gas of Cl2 and H2, the SiNx mask is protected by the SiNx mask in the 12 μm wide area and is not etched. The two sides of the SiNx mask are etched to the upper surface of the quantum well layer. Outside the 12 μm wide area, the first mask layer is protected and is not etched.

[0087] In the second and third regions, after the first mask layer is grown and photoresist is applied, the photoresist pattern is not defined. As a result, after development, the photoresist in the second and third regions is completely removed, and the entire first mask layer in the second and third regions can be etched away with BOE solution.

[0088] Step S130: In the first region and the second region, each preset sub-region is etched into the N-InP layer, and in the third region, a SiNx mask is used as a mask to etch into the N-InP layer to form a columnar body.

[0089] In some embodiments, this step is used to etch into the N-InP layer. In the first region, a preset sub-region is a side region containing the area centered on the SiNx mask, i.e., a 12μm wide area on one side. This preset sub-region is 15μm wide and is also called the first sub-region. In the second region, the preset sub-region is the area on both sides of the two SiNx masks. In the third region, except for the area containing the SiNx mask, all areas are to be etched into the N-InP layer, thereby forming a columnar body within the third region. The etching of each region is performed synchronously, ensuring that the etching depth is substantially the same. Especially in the second and third regions, due to their identical epitaxial structure, the etching depth is almost identical, ensuring the accuracy of the bulk resistance measured by the test device in reflecting the bulk resistance of the modulator.

[0090] See Figure 12In the third region, a columnar structure with a square mask 706c at the top is formed. The third quantum well layer 703'c, the third P-InP layer 704c, and the third InGaAs contact layer 705c are all etched into the columnar structure. The third N-InP layer 702c is partially etched into the columnar structure and partially located above the third substrate 701c.

[0091] In some embodiments, in order to protect areas other than the area to be etched from being etched, a second mask layer can be set before etching to the N-InP layer to protect the areas other than the area to be etched.

[0092] For example, a 400nm thick second mask layer can be grown at 280°C using a PECVD device. This mask layer can be composed of SiO2. Then, a 2000nm thick photoresist layer is coated. No photoresist patterning is performed in the third region. Photoresist patterning is performed in the first region based on a 15μm wide area. Photoresist patterning is performed in the second region. In the second region, the second sub-region includes three preset sub-regions and two SiNx mask locations. One of these preset sub-regions is located between two SiNx masks. In the middle of the region where the x-mask is located, two other preset sub-regions are located on the other side of the regions where the two SiNx masks are located. The second sub-region can be a 62μm wide area. The photoresist pattern is defined in the first region, and the photoresist is developed. The remaining photoresist will be used as a mask. Using the photoresist as a mask, each region is etched with BOE solution, so that the second mask layer in the third region is completely etched away, the second mask layer in the 62μm wide area of ​​the second region is etched away, and the second mask layer in the 15μm wide area of ​​the first region is etched away.

[0093] Subsequently, during ICP etching at 300°C using a mixed gas of Cl2 and H2, in the second region, the area outside the 62μm wide region is protected by a second mask layer and is not etched. Within the 62μm wide region, except for the area where the two SiNx masks are located which is protected by SiNx masks, the remaining area is etched into the N-InP layer, forming a 1μm wide double-ridge waveguide structure in the second region. In the first region, a 15μm wide region is etched into the N-InP layer, forming a 15μm wide deep pit structure, and the remaining area is protected by the second mask layer and is not etched. In the third region, except for the area where the SiNx masks are located which is protected by SiNx masks, the remaining area is etched into the N-InP layer, thus forming a columnar structure in the third region.

[0094] Step S140: Grow a SiO2 mask layer, etch the SiO2 mask layer at a preset position in the second region, etch the SiO2 mask layer in the third region of the third sub-region, and obtain a second SiO2 sub-mask located at the top of the column and a first SiO2 sub-mask and a third SiO2 sub-mask located on both sides of the column.

[0095] In some embodiments, this step is used to expose the location of another part of the main structure of the test device in a third region, the main structure being referred to as a platform, which is located below the column, and to expose a preset location in a second region, the preset location being the location in the modulator to be etched to the substrate, where no location exposure is required in the first region.

[0096] The platform's location can be divided into three parts: the location of the column, and the two sides of the column. The preset location of the second region can be included in the middle of the two preset sub-regions on both sides.

[0097] The exposure at the above locations can be achieved by growing and etching a SiO2 mask layer, with the location corresponding to the retained SiO2 mask layer being the location to be exposed.

[0098] For example, a 600 nm thick SiO2 mask layer can be grown at 280 °C using a PECVD device; then a 2000 nm thick photoresist layer is coated, and then a pattern is defined according to the platform position, which is a third sub-region. The third sub-region is a strip-shaped area containing the third region and located in the center of the SiNx mask. The area is small, which can further limit the lateral diffusion of current, improve the accuracy of volume resistance measurement, and facilitate the stable connection of air bridges. The length of the third sub-region can be 3 to 5 times the width of the first SiNx mask, and the width of the third sub-region can be 1.2 to 1.5 times the width of the first SiNx mask. This ensures sufficient mechanical stability of the platform structure and space for N-face electrode arrangement, while avoiding increased lateral current diffusion caused by an excessively large third sub-region area. This achieves an optimized balance between structural reliability and volume resistance accuracy. In this embodiment, the width is specifically 12 μm and the length is 40 μm. The width of 15 μm is slightly larger than the 10 μm width of the SiNx mask, which can balance ensuring the stability of the columnar structure, avoiding excessive lateral current diffusion, and meeting the requirements for arranging N-face electrodes. The length is 40 μm. m, thus leaving 15μm on each side of the columnar body, forming a 15μm×15μm square region to facilitate subsequent electrode arrangement. No photoresist patterning is performed in the first region, while in the second region, the photoresist pattern is defined according to preset positions. The photoresist is then developed, and the remaining photoresist serves as a mask. Using the photoresist as a mask, each region is etched with BOE solution. In the third region, a second SiO2 sub-mask is obtained at the top of the columnar body, and first and third SiO2 sub-masks are located on both sides of the columnar body. The SiO2 mask layer at the preset position in the second region is etched, while the first region is protected by the photoresist and is not etched. After etching the SiO2 mask layer, the photoresist is removed.

[0099] See Figure 13 ,and Figure 12 In comparison, a second SiO2 sub-mask 7072 is added above the square mask 706c, and a first SiO2 sub-mask 7071 and a third SiO2 sub-mask 7073 are added to both sides of the columnar body, respectively.

[0100] Step S150: In the second and third regions, SiO2 mask layer is used as a mask to etch into the substrate.

[0101] In some embodiments, this step is used to etch to the substrate in a third region to form a platform, and to etch to the substrate in a second region, where etching to the substrate is not required in the first region.

[0102] For example, a mixed gas of Cl2 and H2 can be used in an ICP device to perform a second deep etching at 300°C, with an etching depth of approximately 2 μm, to etch into the semi-insulating substrate to a predetermined depth. After this etching step: the third sub-region of the third region forms a platform above the substrate surface below the pillar; the first region is not etched in this step because it is completely protected by the SiO2 mask layer; and the second region is etched into the substrate at a predetermined position.

[0103] Using a mixed gas of Cl2 and H2 for deep etching and precisely controlling the etching depth into the substrate can ensure that the platform structure containing the columnar body has sufficient height for setting the N-side electrode, thereby improving the isolation effect between the N-side electrode and the outside of the platform.

[0104] See Figure 14 The third region has been etched into the third substrate 701c, and the platform above the third substrate 701c belongs to the third N-InP layer 702c.

[0105] Step S160: Remove the SiO2 mask layer and the SiNx mask layer, grow a SiO2 pad layer, etch the SiO2 pad layer to remove the SiO2 pad layer in the first region except at a preset location in the second region, and form a first SiO2 pad, a second SiO2 pad, a third SiO2 pad and a fourth SiO2 pad around the third sub-region, and grow a SiO2 passivation layer.

[0106] In some embodiments, for the third region, this step requires the generation of four pads, while for the first and second regions, this step does not require the generation of pads. After the pads are prepared, a SiO2 passivation layer needs to be grown uniformly to protect the device surface.

[0107] In this step, all mask layers need to be removed to prepare for subsequent processes. Specifically, hydrofluoric acid etching is used for a preset time, such as 1 minute, to completely etch away the SiNx mask layer and all SiO2 mask layers, exposing a clean semiconductor material surface. Using hydrofluoric acid to remove all SiO2 and SiNx mask layers in one step thoroughly removes mask residue accumulated in previous steps, ensuring the interface quality of the subsequently grown SiO2 pad layer and improving the long-term reliability and electrical performance stability of the device.

[0108] After the SiO2 pad layer is grown, by etching the SiO2 pad layer, a first SiO2 pad, a second SiO2 pad, a third SiO2 pad, and a fourth SiO2 pad can be formed around the third sub-region in the third region. In the first region, all SiO2 pad layers need to be etched away. In the second region, SiO2 pad layers except for those at preset positions are etched away. Finally, a SiO2 passivation layer is grown.

[0109] For example, after removing all mask layers, a SiO2 pad layer of a predetermined thickness can be grown using a PECVD device. For instance, a 2000nm thick SiO2 pad layer can be grown at 280°C using a PECVD device. To obtain four SiO2 pads at specific locations, a 2000nm thick photoresist can be coated. Then, the photoresist is patterned at the four predetermined pad locations in the third region. No patterning is performed in the first region, but patterning is performed in the second region according to the predetermined locations. The photoresist is then developed, and the remaining photoresist serves as a mask. Using the photoresist as a mask, BOE solution is used for etching to form four pads in the third region for subsequent pad support. Each pad can be a 70μm×70μm square pad, arranged in a cross shape with a central column as the center. The SiO2 pad layer in the first region and the SiO2 pad layer in the second region, except for the predetermined locations, are completely etched away. All photoresist is then removed.

[0110] After the pad is prepared, a 400 nm thick SiO2 passivation layer can be grown at 280 °C using a PECVD device.

[0111] See Figure 15 Four pads have been formed around the columnar body, where S1 is the first SiO2 pad, S2 is the second SiO2 pad, S3 is the third SiO2 pad, and S4 is the fourth SiO2 pad. It should be noted that at this point, a SiO2 passivation layer covers the top of the four pads, the platform, and the top of the columnar body. Figure 13 , Figure 14 The first SiO2 sub-mask 7071, the second SiO2 sub-mask 7072, and the third SiO2 sub-mask 7073 have been removed in this step. For ease of distinction, the SiO2 passivation layer grown at the location of the first SiO2 sub-mask 7071 is called the first SiO2 passivation layer 7081, the SiO2 passivation layer grown at the location of the second SiO2 sub-mask 7072 is called the second SiO2 passivation layer 7082, the SiO2 passivation layer grown at the location of the third SiO2 sub-mask 7073 is called the third SiO2 passivation layer 7083, and the substrate SiO2 passivation layer above the third substrate 701c is called the fourth SiO2 passivation layer 7084.

[0112] Step S170: Etch SiO2 passivation layers in the first and second regions to prepare P-side and N-side electrodes, etch SiO2 passivation layers on the top of the columnar body to prepare the second electrode, and etch SiO2 passivation layers on both sides of the columnar body to prepare the first and third electrodes.

[0113] In some embodiments, metal electrodes need to be prepared in this step. Specifically, SiO2 passivation layers are etched in the second region and the first region respectively to prepare P-side electrodes and N-side electrodes. Similarly, SiO2 passivation layers need to be etched in the third region to prepare P-side electrodes and N-side electrodes. For ease of distinction, the P-side electrode in the third region can be called the second electrode, and the N-side electrode in the third region includes the first electrode and the third electrode.

[0114] For example, the metal electrode is fabricated via a deposition process. To fabricate the metal electrode at a specific location, a 2000 nm thick photoresist is applied, followed by patterning and development to remove the photoresist at the location where the metal electrode needs to be fabricated. In the third region, the location where the metal electrode needs to be fabricated includes the top and sides of the pillar, while in the second and first regions, the location where the metal electrode needs to be fabricated includes the top of the ridge waveguide and the N-plane bias region.

[0115] After removing the photoresist at the locations where metal electrodes need to be deposited, the remaining photoresist is used as a mask. In a RIE device, a mixed gas of CFH3 and O2 is used to etch the SiO2 passivation layer to form an electrical injection window. The electrical injection window size at each sub-mask location in the third region can be the same and slightly smaller than the size of the first SiNx mask, for example, all can be 8μm×8μm. The size of the electrical injection window in other regions can be determined according to actual needs. A double layer of photoresist is then applied, i.e., another layer of photoresist is coated, and only the photoresist outside the electrical injection window is removed. A metal stack of 40nm Ti, 100nm Pt and 100nm Au is deposited sequentially by electron beam evaporation (E-beam), and then excess metal is removed by a lift-off process, thereby forming metal electrodes within each electrical injection window.

[0116] In the above embodiments, by setting electrical injection windows of uniform size, all smaller than the SiNx mask, the precise alignment of the metal electrode and the semiconductor contact area can be ensured, avoiding the risk of leakage caused by metal climbing over the wall. At the same time, the consistency of each contact area is ensured, improving the accuracy and repeatability of contact resistance testing.

[0117] See Figure 16 ,and Figure 15 In contrast, in this step, a first electrode 7091 is prepared on the first SiO2 passivation layer 7081 in the third region, a second electrode 7092 is prepared on the second SiO2 passivation layer 7082, and a third electrode 7093 is prepared on the third SiO2 passivation layer 7083.

[0118] Step S180: A first air bridge is fabricated in the second region, and a second air bridge and pads are fabricated in the third region. The pads are located on each pad. The second air bridge includes a first sub-bridge, a second sub-bridge, and a third sub-bridge. The first sub-bridge is used to connect the pads on the first SiO2 pad to the first electrode. The second sub-bridge is used to connect the pads on the second SiO2 pad, the second electrode, and the pads on the fourth SiO2 pad. The third sub-bridge is used to connect the pads on the third SiO2 pad to the third electrode.

[0119] In some embodiments, this step requires fabricating pads and air bridges in a third region. The pads are metal pads used to provide contact points for external probes, and the air bridges are metal bridges used to connect the metal electrodes to the pads. In the first region, metal electrodes need to be deposited to ensure their distribution meets predetermined requirements. In the second region, air bridges need to be fabricated to connect the metal electrodes on either side of a predetermined location. For ease of distinction, the air bridge in the second region is referred to as the first air bridge, and the air bridge in the third region is referred to as the second air bridge.

[0120] For example, firstly, a 4μm thick photoresist is uniformly exposed and developed, then baked at 300°C for 5 minutes to obtain air bridge supports. Since the first region does not require air bridge fabrication, no air bridge supports are needed, and all photoresist needs to be removed. Only the photoresist on the top of the ridge waveguide in the second region is exposed a second time to remove the photoresist from the top of the ridge waveguide. During the second exposure, care must be taken to preserve the air bridge supports on both sides of the ridge waveguide. Subsequently, a 20nm thick photoresist is deposited using a sputtering process. A Ti / Au seed gold structure with a thickness of 150 nm was constructed. The substrate was then coated again, exposed, and developed to reveal the electroplating pattern, including the pads and air bridges. The Au layer was thickened to 2 μm through electroplating. After resist removal, the substrate was coated again, exposed, and developed to obtain the protective electrode pattern. The Au layer outside the protective electrode pattern was removed using an I2 / KI etchant, and the Ti layer outside the protective pattern was removed using an ammonia / hydrogen peroxide etchant. Finally, the substrate was removed, and the air bridges were removed using a plasma device with a mixture of O2 and Ar gas to complete the fabrication of the air bridges and pads.

[0121] In the third region, four pads are fabricated on four SiO2 pads, arranged in a cross shape, and connected by an air bridge to form a three-dimensional four-terminal cross-shaped test device.

[0122] See Figure 17 ,and Figure 16In contrast, in this step, a first pad T1 is prepared above the first SiO2 pad in the third region, a second pad T2 is prepared above the second SiO2 pad, a third pad T3 is prepared above the third SiO2 pad, and a fourth pad T4 is prepared above the fourth SiO2 pad. A first subbridge B1 connects the first pad T1 to the first electrode 7091, a second subbridge B2 connects the second pad T2, the second electrode 7092, and the fourth pad T4, and a third subbridge B3 connects the third pad T3 to the third electrode 7093.

[0123] Figure 18 This is a schematic diagram of the structure of a laser according to some embodiments, such as Figure 18 As shown, the laser includes a first substrate 701a, a first N-InP layer 702a, a first preset quantum well layer 703a, a first P-InP layer 704a, a first InGaAs contact layer 705a, a first passivation layer 708a, and a first electrode layer 709a, wherein the first electrode layer 709a also includes a P-side electrode and an N-side electrode.

[0124] The first substrate 701a is a part of substrate 701, the first N-InP layer 702a is a part of N-InP layer 702, the first preset quantum well layer 703a is a part of first quantum well layer 703, the first P-InP layer 704a is a part of P-InP layer 704, and the first InGaAs contact layer 705a is a part of InGaAs contact layer 705.

[0125] See Figure 18 Position A above the first InGaAs contact layer 705a is the position of the SiNx mask retained in step S120 in the first region. In step S120, the 12μm wide region is the region etched from the left side to the top of the first preset quantum well layer 703a and from the right side to the top of the first preset quantum well layer 703a, and the 15μm wide region is the region etched to the first N-InP layer 702a.

[0126] Figure 19 This is a schematic diagram of the modulator according to some embodiments, such as Figure 19 As shown, the modulator includes a second substrate 701b, a second N-InP layer 702b, a second preset quantum well layer 703'b, a second P-InP layer 704b, a second InGaAs contact layer 705b, a second passivation layer 708b, and a second electrode layer 709b. The second electrode layer 709b includes a P-side electrode and an N-side electrode (not shown). There is an arc-shaped first air bridge above the P-side electrode. At a preset position, a SiO2 pad layer is located below the second passivation layer 708b.

[0127] The second substrate 701b is a part of the substrate 701, the second N-InP layer 702b is a part of the N-InP layer 702, the second preset quantum well layer 703'b is a part of the second quantum well layer 703', the second P-InP layer 704b is a part of the P-InP layer 704, and the second InGaAs contact layer 705b is a part of the InGaAs contact layer 705.

[0128] See Figure 19 Positions C1 and C2 above the second InGaAs contact layer 705b are the positions of the two SiNx masks retained in step S120 in the second region. In step S130, the 62μm wide region is the area between the left side and the right side of the second N-InP layer 702b, and the preset position is the position etched to the second substrate 701b.

[0129] Through the above steps, integrated optical chips containing a laser and a modulator can be simultaneously fabricated in different regions of the same epitaxial structure. The columnar structure in the test device retains the complete epitaxial structure above substrate 701 and is identical to the epitaxial structure of the modulator. Its resistance test results can accurately reflect the resistance characteristics of the modulator. Because the cross-section of the columnar structure is small, the injected current does not diffuse laterally significantly, solving the problem that after the laser chip is fabricated, the injected current will diffuse significantly laterally between the modulator and laser, making it impossible to accurately measure the bulk resistance perpendicular to the wafer direction. This provides a reliable basis for optimizing the optical chip process. Other structures in the test device, such as pads and solder pads, provide hardware support and signal output channels for resistance testing, ensuring the stability and convenience of the test.

[0130] After the above preparation is completed, the bulk resistance in the direction perpendicular to the wafer can be tested using a testing device.

[0131] Figure 20 This is a schematic diagram of the resistance distribution according to some embodiments, such as Figure 20 As shown, the resistance distributed in the direction perpendicular to the wafer includes the contact resistance R. c The bulk resistance R of the InGaAs contact layer In The bulk resistance R of the P-InP layer P PIN junction resistance R i and the bulk resistance R of the N-InP layer N Among them, the contact resistance R c It is the contact resistance between the metal electrode and the InGaAs contact layer, where the thickness of the InGaAs contact layer is W. In The thickness of the P-InP layer is W. P PIN junction resistance R iThis is the PIN junction resistance corresponding to the second quantum well layer, and the thickness of the second quantum well layer is W. i The thickness of the N-InP layer is W. N .

[0132] The total resistance in the direction perpendicular to the wafer is: R S =R c +R In +R P +R N PIN junction resistance R i The calculation formula is: R i =[n×VT×ln(I / I0)] / I Where n is the ideality factor, which is 2 in the PIN junction, VT is the thermal voltage, I0 is the reverse saturation current, VT and I0 are known data, and I is the current injected into the test device.

[0133] Measure R respectively S R c R In R P and R N R can be calculated P By connecting a current source and a voltmeter to the test device, R can be measured. S .

[0134] Figure 21 This is a schematic diagram of volume resistance measurement according to some embodiments, such as Figure 21 As shown, a current source is connected between the first pad T1 and the second pad T2, and a voltmeter is connected between the third pad T3 and the fourth pad T4. The first pad T1 is connected to the negative terminal of the current source, the second pad T2 is connected to the positive terminal of the current source, the third pad T3 is connected to the negative terminal of the voltmeter, and the fourth pad T4 is connected to the positive terminal of the voltmeter.

[0135] In some embodiments, different magnitudes of current I are injected sequentially through a current source, and voltmeter readings are obtained under different injection currents to obtain multiple voltages V. The injection current range is from 30mA to 50mA, and the step interval is 5mA. The current values ​​of multiple injection currents and the voltage values ​​corresponding to the voltmeter readings are recorded, and the relationship between voltage V and current I can be fitted.

[0136] The relationship between voltage and current is as follows: V=V on +R S ×I+R i ×I Among them, V on This is the turn-on voltage for the PIN junction.

[0137] Transform the above relationship: dV / dI=R S +n×VT / I A linear fit is performed with dV / dI as the y-axis and 1 / I as the x-axis. The y-intercept of the fitted line is the total resistance R. S .

[0138] In some embodiments, to determine the bulk resistance of the P-InP layer, i.e., R P You also need to obtain R c R In and R N These resistors can be obtained through TLM test patterns.

[0139] TLM test patterns are divided into P-TLM and N-TLM, which can also be prepared simultaneously during the fabrication of laser chips.

[0140] Figure 22 This is a schematic diagram of the wafer region distribution according to some other embodiments. For example... Figure 22 As shown, the wafer may include a first region, a second region, a third region, a fourth region, and a fifth region, wherein, with Figure 9 In contrast, one side of the third region is the fourth and fifth regions. The fourth, fifth, second, and third regions share the same second quantum well layer. The fourth region is used to prepare P-TLM, and the fifth region is used to prepare N-TLM. The third, fourth, and fifth regions are independent of each other and will not interfere with their respective resistance measurements.

[0141] P-TLM can be used to measure R c The corresponding specific contact resistivity ρc can be used to calculate the R of the test device. c The calculation formula is: R c =ρc / L 2 Where L is the width of the columnar body of the test device.

[0142] P-TLM can also be used to measure R In The resistivity ρIn of the corresponding InGaAs contact layer can be used to calculate the R of the test device. In The calculation formula is: R In =ρ In ×W In / L² N-TLM can be used to measure R n The resistivity ρN of the corresponding N-InP layer can be used to calculate the R of the test device. N The calculation formula is: R N=ρN×W N / L² Based on the above embodiments, R can be calculated. P :R P =R S -R c -R In -R N .

[0143] After calculating R of the test device P Then, the resistivity ρ of the P-InP layer can be calculated. P The calculation formula is: ρ P =R P ×L² / W P Thus, the resistivity of graded-doped semiconductor materials in the P-InP layer perpendicular to the wafer direction has been accurately extracted.

[0144] The above embodiments decompose the total resistance into R P R c R In and R N By measuring each of these four components and then discarding the first three, the bulk resistance R of the P-InP layer can be accurately obtained. P This enabled precise analysis of the resistivity characteristics of graded-doped P-InP layers perpendicular to the wafer direction. Since the test device and the MZ modulator have identical epitaxial structures and are fabricated synchronously on the same wafer, the calculated resistivity ρ of the P-InP layer of the test device was obtained. P It can accurately reflect the resistance characteristics of the P-InP layer in the MZ modulator, and has a significant guiding role in subsequent bandwidth optimization.

[0145] In some implementations, if it is necessary to obtain the bulk resistance of the P-InP layer of the laser in the laser chip along the direction perpendicular to the wafer, the test device can be placed close to the first region during fabrication, sharing the same first quantum well layer as the laser, and then the resistivity ρ can be measured. P It can accurately reflect the resistance characteristics of the P-InP layer in the laser.

[0146] It should be noted that this disclosure is not limited to the vertical wafer orientation resistance extraction of laser chips with the above-mentioned structural types; all structures involving a three-dimensional four-terminal cross-shaped structure are within the scope of protection of this disclosure. This structure includes, but is not limited to, the following variations: Regarding waveguide shape, the square columnar shape can be replaced with other shapes such as circles, rectangles, and triangles.

[0147] Regarding the cross-shaped structure, four test terminals can be led out from four directions of the column, and the included angle between the terminals is not limited to 90 degrees, but can be adjusted according to the actual layout requirements.

[0148] In terms of epitaxial structure and substrate, it is not limited to InP-based and its multi-component compound materials, but can also be applied to other semiconductor material systems such as GaAs-based and its multi-component compound materials.

[0149] Regarding electrode placement, it is not limited to coplanar electrodes; other electrode layouts, such as non-coplanar electrodes, can also be used.

[0150] All methods involving the extraction of resistance values ​​using a four-terminal cross-shaped structure are within the scope of protection of this disclosure.

[0151] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a laser chip, characterized in that, include: An N-InP layer and a first quantum well layer are grown on a semi-insulating substrate. A predetermined area of ​​the first quantum well layer is etched and a second quantum well layer is grown in connection. A P-InP layer and an InGaAs contact layer are grown sequentially on the first quantum well layer and the second quantum well layer. A SiNx mask layer is grown, and the SiNx mask layer is etched in a first region, a second region, and a third region to obtain a SiNx mask. In the first region, both sides of the SiNx mask are etched downwards to above the first quantum well layer. The first region is located above the first quantum well layer and is used to fabricate the laser of the laser chip. The second region and the third region are located above the second quantum well layer. The second region is used to fabricate the modulator of the laser chip, and the third region is used to fabricate the test device of the laser chip. In the first region and the second region, each preset sub-region is etched into the N-InP layer, and in the third region, the SiNx mask is used as a mask to etch into the N-InP layer to form a columnar body. A SiO2 mask layer is grown, and the SiO2 mask layer is etched at a predetermined position in the second region. The SiO2 mask layer in the third sub-region is etched in the third region to obtain a second SiO2 sub-mask located at the top of the column and a first SiO2 sub-mask and a third SiO2 sub-mask located on both sides of the column. In the second and third regions, the SiO2 mask layer is used as a mask to etch into the semi-insulating substrate; Remove the SiO2 mask layer and the SiNx mask layer, grow a SiO2 pad layer, etch the SiO2 pad layer to remove the SiO2 pad layer in the first region except for the preset position in the second region, and form a first SiO2 pad, a second SiO2 pad, a third SiO2 pad and a fourth SiO2 pad around the third sub-region, and grow a SiO2 passivation layer; The SiO2 passivation layer is etched in the first region and the second region to prepare a P-side electrode and an N-side electrode. The SiO2 passivation layer is etched on the top of the columnar body to prepare a second electrode. The SiO2 passivation layer is etched on both sides of the columnar body to prepare a first electrode and a third electrode. A first air bridge is fabricated in the second region, and a second air bridge and pads are fabricated in the third region. The pads are located on each pad. The second air bridge includes a first sub-bridge, a second sub-bridge, and a third sub-bridge. The first sub-bridge is used to connect the pads on the first SiO2 pad to the first electrode. The second sub-bridge is used to connect the pads on the second SiO2 pad, the second electrode, and the pads on the fourth SiO2 pad. The third sub-bridge is used to connect the pads on the third SiO2 pad to the third electrode.

2. The method for fabricating a laser chip according to claim 1, characterized in that, The third sub-region is a SiNx mask that includes the third region and the SiNx mask is located in a strip-shaped region at the center.

3. The method for fabricating a laser chip according to claim 2, characterized in that, The width of the third sub-region is 1.2 to 1.5 times the width of the SiNx mask of the third region, and the length of the third sub-region is 3 to 5 times the width of the SiNx mask of the third region.

4. The method for fabricating a laser chip according to claim 1, characterized in that, The first SiO2 pad, the second SiO2 pad, the third SiO2 pad, and the fourth SiO2 pad are distributed in a cross shape around the column.

5. The method for fabricating a laser chip according to claim 1, characterized in that, Before etching both sides of the SiNx mask downwards over the first quantum well layer within the first region, the process further includes: A first mask layer is grown and etched to completely remove the first mask layer in the second region and the third region, and to remove the first mask layer within a predetermined range above and to both sides of the SiNx mask in the first region.

6. The method for fabricating a laser chip according to claim 1, characterized in that, Before etching each preset sub-region into the N-InP layer in the first region and the second region respectively, the process further includes: A second mask layer is grown and etched to remove the second mask layer in a first sub-region within a first region, remove the second mask layer in a second sub-region within a second region, and remove the second mask layer completely within a third region, wherein the second sub-region includes a predetermined sub-region of the second region.

7. The method for fabricating a laser chip according to claim 1, characterized in that, Etching into the semi-insulating substrate in the second and third regions using the SiO2 mask layer as a mask includes: In the second and third regions, the SiO2 mask layer is used as a mask, and Cl2 and H2 are used to etch to a predetermined depth within the semi-insulating substrate.

8. The method for fabricating a laser chip according to claim 1, characterized in that, Removing the SiO2 mask layer and the SiNx mask layer includes: The SiO2 mask layer and the SiNx mask layer are completely etched away by hydrofluoric acid etching for a preset time.

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