Chip structure and chip manufacturing method

Abstract

The application provides a chip structure and a chip preparation method, and relates to the technical field of active semiconductor light-emitting devices. The chip structure comprises an epitaxial structure and a waveguide structure; the epitaxial structure comprises a substrate and a multilayer structure grown on the substrate based on an epitaxial growth technology, and the waveguide structure is arranged on a top layer opposite to the substrate in the multilayer structure; the multilayer structure comprises a plurality of quantum well layers; and the waveguide structure comprises a plurality of combined ridge waveguides. The chip preparation method comprises the following steps: based on a spectral width requirement, arranging the plurality of quantum well layers in the multilayer structure grown on the substrate of the epitaxial structure; and arranging the waveguide structure comprising the plurality of combined ridge waveguides on the top layer opposite to the substrate in the multilayer structure. The epitaxial structure and the waveguide structure are designed in a superposition mode, the spectral width of the chip is widened through the plurality of quantum well layers in the multilayer structure of the epitaxial structure, and the lasing power of the chip is improved through the plurality of combined ridge waveguides, so that a plurality of core indexes are simultaneously optimized.

Description

Technical Field

[0001] This application relates to the field of active semiconductor light-emitting device technology, and more specifically, to a chip structure and a chip fabrication method. Background Technology

[0002] Super luminescent diodes (SLDs) are single-pass amplified spontaneous emission (ASE) side-emitting devices. Their photoelectric characteristics fall between those of lasers and ASEs, combining the high output power of lasers with the wide spectral characteristics of ASEs. They are widely used in fiber optic gyroscopes, optical coherence tomography (OCT), and fiber optic communications. Spectral width, output power, and spectral ripple are key specifications of SLD chips. Full Width at Half Maximum (FWHM) is determined by the spontaneous emission gain spectrum; applications (such as Optical Coherence Tomography, OCT) require the widest possible width to improve resolution. Output power refers to the single-pass amplification of spontaneous emission through a waveguide; power increases exponentially with gain, and applications require sufficiently high power to improve the signal-to-noise ratio. Spectral ripple refers to the parasitic FP interference caused by residual reflections at the cavity surface, resulting in periodic spectral fluctuations; applications require the lowest possible ripple to avoid coherence artifacts. These three core performance indicators are mutually constrained, as follows: increasing power compresses bandwidth and amplifies ripple; widening bandwidth usually sacrifices power and worsens ripple; and suppressing ripple limits both power and bandwidth. Current chip architectures cannot simultaneously improve all three core performance indicators, resulting in poor chip performance that fails to meet practical application requirements. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a chip structure and a chip fabrication method to improve the problem of poor chip performance caused by the inability of the chip structure to improve the three core indicators at the same time in the prior art.

[0004] To address the aforementioned issues, firstly, embodiments of this application provide a chip structure, which includes: an epitaxial structure and a waveguide structure; The epitaxial structure includes: a substrate, and a multilayer structure grown on the substrate based on epitaxial growth technology, wherein the waveguide structure is disposed on the top layer of the multilayer structure opposite to the substrate; The multilayer structure includes multiple quantum well layers; The waveguide structure includes multiple ridge waveguides that combine beams.

[0005] In the above implementation process, an epitaxial structure and a waveguide structure were superimposed. Multiple quantum well layers were incorporated into the multilayer structure grown within the epitaxial structure, and multiple ridge waveguides capable of beam combining were incorporated into the waveguide structure. The multiple quantum well layers in the multilayer structure allow for different distributions of lasing wavelengths from each quantum well, thereby broadening the chip's spectral width. The beam combining ridge waveguides increases the emitting area of ​​the chip, thus improving the lasing power. Furthermore, the bending of the beam combining ridge waveguides further increases the spectral width and reduces spectral ripple. This approach simultaneously optimizes the three core performance indicators of a superluminescent diode (SED) chip: spectral width, output power, and spectral ripple, effectively improving the SED chip's performance and meeting the practical needs of various application scenarios.

[0006] Optionally, the multi-quantum well layer is configured as a non-uniformly graded multi-quantum well structure.

[0007] In the above implementation process, the multi-quantum well layer is set as a non-uniformly graded multi-quantum well structure, so as to achieve non-uniform wavelength distribution through multiple non-uniform and graded quantum well structures, thereby enabling the wavelength to form a wider spectral width through superposition.

[0008] Optionally, the wavelengths excited by the multiple quantum well structures in the non-uniformly graded multi-quantum-well structure are distributed in a stepped manner. The spectral pattern of the multi-quantum-well layer includes a Gaussian distribution pattern or a flat-top pattern.

[0009] In the above implementation process, due to the non-uniformity and gradual characteristics of multiple quantum well structures, the wavelengths excited by multiple quantum well structures can be distributed in a stepped manner, so that the wavelengths can be superimposed to form a wider spectral width. Furthermore, during the epitaxial growth process, the lasing wavelength of each quantum well structure can be continuously optimized, so that the spectrum of the final superimposed multiple quantum well layers presents different spectral patterns, such as Gaussian distribution patterns or flat-top patterns, in order to improve the uniformity of the spectral surface generated by the chip and reduce the unfavorable situation of unevenness on the spectral surface.

[0010] Optionally, the multilayer structure further includes: a buffer layer, a lower confinement layer, a lower waveguide layer, an upper waveguide layer, an upper confinement layer, a capping layer, and a top electrode metal layer sequentially disposed on the substrate; The multiple quantum well layer is disposed between the lower waveguide layer and the upper waveguide layer.

[0011] In the above implementation process, the multilayer structure also includes different layer structures such as buffer layer, lower confinement layer, lower waveguide layer, upper waveguide layer, upper confinement layer, cover layer and top electrode metal layer, which are stacked in sequence. The multi-quantum well layer is set between the lower waveguide layer and the upper waveguide layer so that the epitaxial structure has the corresponding function.

[0012] Optionally, the waveguide structure includes: a symmetrical first ridge waveguide and a second ridge waveguide; The first ridge waveguide includes a first parallel segment and a first beam combiner segment; The second ridge waveguide includes a second parallel segment and a second beam combiner segment; The first parallel segment and the second parallel segment are arranged in parallel on the high-reflectivity end face; The first beam combiner bends toward the second ridge waveguide, and the second beam combiner bends toward the first ridge waveguide. The first beam combiner and the second beam combiner meet at the end face of the antireflection cavity to form a light outlet.

[0013] In the above implementation, the waveguide structure includes a symmetrically arranged first ridge waveguide and a second ridge waveguide. Each ridge waveguide includes a corresponding parallel segment and a beam-combining segment. The two parallel segments are arranged parallel to each other at the high-reflectivity end face, and the two beam-combining ends are bent towards the other ridge waveguide. Furthermore, the two beam-combining segments converge at the antireflection cavity end face to form the light exit port. By designing a beam-combining structure with two symmetrical ridge waveguides, the light-emitting area of ​​the chip is increased, thereby improving the lasing power of the chip. Moreover, designing the beam-combining segment of the two ridge waveguides as a curved waveguide further increases the spectral width, reduces spectral ripple, and reduces the chip cavity length. This mitigates the adverse effects of stimulated emission caused by FP-cavity surface resonance due to long cavities and long ridge waveguides, which leads to increased spectral ripple.

[0014] Optionally, the first ridge waveguide and the second ridge waveguide are configured as narrow ridge waveguides.

[0015] In the above implementation process, the first ridge waveguide and the second ridge waveguide can be configured as narrow ridge waveguides to limit the lateral mode of the chip, thereby enabling the emitted chip to maintain single lateral mode characteristics.

[0016] Optionally, the first ridge waveguide and the second ridge waveguide are configured as a width-gradient structure; The width of the first ridge waveguide gradually increases from narrow to wide from the first parallel segment to the first beam-combining segment; The width of the second ridge waveguide gradually increases from the narrowest point to the widest point from the second parallel segment to the second beam-combining segment.

[0017] In the above implementation process, in order to further improve the power of the chip, the first ridge waveguide and the second ridge waveguide can be set as a width-gradient structure. The width of the two ridge waveguides changes from narrow to wide from the parallel section to the beam-combining section. That is, the ridge waveguide at the high reflection end face is narrower, and the ridge waveguide at the antireflection cavity end face is wider.

[0018] Optionally, the waveguide structure further includes: a ring ridge waveguide; The annular ridge waveguide is disposed on the high-reflection end face; The annular ridge waveguide connects the first parallel segment and the second parallel segment.

[0019] In the above implementation process, a curved annular ridge waveguide can also be provided on the high reflectivity end face of the chip. The annular ridge waveguide connects the first parallel segment and the second parallel segment, which can reduce the adverse situation of laser lasing caused by the FP effect, thereby reducing the initial spectral ripple of the chip. The generated photons can also be reflected back into the ridge waveguide through the sidewall of the ridge waveguide, thereby increasing the power of the chip.

[0020] Secondly, embodiments of this application also provide a chip fabrication method, the method comprising: Based on the spectral width requirement, multiple quantum well layers are set in the multilayer structure grown on the epitaxial substrate; A waveguide structure comprising multiple bundled ridge waveguides is disposed on the top layer opposite to the substrate in the multilayer structure.

[0021] In the above implementation process, based on the actual spectral width requirements of the application scenario, multiple quantum well layers can be set in the multilayer structure grown in the epitaxial structure. A waveguide structure including multiple ridge waveguides capable of beam combining can be set on the top layer of the multilayer structure opposite to the substrate. Through the multiple quantum well layers in the multilayer structure, the lasing wavelengths of each quantum well are distributed differently, thereby broadening the spectral width of the chip. The area of ​​the light-emitting region of the chip is increased by the multiple ridge waveguides that are beam combined, thereby increasing the lasing power of the chip. Furthermore, the multiple ridge waveguides that are beam combined will produce a bending condition, which can further increase the spectral width and reduce spectral ripple.

[0022] Optionally, the multi-quantum well layer is configured as a non-uniformly graded multi-quantum well structure; the non-uniformly graded multi-quantum well structure includes: a barrier layer and a potential well layer of multiple quantum well structures; The method of setting multiple quantum well layers in a multilayer structure grown on an epitaxial substrate based on spectral width requirements includes: Based on the spectral width requirement, the structural parameters of the potential well layer are determined; wherein, the structural parameters include the thickness and composition data of the potential well layer; Based on the structural parameters, the wavelength distribution of the corresponding quantum well structure excitation is determined.

[0023] In the above implementation process, the multiple quantum well layers can be set as non-uniformly graded multiple quantum well structures. The non-uniformly graded multiple quantum well structures include barrier layers and potential well layers of multiple quantum well structures. When designing, the thickness, composition data and other structural parameters of each potential well layer can be determined based on the actual spectral width requirements of the application scenario. Based on the structural parameters of the potential well layer, the wavelength distribution of the quantum well structure it belongs to can be determined, so that multiple wavelengths of multiple quantum well structures can be superimposed to form a wider spectral width.

[0024] Optionally, the waveguide structure comprising a plurality of beam-combining ridge waveguides is disposed on the top layer opposite the substrate in the multilayer structure, including: A symmetrical first ridge waveguide and second ridge waveguide are formed on the multilayer structure by a simultaneous etching process. The first ridge waveguide includes a first parallel segment and a first beam-combining segment; the second ridge waveguide includes a second parallel segment and a second beam-combining segment; the first parallel segment and the second parallel segment are arranged parallel to each other on the high-reflection end face; the first beam-combining segment bends toward the second ridge waveguide, the second beam-combining segment bends toward the first ridge waveguide, and the first beam-combining segment and the second beam-combining segment converge at the anti-reflection cavity end face to form a light outlet.

[0025] In the above implementation process, in order to ensure the similarity of multiple ridge waveguides in the waveguide structure, a symmetrical first ridge waveguide and second ridge waveguide can be etched on the top layer of the multilayer structure through a simultaneous etching process, so as to ensure that the beams emitted by the two ridge waveguides are exactly the same, thereby ensuring the beam quality after beam combining.

[0026] Optionally, the waveguide structure comprising a plurality of beam-combining ridge waveguides disposed on the top layer opposite the substrate in the multilayer structure further includes: The interference detection result of the waveguide structure is determined based on the different bending angles of the first beam combiner segment and the second beam combiner segment; Based on the interference detection results, beam requirements, and area parameters of the multilayer structure, the target bending angles of the first beam combining segment and the second beam combining segment are determined; wherein, the target bending angle is set to 3° to 9°.

[0027] In the above implementation process, the waveguide structure under different bending angles of the first and second beam combining segments can be simulated for interference detection to obtain the interference detection results. Based on the interference detection results, beam requirements and area parameters of the multilayer structure, the appropriate target bending angles of the two beam combining segments can be determined so that the optical fibers after beam combining in the two beam combining segments will not produce interference anomalies and the light generated after beam combining will have only one fundamental mode.

[0028] In summary, the embodiments of this application provide a chip structure and a chip fabrication method, which superimpose an epitaxial structure and a waveguide structure. The spectral width of the chip is broadened by the multiple quantum well layers in the multilayer structure of the epitaxial structure, and the lasing power of the chip is improved by multiple ridge waveguides with bundled beams. This can simultaneously optimize the three core indicators of the superluminescent diode chip: spectral width, output power, and spectral ripple, effectively improving the performance of the superluminescent diode chip and meeting the practical needs of various application scenarios. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of a chip structure provided in an embodiment of this application; Figure 2 This is a schematic diagram of an epitaxial structure provided in an embodiment of this application; Figure 3 This is a schematic diagram of a waveguide structure provided in an embodiment of this application; Figure 4 This is a schematic diagram of another waveguide structure provided in an embodiment of this application; Figure 5 This is a schematic flowchart of a chip fabrication method provided in an embodiment of this application; Figure 6 A detailed flowchart of step S200 provided for an embodiment of this application; Figure 7 A schematic diagram of a spectrum provided for an embodiment of this application; Figure 8 This is a detailed flowchart of step S300 provided in an embodiment of this application.

[0031] Icons: 110 - Epitaxial structure; 120 - Waveguide structure; 111 - Substrate; 130 - Multilayer structure; 131 - Multiple quantum well layer; 1311 - Quantum well structure; 112 - Buffer layer; 113 - Lower confinement layer; 114 - Lower waveguide layer; 115 - Upper waveguide layer; 116 - Upper confinement layer; 117 - Capping layer; 118 - Electrode metal layer; 121 - First ridge waveguide; 122 - Second ridge waveguide; 1211 - First parallel segment; 1212 - First beam combiner segment; 1221 - Second parallel segment; 1222 - Second beam combiner segment; 123 - Light exit port; 124 - Ring ridge waveguide. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of the embodiments of this application.

[0033] Spectral width, output power, and spectral ripple are key performance indicators (SLD) chips. In current chip architectures, these three core indicators are mutually restrictive: increasing power compresses bandwidth and amplifies ripple; widening bandwidth usually sacrifices power and worsens ripple; and suppressing ripple limits both power and bandwidth. Current chip architectures cannot simultaneously improve all three core indicators, resulting in poor chip performance that fails to meet practical application requirements.

[0034] To address the aforementioned issues, this application provides a chip structure and a chip fabrication method. It incorporates an epitaxial structure and a waveguide structure, broadening the chip's spectral width through multiple quantum well layers in the multilayer epitaxial structure, and enhancing the chip's lasing power through multiple ridge waveguides. This approach simultaneously optimizes the three core performance indicators of a superluminescent diode chip: spectral width, output power, and spectral ripple, effectively improving the chip's performance and meeting the practical needs of various application scenarios.

[0035] Please see Figure 1 , Figure 1 This is a schematic diagram of a chip structure provided in an embodiment of the present application. The chip structure includes: an epitaxial structure 110 and a waveguide structure 120. The epitaxial structure 110 includes a substrate 111 and a multilayer structure 130 grown on the substrate 111 based on epitaxial growth technology. The waveguide structure 120 is disposed on the top layer of the multilayer structure 130 opposite to the substrate 111.

[0036] Alternatively, the substrate 111 can be designed as a variety of materials based on actual needs, such as an n-GaAs substrate.

[0037] It should be noted that the multilayer structure 130 includes a multi-quantum well layer 131, and the waveguide structure 120 includes multiple beam-combining ridge waveguides. An epitaxial structure 110 and a waveguide structure 120 are stacked. The multilayer structure 130 grown within the epitaxial structure 110 contains a multi-quantum well layer 131, and the waveguide structure 120 contains multiple beam-combining ridge waveguides. Through the multi-quantum well layer 131 in the multilayer structure 130, the lasing wavelengths of each quantum well are distributed differently, thereby broadening the spectral width of the chip. The beam-combining ridge waveguides increase the emitting area of ​​the chip, thereby increasing the lasing power. Furthermore, the beam-combining ridge waveguides exhibit bending, which further increases the spectral width and reduces spectral ripple.

[0038] Optionally, the waveguide structure 120 may include two or more symmetrically arranged ridge waveguides.

[0039] Optionally, please refer to Figure 2 , Figure 2 This is a schematic diagram of an epitaxial structure provided in an embodiment of this application.

[0040] It should be noted that the multiple quantum well layer 131 can be configured as a non-uniformly graded multiple quantum well structure, so as to achieve a non-uniform distribution of wavelength through multiple non-uniform and graded quantum well structures 1311, thereby enabling the wavelength to form a wider spectral width through superposition.

[0041] For example, a non-uniformly graded multi-quantum-well structure may include three or more non-uniform quantum well structures 1311. Figure 2 The diagram shows a case with five quantum wells 1311; other numbers of quantum wells will not be discussed further.

[0042] Optionally, the materials for the non-uniformly graded multi-quantum-well structure may include a variety of materials such as AlxGaAs, GaAsP, AlxGaAs, GaAsP, and AlxGaAs.

[0043] It should be noted that, due to the non-uniformity and gradient characteristics of the multiple quantum well structures 1311, the wavelengths excited by the multiple quantum well structures 1311 in the non-uniform gradient multiple quantum well structure can be distributed in a stepped manner, so that the wavelengths can be superimposed to form a wider spectral width.

[0044] Optionally, after the growth of multiple quantum well structures 1311, during actual operation, uneven current distribution will lead to certain differences in the lasing power and response speed of different quantum well structures 1311, resulting in unevenness on the spectral surface of the chip and affecting the spectral width of the chip. Therefore, during the epitaxial growth process, the lasing wavelength of each quantum well structure 1311 can be continuously optimized so that the spectrum of the final superposition of multiple quantum well layers 131 presents different spectral patterns, such as Gaussian distribution patterns or flat-top patterns, in order to improve the uniformity of the spectral surface of the chip and reduce the adverse situation of unevenness on the spectral surface.

[0045] Alternatively, please continue reading Figure 2 The multilayer structure 130 may further include: a buffer layer 112, a lower confinement layer 113, a lower waveguide layer 114, an upper waveguide layer 115, an upper confinement layer 116, a capping layer 117, and a top electrode metal layer 118, sequentially disposed on the substrate 111. The multi-quantum well layer 131 is disposed between the lower waveguide layer 114 and the upper waveguide layer 115 to enable the epitaxial structure 110 to possess corresponding functions.

[0046] It should be noted that the buffer layer 112 serves as a "transition zone" between the substrate 111 and the upper crystal layer. Its main function is to repair surface defects on the substrate 111 and alleviate lattice mismatch, providing a smooth substrate for subsequent high-quality epitaxial layer growth. The lower confinement layer 113 and the upper confinement layer 116 are the core confinement layers for light and electricity. Utilizing their wider bandgap and lower refractive index, they confine injected carriers (electrons and holes) to recombine in the active region and confine the light generated in the active region to propagate within the waveguide layer. The lower waveguide layer 114 and the upper waveguide layer 115 are the light transmission channels, confining the light generated in the active region to propagate and amplify within the optical channels they form. Typically, their bandgap is slightly larger than that of the active region but smaller than that of the confinement layer, forming a refractive index step. The multi-quantum well layer 131 serves as the active layer device, where carriers recombine and generate and amplify photons through stimulated emission, achieving electro-optic conversion. The capping layer 117 provides protection and auxiliary functions. It not only protects the underlying epitaxial layer, but also serves as an etch stop layer for precise process control, or as part of a current blocking layer to constrain current. The top electrode metal layer 118 serves as the interface between the external circuit and the chip. By depositing metal on the capping layer 117, ohmic contacts are formed to achieve low-resistance current injection, and gold wires are soldered to connect to the external circuit.

[0047] For example, the buffer layer 112 can be an n-type buffer layer, such as an n-GaAs buffer; the lower confinement layer 113 can be an n-Al0.6GaAs; the lower waveguide layer 114 can be an n-Al0.45GaAs; the upper waveguide layer 115 can be a p-Al0.45GaAs; the upper confinement layer 116 can be a p-Al0.6GaAs; and the capping layer 117 can be a p-GaAs or other capping layer.

[0048] It should be noted that a ridge waveguide can be formed on the electrode metal layer 118 by etching technology.

[0049] Optionally, please refer to Figure 3 , Figure 3 This is a schematic diagram of a waveguide structure provided in an embodiment of this application. The waveguide structure 120 includes a symmetrical first ridge waveguide 121 and a second ridge waveguide 122. The first ridge waveguide 121 includes a first parallel segment 1211 and a first beam-combining segment 1212. The second ridge waveguide 122 includes a second parallel segment 1221 and a second beam-combining segment 1222. The first parallel segment 1211 and the second parallel segment 1221 are arranged parallel to each other on the high-reflection end face. The first beam-combining segment 1212 bends towards the second ridge waveguide 122, and the second beam-combining segment 1222 bends towards the first ridge waveguide 121. The first beam-combining segment 1212 and the second beam-combining segment 1222 converge at the anti-reflection cavity end face to form an exit port 123. Each of the two ridge waveguides includes a corresponding parallel segment and a beam-combining segment. The two parallel segments are arranged parallel to each other on the high-reflection end face, and the two beam-combining ends bend towards the other ridge waveguide. The two beam-combining segments converge at the anti-reflection cavity end face to form the exit port 123. By designing a structure with two symmetrical ridge waveguides combining, the area of ​​the light-emitting region of the chip is increased, thereby improving the lasing power of the chip. Furthermore, the combining section of the two ridge waveguides is designed as a curved waveguide, which can further increase the spectral width and reduce the spectral ripple. It can also reduce the chip cavity length, thereby reducing the adverse effects of stimulated emission caused by FP cavity surface resonance due to long cavities and long ridge waveguides, which leads to increased spectral ripple.

[0050] Optionally, the high-reflectivity end face, i.e., the HR end, and the anti-reflection cavity end face, i.e., the AR end, are two end faces of the chip that have undergone special optical coating treatment. The HR end is usually located on the rear end face of the chip, and its function is to reflect most of the light back to the active region, allowing the light to propagate back and forth within the cavity and be continuously amplified. The reflectivity of the HR end is very high, generally between 80% and 100%. The AR end is located on the front end face of the chip, i.e., the light output end, and its function is to minimize the reflectivity of the end face, allowing most of the light energy to be emitted smoothly. The reflectivity of the AR end is extremely low, typically required to be below 0.1%.

[0051] Optionally, since the first ridge waveguide 121 and the second ridge waveguide 122 are symmetrically arranged, the bending locations in the two beam combining segments are the same. The bent beam combining segment can effectively reduce the increase in spectral ripple caused by FP cavity surface interference and increase the spectral width. The double ridge waveguide design effectively increases the ridge waveguide area.

[0052] It should be noted that the first ridge waveguide 121 and the second ridge waveguide 122 are configured as narrow ridge waveguides to limit the lateral mode of the chip, thereby enabling the emitted chip to maintain single lateral mode characteristics.

[0053] For example, the width of a narrow ridge waveguide can be set to 2μm-9μm.

[0054] It should be noted that the first ridge waveguide 121 and the second ridge waveguide 122 are configured with a gradually changing width structure. The width of the first ridge waveguide 121 gradually increases from the first parallel segment 1211 to the first beam-combining segment 1212, and the width of the second ridge waveguide 122 gradually increases from the second parallel segment 1221 to the second beam-combining segment 1222. The width of the two ridge waveguides gradually increases from the parallel segment to the beam-combining segment, meaning that the ridge waveguide at the high-reflection end face is narrower, and the ridge waveguide at the antireflection cavity end face is wider.

[0055] Optionally, although the two ridge waveguides are configured as a width-gradient structure, the first parallel segment 1211 and the second parallel segment 1221 can both be horizontal ridge waveguides with equal width, that is, there is a corresponding width change between the parallel segment and the beam combining segment.

[0056] Optionally, please refer to Figure 4 , Figure 4 This is a schematic diagram of another waveguide structure 120 provided in an embodiment of this application. The waveguide structure 120 may further include: an annular ridge waveguide 124, which is disposed on the high-reflectivity end face and connects the first parallel segment 1211 and the second parallel segment 1221. A curved annular ridge waveguide 124 may also be disposed on the high-reflectivity end face of the chip, connecting the first parallel segment 1211 and the second parallel segment 1221. This can reduce the adverse situation of increased spectral ripple in the chip caused by FP effect laser lasing. The annular ridge waveguide 124 can also reflect the generated photons back into the ridge waveguide through the sidewall of the ridge waveguide, thereby increasing the power of the chip.

[0057] Optionally, the width and other structural parameters of the annular ridge waveguide 124 can be the same as those of the first parallel segment 1211 and the second parallel segment 1221.

[0058] It should be noted that the structure of the first ridge waveguide 121 and the second ridge waveguide 122 being closed by the annular ridge waveguide 124 set at the HR end allows the HR end to be designed as an annular closed ridge waveguide, so that the two ridge waveguides form an annular connection at the HR end. On the one hand, this reduces the laser lasing caused by the FP effect, which leads to an increase in the initial spectral ripple of the chip. It can also reflect the generated photons back into the ridge waveguide through the sidewall of the ridge waveguide via the annular ridge waveguide 124, thereby increasing the chip power. On the other hand, because the HR end uses an annular waveguide, the number of laser emission ports at the HR end is reduced, which can reduce one coating process on the HR end face.

[0059] Optionally, please refer to Figure 5 , Figure 5 This is a schematic flowchart of a chip fabrication method provided in an embodiment of this application, which includes steps S200-S300.

[0060] Step S200: Based on the spectral width requirement, multiple quantum well layers are set in the multilayer structure grown on the epitaxial substrate.

[0061] Among them, multiple quantum well layers can be set in the multilayer structure grown in the epitaxial structure based on the actual spectral width requirements of the application scenario.

[0062] Step S300: A waveguide structure comprising multiple bundled ridge waveguides is disposed on the top layer opposite the substrate in the multilayer structure.

[0063] In this multilayer structure, a waveguide structure including multiple ridge waveguides capable of beam combining can be set on the top layer opposite the substrate.

[0064] For example, after epitaxial growth is completed, waveguide structures can be etched using photolithography and ICP dry etching. The ridge waveguide width is designed as a gradient width, with a 3.5µm width for the HR end and horizontal waveguide sections (ICP etching requires vertical and smooth sidewalls to reduce light absorption on the sidewalls of curved waveguide sections, thus reducing chip power). In the ridge waveguide, a layer of SiNx is deposited using PECVD. The thickness of the SiNx is determined based on the required spectral width to maximize its reflectivity for that wavelength band, reducing the absorption of lasing photons during reflection within the ridge waveguide and lowering power. Then, a hot reflow process is used for photolithography to fabricate SiNx windows. After the waveguide structure is fabricated, a Ti / Pt / Au metal layer can be sputtered onto the chip surface to form the P-side contact electrode. A thick gold layer (approximately 1.5µm) is electroplated onto the electrode surface for use as a wire bonding electrode. The wafer is then thinned to approximately 100µm. A Ni / Ge / Au layer is deposited on the n-side of the wafer as the n-electrode. The diode strips are cleaved using a cleaving method. Then, a ZnSn thin film is grown at the AR end using MBE technology as a passivation film. Next, a high-transmittance film (reflectivity ≤0.01%) is deposited on the AR end using optical coating, and a high-reflectance film (reflectivity ≥98%) is deposited at the HR end, thereby increasing the chip's output power. After coating, the diode strips are cleaved into single dies, thus completing the fabrication of the SLD chip.

[0065] exist Figure 5 In the illustrated embodiment, the lasing wavelengths of each quantum well are distributed differently through multiple quantum well layers in the multilayer structure, thereby broadening the spectral width of the chip. The area of ​​the light-emitting region of the chip is increased by multiple ridge waveguides that are bundled together, thereby increasing the lasing power of the chip. Furthermore, the multiple ridge waveguides that are bundled together will produce a bending condition, which can further increase the spectral width and reduce spectral ripple.

[0066] Optionally, please refer to Figure 6 , Figure 6 This is a detailed flowchart of step S200 provided in an embodiment of the present application, wherein the multi-quantum well layer is configured as a non-uniformly graded multi-quantum well structure; the non-uniformly graded multi-quantum well structure includes: a barrier layer and a potential well layer of multiple quantum well structures, and step S200 may include steps S210-S220.

[0067] Step S210: Determine the structural parameters of the potential well layer based on the spectral width requirement.

[0068] During the design process, structural parameters such as the thickness and composition data of each potential well layer can be determined based on the actual spectral width requirements of the application scenario.

[0069] Optionally, the potential well layer can be GaAsP, and the structural parameters can include the thickness of GaAsP or its p-component (i.e., composition data).

[0070] Step S220: Based on the structural parameters, determine the wavelength distribution of the corresponding quantum well structure excitation.

[0071] Among them, it is possible to determine the wavelength distribution of the quantum well structure excited by it based on the structural parameters of the potential well layer, so that multiple wavelengths of multiple quantum well structures can be superimposed to form a wider spectral width.

[0072] Optionally, the spectral width requirement can be based on a stepped wavelength distribution across multiple quantum well structures, or a wavelength range requirement. For example, an 840nm SLD requires a chip with a spectral width of 40nm. This can be achieved by designing five non-uniform quantum well structures with excitation wavelengths of 828nm, 835nm, 840nm, 845nm, and 858nm, respectively. Please refer to [link to relevant documentation]. Figure 7 , Figure 7 A spectral diagram provided for an embodiment of this application. Figure 7 The image shows the spectrum obtained by superimposing the excitation wavelengths of the five quantum well structures, which can effectively expand the overall spectral width of the chip structure. The red dashed line is the overall spectrum after fitting multiple quantum well structures, and the five blue curves are the wavelength spectra of the lasing of each of the five quantum well structures.

[0073] exist Figure 6 In the illustrated embodiment, each quantum well structure in the non-uniform gradient multi-quantum well structure can be designed based on actual needs to meet different spectral requirements in different application scenarios.

[0074] Optionally, in order to ensure the similarity of multiple ridge waveguides in the waveguide structure, step S300 may include: setting symmetrical first and second ridge waveguides on the multilayer structure by simultaneous etching process, so as to ensure that the beams emitted by the two ridge waveguides are exactly the same, thereby ensuring the beam quality after beam combining.

[0075] The first ridge waveguide may include a first parallel segment and a first beam combining segment; the second ridge waveguide includes a second parallel segment and a second beam combining segment; the first parallel segment and the second parallel segment are arranged parallel to each other on the high reflection end face; the first beam combining segment bends toward the second ridge waveguide, the second beam combining segment bends toward the first ridge waveguide, and the first beam combining segment and the second beam combining segment meet at the antireflection cavity end face to form a light outlet.

[0076] Optionally, please refer to Figure 8 , Figure 8 This is a detailed flowchart of step S300 provided in an embodiment of the present application. Step S300 may include steps S310-S320.

[0077] Step S310: Determine the interference detection result of the waveguide structure based on the different bending angles of the first and second beam-combining segments.

[0078] In order to ensure that the specific structure of the ridge waveguide meets the actual application requirements, the waveguide structure under different bending angles of the first and second beam combining segments can be simulated for interference detection to obtain the interference detection results.

[0079] Optionally, the chip structure design can be input into simulation software to simulate and detect the interference results, thereby obtaining the interference detection results.

[0080] Step S320: Based on the interference detection results, beam requirements, and area parameters of the multilayer structure, determine the target bending angles of the first and second beam combining segments.

[0081] Among them, the appropriate target bending angle of the two beam combining segments can be determined based on the interference detection results, beam requirements and area parameters of the multilayer structure, so that the optical fibers after beam combining in the two beam combining segments will not produce interference anomalies and the light generated after beam combining has only one fundamental mode.

[0082] Optionally, the beam requirements may include requirements related to interference conditions. The interference conditions of the two ridge waveguides may be determined based on the beam requirements and the interference detection results, thereby determining whether the beam requirements are met. The area parameters of the multilayer structure may include the cavity length, so as to limit the bending angle by limiting the ridge waveguide length.

[0083] It should be noted that the target bending angle is set to 3° to 9°.

[0084] exist Figure 8 In the illustrated embodiment, the bending angle can be precisely designed to improve the chip's performance in processing optical signals.

[0085] It should be noted that the chip structure provided in this application embodiment can be set in various types of optical electronic devices that have stringent requirements for high precision, high resolution, and spectral quality and stability, such as navigation, sensing and precision measurement equipment such as high-precision fiber optic gyroscopes and fiber optic sensing systems, medical imaging and diagnostic equipment such as optical coherence tomography, and fiber optic communication and testing equipment such as optical communication testing and fiber optic link diagnostics.

[0086] In summary, the epitaxial structure of this application incorporates a non-uniformly graded multi-quantum-well structure. By adjusting the thickness and composition data of the potential well layers of the quantum wells, the wavelengths emitted by the multiple quantum well structures are distributed in a stepped manner, and the wavelengths are superimposed to form a wider spectral width. The chip design employs a multi-ridge waveguide beam combiner structure to increase the chip's emitting area. Narrow ridge waveguides are also used to limit the chip's lateral modes, ensuring that the emitted chip is a single lateral mode. The dual-ridge waveguides are etched simultaneously, ensuring the similarity between the two ridge waveguides and thus guaranteeing that the emitted beams are identical, ensuring the beam quality after beam combining. A ring-shaped ridge waveguide can also be incorporated at the HR end to reduce FP effect-induced laser lasing, increase chip power, and reduce the cost of a single HR end-face coating process.

[0087] In the several embodiments provided in this application, it should be understood that the disclosed device can also be implemented in other ways. The device embodiments described above are merely illustrative; for example, the block diagrams in the accompanying drawings illustrate the possible architecture, functions, and operations of the device according to various embodiments of this application. In this regard, each block in the block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram, and combinations of block diagrams, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0088] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0089] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0090] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application. It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0091] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

[0092] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A chip structure, characterized in that, The chip structure includes: an epitaxial structure and a waveguide structure; The epitaxial structure includes: a substrate, and a multilayer structure grown on the substrate based on epitaxial growth technology, wherein the waveguide structure is disposed on the top layer of the multilayer structure opposite to the substrate; The multilayer structure includes multiple quantum well layers; The waveguide structure includes multiple ridge waveguides that combine beams.

2. The chip structure according to claim 1, characterized in that, in, The multi-quantum well layer is configured as a non-uniformly graded multi-quantum well structure.

3. The chip structure according to claim 2, characterized in that, in, The wavelengths excited by the multiple quantum well structures in the non-uniformly graded multi-quantum-well structure are distributed in a stepped manner. The spectral pattern of the multi-quantum-well layer includes a Gaussian distribution pattern or a flat-top pattern.

4. The chip structure according to any one of claims 1-3, characterized in that, The multilayer structure further includes: a buffer layer, a lower confinement layer, a lower waveguide layer, an upper waveguide layer, an upper confinement layer, a capping layer, and a top electrode metal layer, which are sequentially disposed on the substrate; The multiple quantum well layer is disposed between the lower waveguide layer and the upper waveguide layer.

5. The chip structure according to any one of claims 1-3, characterized in that, The waveguide structure includes: a symmetrical first ridge waveguide and a second ridge waveguide; The first ridge waveguide includes a first parallel segment and a first beam combiner segment; The second ridge waveguide includes a second parallel segment and a second beam combiner segment; The first parallel segment and the second parallel segment are arranged in parallel on the high-reflectivity end face; The first beam combiner bends toward the second ridge waveguide, and the second beam combiner bends toward the first ridge waveguide. The first beam combiner and the second beam combiner meet at the end face of the antireflection cavity to form a light outlet.

6. The chip structure according to claim 5, characterized in that, in, The first ridge waveguide and the second ridge waveguide are configured as narrow ridge waveguides.

7. The chip structure according to claim 5, characterized in that, in, The first ridge waveguide and the second ridge waveguide are configured as a width-gradient structure; The width of the first ridge waveguide gradually increases from narrow to wide from the first parallel segment to the first beam-combining segment; The width of the second ridge waveguide gradually increases from the narrowest point to the widest point from the second parallel segment to the second beam-combining segment.

8. The chip structure according to claim 5, characterized in that, The waveguide structure further includes: a ring ridge waveguide; The annular ridge waveguide is disposed on the high-reflection end face; The annular ridge waveguide connects the first parallel segment and the second parallel segment.

9. A chip fabrication method, characterized in that, The method includes: Based on the spectral width requirement, multiple quantum well layers are set in the multilayer structure grown on the epitaxial substrate; A waveguide structure comprising multiple bundled ridge waveguides is disposed on the top layer opposite to the substrate in the multilayer structure.

10. The method according to claim 9, characterized in that, in, The multi-quantum well layer is configured as a non-uniformly graded multi-quantum well structure; the non-uniformly graded multi-quantum well structure includes: a barrier layer and a potential well layer with multiple quantum well structures; The method of setting multiple quantum well layers in a multilayer structure grown on an epitaxial substrate based on spectral width requirements includes: Based on the spectral width requirement, the structural parameters of the potential well layer are determined; wherein, the structural parameters include the thickness and composition data of the potential well layer; Based on the structural parameters, the wavelength distribution of the corresponding quantum well structure excitation is determined.

11. The method according to claim 9, characterized in that, The waveguide structure comprising multiple beam-combining ridge waveguides disposed on the top layer opposite the substrate in the multilayer structure includes: A symmetrical first ridge waveguide and second ridge waveguide are formed on the multilayer structure by a simultaneous etching process. The first ridge waveguide includes a first parallel segment and a first beam-combining segment; the second ridge waveguide includes a second parallel segment and a second beam-combining segment; the first parallel segment and the second parallel segment are arranged parallel to each other on the high-reflection end face; the first beam-combining segment bends toward the second ridge waveguide, the second beam-combining segment bends toward the first ridge waveguide, and the first beam-combining segment and the second beam-combining segment converge at the anti-reflection cavity end face to form a light outlet.

12. The method according to claim 11, characterized in that, The waveguide structure comprising multiple beam-combining ridge waveguides disposed on the top layer opposite the substrate in the multilayer structure further includes: The interference detection result of the waveguide structure is determined based on the different bending angles of the first beam combiner segment and the second beam combiner segment; Based on the interference detection results, beam requirements, and area parameters of the multilayer structure, the target bending angles of the first beam combining segment and the second beam combining segment are determined; wherein, the target bending angle is set to 3° to 9°.

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