Semiconductor laser secondary epitaxial surface flattening and defect processing method

Abstract

The application discloses a semiconductor laser secondary epitaxial surface flattening and defect processing method, and relates to the technical field of semiconductor lasers. The method comprises the following steps: forming a hard mask layer on the wafer surface after active region structure epitaxial growth and patterning; etching a laser ridge and two side grooves by taking the patterned hard mask layer as an etching mask, and then reserving the hard mask layer; overgrowing a buried material in the groove, so that the groove is completely filled and a protrusion is formed on the upper surface of the groove opening; polishing the protrusion and reserving at least a part of the hard mask layer, and simultaneously removing surface impurities and growth defects generated in the secondary epitaxy; removing the remaining hard mask layer to obtain a chip wafer with a flat surface. The secondary epitaxial overgrowth, surface flattening and defect removal are integrated in the same process, the steps are simple, the method is controllable, and the method is conducive to improving the heat dissipation performance, manufacturing yield and long-term working reliability of high-power semiconductor laser chips.

Description

Technical Field

[0001] This invention relates to the field of semiconductor laser technology, and in particular to a method for surface planarization and defect treatment of secondary epitaxy in semiconductor lasers. Background Technology

[0002] Continuous-wave semiconductor lasers are core light sources in fields such as optical communication, quantum technology, scientific research, and industrial inspection, encompassing core devices such as lasers in the visible to near-infrared communication bands and quantum cascade lasers in the mid-infrared to terahertz bands. Under high-power continuous-wave operation, these devices generate significant heat, and their heat dissipation capacity directly determines their output power and lifespan. Secondary epitaxy, by growing semi-insulating buried materials within trenches on both sides of the laser ridge, can fabricate a highly thermally conductive buried layer and optimize the internal heat conduction pathways of the chip. This is a key process for improving device thermal resistance, increasing power, and enhancing reliability.

[0003] However, the secondary epitaxial growth stage of semiconductor lasers is highly susceptible to defects such as lattice dislocations, interface voids, mesa edge polycrystalline structures, and interface impurities. This results in an uneven wafer surface in the secondary epitaxial growth region. Even in areas where secondary epitaxial growth was not performed, large-area defects may grow on the deposited dielectric mask film or even through gaps in the dielectric material from the wafer surface. These defects significantly increase the device's series resistance, induce leakage current, exacerbate non-radiative recombination heating, and counteract the heat dissipation performance of secondary epitaxy. Defect concentrations can create localized hot spots, leading to device breakdown and shortened lifespan. The yield of high-power quantum cascade lasers and high-power lasers has long been constrained by secondary epitaxial defects.

[0004] Currently, the industry's conventional secondary epitaxial process uses a trench undergrowth method, which involves adjusting epitaxial growth parameters to grow the buried material within a trench to near the top, leaving a certain depression. This undergrowth process creates an air gap that is sealed during flip-flop bonding. Because air has extremely low thermal conductivity, this becomes a bottleneck for device heat dissipation, leading to increased device temperature, performance degradation, and even failure during continuous wave operation.

[0005] The literature (Buried-heterostructure mid-infrared quantum cascade lasers fabricated by non-selective regrowth and chemical polishing) proposes a surface planarization approach combining secondary epitaxy with chemical polishing. However, this approach requires an additional 100 nm indium gallium arsenide (IGaAs) chemical polishing stop layer and the removal of the original etched hard mask before regrowth and subsequent stop layer removal. Therefore, it introduces an additional epitaxial stop layer and its corresponding removal step. Furthermore, the method uses a combination of dry and wet etching to form trenches, resulting in poor uniformity of secondary epitaxial growth, sharp peaks on the surface, numerous defects at the interface between the buried material and the laser ridge, and a tendency for interfacial heat accumulation. This method can only utilize chemical polishing, resulting in limited final surface flatness, high process complexity, and poor reliability and repeatability.

[0006] In summary, the existing technology lacks a simple process that can simultaneously achieve surface smoothing and defect removal during the secondary epitaxy process, which fails to fully utilize the heat dissipation advantages of secondary epitaxy and severely limits the performance ceiling and long-term operational reliability of high-power semiconductor lasers. Summary of the Invention

[0007] The technical problem to be solved by this invention is how to optimize the secondary epitaxial process of semiconductors to achieve wafer surface planarization and defect removal.

[0008] To address the above problems, the present invention proposes the following technical solution: In a first aspect, the present invention provides a method for surface planarization and defect treatment of a secondary epitaxial layer in a semiconductor laser, comprising the following steps: Step 1: Provide a wafer with completed epitaxial growth of the active region structure; Step 2: A hard mask layer is formed on the surface of the wafer, and the hard mask layer is patterned to obtain a patterned hard mask layer. Step 3: Using the patterned hard mask layer as an etching mask, laser ridges and trenches located on both sides of the laser ridges are etched on the wafer surface. After etching is completed, the patterned hard mask layer is retained. Step 4: The buried material is epitaxially grown in the trench, and the trench is completely filled by overgrowth, so that the buried material extends beyond the upper surface of the trench opening, forming a protrusion above the left and right sides of the laser ridge. Step 5: Using the patterned hard mask layer as the polishing stop layer, polish the wafer to remove the protrusions and retain at least a portion of the patterned hard mask layer. Step six: Use a selective removal process for the hard mask layer to remove the remaining patterned hard mask layer and obtain a chip with a smooth surface.

[0009] Furthermore, the height of the burial material extending beyond the upper surface of the trench opening is 2~5μm.

[0010] Furthermore, the thickness of the hard mask layer is 0.5~2μm.

[0011] Furthermore, in step five, polishing is stopped when the remaining thickness of the patterned hard mask layer is 50~100nm.

[0012] Furthermore, the hard mask layer is a single dielectric layer or a multilayer composite structure composed of two or more dielectric layers; the material of the hard mask layer is selected from at least one of silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide and zirconium oxide.

[0013] Furthermore, the buried material is a semi-insulating semiconductor material or a high-resistivity semiconductor material that is epitaxially compatible with the wafer material system.

[0014] Furthermore, the polishing rate selection ratio between the buried material and the hard mask layer is 5:1 to 20:1.

[0015] Furthermore, the material system of the wafer is any one of indium phosphide, gallium arsenide, gallium nitride, gallium antimonide, silicon carbide, silicon, germanium, silicon germanium, germanium tin, or silicon germanium tin.

[0016] In a second aspect, the present invention provides a semiconductor laser chip, the chip being prepared by the method described in the first aspect.

[0017] Thirdly, the present invention provides a semiconductor laser, comprising the chip described in the second aspect.

[0018] Compared with the prior art, the technical effects achieved by the present invention include: The present invention provides a method for surface planarization and defect handling in secondary epitaxy of semiconductor lasers. This method retains a patterned hard mask layer as a polishing stop layer and uses overgrowth to completely fill the etched trenches with buried material, forming a protrusion above the laser ridge. During polishing, this protruding layer is preferentially removed, and surface defects are simultaneously eliminated. Simultaneously, the patterned hard mask layer stops polishing within its own layer, avoiding direct grinding of the laser ridge top by mechanical polishing, thus maintaining the top morphology quality of the ridge waveguide and the integrity of the interface during planarization. Furthermore, the overgrowth filling method eliminates residual recessed cavities within the trenches, creating continuous contact between the buried material and the trench sidewalls and bottom. This establishes a highly efficient, air-gap-free thermal path between the chip and heat sink after flip bonding, which helps reduce the overall thermal resistance of the device. Finally, the remaining hard mask layer is selectively removed, ensuring the step height between the buried material surfaces on both sides and the top of the laser ridge is within a controlled range, ultimately resulting in a chip with a planar surface. This invention integrates secondary epitaxial growth, surface planarization, and defect removal into the same process sequence. The process steps are simple and controllable, with high reliability and repeatability, which is beneficial to improving the manufacturing yield and long-term operational reliability of high-power semiconductor laser chips.

[0019] The semiconductor laser chip provided by this invention is fabricated using the above-described method. The trenches on both sides of the ridge waveguide are completely filled with a buried material, resulting in no recessed cavities in the trench area. After flip bonding, a continuous contact interface can be formed between the chip and the heat sink, reducing thermal resistance introduced by air gaps and improving the device's heat dissipation capacity. Simultaneously, the chip surface is flat with few defects, reducing losses and interface carrier recombination caused by surface undulations and residual impurities. The top morphology of the laser ridge is protected by a patterned hard mask layer during planarization, ensuring a complete ridge waveguide structure and improving the reliability of subsequent electrode fabrication and bonding processes.

[0020] The semiconductor laser provided by this invention includes the aforementioned chip. Because the buried material and trench interface are continuous and there are no air gaps, the thermal resistance of the device's heat dissipation path is reduced, and the junction temperature rise during operation is suppressed, which is beneficial for improving power density and long-term operational reliability. Simultaneously, the chip surface is flat with few defects, resulting in lower waveguide loss and enhanced optical and current confinement capabilities, which helps to reduce the threshold current density and improve the output light mode quality. This semiconductor laser is suitable for applications such as high-power, highly integrated optoelectronic modules. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1This is a schematic flowchart of the method for surface planarization and defect treatment of a semiconductor laser secondary epitaxy provided in an embodiment of the present invention; Figure 2 This is a cross-sectional SEM image of the chip obtained in Comparative Example 2 of the present invention; Figure 3 This is a cross-sectional SEM image of the chip obtained in Embodiment 1 of the present invention; Figure 4 A schematic diagram of the structure of a wafer after step four processing, which is provided by the semiconductor laser secondary epitaxial surface planarization and defect treatment method of the present invention. Figure 5 for Figure 4 Another perspective structural diagram; Figure 6 A schematic diagram of the structure of a wafer after step five of the semiconductor laser secondary epitaxial surface planarization and defect treatment method provided by the present invention. Figure 7 This is a schematic diagram of the structure of a wafer after step six of the semiconductor laser secondary epitaxial surface planarization and defect treatment method provided by the present invention.

[0023] Figure 4-7 The reference numerals in the figures are: 103 patterned hard mask layer, 104 buried material, and 105 surface impurities and growth defects. Detailed Implementation

[0024] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Similar component reference numerals in the drawings represent similar components. Obviously, the embodiments described below are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0025] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0026] It should also be understood that the terminology used in the specification of embodiments of the present invention is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of the present invention. As used in the specification of embodiments of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to include the plural forms.

[0027] In the secondary epitaxy process of semiconductor lasers, if traditional undergrowth filling methods are used, residual depressions often remain in the trenches, forming air gaps after flip bonding, leading to increased thermal resistance. Simultaneously, surface particles and edge polycrystalline defects generated during the secondary epitaxy stage are difficult to remove using conventional methods, affecting the device's output power and long-term reliability. To address these issues, this invention provides a method for surface planarization and defect handling in the secondary epitaxy of semiconductor lasers. The core of this method lies in retaining the patterned hard mask layer from the etching stage and reusing it as a polishing stop layer. Overgrowth is used to completely fill the trenches with buried material, followed by polishing to remove protrusions and surface defects. Finally, the remaining hard mask layer is selectively removed to obtain a chip with a planar surface. This invention integrates complete trench filling, surface planarization, and defect removal into a single process sequence, resulting in simple process steps and a controllable method.

[0028] See Figure 1 This is a flowchart illustrating a method for surface planarization and defect treatment in secondary epitaxy of a semiconductor laser, provided by the present invention. The method of the present invention includes the following steps: Step 1: Provide a wafer with completed epitaxial growth of the active region structure.

[0029] In specific implementations, a wafer with a pre-grown active region structure is provided. This wafer can be fabricated using methods such as molecular beam epitaxy or metal-organic chemical vapor deposition, and its surface already contains the complete epitaxial structure required by the laser, including the active region, cladding, and capping layer. Taking indium phosphide as an example, the wafer can sequentially include, from bottom to top, an n-type indium phosphide substrate layer, an n-type indium phosphide buffer layer, a quantum cascade active region, a lightly doped n-type indium phosphide cladding layer, and a heavily doped n-type indium phosphide capping layer; wherein the thickness of the active region can be, for example, 1 μm, 1.5 μm, 2 μm, or other values ​​between 1 μm and 2 μm; the cladding thickness can be, for example, 2 μm, 3 μm, 4 μm, or 5 μm; and the capping layer thickness can be, for example, 0.5 μm, 1 μm, or 1.5 μm. The above thickness values ​​are merely examples and do not constitute a limitation of the present invention. The active region typically consists of alternating quantum wells and barrier layers grown over multiple periods. Its average doping concentration can be controlled at a low level, such as 1 × 10⁻⁶, depending on the device design. 16 cm -3 1.8×10 16 cm -3 Or 2×10 16 cm -3 These doping concentration values ​​are merely examples and do not constitute a limitation. The wafer material system is not limited to indium phosphide; gallium arsenide, gallium nitride, gallium antimony, silicon carbide, silicon, germanium, silicon-germanium, germanium-tin, or silicon-germanium-tin, etc., may also be selected depending on the device's operating wavelength. Wafers that have completed epitaxial growth of the active region structure retain their epitaxial growth state before performing subsequent steps of this method, requiring no additional etching or thinning.

[0030] Step 2: A hard mask layer is formed on the surface of the wafer, and the hard mask layer is patterned to obtain a patterned hard mask layer.

[0031] In specific implementations, the hard mask layer can be formed on the wafer surface using methods such as plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer deposition, or magnetron sputtering. The hard mask layer is a single-layer dielectric layer or a multilayer composite structure composed of two or more dielectric layers; the material of the hard mask layer is selected from at least one of silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, and zirconium oxide. The multilayer composite structure is not limited to a specific number of layers, layer sequence, or material combination; as long as it can maintain structural integrity during trench etching and secondary epitaxy, and has a lower removal rate relative to the buried material during subsequent planarization, it can be used as the hard mask layer of this invention.

[0032] In some specific embodiments, the hard mask layer is a silicon dioxide layer, or a multilayer composite structure including a silicon dioxide layer near the wafer surface and silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, and / or zirconium oxide layers located on the silicon dioxide layer. The silicon dioxide layer near the wafer surface acts as an adhesion layer and stress buffer layer, forming a stable interface with semiconductor materials such as indium phosphide, preventing mask warping, peeling, or induced defects during subsequent high-temperature epitaxy and polishing. The upper silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, and / or zirconium oxide layers primarily provide higher mechanical strength and polishing selectivity, which is beneficial for controlling the polishing endpoint. For the silicon dioxide layer in direct contact with the wafer, it is advisable to improve the film density by optimizing deposition parameters and performing oxygen plasma densification treatment. For example, the deposition rate can be controlled at approximately 60–90 nm / min. After deposition, oxygen plasma treatment is used to achieve a SiO2 refractive index of 1.4–1.6 at 633 nm, and a buffered oxide etchant (BOE) etching rate of 7–9 nm / s. Oxygen plasma treatment can be performed under conventional conditions, such as a power of 100–200 W, a time of 5–10 min, and an oxygen flow rate of 50–100 sccm. These process parameters are merely examples and do not constitute limitations; specific adjustments can be made based on equipment conditions and film quality requirements. The densified SiO2 layer exhibits higher mechanical strength and chemical stability, maintaining its integrity during subsequent high-temperature epitaxy and polishing processes.

[0033] The total thickness of the hard mask layer is 0.5 μm to 2 μm, for example, 0.5 μm, 1 μm, 1.5 μm or 2 μm can be selected, preferably 0.8~1.2 μm, or other thickness values ​​within this range. In multilayer composite structures, the total thickness is also within this range. The thickness of the bottom silicon dioxide layer can be selected according to adhesion and stress control requirements, for example, 200 nm. The thicknesses of the upper silicon nitride layer, silicon oxynitride layer, aluminum oxide layer, hafnium oxide layer and / or zirconium oxide layer are adjusted accordingly according to the total thickness requirements. When the total thickness of the hard mask layer is less than 0.5 μm, it is easy to be prematurely worn through during subsequent polishing, which cannot effectively protect the top of the laser ridge and accurately control the polishing stop position. When the total thickness of the hard mask layer is greater than 2 μm, the patterning etching difficulty increases, and side etching and morphological distortion are prone to occur at the trench edges. At the same time, the internal stress of the film increases, which may cause cracking or peeling.

[0034] After forming the hard mask layer, laser ridge patterns are defined on the wafer surface using ultraviolet lithography, laser direct writing, or other methods. Then, selective removal processes such as chemical etching, dry etching, or physical lift-off are used to remove the hard mask layer in the trench area, retaining only the hard mask layer at the top of the laser ridges and the edges of the trenches, exposing the wafer surface at the bottom of the trench to be etched. The patterned hard mask layer is used as an etching mask in subsequent trench etching, and as a growth mask and polishing stop layer in subsequent secondary epitaxy and polishing, thus achieving mask function reuse without the need for additional semiconductor etching stop layers.

[0035] Step 3: Using the patterned hard mask layer as an etching mask, laser ridges and trenches located on both sides of the laser ridges are etched on the wafer surface. After etching is completed, the patterned hard mask layer is retained.

[0036] In practice, a patterned hard mask layer is used as the etching mask. The etching process can be selected based on the wafer material system and trench morphology requirements, choosing methods such as wet etching. For example, for InP material systems, an acidic etching system containing hydrochloric acid and hydrogen peroxide, such as the HBr / HCl / H2O2 / H2O system, can be used for wet etching; alternatively, an acidic etching system containing phosphoric acid and hydrogen peroxide, such as the H3PO4 / H2O2 / H2O system, can be used. The specific composition ratio can be adjusted according to the wafer crystal orientation, trench depth, sidewall morphology, and etching rate. The trench depth and laser ridge width can be conventionally designed according to the device structure. For example, the trench depth can be 8μm, 10μm, or 15μm, and the laser ridge width can be 5μm, 10μm, 15μm, or 20μm. These values ​​are merely examples and do not constitute limitations. The etching process penetrates the cap layer, upper cladding layer, and active region, terminating in the lower cladding layer or substrate material above the substrate. This causes the laser ridge to protrude from the wafer surface, forming trenches on both sides. After etching, the wafer is cleaned, but the patterned hard mask layer is retained. This patterned hard mask layer covers the top of the laser ridge, continuously protecting it from the direct effects of the epitaxial atmosphere and mechanical grinding during subsequent secondary epitaxy and polishing processes, thereby maintaining the geometry and interface integrity of the ridge waveguide.

[0037] Step four: Epitaxial growth of the buried material is performed in the trench. The trench is completely filled by over-growth, and the buried material extends beyond the upper surface of the trench opening, forming a protrusion above the left and right sides of the laser ridge.

[0038] In practice, the buried material undergoes epitaxial growth (also known as secondary epitaxial growth) within the trench. This overgrowth process completely fills the trench, causing the buried material to extend beyond the top surface of the trench opening, forming protrusions on the left and right sides above the laser ridge. A structural diagram is shown below. Figure 4 and Figure 5 In the figure, 103 represents the patterned hard mask layer, 104 represents the buried material, and 105 represents surface impurities and growth defects. The buried material 104 is a semi-insulating semiconductor material or a high-resistivity semiconductor material that is epitaxially compatible with the wafer material system, and can be grown by metal-organic chemical vapor deposition or vapor phase epitaxy. For example, for an indium phosphide material system, the buried material can be iron-doped semi-insulating indium phosphide or ruthenium-doped semi-insulating indium phosphide; for a gallium arsenide material system, the buried material can be semi-insulating GaInP, semi-insulating GaAs, or high-resistivity AlGaAs; for a gallium nitride material system, the buried material can be Fe-doped GaN, C-doped GaN, or other GaN-based materials capable of forming high-resistivity characteristics.

[0039] Taking the growth of iron-doped semi-insulating indium phosphide by metal-organic chemical vapor deposition as an example, trimethylindium and phosphine can be used as source gases, and ferrocene as the dopant source. The growth temperature is controlled between 600℃ and 700℃; this temperature range is only an example and does not constitute a limitation. By precisely controlling the growth time and growth rate, the buried material 104 first nucleates at the bottom and sidewalls of the trench and gradually fills the inside of the trench, and then continues to grow outward to the upper surface of the trench opening. The height of the buried material 104 beyond the upper surface of the trench opening is in the range of 2μm to 5μm, for example, 2μm, 3μm, 4μm, or 5μm, or other height values ​​within this range can be selected. When the overgrowth height is less than 2μm, the protrusion may not be sufficient to completely cover and encapsulate surface particles, edge polycrystalline defects, and other defects generated in the secondary epitaxial stage, resulting in defect residue after polishing; when the overgrowth height is greater than 5μm, the amount removed by polishing increases significantly, and the production efficiency decreases.

[0040] Under process conditions with low pattern density and good regrowth uniformity, the overgrowth allowance can be optimized to 2-3 μm to reduce the amount removed during subsequent polishing and improve production efficiency. The buried layer is preferably made of Fe-doped InP semi-insulating material; however, without altering the lateral current blocking and thermal conductivity, other deep-level compensation doping systems that have been proven to form high-resistivity semi-insulating InP buried layers can also be used, such as Ru-doped or Ti-doped InP.

[0041] This invention utilizes overgrowth to eliminate residual recessed cavities within the trench, allowing the buried material 104 to form a continuous and dense contact with the trench sidewalls and bottom, thus establishing a highly efficient heat conduction path without air gaps between the chip and the heat sink after flip bonding. Simultaneously, surface particles, edge polycrystalline structures, and irregular morphologies (i.e., surface impurities and growth defects 105) generated during the epitaxial stage are mainly distributed on the surface of the raised portions and the patterned hard mask layer 103, far from the active region of the device. These defects can be removed along with the raised layer during subsequent polishing, without remaining on the final working surface.

[0042] Step 5: Using the patterned hard mask layer as the polishing stop layer, polish the wafer to remove the protrusions and retain at least a portion of the patterned hard mask layer.

[0043] In specific implementation, the patterned hard mask layer 103 is used as the polishing stop layer to polish the wafer, remove the protrusions, and retain at least a portion of the patterned hard mask layer 103. A schematic diagram is shown below. Figure 6Polishing can be performed using chemical mechanical polishing (CMP) or mechanical polishing. During polishing, the polishing rate selection ratio between the embedded material 104 and the patterned hard mask layer 103 is limited to a range of 5:1 to 20:1 in this invention. For example, 5:1, 10:1, 15:1, or 20:1, or other ratios within this range, can be selected. When the polishing rate selection ratio is relatively small, the wear rate of the patterned hard mask layer 103 is too fast, making it difficult to control the polishing endpoint and easily damaging the top of the laser ridge. When the polishing rate selection ratio is relatively large, the removal rate of the embedded material 104 is too slow, reducing production efficiency, and the difference in polishing rate between the center and edge of the trench may increase, leading to unevenness such as dish-shaped depressions on the surface. During polishing, the polishing endpoint can be determined in real time through optical reflection, film thickness monitoring, or time window control. Polishing is stopped when the remaining thickness of the patterned hard mask layer 103 is in the range of 50nm to 100nm; for example, it can be stopped when the remaining thickness is within this range, such as 50nm, 70nm, or 100nm. When the remaining thickness is less than 50nm, the patterned hard mask layer 103 is almost worn through, posing a risk of mechanical damage to the top of the laser ridge; when the remaining thickness is greater than 100nm, the steps formed after removing the remaining patterned hard mask layer 103 are too large, which may affect the surface flatness and the quality of subsequent electrode deposition.

[0044] At this point, the protrusion has been removed, and the surface impurities and growth defects 105 generated during the secondary epitaxial growth stage are ground away along with the protrusion. The top of the laser ridge is still protected by the hard mask layer, avoiding direct damage to the ridge top caused by mechanical polishing.

[0045] Step six: Use a selective removal process for the hard mask layer to remove the remaining patterned hard mask layer and obtain a chip with a smooth surface.

[0046] In practice, a selective removal process for the hard mask layer is used to remove the remaining patterned hard mask layer 103, resulting in a chip with a smooth surface. A schematic diagram is shown below. Figure 7 The selective removal process is selected based on the material of the hard mask layer. For example, for silicon dioxide hard mask layers, diluted hydrofluoric acid solution or BOE can be used for short-time etching at room temperature (30-50 s); for silicon nitride hard mask layers, hot phosphoric acid solution can be used for selective etching; for alumina hard mask layers, alkaline solution or dry etching can be used for removal. During the removal process, since the buried material on the top and sides of the laser ridge below the patterned hard mask layer 103 is exposed to the etching environment, it is necessary to control the process time and temperature to ensure that the patterned hard mask layer 103 is completely removed while minimizing damage to the top of the laser ridge and the buried material. After etching, rinse with deionized water for 2 to 3 minutes and dry with nitrogen. The etching time is calibrated based on the actual remaining thickness and the measured etching rate, and can be adjusted according to the actual material system and equipment conditions, without constituting a limitation.

[0047] After removing the remaining patterned hard mask layer 103, the top surface of the laser ridge is exposed, forming a basically continuous and flat interface with the surfaces of the buried materials 104 on both sides, which does not affect subsequent electrode deposition and bonding. At this point, there are no air gaps in the trench, and surface impurities and growth defects 105 are removed simultaneously. The chip surface is flat, heat dissipation performance is improved, which is beneficial for reducing device thermal resistance, increasing output power, and improving long-term operational reliability.

[0048] This invention is compatible with various material systems and process conditions, and can be directly integrated into existing semiconductor laser manufacturing processes, exhibiting high feasibility for mass production. For example, the materials and processes for cavity surface coating can be selected based on the device's operating wavelength, power level, and application scenario. For the mid-infrared band, antireflection and high reflectivity coatings can be selected from Y2O3, Al2O3, BaF2, ZnS, Ge, and SiN. x Materials and film systems can be single-layer, double-layer, or multi-period dielectric films. High-reflectivity films can also be all-dielectric distributed Bragg reflector films, such as alternating stacks of Y₂O₃ / Ge or Al₂O₃ / TiO₂, or dielectric-metal composite films, such as Y₂O₃ / Au / Ti or Al₂O₃ / Ag / Cr. Coating processes can include electron beam evaporation, magnetron sputtering, ion beam sputtering, atomic layer deposition, or plasma-enhanced chemical vapor deposition.

[0049] Parameter optimization experiment This experiment was used to determine the optimal range of three key process parameters: overgrowth thickness, mask thickness, and polishing selectivity, providing the best process conditions for subsequent embodiments.

[0050] The experiment focused on an InP-based buried ridge quantum cascade laser. The basic fabrication process was as follows: After epitaxial growth, a 1 μm thick SiO2 hard mask layer was deposited using plasma-enhanced chemical vapor deposition (PECVD). Following deposition, the SiO2 hard mask layer underwent oxygen plasma densification. After photolithography and dry etching patterning, a 10 μm deep trench and a 10 μm wide laser ridge were formed using wet etching. Fe:InP secondary epitaxial overgrowth was performed using metal-organic chemical vapor deposition (MOCVD). CMP polishing was performed using the SiO2 hard mask as a polishing stop layer. The remaining SiO2 hard mask was removed using BOE 6:1. Based on this, the effects of overgrowth thickness, mask thickness, and polishing selectivity were investigated using a controlled variable method. For each parameter, only that parameter was changed, while other conditions remained constant.

[0051] 1. The effect of overgrowth thickness With a fixed mask thickness of 1 μm and a polishing selectivity of 12:1, the overgrowth height of Fe:InP beyond the ridge was adjusted, and comparisons were made at approximately 1 μm, 3 μm, 5 μm, and 7 μm. The results are as follows: When the overgrowth thickness is about 1 μm, the raised layer is insufficient to completely cover the polycrystalline and surface defects at the trench edge, and defects remain after polishing, resulting in inadequate trench filling. When the overgrowth thickness is about 3 μm, the raised layer completely encapsulates the epitaxial defects, the polishing allowance is moderate, and it can be precisely stopped at the mask layer, resulting in the best surface flatness. When the overgrowth thickness is about 5 μm, it can also encapsulate defects, the polishing allowance increases slightly, but it is still within a controllable range, and the surface flatness is good. When the overgrowth thickness is about 7 μm, the polishing time increases significantly, the production efficiency decreases, and the risk of mask edge wear increases due to prolonged polishing, with some samples showing over-polishing of the ridge edge.

[0052] The above results indicate that when the overgrowth thickness is 3~5μm, the protrusion layer can completely encapsulate the secondary epitaxial defects, and the polishing allowance is moderate, which can ensure that the defects are completely removed without affecting production efficiency due to excessive removal.

[0053] 2. The Influence of Mask Thickness With a fixed overgrowth thickness of 4 μm and a polishing selectivity of 12:1, the initial thickness of the SiO2 mask was adjusted, and comparisons were made at approximately 0.5 μm, 1 μm, and 1.5 μm. The results are as follows: When the mask thickness is about 0.5 μm, it is insufficient and is easily worn through prematurely during CMP, resulting in damage to the InP at the ridge top and a decrease in yield. When the mask thickness is about 1 μm, it balances the polishing stop margin and the patterning difficulty, leaving 50~100 nm of mask after polishing, which provides the best protection and allows for controllable patterning etching morphology. When the mask thickness is about 1.5 μm, the mask is too thick, resulting in a long dry etching patterning time, severe side etching of the mask at the trench edge, distortion of the ridge morphology, and increased internal stress in the mask, which easily leads to film cracking.

[0054] Therefore, a mask thickness of about 1 μm can provide sufficient polishing stop without affecting the patterning quality and film stability due to excessive thickness, while retaining a suitable processing allowance. The preferred mask thickness is 0.8~1.2 μm.

[0055] 3. The effect of polishing selectivity With a fixed overgrowth thickness of 4 μm and a mask thickness of 1 μm, the polishing slurry formulation and process parameters were adjusted to change the polishing selectivity ratio of Fe:InP to SiO2. Comparisons were made using ratios of approximately 5:1, 10:1, 15:1, and 20:1, with the following results: When the polishing selectivity ratio is about 5:1, the selectivity is too low, the mask wear rate is fast, the endpoint monitoring window is narrow, it is easy to over-polish and damage the ridge, and the surface uniformity is poor. When the polishing selectivity ratio is about 10:1, the selectivity is moderate, the polishing endpoint is clear and controllable, the remaining mask thickness is uniform, the overall surface flatness is the best, and defects are thoroughly removed. When the polishing selectivity ratio is about 15:1, it is still in a good range, but the Fe:InP polishing rate is slightly slower, and the production efficiency is slightly reduced. When the polishing selectivity ratio is about 20:1, the selectivity is too high, the Fe:InP polishing rate is slow, the production efficiency is low, and the difference in polishing rate between the center and edge of the groove increases, making it easy to have dish-shaped depressions.

[0056] Therefore, when the polishing selectivity ratio is 10:1 to 15:1, it can ensure that Fe:InP is removed efficiently, keep the mask wear rate within a controllable range, and achieve a clear polishing endpoint and optimal surface flatness.

[0057] In summary, when the overgrowth thickness is 3–5 μm, the mask thickness is approximately 1 μm, and the polishing selectivity ratio is 10:1–15:1, the requirements of complete trench filling, controllable polishing endpoint, optimal surface smoothness, and thorough defect removal can be simultaneously met. Parameter deviations from this range lead to significant degradation in process performance. Therefore, subsequent embodiments will utilize parameters within the aforementioned optimal window for fabrication.

[0058] Example 1 This embodiment uses an InP-based buried ridge quantum cascade laser with a center wavelength of 4.97 μm as the research object, and it is fabricated using the secondary epitaxial surface smoothing and defect treatment method described in this invention. Based on the above parameter optimization experimental results, this embodiment selects an overgrowth thickness of 3 μm, a mask thickness of 1 μm, and a polishing selectivity ratio of 12:1 as the process parameters.

[0059] First, a complete quantum cascade laser epitaxial structure was sequentially grown on an n-type InP substrate using gas-source molecular beam epitaxy (gsMBE). From bottom to top, the structure consisted of an n-type InP buffer layer, a quantum cascade active region, a lightly doped n-type InP cladding, and a heavily doped n-type InP cap layer. The thickness of the quantum cascade active region was 1.5 μm, the lightly doped n-type InP cladding was 3 μm, and the heavily doped n-type InP cap layer was 1 μm. The average doping concentration of the active region was controlled at 1.8 × 10⁻⁶. 16 cm -3 This epitaxial structure provides the basis for subsequent ridge waveguide etching and secondary epitaxy.

[0060] Then, a dense SiO2 hard mask layer with a thickness of 1 μm was deposited on the entire wafer surface using PECVD at a deposition rate of 50 nm / min. After deposition, the SiO2 hard mask layer underwent an oxygen plasma densification treatment. After oxygen plasma densification, the refractive index of the SiO2 hard mask layer was approximately 1.46@633 nm, and the BOE etching rate was 8.0 nm / s. These refractive index and etching rate indicate that the densified SiO2 film has a dense structure and good chemical stability.

[0061] Laser ridge patterns were defined on the wafer surface using ultraviolet lithography, etching, and resist stripping. A wet etching solution of H3PO4:H2O2:H2O was used to etch symmetrical trenches with a depth of 10 μm on both sides of the laser ridge, forming a raised laser ridge waveguide structure with a width of 11.6 μm. The etching penetrated the upper cladding and the quantum cascade laser active region, terminating within the InP material above the substrate. After etching, the wafer was rinsed with deionized water and dried with nitrogen. This patterned SiO2 hard mask served simultaneously as a growth mask for subsequent secondary epitaxy and a polishing stop layer.

[0062] The patterned wafer is fed into an MOCVD (Multi-access Continuous Chemical Deposition) device. A semi-insulating Fe:InP buried layer is grown using trimethylindium phosphine as the source gas and ferrocene as the dopant source. By precisely controlling the growth time and rate, the Fe:InP thickness extends 3.0 μm beyond the top of the trench, completely filling the 10 μm deep trench and forming a continuous raised layer. The Fe doping concentration is controlled within the range that enables the buried layer to achieve semi-insulating, high-resistivity characteristics. Overgrowth ensures no residual cavities within the trench, and the buried material forms a continuous, dense contact with the trench sidewalls and bottom.

[0063] Subsequently, global planarization polishing was performed on the wafer surface using polishing powder / liquid. A patterned SiO2 hard mask served as the polishing stop layer, and the polishing endpoint was monitored in real time. Polishing was stopped when only about 80 nm of SiO2 remained on the wafer surface. This step simultaneously removed Fe:InP protrusions and surface particles and edge polycrystalline defects generated by secondary epitaxial growth. Because polishing stopped inside the SiO2 hard mask, the top of the laser ridge was protected by the hard mask layer throughout the polishing process and was not directly damaged by mechanical polishing.

[0064] The polished wafer was selectively cleaned using a BOE 6:1 solution to remove the remaining SiO2 hard mask. A short-time controlled etching process was then performed at room temperature for 40 seconds to completely remove the remaining SiO2 hard mask layer after polishing. After etching, the wafer was rinsed with deionized water for 2 to 3 minutes and dried with nitrogen to obtain a globally smooth chip surface.

[0065] The device was then fabricated using conventional processes. A 360nm thick Y2O3 single-layer antireflection film and a Y2O3 / Au / Ti multilayer high reflectivity film were deposited on the front and back cavity surfaces of the chip, respectively. The wafer was cleaved into laser bars with a cavity length of 5mm, and the chip was bonded to a diamond heat sink using indium as solder via flip bonding. Finally, packaging and optoelectronic performance testing were completed.

[0066] In this embodiment, the total mirror loss after coating is equivalent to a 5mm long uncoated cavity surface. However, the above materials and processes are only examples and do not constitute a limitation.

[0067] The quantum cascade laser fabricated in this embodiment has a chip surface free of depressions, steps, and air gaps, effectively eliminating surface defects introduced by secondary epitaxy. In room temperature continuous wave operation mode, the device exhibits significantly improved heat dissipation performance, and its output power and electro-optic conversion efficiency are markedly improved compared to devices using traditional undergrown processes, resulting in a substantial increase in long-term operational reliability.

[0068] Example 2 This embodiment uses a wide-ridge high-power quantum cascade laser as the fabrication target, employing a SiNx-SiO2 composite hard mask instead of a single-layer SiO2 hard mask, and adjusting the polishing and mask removal processes accordingly. This embodiment is an exemplary extension based on the process principle of Embodiment 1, used to illustrate the adaptation of the method of the present invention to different mask materials, different epitaxial devices, and different device structures.

[0069] In this embodiment, the laser ridge width is set to 11.6 μm, and the trench wet etching depth is approximately 10 μm. The basic structure of the epitaxial wafer is consistent with that of Example 1, consisting of an n-type InP substrate, an n-type InP lower cladding, a quantum cascade active region, an n-type InP upper cladding, and an n-type InP cap layer from bottom to top.

[0070] When fabricating the composite hard mask layer, a plasma-enhanced chemical vapor deposition (PECVD) system was used to sequentially deposit a 200 nm thick SiO2 adhesion layer and an 800 nm thick SiN layer. x A hard layer, approximately 1 μm thick in total. After patterning by photolithography and dry etching, a dense composite mask structure is retained at the top of the laser ridge to expose the InP surface in the trench region. The SiO2 underlayer is used to improve interfacial adhesion with the InP material, and the SiN... x The top layer has higher mechanical strength and polishing selectivity, which can further improve the control precision of the polishing endpoint.

[0071] The overgrowth of the semi-insulating buried layer was performed using a metal-organic chemical vapor deposition (MOCVD) system. A secondary epitaxial overgrowth layer of semi-insulating Fe:InP was grown, ensuring the buried layer completely filled the trenches and that its highest surface extended approximately 3 μm beyond the top of the laser ridge. This ensured complete trench filling and the formation of a sufficient raised redundant layer, while avoiding excessive removal during polishing.

[0072] Chemical mechanical polishing (CMP) is performed using an alumina-based polishing slurry for global planarization. Fe:InP and SiN are pre-calibrated before polishing. x The polishing rate ratio. The polishing endpoint is determined by combining optical reflection, film thickness monitoring, or time window control, polishing down to the remaining SiN. x The process stops when the thickness reaches 50-100nm. This step simultaneously removes growth defects such as particles and edge polycrystalline areas from the epitaxial surface, resulting in a globally flat chip surface.

[0073] Selective removal of any remaining SiN using hot phosphoric acid solution at 160°C x A mask was applied; subsequently, a diluted HF solution (HF:H2O=1:3) was used to briefly remove the SiO2 adhesion layer, resulting in a smooth surface. The etching time and temperature were calibrated based on the film density and the measured etching rate to avoid surface roughening caused by prolonged etching.

[0074] This embodiment employs SiO2 / SiN x A composite hard mask, replacing the single-layer SiO2 hard mask, also achieves global planarization and defect removal after secondary epitaxy. This result demonstrates that the method of this invention is not limited to a single dielectric mask material; it can be flexibly selected according to device performance requirements and production line process conditions, exhibiting strong process compatibility.

[0075] Comparative Example 1 This comparative example is based on Example 1, except that the SiO2 mask with oxygen plasma densification treatment used in Example 1 is replaced with a SiO2 mask deposited by conventional PECVD without oxygen plasma densification treatment. All other process conditions are exactly the same as in Example 1.

[0076] The conventional PECVD deposition process parameters for SiO2 masks are as follows: SiH4, N2O, and N2 are used as process gases; the substrate temperature is approximately 300°C; the reaction chamber pressure is approximately 0.9 Torr; a 13.56 MHz RF power of approximately 30 W is used; and the flow rates of SiH4, N2O, and N2 are approximately 10 sccm, 1420 sccm, and 392 sccm, respectively. The deposition rate is controlled at approximately 65 nm / min until the SiO2 layer thickness reaches approximately 1 μm. The SiO2 layer obtained by this conventional process is not subjected to oxygen plasma densification treatment.

[0077] During the high-temperature epitaxy stage of MOCVD, the SiO2 mask prepared in Comparative Example 1 showed cracking and edge peeling. Fe:InP grew laterally along the mask damage, eroding the top of the laser ridge and disrupting the integrity of the ridge waveguide structure. During the CMP polishing stage, due to the low polishing selectivity between Fe:InP and the SiO2 mask, the mask wear rate was significantly faster, and the polishing endpoint window was extremely narrow, making it difficult to accurately control the stop position. This resulted in some samples having their ridge-top InP accidentally polished, causing irreversible device damage.

[0078] The above results indicate that SiO2 masks prepared by conventional PECVD have weak crack resistance in high-temperature epitaxial environments due to the lack of densification treatment, and the wear rate is fast during CMP. Therefore, they cannot simultaneously serve as both high-temperature epitaxial growth masks and high-selectivity CMP stop layers.

[0079] In Example 1, a SiO2 mask was used for PECVD deposition followed by oxygen plasma densification. This enhanced the film density, mechanical strength, and chemical stability, enabling it to remain intact during subsequent MOCVD high-temperature secondary epitaxy and CMP polishing.

[0080] Comparative Example 2 This comparative example is based on Example 1, but with a change in the Fe:InP secondary epitaxial growth method. A QCL device with a ridge width of 10 μm was fabricated using a conventional undergrowth method, while all other conditions remained identical to Example 1. Comparative Example 2 used a conventional undergrowth method, with the Fe:InP growth thickness approximately 8 μm and a residual depression of approximately 2 μm at the top of the trench. Example 1 used an overgrowth method, with the Fe:InP extending 3.0 μm beyond the ridge top.

[0081] The wafers of Comparative Example 2 and Example 1 were CMP polished using the same process, with a patterned SiO2 hard mask as the polishing stop layer, and polishing was stopped when the remaining SiO2 thickness was 80nm; then the remaining SiO2 hard mask was removed with diluted hydrofluoric acid to obtain the chip under test.

[0082] The chips obtained in Comparative Example 2 and Example 1 were respectively subjected to cavity surface coating, cleavage, and flip-chip packaging using the same process to fabricate buried ridge quantum cascade lasers. Performance comparisons were then performed, and the results are as follows: Figure 2-3 As shown in Table 1.

[0083] Surface morphology and defect characterization were performed by observing the cross-sectional morphology of the samples using scanning electron microscopy to determine the trench filling status, surface smoothness, and removal of secondary epitaxial defects.

[0084] The thermal conductivity characteristics were verified using finite element thermal simulation at injection power densities close to the threshold (approximately 1.3 × 10⁻⁶). 14 W / m 3The temperature distribution inside the active region of the device in Example 1 and the device in Comparative Example 2 are compared.

[0085] The core optoelectronic parameters were tested at room temperature and liquid nitrogen temperature (80 K) to measure the threshold current density, output power density, maximum continuous wave output power and electro-optical conversion efficiency of the device in Example 1 and the device in Comparative Example 2.

[0086] The cross-sectional SEM image of the chip obtained in Comparative Example 2 is as follows: Figure 2 As shown. From Figure 2 It can be seen that after CMP polishing, a large area of ​​air gap still exists in the trench, and interface defects (including lattice dislocations, polycrystalline grains, and impurity aggregation) are concentrated on the trench sidewalls, bottom, and ridge sides. These defects are located in the closed area inside the device and cannot be touched by any subsequent surface processing. They will remain permanently near the active region of the device, becoming the source of leakage current and hot spots.

[0087] The cross-sectional SEM image of the chip obtained in Example 1 is shown below. Figure 3 As shown. From Figure 3 It can be seen that the groove is completely filled with Fe:InP, with no air gaps, and the surface is flat. The defects generated by the secondary epitaxy have been ground away along with the raised layer, and there are no residual defects on the final working surface.

[0088] Table 1 Performance Comparison Results

[0089] Table 1 shows that, under room temperature continuous wave operation mode, the device in Example 1 exhibits a lower threshold current density, higher maximum output power and power density, and a significantly reduced peak temperature rise in the active region at the same power. Thermal simulation also indicates that the internal temperature of the active region is reduced by approximately 5°C. Overall, its heat dissipation and optoelectronic performance are superior to those of Comparative Example 2. These results demonstrate that, under the same CMP polishing conditions, overgrowth filling eliminates air gaps within the trenches, effectively reducing the overall thermal resistance of the device and improving heat dissipation performance. Simultaneously, the polishing process removes secondary epitaxial defects, reducing leakage current and localized hot spots, thereby enhancing the device's output power and electro-optical conversion efficiency.

[0090] At liquid nitrogen temperature (80K), the device in Example 1 achieved a maximum output power of 12W and a highest electro-optical conversion efficiency of 41%. This result demonstrates that the device prepared by the method of this invention still exhibits excellent power output capability and energy conversion efficiency at low temperatures.

[0091] Comparative Example 3 This comparative example is based on Example 1, but the SiO2 hard mask is replaced with a single-layer SiNx hard mask of the same thickness, while keeping the other main process conditions the same. Under the deposition and secondary epitaxy process conditions used in this example, the single-layer SiNx hard mask exhibits large interfacial stress and poor edge stability during high-temperature secondary epitaxy, with some samples showing mask edge warping or peeling. In contrast, Example 2, using a SiO2 / SiNx composite hard mask, utilizes the underlying SiO2 to improve interfacial adhesion and stress buffering, resulting in a more stable secondary epitaxy and subsequent planarization process window.

[0092] This invention belongs to the field of semiconductor laser manufacturing technology. The provided methods and devices can be applied to the fabrication of buried ridge semiconductor lasers and semiconductor optical amplifiers using material systems such as indium phosphide, gallium arsenide, gallium nitride, gallium antimony, silicon carbide, silicon, germanium, silicon-germanium, germanium-tin, or silicon-germanium-tin. Through an integrated process of overgrowth filling, surface planarization, and defect removal, this invention can improve the heat dissipation performance of the device, reduce thermal resistance, and increase output power and long-term operational reliability.

[0093] The semiconductor laser prepared by this invention can be used in fields such as free-space laser communication, infrared spectroscopy analysis, gas detection, precision measurement, medical diagnosis, and industrial processing. In free-space laser communication, the mid-infrared quantum cascade laser can cover the atmospheric transparent window, providing a stable continuous wave source; in gas detection and spectral analysis, high-power, low-defect lasers help improve detection sensitivity; in precision measurement and medical diagnosis, devices with smooth surfaces and good heat dissipation are beneficial to improving system stability and service life.

[0094] The method of this invention does not require modification of the core equipment and main process lines of existing semiconductor laser manufacturing, is compatible with existing epitaxial, etching, polishing and mask removal processes, has mass production feasibility, and is suitable for the industrial preparation of high-power continuous wave semiconductor lasers.

[0095] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0096] The above description describes specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for surface planarization and defect treatment of a secondary epitaxial layer in a semiconductor laser, characterized in that, Includes the following steps: Step 1: Provide a wafer with completed epitaxial growth of the active region structure; Step 2: A hard mask layer is formed on the surface of the wafer, and the hard mask layer is patterned to obtain a patterned hard mask layer. Step 3: Using the patterned hard mask layer as an etching mask, laser ridges and trenches located on both sides of the laser ridges are etched on the wafer surface. After etching is completed, the patterned hard mask layer is retained. Step 4: Epitaxial growth of the buried material is performed in the trench. The trench is completely filled by over-growth, and the buried material extends beyond the upper surface of the trench opening, forming a protrusion above the left and right sides of the laser ridge. Step 5: Using the patterned hard mask layer as the polishing stop layer, polish the wafer to remove the protrusions and retain at least a portion of the patterned hard mask layer. Step six: Use a selective removal process for the hard mask layer to remove the remaining patterned hard mask layer and obtain a chip with a smooth surface.

2. The method according to claim 1, characterized in that, The height of the burial material above the opening of the trench is 2~5μm.

3. The method according to claim 1, characterized in that, The thickness of the hard mask layer is 0.5~2μm.

4. The method according to claim 3, characterized in that, In step five, polishing is stopped when the remaining thickness of the patterned hard mask layer is 50~100nm.

5. The method according to claim 1, characterized in that, The hard mask layer is a single-layer dielectric layer or a multilayer composite structure composed of two or more dielectric layers; the material of the hard mask layer is selected from at least one of silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide and zirconium oxide.

6. The method according to claim 1, characterized in that, The buried material is a semi-insulating semiconductor material or a high-resistivity semiconductor material that is epitaxially compatible with the wafer material system.

7. The method according to claim 6, characterized in that, The polishing rate selection ratio between the buried material and the hard mask layer is 5:1 to 20:

1.

8. The method according to claim 1, characterized in that, The material system of the wafer is any one of indium phosphide, gallium arsenide, gallium nitride, gallium antimonide, silicon carbide, silicon, germanium, silicon-germanium, germanium-tin, or silicon-germanium-tin.

9. A semiconductor laser chip, characterized in that, The chip is prepared by the method described in any one of claims 1-8.

10. A semiconductor laser, characterized in that, Includes the chip described in claim 9.

Images