A circuit for implementing relay zero-crossing protection control in hardware

Abstract

The application relates to the technical field of zero-crossing protection, and discloses a circuit for realizing relay zero-crossing protection control by hardware, which comprises a current-limiting resistor Rd, a rectifier bridge U3, an optical coupler U1, a D flip-flop U2, an alternating-current relay RL and a triode, and one end of the current-limiting resistor Rd is electrically connected with an L end of an alternating-current network. In the application, the alternating current input from the L end and an N end of the alternating-current network can be converted into a pulsating direct-current signal changing with alternating-current phase after current limiting and rectification by setting the current-limiting resistor Rd, the rectifier bridge U3, the optical coupler U1 and a first pull-up resistor, an effective zero-crossing detection signal is formed by the optical coupler U1 and a ZERO node when the alternating voltage approaches zero, the pure hardware detection of the alternating-current zero point is realized, the alternating-current strong electric side and the weak electric logic control side are isolated by using the electrical isolation characteristic of the optical coupler U1, and the anti-interference ability and response timeliness of the zero-crossing detection are improved.

Description

Technical Field

[0001] This invention relates to the field of zero-crossing protection technology, and in particular to a circuit for hardware implementation of relay zero-crossing protection control. Background Technology

[0002] With the continuous improvement of the automation level of electrical equipment and the increasing demands for the safety, stability and service life of relay control, higher requirements are also being placed on the control of the relay's operating moment. As an important device in electrical control systems for realizing circuit switching, signal switching and load control, relays are widely used in industrial control, home appliances, power distribution equipment and automated control systems. In the process of controlling AC loads, relays usually drive the contacts to close or release through the energization or de-energization of the coil, thereby realizing the connection or disconnection of the AC network. Since AC voltage and AC current change periodically with time, it is necessary to develop a hardware circuit to realize the zero-crossing protection control of relays.

[0003] However, in existing technologies, the switching of relays is mostly driven directly by external control signals, or the relay is controlled by delay after software detects the AC zero crossing point. Due to sampling delay and execution deviation in the software program, as well as differences in action time, device aging, and changes in the working environment among different relays, in actual use, it is easy for the relay to fail to accurately engage or disengage near the AC voltage zero crossing, which in turn causes a large electric arc and current surge to be generated at the moment of contact action, accelerating contact erosion and aging. Summary of the Invention

[0004] To overcome the above deficiencies, this invention provides a circuit for hardware implementation of relay zero-crossing protection control, aiming to improve the problem in the prior art where the switching of relays is mostly driven directly by external control signals.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a circuit for hardware implementation of relay zero-crossing protection control, including a current-limiting resistor Rd, a rectifier bridge U3, an optocoupler U1, a D flip-flop U2, an AC relay RL, and a transistor;

[0006] One end of the current-limiting resistor Rd is electrically connected to the L terminal of the AC network, and the other end of the current-limiting resistor Rd is electrically connected to one AC input terminal of the rectifier bridge U3. The other AC input terminal of the rectifier bridge U3 is electrically connected to the N terminal of the AC network.

[0007] The positive output terminal of the rectifier bridge U3 is electrically connected to the first input terminal of the optocoupler U1, and the negative output terminal of the rectifier bridge U3 is electrically connected to the second input terminal of the optocoupler U1. The first output terminal of the optocoupler U1 is electrically connected to one end of the first pull-up resistor and the clock terminal CLK of the D flip-flop U2, forming a ZERO node. The other end of the first pull-up resistor is electrically connected to the power supply terminal, and the second output terminal of the optocoupler U1 is grounded.

[0008] The data input terminal D of the D flip-flop U2 is electrically connected to the CTR node, the output terminal Q of the D flip-flop U2 is electrically connected to the OUT node, the OUT node is electrically connected to the base of the transistor through the base resistor, the emitter of the transistor is grounded, the collector of the transistor is electrically connected to the first terminal of the coil of the AC relay RL, and the second terminal of the coil of the AC relay RL is electrically connected to the power supply terminal.

[0009] The contact terminals of the AC relay RL are connected to the AC network and are used to control the on / off state of the AC network.

[0010] Through the above technical solution, the interaction between the current-limiting resistor Rd, rectifier bridge U3, optocoupler U1, D flip-flop U2, transistor, and AC relay RL allows the AC input to the AC network to be current-limited and rectified to form a pulsating DC signal for zero-crossing detection. The optocoupler U1 converts the zero-crossing state of the AC high-voltage side into a ZERO node logic signal on the low-voltage side. By sampling and latching the external control signal of the CTR node at the zero-crossing moment through the D flip-flop U2, the activation or deactivation of the AC relay RL can be limited to the period when the AC voltage is close to zero. This reduces the possibility of arcing and current surges at the moment the relay contacts are switched on and off, and improves the safety, stability, and service life of the relay control.

[0011] As a further description of the above technical solution:

[0012] The two AC input terminals of the rectifier bridge U3 are connected to the L and N terminals of the AC network, respectively. The rectifier bridge U3 converts the AC power input from the AC network into pulsating DC power and outputs it to the input side of the optocoupler U1.

[0013] The above technical solution allows for the rectification of the AC input from the AC network via the rectifier bridge U3, converting both the positive and negative half-cycles of the AC power into pulsating DC power that changes in the same direction. This pulsating DC power is then output to the input side of the optocoupler U1, providing a basis for the optocoupler U1 to detect whether the AC voltage is close to zero. Simultaneously, the current-limiting resistor Rd limits the current entering the rectifier bridge U3 and the input side of the optocoupler U1, reducing the possibility of AC voltage directly affecting the optocoupler U1 and causing device damage.

[0014] As a further description of the above technical solution:

[0015] The optocoupler U1 includes an input-side light-emitting diode and an output-side phototransistor. The two ends of the input-side light-emitting diode are electrically connected to the positive and negative output terminals of the rectifier bridge U3, respectively. The collector of the output-side phototransistor is electrically connected to the ZERO node, and the emitter of the output-side phototransistor is grounded.

[0016] The above technical solution allows for the following: The input-side LED of optocoupler U1 receives the pulsating DC current output from rectifier bridge U3. The output-side phototransistor of optocoupler U1 can be controlled to turn on or off based on changes in the AC network voltage. When the AC network voltage is far from zero, the input-side LED of optocoupler U1 turns on, driving the output-side phototransistor to turn on. When the AC network voltage approaches zero, the input-side LED of optocoupler U1 turns off or its luminous intensity decreases, causing the output-side phototransistor to turn off, thus achieving hardware detection of the AC zero-crossing state. Simultaneously, the electrical isolation provided by optocoupler U1 isolates the AC high-voltage side from the low-voltage logic control side, improving circuit safety and anti-interference capabilities.

[0017] As a further description of the above technical solution:

[0018] The ZERO node is electrically connected to the power supply terminal through a first pull-up resistor. When the phototransistor on the output side of the optocoupler U1 is turned on, the ZERO node is pulled low; when the phototransistor on the output side of the optocoupler U1 is turned off, the ZERO node is pulled up to a high level through the first pull-up resistor.

[0019] The above technical solution provides a stable pull-up level for the ZERO node via the first pull-up resistor. When the phototransistor on the output side of optocoupler U1 is turned on, the ZERO node is pulled to ground via the phototransistor and forms a low-level state. When the AC network voltage approaches zero, causing the phototransistor on the output side of optocoupler U1 to turn off, the ZERO node is no longer pulled down and is pulled up to a high level via the first pull-up resistor, thus forming an effective zero-crossing trigger signal near the zero-crossing of the AC voltage. The level change of the ZERO node provides a clock trigger signal for the D flip-flop U2, enabling subsequent control actions to be updated when the AC voltage approaches zero.

[0020] As a further description of the above technical solution:

[0021] The clock terminal CLK of the D flip-flop U2 is electrically connected to the ZERO node, the data input terminal D of the D flip-flop U2 is electrically connected to the CTR node, the ground terminal GND of the D flip-flop U2 is grounded, and the power supply terminal VCC of the D flip-flop U2 is electrically connected to the power supply terminal.

[0022] The above technical solution allows the CTR node to receive external control signals and the ZERO node to provide a zero-crossing trigger signal to the clock input CLK of the D flip-flop U2. This prevents the D flip-flop U2 from immediately changing its output when the CTR node level changes. Instead, it samples and latches the control level of the CTR node when the AC network voltage approaches zero and a valid clock trigger signal is generated. When the CTR node is high and the ZERO node generates a valid zero-crossing trigger signal, the output Q of the D flip-flop U2 outputs a high level. When the CTR node is low and the ZERO node generates a valid zero-crossing trigger signal, the output Q of the D flip-flop U2 outputs a low level. This limits the relay's activation or deactivation to the zero-crossing trigger moment, reducing the likelihood of the relay activating instantaneously under high voltage or high current.

[0023] As a further description of the above technical solution:

[0024] The preset terminal PRE# of the D flip-flop U2 is electrically connected to the power supply terminal through a second pull-up resistor, and the clear terminal CLR# of the D flip-flop U2 is electrically connected to the power supply terminal through a third pull-up resistor, so that the preset terminal PRE# and the clear terminal CLR# of the D flip-flop U2 are kept in an invalid level state.

[0025] The above technical solution allows the second and third pull-up resistors to maintain the preset (PRE#) and clear (CLR#) terminals of the D flip-flop U2 at high levels, respectively. Since the preset (PRE#) and clear (CLR#) terminals are active low, they remain inactive during normal operation, preventing the D flip-flop U2 from being falsely set or reset due to floating preset or clear terminals. By fixing the preset (PRE#) and clear (CLR#) terminals, the stability of the output state of the D flip-flop U2 can be improved, making the output of the OUT node mainly determined by the CTR and ZERO nodes, thereby ensuring the reliability of the zero-crossing sampling and latching control process.

[0026] As a further description of the above technical solution:

[0027] The OUT node is electrically connected to one end of the base resistor, the other end of the base resistor is electrically connected to the base of the transistor, the collector of the transistor is electrically connected to the first end of the coil of the AC relay RL, and the emitter of the transistor is grounded, so that the output terminal Q of the D flip-flop U2 controls the coil of the AC relay RL to be energized or de-energized via the OUT node.

[0028] The above technical solution allows the following: the OUT node receives the latching control level of the output Q of the D flip-flop U2 and transmits this control level to the base of the transistor via the base resistor. The base resistor limits the base current of the transistor, reducing the adverse effects of excessive drive current on the transistor. When the OUT node is high, the transistor conducts, grounding the first terminal of the AC relay RL coil via the transistor, forming a power supply circuit for the AC relay RL coil and energizing it. When the OUT node is low, the transistor is cut off, the power supply circuit for the AC relay RL coil is disconnected, and it is de-energized and released. By driving the relay coil with the transistor, the weak current logic output of the D flip-flop U2 can stably control the mechanical action of the AC relay RL.

[0029] As a further description of the above technical solution:

[0030] The AC relay RL includes a coil terminal and a contact terminal. The coil terminal includes a first coil terminal and a second coil terminal. The first coil terminal is electrically connected to the collector of a transistor, and the second coil terminal is electrically connected to a power supply terminal. The contact terminal includes a first contact terminal and a second contact terminal. The first contact terminal is electrically connected to the L terminal of the AC network, and the second contact terminal serves as a controlled AC output terminal.

[0031] The above technical solution allows the coil of the AC relay RL to receive drive control from the transistor output, and the contacts of the AC relay RL to connect to the power path of the AC network. When the coil of the AC relay RL is energized, the contacts of the AC relay RL close, connecting the L terminal of the AC network to the controlled AC output terminal, thus supplying AC power to the external load. When the coil of the AC relay RL is de-energized, the contacts of the AC relay RL open, disconnecting the L terminal of the AC network from the controlled AC output terminal, thus stopping the power supply to the external load. Since the energization or de-energization of the AC relay RL coil is latched by the D flip-flop U2 when a zero-crossing trigger signal is generated at the ZERO node, the switching action of the AC relay RL contacts can occur when the AC network voltage is close to zero, thereby reducing the possibility of arcing during the moment the relay contacts close or release, and extending the service life of the relay.

[0032] The present invention has the following beneficial effects:

[0033] 1. In this invention, by setting a current-limiting resistor Rd, a rectifier bridge U3, an optocoupler U1, and a first pull-up resistor, the AC power input at the L and N terminals of the AC network can be converted into a pulsating DC signal that changes with the AC phase after current limiting and rectification. When the AC voltage approaches zero, an effective zero-crossing detection signal is formed through the optocoupler U1 and the ZERO node, realizing pure hardware detection of AC zero crossing. By utilizing the electrical isolation characteristics of the optocoupler U1, the AC high-voltage side is isolated from the low-voltage logic control side, improving the anti-interference capability and response timeliness of zero crossing detection.

[0034] 2. In this invention, by setting up a D flip-flop U2, a CTR node, a ZERO node, an OUT node, a base resistor, a transistor, and an AC relay RL, the external control signal does not directly control the relay action. Instead, when the ZERO node generates a zero-crossing trigger signal, the D flip-flop U2 samples, latches, and outputs the control level of the CTR node to the relay drive circuit. This limits the activation or deactivation of the AC relay RL to the period when the AC network voltage is close to zero, avoiding the problem that traditional software delay control makes it difficult for the relay to operate accurately at the zero-crossing point due to differences in components, aging, and execution delays. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of a circuit structure for hardware implementation of relay zero-crossing protection control proposed in this invention. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] Reference Figure 1 One embodiment of the present invention includes:

[0038] The current limiting detection unit includes a current limiting resistor Rd, one end of which is electrically connected to the L terminal of the AC network, and the other end is electrically connected to an AC input terminal of the rectifier bridge U3.

[0039] The rectifier unit includes a rectifier bridge U3, another AC input terminal of which is electrically connected to the N terminal of the AC network. The rectifier bridge U3 is used to convert the AC power input from the AC network into pulsating DC power.

[0040] The zero-crossing detection unit includes an optocoupler U1, the first input end of which is electrically connected to the positive output end of the rectifier bridge U3, and the second input end of which is electrically connected to the negative output end of the rectifier bridge U3.

[0041] The logic latch unit includes a D flip-flop U2, the clock terminal CLK of the D flip-flop U2 is electrically connected to the ZERO node, the data input terminal D of the D flip-flop U2 is electrically connected to the CTR node, and the output terminal Q of the D flip-flop U2 is electrically connected to the OUT node.

[0042] The relay driving unit includes a base resistor and a transistor. The OUT node is electrically connected to the base of the transistor through the base resistor. The emitter of the transistor is grounded. The collector of the transistor is electrically connected to the first terminal of the coil of the AC relay RL.

[0043] An AC relay RL has its coil second terminal electrically connected to the power supply terminal, and its contact terminal connected to an AC network to control the on / off state of the AC network.

[0044] Specifically, the AC network includes an L terminal and an N terminal. A current-limiting resistor Rd is connected in series between the L terminal of the AC network and the rectifier bridge U3 to limit the current entering the rectifier bridge U3 and the input side of the optocoupler U1, preventing AC voltage from directly affecting the input side of the optocoupler U1 and causing device damage. The two AC input terminals of the rectifier bridge U3 are connected to the L terminal and the N terminal of the AC network, respectively. The positive and negative output terminals of the rectifier bridge U3 output pulsating DC voltages, which are applied to the input side of the optocoupler U1. The output side of the optocoupler U1 and the first pull-up resistor together constitute the level conversion structure of the ZERO node. The ZERO node is connected to the clock terminal CLK of the D flip-flop U2; the CTR node, as an external control signal input node, is connected to the data input terminal D of the D flip-flop U2; the output terminal Q of the D flip-flop U2 outputs a control level through the OUT node. This control level is current-limited by the base resistor and then sent to the base of the transistor, causing the transistor to turn on or off according to the level state of the OUT node, thereby controlling the energization or de-energization of the AC relay RL coil; the contact terminal of the AC relay RL is connected in series in the L terminal output path of the AC network, and the on / off control of the controlled AC output terminal is realized by the closing or opening of the contacts.

[0045] Reference Figure 1 The two AC input terminals of the rectifier bridge U3 are connected to the L and N terminals of the AC network, respectively. The rectifier bridge U3 converts the AC power input from the AC network into pulsating DC power and outputs it to the input side of the optocoupler U1.

[0046] Specifically, one end of the current-limiting resistor Rd is connected to the L terminal of the AC network, and the other end of the current-limiting resistor Rd is connected to the first AC input terminal of the rectifier bridge U3. The second AC input terminal of the rectifier bridge U3 is connected to the N terminal of the AC network. When there is AC voltage in the AC network, the AC voltage enters the rectifier bridge U3 after being limited by the current-limiting resistor Rd. The rectifier bridge U3 rectifies both the positive and negative half-cycle AC voltages, so that the positive output terminal of the rectifier bridge U3 forms a pulsating DC voltage relative to the negative output terminal. This pulsating DC voltage changes periodically with the AC network voltage. When the AC voltage is far from zero, its voltage amplitude can drive the input side of the optocoupler U1 to conduct. When the AC voltage is close to zero, its voltage amplitude drops to a level insufficient to maintain the conduction of the input side of the optocoupler U1, thus providing a detection basis for the subsequent ZERO node to change with the AC zero point.

[0047] Reference Figure 1 The optocoupler U1 includes an input-side light-emitting diode and an output-side phototransistor. The two ends of the input-side light-emitting diode are electrically connected to the positive and negative output terminals of the rectifier bridge U3, respectively. The collector of the output-side phototransistor is electrically connected to the ZERO node, and the emitter of the output-side phototransistor is grounded.

[0048] Specifically, the LED on the input side of optocoupler U1 receives the pulsating DC current output from rectifier bridge U3. When the AC network voltage is in the non-zero-crossing region, the pulsating DC voltage output by rectifier bridge U3 is higher than the conduction threshold of the LED on the input side of optocoupler U1, causing the LED on the input side of optocoupler U1 to light up, thus turning on the phototransistor on the output side of optocoupler U1. When the AC network voltage is close to zero, the output voltage of rectifier bridge U3 drops, the LED on the input side of optocoupler U1 turns off or its luminous intensity decreases, and the phototransistor on the output side of optocoupler U1 turns off. Through the electrical isolation between the input and output sides of optocoupler U1, the high-voltage AC network and the low-voltage logic control circuit can be kept isolated while detecting the zero-crossing state of the AC network, improving the safety and anti-interference capability of the control circuit.

[0049] Reference Figure 1 The ZERO node is electrically connected to the power supply terminal through the first pull-up resistor. When the phototransistor on the output side of the optocoupler U1 is turned on, the ZERO node is pulled low; when the phototransistor on the output side of the optocoupler U1 is turned off, the ZERO node is pulled up to a high level through the first pull-up resistor.

[0050] Specifically, one end of the first pull-up resistor is connected to the power supply, and the other end is connected to the ZERO node. The ZERO node is simultaneously connected to the collector of the phototransistor on the output side of optocoupler U1 and the clock terminal CLK of D flip-flop U2. The emitter of the phototransistor on the output side of optocoupler U1 is grounded. When the phototransistor on the output side of optocoupler U1 is turned on, the ZERO node is pulled to ground through the phototransistor, forming a low-level state. When the AC network voltage approaches zero, causing the phototransistor on the output side of optocoupler U1 to turn off, the ZERO node is no longer pulled down, and the first pull-up resistor pulls the ZERO node up to a high level, thereby forming a high-level pulse signal near the AC zero crossing. This high-level pulse of the ZERO node serves as the clock trigger signal for D flip-flop U2, allowing the subsequent relay control action to be updated only near the AC voltage zero crossing.

[0051] Reference Figure 1 The clock terminal CLK of the D flip-flop U2 is electrically connected to the ZERO node, the data input terminal D of the D flip-flop U2 is electrically connected to the CTR node, the ground terminal GND of the D flip-flop U2 is grounded, and the power supply terminal VCC of the D flip-flop U2 is electrically connected to the power supply terminal.

[0052] Specifically, the CTR node is used to receive external control signals, which can be a high-level closing instruction or a low-level opening instruction. The data input D of the D flip-flop U2 continuously receives the control level of the CTR node, but the output Q of the D flip-flop U2 does not change immediately with the level change of the CTR node. Instead, when the ZERO node provides a valid clock edge to its clock input CLK, the level state of the CTR node is sampled and latched. When the CTR node is high and the ZERO node generates a valid zero-crossing trigger signal, the output Q of the D flip-flop U2 outputs a high level, and the OUT node synchronously becomes high. When the CTR node is low and the ZERO node generates a valid zero-crossing trigger signal, the output Q of the D flip-flop U2 outputs a low level, and the OUT node synchronously becomes low. This restricts the activation or deactivation of the AC relay RL to be executed near the zero-crossing of the AC network voltage, preventing the relay contacts from operating when the AC voltage or current is high.

[0053] Reference Figure 1 The preset terminal PRE# of the D flip-flop U2 is electrically connected to the power supply terminal through a second pull-up resistor, and the clear terminal CLR# of the D flip-flop U2 is electrically connected to the power supply terminal through a third pull-up resistor, so that the preset terminal PRE# and the clear terminal CLR# of the D flip-flop U2 are kept in an invalid level state.

[0054] Specifically, the preset terminal PRE# and the clear terminal CLR# of the D flip-flop U2 are active low-level control terminals. After being connected to the power supply through the second and third pull-up resistors respectively, the preset terminal PRE# and the clear terminal CLR# remain at a high level under normal operating conditions, thus being in an inactive state. Under this connection method, the D flip-flop U2 will not be falsely triggered due to the preset or clear terminal being floating, nor will it be abnormally set or reset during relay control. By fixing the preset terminal PRE# and the clear terminal CLR#, the stability of the output state of the D flip-flop U2 can be improved, so that the output of the OUT node is mainly determined by the CTR node and the ZERO node, ensuring the reliable execution of the zero-crossing sampling control logic.

[0055] Reference Figure 1 The OUT node is electrically connected to one end of the base resistor, the other end of the base resistor is electrically connected to the base of the transistor, the collector of the transistor is electrically connected to the first end of the coil of the AC relay RL, and the emitter of the transistor is grounded, so that the output terminal Q of the D flip-flop U2 controls the coil of the AC relay RL to be energized or de-energized via the OUT node.

[0056] Specifically, a base resistor is connected in series between the OUT node and the base of the transistor to limit the base current of the transistor. The transistor is preferably an NPN type, with its emitter grounded and its collector connected to the first terminal of the coil of the AC relay RL. The second terminal of the coil of the AC relay RL is connected to the power supply. When the output Q of the D flip-flop U2 outputs a high level, the OUT node is high, and the OUT node provides drive current to the base of the transistor through the base resistor, causing the transistor to enter the conducting state. The first terminal of the coil of the AC relay RL is grounded through the transistor, and the second terminal of the coil is connected to the power supply. The AC relay RL coil forms a complete power supply circuit and is energized and engaged. When the output Q of the D flip-flop U2 outputs a low level, the OUT node is low, there is no effective drive current to the base of the transistor, the transistor is cut off, the power supply circuit of the AC relay RL coil is cut off, and the AC relay RL is de-energized and released. By amplifying and driving the relay coil current through the transistor, the logic output of the D flip-flop U2 can stably control the mechanical contact action of the AC relay RL.

[0057] Reference Figure 1 The AC relay RL includes a coil terminal and a contact terminal. The coil terminal includes a first coil terminal and a second coil terminal. The first coil terminal is electrically connected to the collector of a transistor, and the second coil terminal is electrically connected to a power supply terminal. The contact terminal includes a first contact terminal and a second contact terminal. The first contact terminal is electrically connected to the L terminal of the AC network, and the second contact terminal serves as a controlled AC output terminal.

[0058] Specifically, the coil of the AC relay RL is used to receive the on / off control output from the relay drive unit, and the contact of the AC relay RL is used to connect to the power path of the AC network. The first contact of the AC relay RL is connected to the L terminal of the AC network, and the second contact of the AC relay RL serves as the controlled AC output terminal. When the coil of the AC relay RL is energized, the contact closes, making the L terminal of the AC network and the controlled AC output terminal conduct, and the external load receives AC power. When the coil of the AC relay RL is de-energized, the contact opens, making the L terminal of the AC network and the controlled AC output terminal disconnected, and the external load stops receiving power. Since the energization or de-energization of the AC relay RL coil is latched by the D flip-flop U2 when it is triggered at the zero crossing of the ZERO node, the on / off action of the AC relay RL contact occurs when the AC network voltage is close to zero, thereby reducing the arc impact at the moment the contact closes or opens.

[0059] Working principle: In relay on / off control mode, the L and N terminals of the AC network are connected to the rectifier bridge U3 through the current-limiting resistor Rd. The rectifier bridge U3 converts the AC power into pulsating DC power that varies with the AC phase period and outputs it to the input side of the optocoupler U1. When the AC network voltage is in the non-zero-crossing region, the output voltage of the rectifier bridge U3 can drive the input side of the optocoupler U1 to conduct, causing the phototransistor on the output side of the optocoupler U1 to conduct and pull the ZERO node low. When the AC network voltage is close to zero, the output voltage of the rectifier bridge U3 drops to a level that is insufficient to maintain the conduction of the input side of the optocoupler U1, the output side of the optocoupler U1 is cut off, and the ZERO node is pulled up through the first pull-up resistor to form an effective zero-crossing trigger signal. By cooperating with the current-limiting resistor Rd, the rectifier bridge U3, the optocoupler U1, and the first pull-up resistor, the zero-crossing state of the AC high-voltage side can be converted into a logic level signal on the low-voltage side. The isolation characteristics of the optocoupler U1 are used to achieve strong-weak isolation, thereby achieving the effect of pure hardware detection of AC zero-crossing points. This solves the problems of sampling delay, execution deviation, and untimely control in traditional software zero-crossing detection, and helps to improve the safety, timeliness, and reliability of relay zero-crossing control.

[0060] After receiving an external CTR control signal, the circuit does not directly drive the AC relay RL to operate. Instead, it connects to the data input terminal D of the D flip-flop U2. The ZERO node serves as the clock input CLK of the D flip-flop U2, triggering the D flip-flop U2 to sample and latch the control level of the CTR node only when the AC network voltage approaches zero and generates a valid zero-crossing trigger signal. If the CTR node is high, the output Q of the D flip-flop U2 outputs a high level through the OUT node, which drives the transistor to conduct through the base resistor, energizing the coil of the AC relay RL and connecting the relay contacts to the AC network. If the CTR node is low, the output Q of the D flip-flop U2 outputs a low level through the OUT node, the transistor is cut off, the coil of the AC relay RL is de-energized and released, and the relay contacts disconnect the AC network. By coordinating the D flip-flop U2, CTR node, ZERO node, OUT node, base resistor, transistor, and AC relay RL, the relay's activation or deactivation is restricted to near the zero-crossing of the AC voltage. This achieves the effect of hardware latching control of the relay's zero-crossing action, solving the problem of traditional solutions that rely on software delay or fixed offset time to control the relay and thus making it difficult to accurately land at the zero-crossing point. This helps reduce the arc impact and contact wear at the moment of relay contact opening and closing, and extends the relay's service life.

[0061] In practical applications, this hardware-based circuit for relay zero-crossing protection control not only achieves the effect of pure hardware detection of AC zero-crossing points, solving the problems of sampling delay, execution deviation, and untimely control in traditional software zero-crossing detection, but also improves the safety, timeliness, and reliability of relay zero-crossing control. In addition, it can also achieve the effect of hardware latching control of relay zero-crossing action, solving the problem that traditional solutions rely on software delay or fixed offset time to control the relay and make it difficult to accurately land at the zero-crossing point. This helps to reduce the arc impact and contact wear at the moment of relay contact opening and closing, and extend the service life of the relay.

[0062] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A circuit for hardware implementation of relay zero-crossing protection control, characterized in that, This includes a current-limiting resistor Rd, a rectifier bridge U3, an optocoupler U1, a D flip-flop U2, an AC relay RL, and a transistor; One end of the current-limiting resistor Rd is electrically connected to the L terminal of the AC network, and the other end of the current-limiting resistor Rd is electrically connected to one AC input terminal of the rectifier bridge U3. The other AC input terminal of the rectifier bridge U3 is electrically connected to the N terminal of the AC network. The positive output terminal of the rectifier bridge U3 is electrically connected to the first input terminal of the optocoupler U1, and the negative output terminal of the rectifier bridge U3 is electrically connected to the second input terminal of the optocoupler U1. The first output terminal of the optocoupler U1 is electrically connected to one end of the first pull-up resistor and the clock terminal CLK of the D flip-flop U2, forming a ZERO node. The other end of the first pull-up resistor is electrically connected to the power supply terminal, and the second output terminal of the optocoupler U1 is grounded. The data input terminal D of the D flip-flop U2 is electrically connected to the CTR node, the output terminal Q of the D flip-flop U2 is electrically connected to the OUT node, the OUT node is electrically connected to the base of the transistor through the base resistor, the emitter of the transistor is grounded, the collector of the transistor is electrically connected to the first terminal of the coil of the AC relay RL, and the second terminal of the coil of the AC relay RL is electrically connected to the power supply terminal. The contact terminals of the AC relay RL are connected to the AC network and are used to control the on / off state of the AC network.

2. The circuit for hardware implementation of relay zero-crossing protection control according to claim 1, characterized in that: The two AC input terminals of the rectifier bridge U3 are connected to the L and N terminals of the AC network, respectively. The rectifier bridge U3 converts the AC power input from the AC network into pulsating DC power and outputs it to the input side of the optocoupler U1.

3. The circuit for hardware implementation of relay zero-crossing protection control according to claim 1, characterized in that: The optocoupler U1 includes an input-side light-emitting diode and an output-side phototransistor. The two ends of the input-side light-emitting diode are electrically connected to the positive and negative output terminals of the rectifier bridge U3, respectively. The collector of the output-side phototransistor is electrically connected to the ZERO node, and the emitter of the output-side phototransistor is grounded.

4. The circuit for hardware implementation of relay zero-crossing protection control according to claim 3, characterized in that: The ZERO node is electrically connected to the power supply terminal through a first pull-up resistor. When the phototransistor on the output side of the optocoupler U1 is turned on, the ZERO node is pulled low; when the phototransistor on the output side of the optocoupler U1 is turned off, the ZERO node is pulled up to a high level through the first pull-up resistor.

5. The circuit for hardware implementation of relay zero-crossing protection control according to claim 1, characterized in that: The clock terminal CLK of the D flip-flop U2 is electrically connected to the ZERO node, the data input terminal D of the D flip-flop U2 is electrically connected to the CTR node, the ground terminal GND of the D flip-flop U2 is grounded, and the power supply terminal VCC of the D flip-flop U2 is electrically connected to the power supply terminal.

6. The circuit for hardware implementation of relay zero-crossing protection control according to claim 5, characterized in that: The preset terminal PRE# of the D flip-flop U2 is electrically connected to the power supply terminal through a second pull-up resistor, and the clear terminal CLR# of the D flip-flop U2 is electrically connected to the power supply terminal through a third pull-up resistor, so that the preset terminal PRE# and the clear terminal CLR# of the D flip-flop U2 are kept in an invalid level state.

7. The circuit for hardware implementation of relay zero-crossing protection control according to claim 1, characterized in that: The OUT node is electrically connected to one end of the base resistor, the other end of the base resistor is electrically connected to the base of the transistor, the collector of the transistor is electrically connected to the first end of the coil of the AC relay RL, and the emitter of the transistor is grounded, so that the output terminal Q of the D flip-flop U2 controls the coil of the AC relay RL to be energized or de-energized via the OUT node.

8. The circuit for hardware implementation of relay zero-crossing protection control according to claim 1, characterized in that: The AC relay RL includes a coil terminal and a contact terminal. The coil terminal includes a first coil terminal and a second coil terminal. The first coil terminal is electrically connected to the collector of a transistor, and the second coil terminal is electrically connected to a power supply terminal. The contact terminal includes a first contact terminal and a second contact terminal. The first contact terminal is electrically connected to the L terminal of the AC network, and the second contact terminal serves as a controlled AC output terminal.

Images