Electromagnetic immunity method, electronic device, medium and product

Abstract

The application provides an electromagnetic interference resisting method, an electronic device, a medium and a product, which can be applied to the field of electromagnetic interference protection. The method comprises the following steps: in response to determining that a monitoring index value of a to-be-monitored module meets at least one target abnormal condition in a plurality of abnormal conditions, determining that an abnormal event corresponding to the at least one target abnormal condition occurs; and performing a target recovery action corresponding to the abnormal event in a plurality of preset recovery actions.

Description

Technical Field

[0001] This application relates to the field of electromagnetic interference protection, specifically to electromagnetic interference protection technology for electronic circuits, and more specifically to an electromagnetic interference suppression method, electronic equipment, medium, and product. Background Technology

[0002] Electromagnetic interference (EMI) protection technology, as a core means of ensuring the electromagnetic safety of electronic systems, is widely used in industrial control, automotive electronics, medical monitoring, and other scenarios. In deployment scenarios with complex electromagnetic environments, electronic devices can use threshold judgments on monitored indicators. When the monitored indicators exceed preset thresholds, the system can be reset or restarted to ensure the stable operation of the electronic devices. Summary of the Invention

[0003] In view of the above problems, embodiments of this application provide an electromagnetic interference immunity method, electronic device, medium, and product.

[0004] According to a first aspect of this application, an electromagnetic interference suppression method is provided, comprising: in response to determining that a monitoring index value of a module under test satisfies at least one target abnormal condition among a plurality of abnormal conditions, determining that an abnormal event corresponding to the at least one target abnormal condition has occurred, wherein the plurality of abnormal conditions include: the monitoring index value is greater than or equal to a preset index threshold, the duration of the monitoring index value deviating from the normal value is greater than or equal to a preset duration threshold, the recovery time of the monitoring index value returning to the normal value is less than or equal to a preset recovery time threshold, the number of deviations of the monitoring index value from the normal value is greater than or equal to a preset number of deviations threshold, and the normal value is the monitoring index value when the module under test is not subject to electromagnetic interference; executing a target recovery action corresponding to the abnormal event among a plurality of preset recovery actions, wherein the plurality of preset recovery actions include a first preset recovery action, a second preset recovery action, and a third preset recovery action, wherein the first preset recovery action includes re-executing the abnormal operation of the module under test, the second preset recovery action includes resetting the module under test, and the third preset recovery action includes reducing the operating power of the electronic device, wherein the abnormal operation is an operation performed by the module under test within a preset period before the occurrence of the abnormal event.

[0005] According to an embodiment of this application, the method further includes: using a transient suppression circuit to perform transient suppression processing on electromagnetic transient energy entering from the external interface of the electronic device, so as to reduce the probability that the monitoring index value meets the abnormal conditions. The transient suppression circuit is composed of at least one of a series resistor, a filter capacitor, an anti-static device TVS, and a surge protection device TSS.

[0006] According to embodiments of this application, the monitored index values ​​include voltage values, and the abnormal events include a first abnormal event, a second abnormal event, and a third abnormal event. The target recovery action corresponding to the first abnormal event is a first preset recovery action. The first abnormal event corresponds to the following abnormal conditions: the voltage value is greater than or equal to a first preset index threshold and less than a second preset index threshold; the duration of the voltage value deviating from the normal value is greater than or equal to a first preset duration threshold and less than a second preset duration. The target recovery action corresponding to the second abnormal event is a second preset recovery action. The second abnormal event corresponds to the following abnormal conditions: the voltage value is greater than or equal to a second preset index threshold and less than a third preset index threshold; the duration of the voltage value deviating from the normal value is greater than or equal to a second preset duration threshold and less than a third preset duration threshold. The target recovery action corresponding to the third abnormal event is a third preset recovery action. The third abnormal event corresponds to the following abnormal conditions: the voltage value is greater than or equal to a third preset index threshold; the duration of the voltage value deviating from the normal value is greater than or equal to a third preset duration threshold.

[0007] According to an embodiment of this application, the monitoring index value includes the level indication value corresponding to the overvoltage protection trigger signal, and the abnormal events include a fourth abnormal event and a fifth abnormal event. The target recovery action corresponding to the fourth abnormal event is a second preset recovery action. The fourth abnormal event corresponds to the following abnormal conditions: the level indication value is greater than or equal to the preset level indication value, and the number of deviations of the level indication value from the normal value within the preset time window is greater than or equal to a first deviation threshold and less than a second deviation threshold. The target recovery action corresponding to the fifth abnormal event is a third preset recovery action. The fifth abnormal event corresponds to the following abnormal conditions: the level indication value is greater than or equal to the preset level indication value, and the number of deviations of the level indication value from the normal value within the preset time window is greater than or equal to a second deviation threshold.

[0008] According to an embodiment of this application, the monitoring index value includes the status identifier value corresponding to the port negotiation result of the Type-C port, and the abnormal events include a sixth abnormal event and a seventh abnormal event. The target recovery action corresponding to the sixth abnormal event is a first preset recovery action. The sixth abnormal event corresponds to the following abnormal conditions: the status identifier value is equal to the first preset status identifier value, and the recovery time for the status identifier value to return to the normal value is less than or equal to the first preset recovery time threshold. The target recovery action corresponding to the seventh abnormal event is a second preset recovery action. The seventh abnormal event corresponds to the following abnormal conditions: the status identifier value is equal to the first preset status identifier value, and the duration for which the status identifier value deviates from the normal value is greater than or equal to the fourth preset duration.

[0009] According to an embodiment of this application, the abnormal event also includes an eighth abnormal event, and the target recovery action corresponding to the eighth abnormal event is a third preset recovery action. The eighth abnormal event corresponds to the following abnormal conditions: the status identifier value is equal to the second preset status identifier value, and the number of consecutive deviations of the status identifier value from the normal value is greater than or equal to the third deviation number threshold.

[0010] According to an embodiment of this application, the first preset recovery action includes at least one of the following: recording the log corresponding to the abnormal event, adjusting the sampling parameters of the analog-to-digital converter, and enabling the digital filter inside the general-purpose input / output port. The analog-to-digital converter is used to determine the monitoring index value, and the digital filter is used to filter out glitches and interference in the signal received by the module under monitoring. The second preset recovery action includes at least one of the following: resetting the module under monitoring. The third preset recovery action also includes at least one of the following: triggering a system power restart, triggering system hibernation, and limiting system power.

[0011] According to a second aspect of this application, an electromagnetic interference suppression device is provided, comprising: a determining module, configured to determine an abnormal event corresponding to the at least one target abnormal condition in response to determining that a monitoring index value of a module under test satisfies at least one of a plurality of abnormal conditions, the plurality of abnormal conditions including: a monitoring index value greater than or equal to a preset index threshold, a duration of deviation of the monitoring index value from the normal value greater than or equal to a preset duration threshold, a recovery time of the monitoring index value to the normal value less than or equal to a preset recovery time threshold, and a number of deviations of the monitoring index value from the normal value greater than or equal to a preset number of deviations threshold, the normal value being the monitoring index value when the module under test is not subject to electromagnetic interference; and an execution module, configured to execute a target recovery action corresponding to the abnormal event among a plurality of preset recovery actions, the plurality of preset recovery actions including a first preset recovery action, a second preset recovery action, and a third preset recovery action, the first preset recovery action including re-executing the abnormal operation of the module under test, the second preset recovery action including resetting the module under test, and the third preset recovery action including reducing the operating power of the electronic device, the abnormal operation being an operation performed by the module under test within a preset period before the occurrence of the abnormal event.

[0012] According to a third aspect of this application, an electronic device is provided, comprising: one or more processors; and a memory for storing one or more computer programs, wherein the one or more processors execute the one or more computer programs to implement the steps of the method described above.

[0013] According to a fourth aspect of this application, a computer-readable storage medium is also provided, on which a computer program or instructions are stored, wherein the computer program or instructions, when executed by a processor, implement the steps of the above-described method.

[0014] According to a fifth aspect of this application, a computer program product is also provided, comprising a computer program or instructions that, when executed by a processor, implement the steps of the above-described method.

[0015] The electromagnetic interference suppression device provided in this application has at least the following advantages compared with related technologies: By setting abnormal conditions in multiple dimensions, the severity of electromagnetic interference can be comprehensively determined from multiple dimensions, making the triggering of abnormal events more accurate and avoiding missed or false judgments that may be caused by a single judgment dimension. At the same time, recovery actions with different costs are performed according to the type of abnormal event, so that minor abnormal events can be quickly recovered with light recovery actions, while severe abnormal events are protected by system-level protection measures to ensure hardware safety, thereby improving the electromagnetic interference suppression protection effect while ensuring the continuity of system operation. Attached Figure Description

[0016] The above-mentioned contents, other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0017] Figure 1 The illustration shows an application scenario of the electromagnetic interference suppression method and apparatus according to embodiments of this application.

[0018] Figure 2 A flowchart illustrating an electromagnetic interference suppression method according to an embodiment of this application is shown schematically.

[0019] Figure 3 The schematic diagram illustrates the architecture of an electromagnetic interference suppression method according to an embodiment of this application;

[0020] Figure 4A This illustration schematically demonstrates the hierarchical handling process of hardware and software collaboration in the electromagnetic interference suppression method according to an embodiment of this application;

[0021] Figure 4B This illustration schematically shows a circuit board layout and domaining diagram in an electromagnetic interference suppression method according to an embodiment of this application;

[0022] Figure 5 The illustration shows a schematic diagram of the collaboration between the hard failure protection chain and the soft failure recovery chain in the electromagnetic interference suppression method according to an embodiment of this application;

[0023] Figure 6 This schematically illustrates the overall implementation framework of the electromagnetic interference suppression method according to embodiments of this application;

[0024] Figure 7 A flowchart illustrating the multi-level detection and dynamic reset decision-making process in the electromagnetic interference immunity method according to an embodiment of this application is shown schematically.

[0025] Figure 8This schematically illustrates a flowchart of the interaction between a reset command and hardware state in an electromagnetic interference suppression method according to an embodiment of this application;

[0026] Figure 9 The flowchart illustrating the system control hierarchy and master-slave device reset intervention in the electromagnetic interference immunity method according to an embodiment of this application is shown in the schematic diagram.

[0027] Figure 10 The schematic diagram illustrates the circuit architecture for hard failure protection and soft failure observation using a Type-C power supply link as an example;

[0028] Figure 11 The schematic diagram illustrates an electromagnetic interference suppression device 1100 according to an embodiment of this application;

[0029] Figure 12 A block diagram schematically illustrates an electronic device suitable for implementing an electromagnetic interference immunity method according to an embodiment of this application. Detailed Implementation

[0030] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of this application for ease of explanation. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The terms “comprising,” “including,” etc., as used herein indicate the presence of features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0032] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0033] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0034] Figure 1 The illustration shows an application scenario of the electromagnetic interference suppression method and apparatus according to embodiments of this application.

[0035] like Figure 1 As shown, application scenario 100 according to an embodiment of this application may include a first terminal device 101, a second terminal device 102, a database 103, a network 104, and a server 105. The network 104 serves as a medium for providing a communication link between the first terminal device 101, the second terminal device 102, the database 103, and the server 105. The network 104 may include various connection types, such as wired or wireless communication links or fiber optic cables. For example, a user can use the first terminal device 101 and the second terminal device 102 to interact with the server 105 and / or the database 103 through the network 104 to receive or send information, etc.

[0036] The first terminal device 101 and the second terminal device 102 can be electronic devices such as smartphones, wearable devices, personal computers, intelligent voice interaction devices, smart home appliances, intelligent vehicles, in-vehicle terminals, aircraft, unmanned vending terminals, and extended reality devices. Extended reality devices can include virtual reality devices, augmented reality devices, and mixed reality devices. A client application for the target application can be installed and run on the terminal device. This target application can include, but is not limited to, financial transaction applications, payment applications, shopping applications, web browser applications, search applications, instant messaging tools, email clients, and social media platform software (these are just examples). Furthermore, this application embodiment does not limit the form of the target application, including but not limited to applications, mini-programs, etc., installed on the terminal device, and can also be in web page form.

[0037] Server 105 can be a server providing various services, such as a backend management server supporting websites browsed by users using the first terminal device 101 and the second terminal device 102 (this is just an example). The backend management server can analyze and process received user requests and other data, and feed back the processing results (such as web pages, information, or data obtained or generated according to user requests) to the terminal devices. The server can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud computing services such as cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks, and big data. The server can be a backend server for the aforementioned target application, used to provide backend services to the clients of the target application.

[0038] Database 103 is a professional storage system for storing and managing data. It can store various types of data related to the target application, such as user account information, business transaction records, and content resource data. It supports structured, semi-structured, or unstructured data storage and has management capabilities such as data creation, deletion, modification, querying, backup, and recovery. In this application scenario, database 103 can be connected to server 105 via a communication link. Server 105 can retrieve the required data from database 103 for processing based on requests from the first terminal device 101 and the second terminal device 102. It can also synchronously store new data generated by the operations of the first terminal device 101 and the second terminal device 102 into database 103, thereby achieving data persistence and efficient retrieval.

[0039] It should be noted that the electromagnetic interference suppression method provided in the embodiments of this application can generally be executed by server 105 and / or terminal devices 101-102. Accordingly, the electromagnetic interference suppression device provided in the embodiments of this application can generally be installed in server 105 and / or terminal devices 101-102.

[0040] It should be understood that Figure 1 The number of terminal devices, networks, databases, and servers shown is merely illustrative. Depending on implementation needs, any number of terminal devices, networks, databases, and servers can be included.

[0041] Figure 2 A flowchart illustrating an electromagnetic interference suppression method according to an embodiment of this application is shown schematically. Figure 2 As shown, the electromagnetic interference suppression method 200 according to the embodiments of this application may include steps S210 to S220.

[0042] In step S210, in response to determining that the monitoring index value of the module to be monitored meets at least one target abnormal condition among multiple abnormal conditions, an abnormal event corresponding to at least one target abnormal condition is determined to have occurred. The multiple abnormal conditions include: the monitoring index value is greater than or equal to a preset index threshold, the duration of the monitoring index value deviating from the normal value is greater than or equal to a preset duration threshold, the recovery time of the monitoring index value to the normal value is less than or equal to a preset recovery time threshold, the number of deviations of the monitoring index value from the normal value is greater than or equal to a preset number of deviations threshold, and the normal value is the monitoring index value when the module to be monitored is not subject to electromagnetic interference.

[0043] In some embodiments, the module to be monitored may include circuitry or functional units in an electronic device for acquiring or generating monitoring index values ​​related to electromagnetic interference. For example, the module to be monitored may include a temperature monitoring circuit, a clock jitter detection circuit, etc.

[0044] In some embodiments, electromagnetic interference may include events such as electrostatic discharge (ESD), electrical fast transient bursts (EFT), surges, or radiated radio frequency interference (RFI). These ESD events can cause various types of malfunctions in electronic devices. For example, ESD may cause interface disconnections, system restarts, communication errors, or occasional crashes; EFT may cause false alarms from sensors, control loop oscillations, or data link packet loss; surges may cause damage to port devices, power supply anomalies, or protection device activation; and RFI may cause performance degradation, false triggering, or reduced data throughput.

[0045] In some embodiments, the monitoring index value may include a quantified numerical value or logical value collected or generated by the module under monitoring to reflect the state of the module under monitoring. For example, the monitoring index value may include ambient temperature value, clock frequency offset value, etc.

[0046] In some embodiments, abnormal conditions may include preset judgment rules for determining whether the monitored indicator value deviates from the normal state. For example, abnormal events may include soft failure events or hard failure events caused by electromagnetic interference. Soft failure events may include functional degradation, transient errors, and anomalies that can be automatically or manually recovered, such as communication reconnection or device reinitialization. Hard failure events may include irreversible physical damage such as device damage, circuit breakdown, or permanent failure of critical chips. By setting abnormal conditions in multiple dimensions, abnormal changes in monitored indicator values ​​can be detected in a timely manner and corresponding recovery actions can be triggered before electromagnetic interference causes soft or hard failures.

[0047] In some embodiments, the target anomaly condition may include one or more anomaly conditions that are actually satisfied by the current monitoring indicator value among a plurality of anomaly conditions.

[0048] In some embodiments, an abnormal event may include an event determined in response to a monitoring indicator value meeting a target abnormal condition, which is used to trigger a corresponding recovery action.

[0049] In some embodiments, the preset index threshold may include a pre-set reference value or reference logic value used to compare with the monitoring index value to determine whether it deviates from the normal value, such as a preset temperature threshold, a preset frequency offset threshold, etc.

[0050] In some embodiments, the preset duration threshold may include a pre-set time threshold value used to determine whether the duration of the monitoring indicator value deviating from the normal value is too long.

[0051] In some embodiments, the preset recovery time threshold may include a pre-set time threshold value used to determine whether the recovery time of the monitored indicator value from deviation from the normal value back to the normal value is short enough.

[0052] In some embodiments, the preset deviation threshold may include a pre-set threshold value for determining whether the number of times the monitoring indicator value deviates from the normal value within a preset time window is too many.

[0053] In step S220, the target recovery action corresponding to the abnormal event among multiple preset recovery actions is executed. The multiple preset recovery actions include a first preset recovery action, a second preset recovery action, and a third preset recovery action. The first preset recovery action includes re-executing the abnormal operation of the module to be monitored. The second preset recovery action includes resetting the module to be monitored. The third preset recovery action includes reducing the operating power of the electronic device. The abnormal operation is the operation performed by the module to be monitored within a preset time period before the abnormal event occurs.

[0054] In some embodiments, preset recovery actions may include pre-set recovery measures designed for different types of abnormal events.

[0055] In some embodiments, the target recovery action may include a recovery action corresponding to the currently occurring abnormal event from a plurality of preset recovery actions.

[0056] In some embodiments, abnormal operation of the monitored module may include operations related to the acquisition or processing of monitoring indicator values ​​that the monitored module just performed before the abnormal event occurred.

[0057] In some embodiments, the preset time period may include a time window preceding the occurrence of an abnormal event.

[0058] This application provides an electromagnetic interference suppression method. In response to a monitored module's index value satisfying at least one of multiple abnormal conditions, an abnormal event is determined to have occurred, and a target recovery action corresponding to the abnormal event is executed. Thus, by setting abnormal conditions across multiple dimensions, the severity of electromagnetic interference can be comprehensively determined from multiple perspectives, making the triggering of abnormal events more accurate and avoiding missed or false detections that might occur with a single judgment dimension. Simultaneously, recovery actions with different costs are executed according to the type of abnormal event, allowing minor abnormal events to be quickly recovered with lightweight recovery actions, while severe abnormal events are protected by system-level protection measures to ensure hardware safety. This improves the electromagnetic interference suppression effect while maintaining the continuity of system operation.

[0059] In some embodiments, the method further includes: using a transient suppression circuit to perform transient suppression processing on electromagnetic transient energy entering from the external interface of the electronic device, so as to reduce the probability that the monitoring index value meets the abnormal conditions. The transient suppression circuit is composed of at least one of a series resistor, a filter capacitor, an anti-static device TVS, and a surge protection device TSS.

[0060] In some embodiments, the transient suppression circuit may include a protective circuit deployed along the electromagnetic interference energy intrusion path to reduce the impact of interference energy on subsequent circuits.

[0061] In some embodiments, the external interface of an electronic device may include ports in the electronic device for physical connection with external devices or external power supplies. For example, the external interface of an electronic device may include a power input port, a communication signal port, a data transmission port, etc.

[0062] In some embodiments, electromagnetic transient energy may include transient electromagnetic energy that occurs in the form of overvoltage or overcurrent for a very short time, caused by electromagnetic interference events such as electrostatic discharge, electrical fast transient bursts, surges, or radiated radio frequency interference.

[0063] In some embodiments, transient suppression processing may include protective measures such as clamping, energy limiting, and isolation to attenuate, absorb, or bypass electromagnetic transient energy entering from external interfaces to limit it within a safe range.

[0064] In some embodiments, transient suppression processing may include three-stage port protection, which involves clamping, limiting and isolating electromagnetic transient energy entering from an external interface in sequence.

[0065] In some embodiments, the first segment of the three-stage port protection is connector-side clamping. In this segment, a transient voltage suppression (TVS) device or an electrostatic discharge (ESD) protection array deployed on the connector side preferentially absorbs fast transient interference, reducing the peak energy entering the circuit board. The TVS device may include a semiconductor protection device that utilizes the avalanche breakdown effect to clamp high-voltage pulses to a low level in a very short time.

[0066] In some embodiments, the second stage of the three-stage port protection is transmission line-side energy limiting. In this stage, residual transient energy is further attenuated by a common-mode choke (CMC), ferrite bead, or impedance isolation element deployed on the transmission line side. The CMC may include a common-mode inductor wound on a magnetic core to suppress common-mode interference signals; the ferrite bead may include a ferrite bead element made of ferrite material to absorb high-frequency noise energy and convert it into heat dissipation.

[0067] In some embodiments, the third segment of the port three-segment protection is chip-side isolation. In this segment, residual interference is suppressed using a retimer, a multiplexer (MUX), or a physical layer chip (PHY). Simultaneously, resettable nodes are designed to reduce hard damage while providing recovery points for the soft failure recovery chain. Specifically, the retimer may include a chip for clock recovery and signal reconstruction of high-speed signals, used to eliminate jitter and attenuation accumulated during signal transmission; the multiplexer (MUX) may include a signal selection circuit that selects one output from multiple input signals; and the physical layer chip (PHY) may include an interface chip that implements physical layer protocol functions, responsible for signal conversion between the data link layer and the physical transmission medium.

[0068] In some embodiments, the series resistor may include a resistor device connected in series in the signal line or power line to limit the amplitude of the current, such as a carbon film resistor, a metal film resistor, a wire-wound resistor, etc.

[0069] In some embodiments, the filter capacitor may include a capacitor connected in parallel between the signal line or power line and a reference ground to bypass transient interference signals. For example, the filter capacitor may include ceramic capacitors, tantalum capacitors, aluminum electrolytic capacitors, etc.

[0070] In some embodiments, the anti-static device may include a semiconductor protection device that clamps transient high-voltage pulses to a low level using the avalanche breakdown effect or the Zener breakdown effect. For example, the type of anti-static device may include transient voltage suppressor diodes, multilayer varistors, polymer electrostatic suppressors, etc.

[0071] In some embodiments, a surge protection device (TSS) may include an overvoltage protection device for protecting against surge events. For example, the type of surge protection device (TSS) may include a semiconductor discharge tube, a gas discharge tube, a varistor, etc.

[0072] Through the embodiments of this application, the transient suppression circuit deployed at the external interface is used to suppress electromagnetic transient energy entering from the external interface. This can physically attenuate the interference energy and reduce the impact of electromagnetic interference on subsequent circuits from the source. This effectively reduces the probability that the monitoring index value deviates from the normal state due to electromagnetic interference, reduces the triggering frequency of abnormal events, and enables electronic equipment to maintain a stable operating state in complex electromagnetic environments.

[0073] In some embodiments, the monitored index values ​​include voltage values, and the abnormal events include a first abnormal event, a second abnormal event, and a third abnormal event. The target recovery action corresponding to the first abnormal event is a first preset recovery action. The first abnormal event corresponds to the following abnormal conditions: the voltage value is greater than or equal to a first preset index threshold and less than a second preset index threshold, and the duration of the voltage value deviating from the normal value is greater than or equal to a first preset duration threshold and less than a second preset duration threshold. The target recovery action corresponding to the second abnormal event is a second preset recovery action. The second abnormal event corresponds to the following abnormal conditions: the voltage value is greater than or equal to a second preset index threshold and less than a third preset index threshold, and the duration of the voltage value deviating from the normal value is greater than or equal to a second preset duration threshold and less than a third preset duration threshold. The target recovery action corresponding to the third abnormal event is a third preset recovery action. The third abnormal event corresponds to the following abnormal conditions: the voltage value is greater than or equal to a third preset index threshold, and the duration of the voltage value deviating from the normal value is greater than or equal to a third preset duration threshold.

[0074] In some embodiments, the first abnormal event may include a minor abnormal event in which the voltage value deviates from the normal range but the deviation is small and the duration is short.

[0075] In some embodiments, the second abnormal event may include a moderate abnormal event where the voltage value deviates from the normal range to a moderate degree and lasts for a relatively long period.

[0076] In some embodiments, the third abnormal event may include a severe abnormal event in which the voltage value is outside the normal range and the deviation is significant and lasts for a long time.

[0077] In some embodiments, the first preset index threshold may include a voltage reference value used to distinguish between normal and slightly abnormal states. For example, the first preset index threshold may include 105% of the nominal voltage.

[0078] In some embodiments, the second preset index threshold may include a voltage reference value used to distinguish between mild and moderate abnormal states. For example, the second preset index threshold may include 145% of the nominal voltage.

[0079] In some embodiments, the third preset index threshold may include a voltage reference value used to distinguish between moderate and severe abnormal states. For example, the third preset index threshold may include 210% of the nominal voltage.

[0080] In some embodiments, the first preset duration threshold may include a reference value, such as 1 microsecond, for determining whether the duration of the voltage value deviating from the normal value reaches the mild abnormality time threshold.

[0081] In some embodiments, the second preset duration threshold may include a reference value, such as 10 microseconds, for determining whether the duration of the voltage value deviating from the normal value reaches a moderate abnormal time threshold.

[0082] In some embodiments, the third preset duration threshold may include a reference value, such as 100 microseconds, for determining whether the duration of the voltage value deviating from the normal value reaches a severe abnormality time threshold.

[0083] In some embodiments, the voltage value may be the power supply bus input voltage value (the voltage value obtained by sampling the power supply bus voltage on the Type-C port power supply link through an analog-to-digital converter).

[0084] This application's embodiments compare voltage values ​​with multiple preset threshold values ​​and, based on the duration of voltage deviation from normal values, subdivide voltage anomaly events into first, second, and third anomaly events. This allows the system to comprehensively assess the severity of electromagnetic interference based on the degree and duration of voltage amplitude exceeding limits. In this way, mild voltage fluctuations, moderate overvoltage, and severe sustained overvoltage can be accurately distinguished, triggering corresponding recovery actions. This achieves a graded response based on the actual impact of electromagnetic interference, thereby improving electromagnetic interference protection while maintaining system continuity.

[0085] In some embodiments, the monitoring index value includes the level indication value corresponding to the overvoltage protection trigger signal, and the abnormal events include a fourth abnormal event and a fifth abnormal event. The target recovery action corresponding to the fourth abnormal event is a second preset recovery action. The fourth abnormal event corresponds to the following abnormal conditions: the level indication value is greater than or equal to the preset level indication value, and the number of deviations of the level indication value from the normal value within the preset time window is greater than or equal to a first deviation threshold and less than a second deviation threshold. The target recovery action corresponding to the fifth abnormal event is a third preset recovery action. The fifth abnormal event corresponds to the following abnormal conditions: the level indication value is greater than or equal to the preset level indication value, and the number of deviations of the level indication value from the normal value within the preset time window is greater than or equal to a second deviation threshold.

[0086] In some embodiments, the overvoltage protection trigger signal may include a status indication signal output by the overvoltage protection device when it detects that a transient voltage exceeds its protection threshold, such as a level signal output by the fault indication pin of the overvoltage protection device.

[0087] In some embodiments, the level indication value may include a numerical value obtained by the system after sampling or reading the overvoltage protection trigger signal, which characterizes the level state of the signal. For example, the level indication value may include a logic value read from the input / output port, such as the value (1) corresponding to a logic high level or the value (0) corresponding to a logic low level.

[0088] In some embodiments, the fourth abnormal event may include a moderate abnormal event in which the overvoltage protection trigger signal is triggered and the number of deviations is relatively small.

[0089] In some embodiments, the fifth abnormal event may include a severe abnormal event in which the overvoltage protection trigger signal is repeatedly triggered within a short period of time.

[0090] In some embodiments, the preset level indication value may include a reference value used for comparison with the level indication value to determine whether the overvoltage protection trigger signal has been triggered. For example, the preset level indication value may include a preset logic value (such as 1) that characterizes the overvoltage protection being triggered.

[0091] In some embodiments, a preset time window may include a reference value for defining a time range within which the deviation count is performed, and the number of times the level indicator value deviates from the normal value is counted within this time window. For example, the preset time window may include 1 microsecond, 10 microseconds, 100 microseconds, etc.

[0092] In some embodiments, the first deviation number threshold may include a reference value, such as 1 time, 2 times, 3 times, etc., for determining whether the number of deviations of the level indication value within a preset time window reaches the medium abnormal number threshold.

[0093] In some embodiments, the second deviation number threshold may include a reference value for determining whether the number of deviations of the level indication value within a preset time window reaches the severe abnormality number threshold. The second deviation number threshold is greater than the first deviation number threshold, such as 2 times, 3 times, 4 times, etc.

[0094] By comparing the level indication value of the overvoltage protection trigger signal with the preset level indication value and combining it with the deviation count within the preset time window, it is possible to distinguish between single-trigger accidental events and repeated events triggered repeatedly within a short period of time based on the number of deviations. This avoids the problem that the persistence of interference cannot be determined by simply detecting the level change itself. It enables the accurate differentiation between moderate occasional overvoltage events and severe repeated overvoltage events, thereby improving the electromagnetic interference protection effect while ensuring the continuity of system operation.

[0095] In some embodiments, the monitoring index value includes the status identifier value corresponding to the port negotiation result of the Type-C port, and the abnormal events include a sixth abnormal event and a seventh abnormal event. The target recovery action corresponding to the sixth abnormal event is a first preset recovery action. The sixth abnormal event corresponds to the following abnormal conditions: the status identifier value is equal to the first preset status identifier value, and the recovery time for the status identifier value to return to the normal value is less than or equal to the first preset recovery time threshold. The target recovery action corresponding to the seventh abnormal event is a second preset recovery action. The seventh abnormal event corresponds to the following abnormal conditions: the status identifier value is equal to the first preset status identifier value, and the duration for which the status identifier value deviates from the normal value is greater than or equal to the fourth preset duration.

[0096] In some embodiments, a Type-C port may include a physical connection port conforming to the USB Type-C interface standard for power supply and data transfer.

[0097] In some embodiments, the port negotiation result may include the negotiation status of power supply parameters or functional mode configuration reached between the Type-C port and the connected external device through protocol interaction, such as power supply voltage negotiation result, current level negotiation result, data transmission mode negotiation result, etc.

[0098] In some embodiments, the status identifier value may include an identifier value that characterizes the logical state of the port negotiation result, such as a negotiation success status identifier value, a connection loss status identifier value, or a negotiation failure status identifier value.

[0099] In some embodiments, the sixth abnormal event may include a lightweight abnormal event that quickly recovers after a brief loss of Type-C port connectivity.

[0100] In some embodiments, the seventh abnormal event may include a moderate abnormal event in which the Type-C port connection status is lost and persists for an extended period of time.

[0101] In some embodiments, the first preset status identifier value may include an identifier value that indicates the loss of the Type-C port connection status, such as a preset encoded value in the status register that indicates "port not connected" or "connection has been lost".

[0102] In some embodiments, the first preset recovery time threshold may include a time threshold value for determining whether the recovery time of the status identifier value from deviating from the normal value to the normal value is short enough, such as 1 microsecond, 10 microseconds, 100 microseconds, etc.

[0103] In some embodiments, the fourth preset duration may include a reference value, such as 2 milliseconds, 3 milliseconds, 4 milliseconds, etc., for determining whether the duration of the status indicator value deviating from the normal value reaches the medium abnormal time threshold.

[0104] By comparing the status flag value corresponding to the port negotiation result of the Type-C port with a preset status flag value, and combining the recovery time for the status flag value to return to the normal value and the duration of deviation from the normal value—two time dimensions—it is possible to accurately distinguish between instantaneous connection jitter and continuous disconnection. This avoids the problem of failing to determine the actual impact of connection loss simply by detecting changes in the status flag value itself. It allows instantaneous connection jitter and continuous connection disconnection to be accurately identified as different levels of abnormal events, thereby improving the accuracy of port connection status determination while reducing the impact of unnecessary recovery actions on port communication.

[0105] In some embodiments, the abnormal event also includes an eighth abnormal event, and the target recovery action corresponding to the eighth abnormal event is a third preset recovery action. The eighth abnormal event corresponds to the following abnormal conditions: the status identifier value is equal to the second preset status identifier value, and the number of consecutive deviations of the status identifier value from the normal value is greater than or equal to the third deviation number threshold.

[0106] In some embodiments, the eighth exception event may include a critical exception event in which port negotiation on the Type-C port repeatedly fails.

[0107] In some embodiments, the second preset status flag value may include a flag value indicating a port negotiation failure of the Type-C port, such as a preset encoded value in the status register indicating "negotiation error" or "power capability negotiation timeout".

[0108] In some embodiments, the third deviation threshold may include a reference value, such as 3 times, 4 times, 5 times, etc., for determining whether the number of times the status identifier value deviates continuously from the normal value reaches the severe abnormality threshold.

[0109] Table 1 schematically illustrates the definition of monitoring index values ​​according to embodiments of this application.

[0110] Table 1 Definition of Monitoring Indicator Values

[0111]

[0112] As shown in Table 1, different monitoring index values ​​correspond to different sources and classification thresholds. The power supply bus input voltage value (VBUS_IN) originates from the analog-to-digital converter (ADC) channel, which is connected to the power supply bus (VBUS) voltage divider resistor. The first abnormal event belongs to the first severity level (L1), with a threshold of voltage value greater than 110% of the nominal value for more than one microsecond; the second abnormal event belongs to the second severity level (L2), with a threshold of voltage value greater than 150% of the nominal value for more than ten microseconds; the third abnormal event belongs to the third severity level (L3), with a threshold of voltage value greater than 200% of the nominal value for more than one hundred microseconds, and a filtering time of ten microseconds based on the sampling rate.

[0113] The overvoltage protection trigger signal's corresponding level indication value (OVP_FLAG) originates from a general purpose input / output (GPIO) port, which is connected to the fault indication (FAULT) pin of the overvoltage protection (OVP) device. The fourth abnormal event belongs to the second severity level (L2), with a threshold of the level indication value equal to a preset level indication value. The fifth abnormal event belongs to the third severity level (L3), with a threshold of the level indication value being equal to the preset level indication value three or more times within a preset time window, where the preset time window is one hundred microseconds.

[0114] The port connection status (CC_STATUS) is derived from the power transfer controller (PD) status register. The sixth anomaly belongs to the first severity level (L1), with a threshold of less than or equal to 100 microseconds for the recovery time after the status flag value equals the preset code value indicating connection loss. The seventh anomaly belongs to the second severity level (L2), with a threshold of more than or equal to 2 milliseconds for the duration of the deviation from the preset code value indicating connection loss. The eighth anomaly belongs to the third severity level (L3), with a threshold of more than or equal to three consecutive deviations from the preset code value indicating negotiation failure.

[0115] Table 2 schematically illustrates the correspondence between monitoring index values ​​and graded treatment state machines according to embodiments of this application.

[0116] Table 2. Correspondence between monitoring indicator values ​​and the tiered response status machine

[0117]

[0118] As shown in Table 2, for the monitoring indicator value of the power supply bus input voltage (VBUS_IN), the first abnormal event belongs to the first severity level (L1), and the corresponding target recovery action is a light recovery action, including logging and adjusting the analog-to-digital converter (ADC) sampling parameters; the second abnormal event belongs to the second severity level (L2), and the corresponding target recovery action is a module reset action, including resetting the power transfer (PD) controller and reinitializing the Type-C port connection; the third abnormal event belongs to the third severity level (L3), and the corresponding target recovery action is a system protection action, including triggering a system power restart or triggering system hibernation. For the monitoring indicator value of the overvoltage protection trigger signal corresponding to the level indication value (OVP_FLAG), the fourth abnormal event belongs to the first severity level, and the corresponding target recovery action is a light recovery action, including logging and enabling the digital filter inside the general purpose input / output port; the fifth abnormal event belongs to the second severity level, and the corresponding target recovery action is a module reset action, including resetting the power transfer controller and reinitializing the Type-C port connection; the sixth abnormal event belongs to the third severity level, and the corresponding target recovery action is a system protection action, including limiting power or system restart. For the monitoring indicator value (CC_STATUS) corresponding to the port negotiation result of the Type-C port, the seventh abnormal event belongs to the first severity level, and the corresponding target recovery action is a light recovery action, including ignoring the brief disconnection and waiting for self-recovery; the eighth abnormal event belongs to the second severity level, and the corresponding target recovery action is a module reset action, including resetting the power transmission controller and reinitializing the Type-C port connection; the ninth abnormal event belongs to the third severity level, and the corresponding target recovery action is a system protection action, including downgrading to basic functions or system restart.

[0119] In some embodiments, the lightweight recovery action corresponding to the first severity level (L1), the module reset action corresponding to the second severity level (L2), and the system protection action corresponding to the third severity level (L3) are respectively classified as the first preset recovery action, the second preset recovery action, and the third preset recovery action. Specifically, logging, adjusting analog-to-digital converter sampling parameters, enabling the digital filter inside the general purpose input / output port, ignoring brief disconnections, and waiting for self-recovery are classified as the first preset recovery actions. Resetting the power transfer controller and reinitializing the Type-C port connection are classified as the second preset recovery actions. Triggering a system power restart, triggering system hibernation, limiting power, degrading to basic functions, and system restart are classified as the third preset recovery actions.

[0120] In some embodiments, a graded treatment state machine refers to a state transition logic that determines the corresponding severity level based on the abnormal conditions met by the monitoring index values, and drives the system to execute the corresponding preset recovery action based on the severity level.

[0121] Table 3 schematically illustrates the firmware interface definitions according to embodiments of this application.

[0122] Table 3 Firmware Interface Definitions

[0123]

[0124] As shown in Table 3, the observation point for the overvoltage protection device (OVP) is the fault indication pin (FLT), with a signal type of general purpose input / output (GPIO) input mode, connected to the first GPIO pin (EC_GPIOx) of the embedded controller, used to output a low level when overcurrent or overvoltage protection is triggered. The first observation point for the power transfer controller (PD) is the alarm pin (ALERT#), with a signal type of general purpose input / output (GPIO) input mode, connected to the second GPIO pin (EC_GPIOz) of the embedded controller, used to pull low when an internal event occurs, including connection status changes or errors. The second observation point for the power transfer controller is the internal integrated circuit bus (I2C), with a signal type of internal integrated circuit bus slave mode (I2C slave), connected to the internal integrated circuit bus interface (EC_I2Cx) of the embedded controller, used to read and write the power transfer controller's status register and control register. The observation point of the power monitoring component is the power supply bus input voltage (VBUS_IN), the signal type is the analog-to-digital converter channel (ADC channel), which is connected to the analog-to-digital converter input channel (EC_ADC0) of the embedded controller, and is used to monitor the input voltage after voltage division by the voltage divider resistor.

[0125] In some embodiments, the Fault Indication Pin (FLT) may include a pin on the overvoltage protection device for outputting a fault indication signal. When this pin outputs a low level, it indicates that the overvoltage protection device has triggered a protection action. The Alarm Pin (ALERT#) may include a pin on the power transmission controller for outputting an alarm signal. When this pin is pulled low, it indicates that an event requiring firmware intervention has occurred within the power transmission controller. The status register of the power transmission controller may include registers within the power transmission controller for storing connection status information and negotiation result information. The embedded controller reads the status register value as a monitoring indicator value via the internal integrated circuit bus (I2C).

[0126] In some embodiments, the aforementioned firmware interface forms the physical basis of the hardware-software interaction layer and the software monitoring layer. The fault indication pin (FLT) of the overvoltage protection device and the alarm pin (ALERT#) of the power transfer controller report hardware anomalies to the embedded controller in real time via a general-purpose input / output port. The embedded controller reads the status register value of the power transfer controller via the internal integrated circuit bus (I2C), acquires the power supply bus input voltage value (VBUS_IN) via the analog-to-digital converter channel, and determines the severity level of the anomaly based on judgment conditions. The embedded controller also configures the hardware detection threshold in reverse via the internal integrated circuit bus or general-purpose input / output port, enabling bidirectional information exchange between hardware and software.

[0127] By comparing the status identifier value with the second preset status identifier value and combining the number of times the status identifier value deviates from the normal value, the health status of the port communication link can be assessed based on the number of consecutive failures. This avoids the overreaction problem of triggering serious protection actions based on a single negotiation failure, and enables the accurate differentiation between occasional negotiation failures and continuous communication faults. Thus, while ensuring the stability of port communication, it also takes into account the timely response to serious faults.

[0128] In some embodiments, the first preset recovery action includes at least one of the following: recording the log corresponding to the abnormal event, adjusting the sampling parameters of the analog-to-digital converter, and enabling the digital filter inside the general-purpose input / output port. The analog-to-digital converter is used to determine the monitoring index value, and the digital filter is used to filter out glitches and interference in the signal received by the module under monitoring. The second preset recovery action includes at least one of the following: resetting the module under monitoring. The third preset recovery action also includes at least one of the following: triggering a system power restart, triggering system hibernation, and limiting system power.

[0129] In some embodiments, the log corresponding to an abnormal event may include data records recorded by the system when the abnormal event is detected, which describe the key characteristics of the abnormal event. For example, the log content may include the time of occurrence of the abnormal event, the type of abnormal condition met, and the trajectory of changes in monitoring indicator values ​​before and after the occurrence of the abnormality.

[0130] In some embodiments, an analog-to-digital converter (ADC) may include electronic devices that convert continuously varying analog voltage signals into discrete digital quantities. For example, an ADC may include a successive approximation ADC, an integrating ADC, and the like.

[0131] In some embodiments, the analog-to-digital converter (ADC) sampling parameters may include configurable parameters that control the ADC's operating mode, such as sampling rate, sampling accuracy, and sampling window duration.

[0132] In some embodiments, a general-purpose input / output port may include a general-purpose interface pin on the processor or controller that can be configured to input or output modes.

[0133] In some embodiments, the digital filter inside the general purpose input / output port may include a filtering circuit integrated within the general purpose input / output port hardware to filter out glitches and interference in the signal received by the module under monitoring.

[0134] In some embodiments, glitches in the signal received by the module under monitoring may include transient voltage spikes or logic state jitters that are superimposed on the normal signal and have a very short duration.

[0135] In some embodiments, resetting the module under monitoring may include an operation that restores the module under monitoring to its initial working state.

[0136] In some embodiments, limiting system power may include reducing the operating power of electronic devices or some of their functional modules to reduce the risk of further conduction or diffusion of transient energy, such as reducing the charging power of power supply ports, reducing the operating frequency of processors, or degrading system functions to basic functions.

[0137] In some embodiments, the selection of preset recovery actions can be based on a graded handling strategy, which divides abnormal events into three levels according to their severity, with each level corresponding to different triggering conditions, and selects different types of recovery actions.

[0138] Table 4 schematically illustrates a library of hierarchical processing actions according to embodiments of this application.

[0139] Table 4. Tiered Disposal Action Library

[0140]

[0141] As shown in Table 4, the triggering conditions for the first severity level (L1) include a sudden increase in the link error check count (CRC) or a brief timeout. The corresponding recovery action is the first preset recovery action, with the goal of rapid recovery without the user noticing. The triggering conditions for the second severity level (L2) include the disconnection of the monitored module or training failure. The corresponding recovery action is the second preset recovery action, with the goal of prioritizing system stability. The triggering conditions for the third severity level (L3) include power failure of the power transfer controller (PD) or overcurrent protection (OCP) triggering. The corresponding recovery action is the third preset recovery action, with the goal of protecting hardware and data security and resetting the system as a last resort.

[0142] In some embodiments, the goal of the tiered handling strategy is to allow recoverable anomalies corresponding to the first and second severity levels, provided that no hard failure has occurred, and to use system reset as a last resort only at the third severity level. This tiered handling strategy involves uniformly collecting status information from multiple observations, classifying and grading them, and then selecting the least costly recovery action from preset recovery actions.

[0143] In some embodiments, the observations may include specific indicators selected from a plurality of monitoring indicator values ​​for classifying abnormal events and selecting recovery actions.

[0144] In some embodiments, the observations used for classification and grading may include at least one of the following: a Power Good signal (PG) to indicate whether the power rail is in place or has dropped; a Fault Flag signal (FAULT) to indicate whether overcurrent, overvoltage, or overtemperature protection has been triggered; a Power Transfer Controller Alert signal (PD Alert) to notify the Type-C port of connection status, fault, or negotiation event; a Hot-Plug Detection signal (HPD) to indicate a hot-plug or interruption request for the display interface and trigger link retraining; a Link Error Check Count (CRC) to detect bit error conditions in high-speed signal links; and a Hardware Error Log (WHEA) to record hardware error information related to system reset.

[0145] In some embodiments, the method further includes: establishing a mapping relationship between test items and abnormal conditions, abnormal events and preset recovery actions to form a test mapping matrix.

[0146] In some embodiments, test items may include standard electromagnetic interference test types injected into electronic devices during electromagnetic immunity verification. For example, test items may include at least one of electrostatic discharge immunity test (IEC61000-4-2 ESD), electrical fast transient / burst immunity test (IEC61000-4-4 EFT), surge immunity test (IEC61000-4-5 Surge), and radiated radio frequency immunity test (IEC61000-4-3 Radiated RF).

[0147] In some embodiments, the test mapping matrix may include a mapping table that associates different electromagnetic interference test items, the corresponding level conditions for each test item, expected performance, log fields, hardware protection strategies, and software recovery strategies.

[0148] In some embodiments, rating conditions may include the test parameters used in the verification process for each test item. For example, the rating conditions for electrostatic discharge immunity test (IEC61000-4-2 ESD) may include a preset contact discharge voltage or a preset air discharge voltage, and the rating conditions for surge immunity test (IEC61000-4-5 Surge) may include a preset voltage amplitude and a preset source impedance.

[0149] In some embodiments, the corresponding hardware strategy may include hardware protection measures adopted for different test items. For example, the corresponding hardware strategy may include transient voltage suppression device protection (TVS) and return path design, inductor-capacitor filtering (LC filtering) and electronic fuse protection (eFuse), varistor protection (MOV) and electronic fuse protection, or shielding and filtering.

[0150] In some embodiments, the corresponding software strategy may include software recovery strategies adopted for different test items. For example, the corresponding software strategy may include a recovery strategy for a first severity level or a second severity level, jitter filtering and rollback, a safety shutdown for a third severity level, or adaptive threshold adjustment. Jitter filtering may include de-jittering the input signal using a software algorithm to filter out transient fluctuations of extremely short duration, and rollback may include restoring the system state to a known normal state before the abnormal event occurred.

[0151] Table 5 schematically illustrates the test mapping matrix according to an embodiment of this application.

[0152] Table 5 Test Mapping Matrix

[0153]

[0154] As shown in Table 5, the electrostatic discharge immunity test (IEC61000-4-2 ESD) has a preset contact discharge voltage or preset air discharge voltage. The expected performance is non-damaging and allows triggering of recoverable anomalies at severity level 1 or 2. Log fields include the ESD count (ESD_cnt) and port reset count (port_rst_cnt). The corresponding hardware strategies are transient voltage suppression device (TVS) protection and return path design, while the corresponding software strategies are recovery strategies at severity level 1 or 2. The electrical fast transient / burst immunity test (IEC61000-4-4 EFT) has a preset voltage amplitude and preset frequency. The expected performance is non-crashing and functionally recoverable. Log fields include the undervoltage count (brownout_cnt). The corresponding hardware strategies are inductor-capacitor filtering (LC filtering) and electronic fuse protection (eFuse), while the corresponding software strategies are jitter filtering and rollback. The surge immunity test (IEC 61000-4-5 Surge) has preset voltage amplitude and source impedance conditions, and is expected to perform without damage and recover through controlled shutdown. Log fields include the overvoltage protection trigger count (ovp_trip_cnt). The corresponding hardware strategies are varistor protection (MOV) and electronic fuse protection (eFuse), and the corresponding software strategy is a safe shutdown at severity level 3. The radiated radio frequency immunity test (IEC 61000-4-3 Radiated RF) has preset field strength conditions, and is expected to perform with acceptable service degradation. Log fields include RF degradation time (rf_degrade_time), and the corresponding hardware strategies are shielding and filtering, and the corresponding software strategy is adaptive threshold adjustment.

[0155] In some embodiments, the method further includes: establishing a mapping relationship between disturbance types and common injection paths, typical soft failure behaviors, typical hard failure behaviors, hardware countermeasures and software countermeasures, forming a failure classification mapping matrix.

[0156] In some embodiments, common injection paths may include the main physical channel through which electromagnetic interference energy enters the electronic device. For example, common injection paths may include ports, housings, cables, power harnesses, power inlets, or spatial couplings.

[0157] In some embodiments, hardware countermeasures may include protective measures taken in a hard failure protection chain for different types of disturbances. For example, hardware countermeasures may include at least one of the following: transient voltage suppression devices (TVS) or electrostatic discharge protection arrays (ESD arrays), return path design, isolation, inductor-capacitor filtering (LC filtering), electronic fuse protection (eFuse), segmented power supply, varistor protection (MOV), gas discharge tube protection (GDT), overcurrent protection (OCP), overvoltage protection (OVP), shielding, filtering, or grounding.

[0158] In some embodiments, software countermeasures may include recovery measures taken in the soft failure recovery chain for different types of disturbances. For example, software countermeasures may include at least one of error detection, port reconstruction, abnormal reset attribution, jitter filtering, timeout rollback, degraded operation, safe shutdown, logging, gradual recovery, adaptive threshold adjustment, or disturbance rejection scheduling rate limiting. Abnormal reset attribution may include source analysis of the cause of the system reset to distinguish whether the reset is caused by electromagnetic interference or other system faults. Gradual recovery may include gradually restoring the normal operating state of each module in a preset order after safe shutdown to avoid secondary impacts caused by simultaneous restoration.

[0159] Table 6 schematically illustrates the failure classification mapping matrix according to an embodiment of this application.

[0160] Table 6 Failure Classification Mapping Matrix

[0161]

[0162] As shown in Table 6, common injection paths for electrostatic discharge (ESD) disturbances are ports, chassis, or cables. Typical soft failures manifest as disconnections, false triggers, or system crashes, while typical hard failures manifest as input / output interface (IO) damage or latch-up. Corresponding hardware countermeasures include transient voltage suppression devices (TVS) or electrostatic discharge protection arrays (ESD arrays), return path design, and isolation. Corresponding software countermeasures include error detection, port reconstruction, and abnormal reset attribution. Common injection paths for electrical fast transient / burst (EFT / Burst) disturbances are power supply harnesses. Typical soft failures manifest as sensor jitter or communication packet loss, while typical hard failures manifest as power integrated circuit (IC) damage. Corresponding hardware countermeasures include inductor-capacitor filtering (LC filtering), electronic fuse protection (eFuse), and segmented power supply. Corresponding software countermeasures include jitter filtering, timeout rollback, and degraded operation. Surge disturbances commonly originate from power supply inputs. Typical soft failures manifest as resets or system shutdowns, while typical hard failures involve breakdowns in power supply or interface devices. Corresponding hardware countermeasures include varistor protection (MOV), gas discharge tube protection (GDT), transient voltage suppressor (TVS), overcurrent protection (OCP), overvoltage protection (OVP), and isolation. Corresponding software countermeasures include safe shutdown, logging, and gradual recovery. Radiated RF disturbances commonly originate from spatial coupling or cables. Typical soft failures manifest as performance degradation or false interruptions, while typical hard failures are extremely rare. Corresponding hardware countermeasures include shielding, filtering, and grounding, while corresponding software countermeasures include adaptive threshold adjustment and disturbance rejection scheduling rate limiting.

[0163] In some embodiments, the test mapping matrix and the failure classification mapping matrix together constitute a closed-loop verification matrix. During electromagnetic interference (EMI) verification, for each test item injected in the laboratory, the closed-loop verification matrix can output the following information: whether a preset observation was triggered; which level of recovery action was performed; whether the verification result is pass or fail; and the recurrence threshold. If the verification result is fail, the rectification point of the hard failure protection chain or the strategy parameters of the soft failure recovery chain are located based on the output information of the closed-loop verification matrix. The recurrence threshold may include the maximum number of times the same type of abnormal event is allowed to occur repeatedly within a preset time range; when the number of recurrences exceeds this threshold, a downgrade or mode-limiting operation is triggered.

[0164] In this application, recovery actions are categorized into three types based on their impact on the system. Light recovery actions, such as logging, adjusting sampling parameters, or enabling filters, can address minor anomalies without interrupting normal system operation. Moderate recovery actions restore partial functionality by resetting the monitored module. Severe recovery actions ensure hardware safety by triggering system power restarts, system hibernation, or limiting system power. This approach achieves recovery measures with varying costs based on the severity of the abnormal event, avoiding the impact of system resets triggered by minor anomalies on continuous equipment operation. Thus, it improves electromagnetic interference protection while maintaining system continuity.

[0165] Figure 3 The schematic diagram illustrates the architecture of an electromagnetic interference suppression method according to an embodiment of this application.

[0166] like Figure 3 As shown, the architecture includes input / output ports (I / O ports), protection devices, transmission devices, retimers or hubs, and system-on-a-chip (SOC) connected in sequence. The connection between the modules is represented by a solid black triangle pointing to the right, which indicates the conduction path of electromagnetic interference energy after entering the electronic device from the external interface.

[0167] In this architecture, protection against electromagnetic interference is achieved through the coordinated efforts of the following five functional layers:

[0168] Hardware protection layers, deployed at the entry points of electromagnetic interference sources into the equipment (such as connectors and interface terminals), are used to attenuate and clamp transient overvoltages or overcurrents, preventing interference energy from entering the equipment and damaging core components. Typical protective devices deployed in the hardware protection layer include series resistors, filter capacitors, anti-static devices, and surge protectors.

[0169] The hardware tolerance layer includes components that inherently possess normal circuit functions in signal conditioning, power management, and protocol processing, such as re-drivers, re-timers, metal-oxide-semiconductor transistors, or specific integrated circuits. These components simultaneously assume a secondary protection role along the electromagnetic interference path, enhancing the tolerance of local circuits to residual interference through their own electrical characteristics or integrated protection structures.

[0170] The software monitoring layer, deployed at the system firmware or driver level, collects various abnormal indication signals and protocol status information from the hardware in real time. Through state machines and decision logic, it dynamically triggers appropriate software fault tolerance or recovery strategies. For example, based on the duration and type of interference, it executes tiered response measures such as task switching, data backup, or partial functional module reset.

[0171] The hardware-software interaction layer serves as a bidirectional communication and control interface between hardware and software. The hardware reports abnormal events to the software in real time through status registers, dedicated interrupt lines, and sideband signals. The software dynamically sets hardware detection thresholds, enables specific protection circuits, or adjusts response parameters through configuration registers, general-purpose input / output ports, internal integrated circuit buses, or serial peripheral interface buses, thereby achieving an integrated hardware-software adaptive control mechanism.

[0172] The system control layer, as the scheduling center of the overall anti-interference strategy, integrates multiple detection circuits, such as transient voltage detection circuits, current surge detection circuits, and clock frequency drift detection circuits. It performs fusion judgment and decision-making on the abnormal information reported by each layer, coordinates the timing and action of hardware protection, hardware tolerance and software response, and realizes full-process management from interference perception to system recovery.

[0173] When electromagnetic interference such as electrostatic discharge, electrical fast transient bursts, or surges occurs, the hardware protection layer prioritizes limiting the interference energy from entering sensitive areas. The software monitoring layer integrates multi-dimensional observations in key integrated circuits such as power transmission controllers and embedded controllers, including chip anomaly warnings, port enumeration status, hot-plug detection signals, link training status, hardware error logging, and reset source determination. It then selects the least-cost recovery action, such as renegotiation, re-enumeration, link retraining, hub or timer re-reset, downgrading or disabling the fourth-generation universal serial bus or displaying port alternation mode, and safe reset. Through the collaborative mechanism of these five functional layers, layered, time-based, and category-based processing of electromagnetic interference is achieved.

[0174] Figure 4A This illustration schematically demonstrates the hierarchical processing flow of hardware and software collaboration in the electromagnetic interference immunity method according to an embodiment of this application.

[0175] like Figure 4AAs shown, this tiered handling process can include seven sequentially executed stages: injection path identification, zone / domain segmentation, failure protection chain, failure monitoring point, event classification and grading, collaborative decision-making, and verification and solidification. During the execution of these seven stages, each stage is mapped to a module in the hardware link through control points. The hardware link includes sequentially connected input / output ports (I / O ports), protection devices, transmission devices, retimers or hubs, and a system-on-a-chip (SOC), representing the conduction path of electromagnetic interference energy after entering the electronic device from an external interface. Control points 1 to 5 correspond one-to-one with the five hardware modules mentioned above, identifying the position of each module in the entire protection link. Different combinations of control points can form protection strategies with varying scopes and methods. Among them, control points 1 and 2 correspond to structural or electronic combined hardware protection, control points 2 and 3 correspond to electronic balanced hardware protection, control points 2, 3 and 4 correspond to combined protection of "software against soft and hardware against hardware", control points 4 and 5 correspond to restart protection based on soft failure monitoring, and control points 1 to 5 together correspond to collaborative protection based on "hard failure chain and soft failure chain".

[0176] In some embodiments, the injection path identification stage may include a processing stage for identifying the injection path of electromagnetic interference. For example, the injection path may include port injection, power inlet injection, or chassis coupling injection.

[0177] In some embodiments, the partitioning and zoning stage may include a process stage in which the electronic device is divided into different functional regions based on energy flow and isolation boundaries, and corresponding protection strategies are applied to each region. For example, the electronic device may be divided into an energy domain, an isolation domain, and a sensitive domain. The energy domain is the area where the port or power supply input is located, and it is the main injection point of disturbance energy; the isolation domain is set between the energy domain and the sensitive domain, and it undertakes path selection, segmented power supply, buffering, or isolation functions to decouple the energy domain from the sensitive domain; the sensitive domain is the area containing system-on-a-chip, embedded controller, high-speed signal link, or storage unit, and it is the area where soft and hard failures are most concentrated.

[0178] In some embodiments, the failure protection chain stage may include a processing stage that protects against electromagnetic interference through a hard failure protection chain. For example, transient energy may be suppressed by at least one of clamping, isolation, and energy limiting.

[0179] In some embodiments, the failure monitoring point stage may include a processing stage for acquiring observation signals through soft failure monitoring points. For example, the observation signals may include at least one of a Power Good (PG) signal, a Hot-Plug Detection (HPD) signal, and a Hardware Error Log (WHEA).

[0180] In some embodiments, the event classification and grading phase may include a processing phase for classifying and grading abnormal events according to their severity. For example, abnormal events may be graded according to a first severity level (L1), a second severity level (L2), and a third severity level (L3).

[0181] In some embodiments, the first severity level may include a lightweight anomaly level where the abnormal event has a minor impact on system operation. When assessed as the first severity level, the corresponding target recovery action is a first preset recovery action.

[0182] In some embodiments, the second severity level may include an intermediate severity level, where the impact of the abnormal event on system operation is moderate. When assessed as the second severity level, the corresponding target recovery action is a second preset recovery action.

[0183] In some embodiments, the third severity level may include a heavyweight anomaly level where the abnormal event has a significant impact on system operation. When assessed as the third severity level, the corresponding target recovery action is the third preset recovery action.

[0184] In some embodiments, the collaborative decision-making phase may include a processing phase that selects a recovery action based on the principle of least cost action. For example, the recovery action with the least impact on system operation can be selected from a preset set of recovery actions.

[0185] In some embodiments, the verification and solidification phase may include a process of verifying and solidifying the protection strategy through a test mapping matrix and parameter set. For example, the verified protection parameters may be solidified into a parameter set that can be reused across different machine models.

[0186] In some embodiments, a hardware link may include input / output ports (I / O ports), protection devices, transmission devices, retimers or hubs, and system-on-a-chip (SOC) connected in sequence, representing the conduction path of electromagnetic interference energy after entering the electronic device from an external interface.

[0187] In some embodiments, control points may include identifiers that correspond one-to-one with each module in the hardware link, used to identify the stage of each module in the entire protection link. For example, control point 1 corresponds to an input / output port (I / O port), control point 2 corresponds to a protection device, control point 3 corresponds to a transmission device, control point 4 corresponds to a retimer or hub, and control point 5 corresponds to a system-on-a-chip (SOC).

[0188] Figure 4B The schematic diagram illustrates the circuit board layout and domaining in the electromagnetic interference suppression method according to an embodiment of this application.

[0189] like Figure 4B As shown, the circuit board is marked with five functional areas, arranged sequentially according to the conduction path of electromagnetic interference energy entering from the external interface. Area 1 (marked by a circle containing the number 1) corresponds to the input / output ports (I / O ports), located in the physical interface area at the edge of the circuit board. Area 2 (marked by a circle containing the number 2) corresponds to the protection devices, located in the hardware protection component area adjacent to the interface. Area 3 (marked by a circle containing the number 3) corresponds to the transmission devices, located in the signal buffer or drive component area. Area 4 (marked by a circle containing the number 4) corresponds to the retimer or hub, located in the signal retimer or hub chip area. Area 5 (marked by a circle containing the number 5) corresponds to the system-on-a-chip (SOC), located in the system-on-a-chip area on the right side of the circuit board.

[0190] In this embodiment of the application, the energy flow direction and isolation boundary are defined by dividing the area into a domain, the whole machine is divided into an energy domain, an isolation domain and a sensitive domain.

[0191] In some embodiments, the energy domain may include the area where the port or power supply inlet is located, which is the main injection point of disturbance energy. For example, the energy domain may include the input / output port (I / O port) area and the protection device area, namely area 1 and area 2.

[0192] In some embodiments, the isolation domain may include a region disposed between the energy domain and the sensitive domain, which performs path selection, segmented power supply, buffering, or isolation functions to decouple the energy domain from the sensitive domain. For example, the isolation domain may include a transmission device region, i.e., region 3.

[0193] In some embodiments, the sensitive domain may include an area containing a system-on-a-chip (SOC), an embedded controller (EC), a high-speed signal link, or a memory unit, which is the area where soft and hard failures are most concentrated. For example, the sensitive domain may include a retimer or hub chip area and a system-on-a-chip (SOC) area, namely areas 4 and 5.

[0194] Figure 5 The illustration shows a schematic diagram of the collaboration between the hard failure protection chain and the soft failure recovery chain in the electromagnetic interference suppression method according to an embodiment of this application.

[0195] like Figure 5As shown, the hard failure protection chain covers ports, power inlets, loads, and source ends, and its protection categories include clamping, isolation, current limiting, and graded protection. The soft failure recovery chain covers device loss, black screen, blue screen, and restart, and its recovery categories include monitoring, classification, grading, recording, and adaptive. The hard failure protection chain transmits its protection status information to the collaborative judgment stage via a downward arrowed broken line, and the soft failure recovery chain transmits its recovery status information to the collaborative judgment stage via a downward arrowed broken line. After receiving the above information, the collaborative judgment stage integrates at least one of the following observations: Power Good Signal (PG) or Fault Monitoring Signal (FAULT), Power Transfer Controller Alarm Signal (PD Alert), Hot-plug Detection Signal (HPD), Link Error Check (CRC), and Hardware Error Record (WHEA), performs a comprehensive judgment, and transmits parameter adjustment signals back to the hard failure protection chain and the soft failure recovery chain respectively via upward arrowed broken lines to dynamically modify the protection threshold of the hard failure protection chain or the recovery trigger condition of the soft failure recovery chain, forming a two-way closed-loop interaction. The strategies output by the collaborative decision-making process include the minimum recovery cost strategy and the downgrade or mode-limiting strategy.

[0196] In some embodiments, the hard failure protection chain and the soft failure recovery chain can cooperate through at least one of the following synergistic strategies.

[0197] Collaborative Strategy 1: Strengthen both the hardware failure protection chain and the software failure recovery chain. This strategy focuses on product reliability and lifespan, reducing the probability of hardware damage. For example, industrial personal computers requiring uninterrupted power-on or medical personal computers requiring strong immunity to sensitive sources can have their software failure mechanisms configured primarily for warm restarts, preventing major industrial and medical accidents caused by frequent cold restarts to protect hardware. Collaborative Strategy 1 can be adopted for industrial or medical equipment.

[0198] Collaborative Strategy Two: Strengthen the protection of the hardware failure protection chain while weakening the recovery of the soft failure recovery chain. This strategy focuses on user experience, reducing the soft failure trigger threshold and shortening the soft failure recovery time. For example, consumer PCs, designed for diverse scenarios such as gaming, movies, and light office work, can have a balanced setting for the soft failure trigger threshold and hardware failure tolerance to ensure the product can withstand a certain degree of cumulative electrical damage at the hardware level while also considering user experience. Collaborative Strategy Two can be adopted for consumer devices.

[0199] Collaborative Strategy Three: Reduce the protective strength of the hard failure protection chain while strengthening the recovery strength of the soft failure recovery chain. This strategy focuses on low-cost product compliance and agile project development. For example, commercial personal computers designed for general office scenarios can trigger partial or overall system self-recovery through more sensitive soft failure monitoring thresholds, ensuring that critical internal components suffer less cumulative electrical damage, ensuring no major hardware functional damage during the product's lifecycle, and reducing return rates and after-sales maintenance costs. Collaborative Strategy Three can be adopted for commercial equipment.

[0200] Figure 6 The schematic illustration shows the overall implementation framework of the electromagnetic interference immunity method according to embodiments of this application.

[0201] like Figure 6 As shown, the implementation framework comprises five sequentially executed stages: hardware monitoring, interrupt / reporting, event classification, collaborative decision-making, and action execution. Hardware monitoring monitors the indicator values ​​of the modules to be monitored and classifies them according to preset indicator thresholds. The interrupt reporting stage reports the monitoring indicator values ​​collected by the hardware monitoring stage to the event processing stage via general-purpose input / output ports or registers, while simultaneously transmitting module identifiers and master / slave device identifiers. The event classification stage attributes and classifies reported interrupt events according to severity levels: first, second, and third. The collaborative decision-making stage selects a target recovery action from multiple preset recovery actions based on the principle of least cost priority. The action execution stage executes the target recovery action selected by the collaborative decision-making stage, including at least one of isolating the abnormal module, resetting the module to be monitored, or triggering system hibernation.

[0202] In some embodiments, the hardware monitoring process may include a processing stage for collecting and comparing the monitoring index values ​​of the module to be monitored. For example, multiple preset index thresholds may be set, and when the monitoring index value exceeds the threshold at different levels, an interrupt report of the corresponding level is triggered.

[0203] In some embodiments, the interrupt reporting stage may include a signal transmission channel that transmits information collected by the hardware monitoring stage to the event processing stage. For example, monitoring information can be reported through a general-purpose input / output port or a register, along with a module identifier and a master / slave device identifier, so that the event processing stage can distinguish the source of the interrupt. The module identifier may include coded information identifying the specific hardware module that triggered the interrupt; the master / slave device identifier may include coded information identifying whether the module that triggered the interrupt is a master or slave device.

[0204] In some embodiments, the event classification process may include a stage for attribution analysis and severity classification of reported disruption events. For example, events can be classified and graded according to a first severity level, a second severity level, and a third severity level to provide a basis for subsequent collaborative decision-making.

[0205] In some embodiments, the collaborative decision-making process may include a processing stage for determining a target recovery action based on the severity level of the event and the principle of minimum cost. For example, the recovery action with the least impact on system operation may be selected from a first preset recovery action, a second preset recovery action, and a third preset recovery action.

[0206] In some embodiments, the action execution phase may include an execution stage that transforms the target recovery action selected in the collaborative decision-making phase into specific hardware operation instructions. For example, it may perform operations such as isolating abnormal modules, resetting modules to be monitored, triggering system power restart, triggering system hibernation, or limiting system power.

[0207] In some embodiments, the monitoring process further includes logging and assetization. Monitoring data generated during the monitoring process is written to logs, which include counters, timestamps, and context information. The test mapping matrix and parameter set are updated based on the logs, and the verified protection strategies are solidified into reusable assets.

[0208] In some embodiments, the collaborative decision-making process can also incorporate historical patterns for adaptive threshold adjustment, balancing robustness and reliability to optimize decision-making performance.

[0209] In some embodiments, the execution results of the action execution phase are fed back to the collaborative decision-making phase to evaluate the recovery effect and adjust subsequent decision-making strategies.

[0210] The framework emphasizes a closed-loop interaction between hardware and software. The monitoring stage provides monitoring indicator values ​​as evidence, the event handling stage and the collaborative decision-making stage make decisions based on evidence, and the execution results are recorded in logs and accumulated into a reusable set of parameters and processes.

[0211] Figure 7 The flowchart illustrating the multi-level detection and dynamic reset decision-making process in the electromagnetic interference immunity method according to an embodiment of this application is shown in the illustration.

[0212] like Figure 7 As shown, the process includes: real-time monitoring of voltage transients; when a voltage transient exceeds a first preset threshold (threshold 1), a primary interrupt is triggered, and load reduction operations are performed, such as reducing power consumption or reducing operating frequency; when the voltage continues to rise and exceeds a second preset threshold (threshold 2), an advanced interrupt is triggered, the current data is saved, and the system enters a sleep state; when the voltage returns to normal, a gradual recovery operation is performed, sequentially waking up the system, restoring the system running state, and restoring the application running state; when the voltage does not return to normal, a forced shutdown is triggered.

[0213] In some embodiments, voltage transients may include transient changes in the supply voltage that occur over a very short period of time, such as voltage spikes or voltage drops caused by electromagnetic interference events such as electrostatic discharge, electrical fast transient bursts, or surges.

[0214] In some embodiments, the first preset threshold may include a voltage reference value for triggering a primary interrupt, the second preset threshold may include a voltage reference value for triggering a high-level interrupt, and the voltage deviation of the second preset threshold is greater than that of the first preset threshold.

[0215] In some embodiments, a primary interrupt may include an interrupt response executed by the system when the voltage deviates beyond a first preset threshold but has not yet reached a second preset threshold, reducing the system's sensitivity to transient energy by lowering the load while allowing the system to continue operating. An advanced interrupt may include an interrupt response executed by the system when the voltage deviates beyond the second preset threshold, protecting hardware and data security by saving critical data and entering a system sleep state.

[0216] In some embodiments, gradual recovery may include restoring the normal operating states of each module of the system in a preset order after the voltage returns to normal. For example, the operations of waking up the system, restoring the system's operating state, and restoring the application's operating state may be performed sequentially to avoid secondary impacts caused by simultaneous recovery.

[0217] In some embodiments, if the voltage remains abnormal and does not return to normal, a forced shutdown is triggered to protect the hardware from permanent damage. After the process is completed, the system records relevant information about this event.

[0218] Figure 8 The flowchart illustrating the interaction between reset instructions and hardware states in an electromagnetic interference suppression method according to an embodiment of this application is shown in the illustration.

[0219] like Figure 8 As shown, the process includes: the hardware monitoring stage detects an abnormal current in the module to be monitored; the hardware reporting stage sends the module number (ID) of the abnormal module to the software processing stage; the software processing stage isolates the current task of the abnormal module, enables the backup module to take over the business path, and records the fault information, including the module number, timestamp and context information; after the backup module takes over, the system continues to run to avoid overall failure due to the spread of a single point of failure.

[0220] In some embodiments, the hardware monitoring stage may include a processing phase that monitors the current state of the module to be monitored. For example, the operating current of each module can be monitored by a current detection circuit, and when the current of a module exceeds the normal range, the module is determined to be abnormal.

[0221] In some embodiments, the hardware reporting stage may include a signal transmission stage that transmits the identification information of the faulty module to the software processing stage. For example, the module number of the faulty module can be sent to the software via a general-purpose input / output port or a register, so that the software processing stage can locate the specific faulty module. The module number may include coded information used to uniquely identify each hardware module in the electronic device.

[0222] In some embodiments, the software processing phase may include a stage for isolating abnormal modules. For example, new tasks may be stopped from being assigned to the abnormal module, and unfinished tasks already assigned to that module may be transferred to other normal modules for continued execution.

[0223] In some embodiments, the backup module may include a standby hardware module that has the same or compatible functions as the primary module, and takes over the work of the primary module when it malfunctions. For example, after receiving an enable command from the software processing stage, the backup module can take over the business path of the malfunctioning module to ensure that the system function is not affected.

[0224] In some embodiments, fault information may include data records that describe key characteristics of the abnormal event when a module abnormality is detected. For example, fault information may include a module number, a timestamp, and context information. The timestamp may include a time stamp indicating when the abnormal event was detected; the context information may include operational status information such as the type of task the module was performing before the abnormality occurred, the current voltage and current status, and the list of allocated resources.

[0225] Figure 9 The flowchart illustrating the system control hierarchy and master-slave device reset intervention in the electromagnetic interference immunity method according to an embodiment of this application is shown in the illustration.

[0226] like Figure 9 As shown, the method includes: the hardware monitoring stage detects an abnormal state in the monitored module and reports the master device number and slave device number to the software processing stage; the software processing stage first attempts to perform a soft restart on the slave device and records the fault information; if the slave device's function returns to normal after the soft restart, the system continues to run; if the slave device's function does not return to normal after the soft restart, it continues to attempt to perform a soft restart on the master device and records the fault information; if the master device's function returns to normal after the soft restart, the system continues to run; if the master device's function still does not return to normal after the soft restart, it saves the key data and performs a hard restart on both the master device and the slave device, restores the system function, terminates the process, and records the event.

[0227] In some embodiments, the master device may include a hardware module that performs primary control or core processing functions in an electronic device, and the slave device may include a hardware module controlled by the master device or performing auxiliary processing functions. For example, the master device may include a system-on-a-chip or an embedded controller, and the slave device may include a power delivery controller, a timer, or a hub, etc. The master device number may include coded information for uniquely identifying the master device, and the slave device number may include coded information for uniquely identifying the slave device.

[0228] In some embodiments, a soft reset may include resetting the device via software instructions without disconnecting the power supply. During a soft reset, the device's registers are reinitialized, but power supply remains normal, and the device can quickly return to its operating state after the reset is complete. A hard reset may include resetting the device by disconnecting the power supply and then reconnecting it. Hard resets take longer to recover than soft resets, but can clear hardware state errors caused by latch-up or power rail anomalies.

[0229] In some embodiments, fault information may include data records describing the reset event, recorded during the execution of a reset operation. For example, fault information may include a timestamp and context information. The timestamp may include a time stamp indicating when the reset event occurred; the context information may include the fault module number that triggered the reset, the type of reset performed, and operational status information such as the device status before and after the reset.

[0230] Figure 10 The schematic diagram illustrates the circuit architecture for hard failure protection and soft failure observation using a Type-C power supply link as an example.

[0231] like Figure 10 As shown, in this circuit architecture, the embedded controller (EC) works in conjunction with the central processing unit (CPU). Both the first Type-C connector (Type-C CONN 1) and the second Type-C connector (Type-C CONN 2) support full-function Type-C features, including Universal Serial Bus 3.2 (USB 3.2), Alternate mode DisplayPort (DP), and DC-IN power delivery via Power Delivery Protocol (PD). The circuit as a whole is divided into an energy domain, an isolation domain, and a sensitive domain according to a zoned and domaind architecture.

[0232] In some embodiments, the first Type-C connector (Type-C CONN 1) belongs to the energy domain, and its Universal Serial Bus 2.0 (USB 2.0) signal, first Type-C port control signal (TCP1), and auxiliary signal (AUX) are respectively connected to corresponding modules in the isolation domain and the sensitive domain. The isolation domain is equipped with a Type-C port overvoltage protection module (CC OVP) for clamping and limiting transient overvoltages entering from the Type-C port. The sensitive domain is equipped with a Parade Re-Timer chip (PS8818) for signal reconstruction and jitter elimination of high-speed signals from Universal Serial Bus 3.2 Gen2 and DisplayPort 1.4 (USB 3.2 Gen2 / DP 1.4), and the recovered signals are transmitted to the central processing unit (CPU).

[0233] In some embodiments, the sensitive domain is further equipped with a power transfer controller chip (PD TPS65994BF). This chip interacts with the first and second Type-C port connectors respectively via the Type-C port configuration channel signals (CC / CC2) to monitor the port connection status and negotiation results. The embedded controller (EC) connects to the power transfer controller chip via the embedded controller system management bus (EC_SMBus), reads the power transfer controller's status register values, and obtains port connection status information and negotiation failure information as observations. The power transfer controller chip reports the status information to the central processing unit (CPU) via the internal integrated circuit bus (I2C).

[0234] In some embodiments, the second Type-C connector (Type-C CONN 2) belongs to the energy domain, and its circuit structure is symmetrical to that of the first Type-C connector. Similarly, it transmits Universal Serial Bus 2.0 (USB 2.0) signals, second Type-C port control signals (TCP0), and auxiliary signals (AUX) to the central processing unit (CPU) after being processed by the Type-C port overvoltage protection module (CC OVP) in the isolation domain and the re-timer chip in the sensitive domain.

[0235] In some embodiments, a Type-C port overvoltage protection module (CC OVP) is deployed on the configuration channel pin of the Type-C port for detecting and clamping transient overvoltages entering from the port. When the voltage on the configuration channel pin exceeds a preset protection threshold, the overvoltage protection module outputs a fault indication signal, which can be acquired by the embedded controller as a first observation.

[0236] In some embodiments, a re-timer chip performs clock recovery and signal reconstruction for high-speed signals, eliminating jitter and attenuation accumulated in transmission cables and connectors. The re-timer chip is part of a hardware tolerance layer, enhancing the local circuitry's tolerance to residual interference through its own electrical characteristics.

[0237] In some embodiments, the Type-C Port Overvoltage Protection Module (CC OVP) in the energy domain constitutes the first-level clamping protection of the hard failure protection chain; signal isolation and power limiting measures in the isolation domain constitute the second-level power limiting protection; and the re-timer chip in the sensitive domain provides the third-level signal reconstruction protection. Simultaneously, the power transfer controller chip (PD) and the embedded controller (EC) constitute the observation points of the soft failure recovery chain. By collecting port connection status information, negotiation failure information, and overvoltage protection trigger information as observations, they provide a basis for the hierarchical handling decisions of the system control layer.

[0238] Table 7 schematically illustrates the working principle of hard failure protection and soft failure observation in a Type C port power supply link according to an embodiment of this application.

[0239] Table 7 Working Principles of Hard Failure Protection and Soft Failure Observation in Type-C Port Power Supply Links

[0240]

[0241] As shown in Table 7, the power supply link is divided into an energy domain, an isolation domain, and a sensitive domain according to a zoned and domained architecture. Each domain corresponds to different key nodes and protection monitoring devices. In the energy domain, the key node is the power supply bus input (VBUS_IN), which is equipped with a transient voltage suppressor (TVS) as a protection device. Its key parameters include a clamping voltage that does not exceed 90% of the maximum withstand voltage of the downstream chip, and an overvoltage protection level that meets the electrostatic discharge immunity test standard (IEC61000-4-2) and related extended test standards. The design goal is to clamp the transient spikes at the port to below the safe voltage. In the isolation domain, the key node is the power supply bus output (VBUS_OUT), which is equipped with an overvoltage protection device (OVP) as a protection monitoring device. Its key parameters include an overcurrent threshold set to 1.5 times the rated current, a response time of less than one microsecond, and a fault flag signal (FLAG) delay of less than five microseconds from the occurrence of a fault to the low signal of the fault flag. The design goal is to limit electromagnetic transient energy from entering the sensitive domain and provide a microsecond-level fault warning signal as a monitoring device. In the sensitive domain, the key node is the configuration channel logic circuit (CC-Logic), which is deployed with a power transmission controller (PD) as a protection monitoring device. Its key parameters include the alarm signal (ALERT#) interruption dejitter time, which can be configured by the firmware to be from fifty microseconds to one millisecond after hardware filtering, and the firmware polling frequency, which reads the key status register once every ten microseconds. The design goal is to filter out brief interference and accurately capture abnormal events that require recovery actions.

[0242] In some embodiments, the power supply bus input (VBUS_IN) may include the node location where electromagnetic transient energy first arrives in the Type-C port power supply link, serving as the entry point into the energy domain. The power supply bus output (VBUS_OUT) may include a power supply voltage output node after isolation domain energy limiting processing. The voltage and current states of this node can serve as observational criteria for determining whether electromagnetic interference has penetrated the energy domain.

[0243] In some embodiments, the clamping voltage may include a transient voltage suppression device limiting the voltage across its terminals to a maximum value when subjected to a transient surge current, which should be lower than the maximum withstand voltage of the downstream protected chip. Response time may include the time interval from the occurrence of a transient overvoltage or overcurrent event to the start of protective action by the overvoltage protection device. Fault flag signal delay may include the time interval from the actual occurrence of a fault event to the completion of a transition on the fault flag signal (FLAG) pin and its detection by an external controller.

[0244] In some embodiments, the alarm signal interruption dejittering time may include a time parameter for the firmware to perform software dejittering on the power transfer controller's alarm signal (ALERT#). Only alarm signals that remain valid for this time will be recognized as valid interrupt events, and transient glitches shorter than this time will be filtered out. The firmware polling frequency may include the frequency at which the firmware periodically reads the power transfer controller's status register via the internal integrated circuit bus. This frequency determines the system's response delay to port connection status changes and negotiation failure events.

[0245] In some embodiments, the following correlation mechanism exists between soft failures and hard failures:

[0246] In terms of causal relationships, persistent or high-energy hard failures, such as device burnout, are often the final physical manifestation of accumulated or improperly handled soft failures. Soft failures include electrical overstress or state disturbances. This application's embodiments, by timely capturing the signs of soft failures before hard failures occur—that is, acquiring monitoring index values ​​as observations and proactively executing target recovery actions—can effectively cut off the path from soft failure to hard failure.

[0247] In terms of protective coordination, the clamping, energy limiting, and isolation processes of the hard failure protection chain constitute the first line of defense. Its goal is to reduce electromagnetic transient energy, creating a working prerequisite for the soft failure recovery chain. The soft failure recovery chain is the second line of defense, aiming to resolve functional disturbances through logic and state recovery, provided that electromagnetic transient energy has been controlled within a safe range. The two constitute a complementary relationship between functional recovery and energy control.

[0248] In terms of information loop, certain observation points in the hard failure protection chain, such as the fault flag signals of overvoltage protection devices and the power good signal of the power transfer controller, provide key inputs to the hardware health status for the soft failure recovery chain. Conversely, certain reset actions performed by the soft failure recovery chain, such as resetting the power transfer controller, also influence the hardware's power consumption and electrical stress, forming a two-way information and energy interaction. Together, these constitute a complete closed loop from energy injection to functional recovery.

[0249] Figure 11 A schematic diagram of an electromagnetic interference suppression device 1100 according to an embodiment of this application is shown. Figure 11 As shown, the electromagnetic interference suppression device 1100 according to an embodiment of this application may include a determination module 1101 and an execution module 1102.

[0250] The determination module 1101 is used to determine an abnormal event corresponding to at least one of a plurality of abnormal conditions in response to determining that the monitoring index value of the module to be monitored meets at least one target abnormal condition among a plurality of abnormal conditions. The plurality of abnormal conditions include: the monitoring index value is greater than or equal to a preset index threshold, the duration of the monitoring index value deviating from the normal value is greater than or equal to a preset duration threshold, the recovery time of the monitoring index value to the normal value is less than or equal to a preset recovery time threshold, the number of deviations of the monitoring index value from the normal value is greater than or equal to a preset number of deviations threshold, and the normal value is the monitoring index value when the module to be monitored is not subject to electromagnetic interference.

[0251] The execution module 1102 is used to execute the target recovery action corresponding to the abnormal event among a plurality of preset recovery actions. The plurality of preset recovery actions include a first preset recovery action, a second preset recovery action, and a third preset recovery action. The first preset recovery action includes re-executing the abnormal operation of the module to be monitored. The second preset recovery action includes resetting the module to be monitored. The third preset recovery action includes reducing the operating power of the electronic device. The abnormal operation is the operation performed by the module to be monitored within a preset period before the abnormal event occurs.

[0252] In some embodiments, the electromagnetic interference suppression device 1100 further includes: a transient suppression module 1103, used to perform transient suppression processing on electromagnetic transient energy entering from the external interface of the electronic device using a transient suppression circuit, so as to reduce the probability that the monitoring index value meets the abnormal condition; the transient suppression circuit is composed of at least one of a series resistor, a filter capacitor, an anti-static device TVS, and a surge protection device TSS.

[0253] In some embodiments, the monitored index value includes a voltage value, and the abnormal events include a first abnormal event, a second abnormal event, and a third abnormal event. The target recovery action corresponding to the first abnormal event is the first preset recovery action. The first abnormal event corresponds to the following abnormal conditions: the voltage value is greater than or equal to a first preset index threshold and less than a second preset index threshold; the duration of the voltage value deviating from the normal value is greater than or equal to a first preset duration threshold and less than a second preset duration threshold. The target recovery action corresponding to the second abnormal event is the second preset recovery action. The second abnormal event corresponds to the following abnormal conditions: the voltage value is greater than or equal to a second preset index threshold and less than a third preset index threshold; the duration of the voltage value deviating from the normal value is greater than or equal to a second preset duration threshold and less than a third preset duration threshold. The target recovery action corresponding to the third abnormal event is the third preset recovery action. The third abnormal event corresponds to the following abnormal conditions: the voltage value is greater than or equal to a third preset index threshold; the duration of the voltage value deviating from the normal value is greater than or equal to a third preset duration threshold.

[0254] In some embodiments, the monitoring index value includes the level indication value corresponding to the overvoltage protection trigger signal, the abnormal event includes a fourth abnormal event and a fifth abnormal event, the target recovery action corresponding to the fourth abnormal event is the second preset recovery action, and the fourth abnormal event corresponds to the following abnormal conditions: the level indication value is greater than or equal to the preset level indication value, and the number of deviations of the level indication value from the normal value within the preset time window is greater than or equal to the first deviation threshold and less than the second deviation threshold; the target recovery action corresponding to the fifth abnormal event is the third preset recovery action, and the fifth abnormal event corresponds to the following abnormal conditions: the level indication value is greater than or equal to the preset level indication value, and the number of deviations of the level indication value from the normal value within the preset time window is greater than or equal to the second deviation threshold.

[0255] In some embodiments, the monitoring indicator value includes the status identifier value corresponding to the port negotiation result of the Type-C port, the abnormal event includes a sixth abnormal event and a seventh abnormal event, the target recovery action corresponding to the sixth abnormal event is the first preset recovery action, and the sixth abnormal event corresponds to the following abnormal conditions: the status identifier value is equal to the first preset status identifier value, and the recovery time of the status identifier value to the normal value is less than or equal to the first preset recovery time threshold; the target recovery action corresponding to the seventh abnormal event is the second preset recovery action, and the seventh abnormal event corresponds to the following abnormal conditions: the status identifier value is equal to the first preset status identifier value, and the duration of the status identifier value deviating from the normal value is greater than or equal to the fourth preset duration.

[0256] In some embodiments, the abnormal event further includes an eighth abnormal event, and the target recovery action corresponding to the eighth abnormal event is the third preset recovery action. The eighth abnormal event corresponds to the following abnormal conditions: the status identifier value is equal to the second preset status identifier value, and the number of consecutive deviations of the status identifier value from the normal value is greater than or equal to the third deviation number threshold.

[0257] In some embodiments, the first preset recovery action includes at least one of the following: recording the log corresponding to the abnormal event, adjusting the sampling parameters of the analog-to-digital converter, and enabling the digital filter inside the general purpose input / output port, wherein the analog-to-digital converter is used to determine the monitoring index value, and the digital filter is used to filter out glitches in the signal received by the module under monitoring; the second preset recovery action includes at least one of the following: resetting the module under monitoring; the third preset recovery action further includes at least one of the following: triggering a system power restart, triggering system hibernation, and limiting system power.

[0258] According to embodiments of this application, any plurality of modules in determining module 1101 and execution module 1102 can be merged into one module, or any one of these modules can be split into multiple modules. Alternatively, at least a portion of the functionality of one or more of these modules can be combined with at least a portion of the functionality of other modules and implemented in one module. According to embodiments of this application, at least one of determining module 1101 and execution module 1102 can be at least partially implemented as hardware circuitry, such as field-programmable gate arrays, programmable logic arrays, systems-on-a-chip, systems-on-a-substrate, systems-on-package, application-specific integrated circuits, or any other reasonable means of integrating or packaging circuitry, or implemented in any one of software, hardware, and firmware methods, or in a suitable combination of any of these. Alternatively, at least one of determining module 1101 and execution module 1102 can be at least partially implemented as a computer program module, which, when run, can perform corresponding functions.

[0259] Figure 12 A block diagram schematically illustrates an electronic device suitable for implementing an electromagnetic interference immunity method according to an embodiment of this application.

[0260] like Figure 12 As shown, an electronic device 1200 according to an embodiment of this application includes a processor 1201, which can perform various appropriate actions and processes according to a program stored in a read-only memory 1202 or a program loaded from a storage portion 1208 into a random access memory 1203. The processor 1201 may include, for example, a general-purpose microprocessor, an instruction set processor and / or an associated chipset and / or a dedicated microprocessor. The processor 1201 may also include onboard memory for caching purposes. The processor 1201 may include a single processing unit or multiple processing units for executing different steps of the method flow according to an embodiment of this application.

[0261] Random access memory 1203 stores various programs and data required for the operation of electronic device 1200. Processor 1201, read-only memory 1202, and random access memory 1203 are interconnected via bus 1204. Processor 1201 executes various steps of the method flow according to embodiments of this application by executing programs in read-only memory 1202 and / or random access memory 1203. It should be noted that programs may also be stored in one or more memories other than read-only memory 1202 and random access memory 1203. Processor 1201 may also execute various steps of the method flow according to embodiments of this application by executing programs stored in one or more memories.

[0262] According to embodiments of this application, the electronic device 1200 may further include an input / output interface 1205, which is also connected to the bus 1204. The electronic device 1200 may also include one or more of the following components connected to the input / output interface 1205: an input section 1206 including a keyboard, mouse, etc.; an output section 1207 including a cathode ray tube, liquid crystal display, etc., and a speaker, etc.; a storage section 1208 including a hard disk, etc.; and a communication section 1209 including a network interface card such as a LAN card, modem, etc. The communication section 1209 performs communication processing via a network such as the Internet. A drive 1210 is also connected to the input / output interface 1205 as needed. A removable medium 1211, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 1210 as needed so that computer programs read from it can be installed into the storage section 1208 as needed.

[0263] Embodiments of this application also provide a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the electromagnetic interference immunity method according to the embodiments of this application.

[0264] According to embodiments of this application, the computer-readable storage medium can be a non-volatile computer-readable storage medium, such as including but not limited to: portable computer disks, hard disks, random access memory, read-only memory, erasable programmable read-only memory, portable compact disk read-only memory, optical storage devices, magnetic storage devices, or any suitable combination thereof. In embodiments of this application, the computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of this application, the computer-readable storage medium may include the read-only memory 1202, and / or random access memory 1203, and / or one or more memories other than read-only memory 1202 and random access memory 1203 described above.

[0265] Embodiments of this application also include a computer program product comprising a computer program containing program code for performing the methods shown in the flowchart. When the computer program product is run on a computer system, the program code is used to cause the computer system to implement the methods provided in the embodiments of this application.

[0266] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and may be downloaded and installed via the communication section 1209, and / or installed from the removable medium 1211. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0267] In embodiments of this application, the computer program can be downloaded and installed from a network via communication section 1209, and / or installed from removable medium 1211. When the computer program is executed by processor 1201, it performs the functions defined in the system of this application embodiment. According to embodiments of this application, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0268] According to embodiments of this application, program code for executing the computer programs provided in the embodiments of this application can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0269] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0270] Those skilled in the art will understand that the features described in the various embodiments of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application.

Claims

1. An electromagnetic interference suppression method, characterized in that, The method is applied to an electronic device, and the method includes: In response to determining that the monitoring index value of the module to be monitored meets at least one target abnormal condition among multiple abnormal conditions, an abnormal event corresponding to at least one of the target abnormal conditions is determined to have occurred. The multiple abnormal conditions include: the monitoring index value is greater than or equal to a preset index threshold; the duration of the monitoring index value deviating from the normal value is greater than or equal to a preset duration threshold; the recovery time of the monitoring index value to the normal value is less than or equal to a preset recovery time threshold; the number of deviations of the monitoring index value from the normal value is greater than or equal to a preset number of deviations threshold; and the normal value is the monitoring index value of the module to be monitored when it is not subject to electromagnetic interference. The target recovery action corresponding to the abnormal event is executed from among a plurality of preset recovery actions. The plurality of preset recovery actions include a first preset recovery action, a second preset recovery action, and a third preset recovery action. The first preset recovery action includes re-executing the abnormal operation of the module to be monitored. The second preset recovery action includes resetting the module to be monitored. The third preset recovery action includes reducing the operating power of the electronic device. The abnormal operation is an operation performed by the module to be monitored within a preset period before the occurrence of the abnormal event.

2. The electromagnetic interference suppression method according to claim 1, characterized in that, The method further includes: A transient suppression circuit is used to suppress electromagnetic transient energy entering from the external interface of the electronic device, thereby reducing the probability that the monitored index value meets the abnormal condition. The transient suppression circuit consists of at least one of a series resistor, a filter capacitor, an electrostatic discharge (TVS) device, and a surge protection (TSS) device.

3. The electromagnetic interference suppression method according to claim 1, characterized in that, The monitored index values ​​include voltage values. The abnormal events include a first abnormal event, a second abnormal event, and a third abnormal event. The target recovery action corresponding to the first abnormal event is the first preset recovery action. The first abnormal event corresponds to the following abnormal conditions: the voltage value is greater than or equal to the first preset index threshold and less than the second preset index threshold, and the duration of the voltage value deviating from the normal value is greater than or equal to the first preset duration threshold and less than the second preset duration. The target recovery action corresponding to the second abnormal event is the second preset recovery action. The second abnormal event corresponds to the following abnormal conditions: the voltage value is greater than or equal to the second preset index threshold and less than the third preset index threshold, and the duration of the voltage value deviating from the normal value is greater than or equal to the second preset duration threshold and less than the third preset duration threshold. The target recovery action corresponding to the third abnormal event is the third preset recovery action. The third abnormal event corresponds to the following abnormal conditions: the voltage value is greater than or equal to the third preset index threshold, and the duration of the voltage value deviating from the normal value is greater than or equal to the third preset duration threshold.

4. The electromagnetic interference suppression method according to claim 1, characterized in that, The monitoring index values ​​include the level indication value corresponding to the overvoltage protection trigger signal. The abnormal events include the fourth and fifth abnormal events. The target recovery action corresponding to the fourth abnormal event is the second preset recovery action. The fourth abnormal event corresponds to the following abnormal conditions: the level indicator value is greater than or equal to the preset level indicator value, and the number of deviations of the level indicator value from the normal value within the preset time window is greater than or equal to the first deviation number threshold and less than the second deviation number threshold. The target recovery action corresponding to the fifth abnormal event is the third preset recovery action. The fifth abnormal event corresponds to the following abnormal conditions: the level indicator value is greater than or equal to the preset level indicator value, and the number of deviations of the level indicator value from the normal value within the preset time window is greater than or equal to the second deviation number threshold.

5. The electromagnetic interference suppression method according to claim 1, characterized in that, The monitoring index values ​​include the status identifier values ​​corresponding to the port negotiation results of the Type-C port. The abnormal events include the sixth and seventh abnormal events. The target recovery action corresponding to the sixth abnormal event is the first preset recovery action. The sixth abnormal event corresponds to the following abnormal conditions: the status identifier value is equal to the first preset status identifier value, and the recovery time for the status identifier value to return to the normal value is less than or equal to the first preset recovery time threshold. The target recovery action corresponding to the seventh abnormal event is the second preset recovery action. The seventh abnormal event corresponds to the following abnormal conditions: the status identifier value is equal to the first preset status identifier value, and the duration of the status identifier value deviating from the normal value is greater than or equal to the fourth preset duration.

6. The electromagnetic interference suppression method according to claim 5, characterized in that, The abnormal events also include an eighth abnormal event. The target recovery action corresponding to the eighth abnormal event is the third preset recovery action. The eighth abnormal event corresponds to the following abnormal conditions: the status identifier value is equal to the second preset status identifier value, and the number of consecutive deviations of the status identifier value from the normal value is greater than or equal to the third deviation number threshold.

7. The electromagnetic interference suppression method according to claim 1, characterized in that: The first preset recovery action includes at least one of the following: recording the log corresponding to the abnormal event, adjusting the sampling parameters of the analog-to-digital converter, and enabling the digital filter inside the general-purpose input / output port. The analog-to-digital converter is used to determine the monitoring index value, and the digital filter is used to filter out glitches and interference in the signal received by the module under monitoring. The second preset recovery action includes at least one of the following: resetting the module to be monitored; The third preset recovery action also includes at least one of the following: triggering system power restart, triggering system hibernation, or limiting system power.

8. An electronic device, comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7.

9. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-7.

10. A computer program product comprising a computer program that, when executed by a processor, implements the method according to any one of claims 1-7.

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