A direct-current blocking device control method and control system

Abstract

The present application relates to the technical field of circuit device of power system, and particularly relates to a DC blocking device control method and a control system. The method comprises the following steps: collecting the capacitor end voltage in the DC blocking device and the loop current of the transformer neutral point, and obtaining the loop current amplitude; calculating the phase difference between the capacitor end voltage and the loop current to obtain the capacitor current phase difference; dividing the DC component dominant feature and the AC component dominant feature based on the capacitor current phase difference; counting the stable time length of the capacitor current phase difference maintaining the DC component dominant feature; if the capacitor current phase difference is in the DC component dominant feature, the current amplitude is over standard, and the stable time length is up to standard, controlling the bypass switch of the DC blocking device to be tripped, and cutting the capacitor of the DC blocking device into the loop between the transformer neutral point and the ground. The present application realizes the accurate identification of the working condition of the DC blocking device and the safe switching of the DC blocking device through synchronous sampling analysis and multiple verification, so as to improve the DC blocking control accuracy and the equipment safety, and ensure the stable operation of the power grid.

Description

Technical Field

[0001] This invention relates to the field of circuit device technology in power systems, and in particular to a DC blocking device control method and control system. Background Technology

[0002] A DC blocking device is an electrical device used to isolate the DC component in a circuit while allowing the AC component to pass through. It utilizes the characteristics of capacitors to "block DC and pass AC" or inductors to "pass DC and block AC". It is widely used in power systems, communications, electronic measurement and other fields. Among them, the DC blocking device of transformer neutral point capacitor is the most common in power systems.

[0003] In actual power system operation, transformer neutral points face the risk of DC component intrusion. The control accuracy and operational stability of DC blocking devices directly affect the overall safety of the power grid. However, existing control schemes for transformer neutral point capacitor DC blocking devices still have room for improvement in terms of adaptability to complex operating conditions and long-term reliable operation, making it difficult to fully meet the refined and high-reliability operation requirements of the power grid. Existing DC blocking control schemes often suffer from problems such as single-dimensional signal analysis and insufficient anti-interference capabilities in the operating condition sensing and judgment stages. Their accuracy in distinguishing between AC and DC components in the circuit is limited, making it difficult to accurately match the dynamic changes of actual operating conditions. In the signal processing and status judgment process, the lack of a robust abnormal signal identification and multi-dimensional verification mechanism makes them susceptible to instantaneous power grid fluctuations and external interference, leading to deviations in control decisions and causing unnecessary equipment actions. This not only affects the DC blocking effect but may also cause additional wear and tear on core components, reducing equipment lifespan and operational safety. Summary of the Invention

[0004] Therefore, it is necessary to provide a DC blocking device control method and control system to solve at least one of the above-mentioned technical problems.

[0005] To achieve the above objective, a method for controlling a DC blocking device is provided, the method comprising the following steps: Step S1: Collect the capacitor terminal voltage in the DC blocking device and the loop current at the neutral point of the transformer to obtain the loop current amplitude; Step S2: Calculate the phase difference between the capacitor terminal voltage and the loop current to obtain the capacitive current phase difference; based on the capacitive current phase difference, divide the DC component dominance characteristic into the AC component dominance characteristic; and statistically analyze the duration for which the capacitive current phase difference maintains the DC component dominance characteristic. Step S3: If the phase difference of the capacitive current is dominated by the DC component, the current amplitude exceeds the standard, and the stable duration is up to the standard, control the bypass switch of the DC blocking device to open, and switch the capacitor of the DC blocking device into the circuit between the transformer neutral point and ground; if the phase difference of the capacitive current is dominated by the AC component, regardless of whether the current amplitude exceeds the standard, keep the bypass switch closed and prohibit the capacitor from being switched in. Step S4: After the capacitor of the DC blocking device is connected to the circuit between the transformer neutral point and ground, the capacitive current phase difference extraction, component dominance feature identification and current amplitude verification are continuously performed; when the capacitive current phase difference deviates from the DC component dominance feature or the current amplitude is lower than the preset DC blocking switching reference, the bypass switch is controlled to close and the capacitor is removed, and the transformer neutral point is restored to direct grounding.

[0006] The present invention also provides a DC blocking device control system for executing the above-described DC blocking device control method, the DC blocking device control system comprising: The data acquisition module is used to acquire the capacitor terminal voltage and the loop current at the neutral point of the transformer in the DC blocking device, and to obtain the loop current amplitude. The phase analysis module is used to calculate the phase difference between the capacitor terminal voltage and the loop current to obtain the capacitive current phase difference; based on the capacitive current phase difference, it divides the DC component dominance feature into the AC component dominance feature; and it calculates the stable duration of the capacitive current phase difference maintaining the DC component dominance feature. The switching control module is used to control the bypass switch of the DC blocking device to open and switch the capacitor of the DC blocking device into the circuit between the transformer neutral point and ground if the phase difference of the capacitive current is dominated by the DC component, the current amplitude exceeds the standard and the stable time is up to the standard. If the phase difference of the capacitive current is dominated by the AC component, the bypass switch is kept closed and the capacitor is prohibited from being switched in, regardless of whether the current amplitude exceeds the standard. The monitoring and reset module is used to continuously perform capacitive current phase difference extraction, component dominance feature identification, and current amplitude verification after the capacitor of the DC blocking device is switched into the circuit between the transformer neutral point and ground. When the capacitive current phase difference deviates from the DC component dominance feature or the current amplitude is lower than the preset DC blocking switching reference, the bypass switch is controlled to close and the capacitor is removed, restoring the transformer neutral point to direct grounding.

[0007] The beneficial effects of this invention are as follows: On the one hand, this invention synchronously collects the capacitor terminal voltage and the transformer neutral point circuit current, extracts the fundamental phase parameters through harmonic analysis, and accurately calculates the capacitive current phase difference after eliminating abnormal data, providing reliable data support for component characteristic determination. Combining a preset phase stability range and fluctuation amplitude to determine the dominant AC / DC components, along with continuous accumulation of the stable duration of the capacitive current phase difference and continuous sampling verification of current amplitude exceeding limits, a multi-layered cross-verification mechanism is formed. This effectively shields interference such as instantaneous current surges and phase drift, avoiding misjudgments of operating conditions. It ensures that control commands are triggered only in core scenarios where a stable DC component dominates and the current continuously exceeds limits, eliminating the impact and losses on equipment caused by ineffective switching, and guaranteeing the accuracy of DC blocking control operations and the safety of equipment operation.

[0008] On the other hand, in the capacitor switching-in stage, this invention achieves precise tripping of the bypass switch through signal detection and position monitoring. Then, after initial capacitor voltage verification, loop continuity verification, and post-connection parameter monitoring, safe switching-in is completed. When the AC component dominates, a closing hold signal is continuously output, and the signal strength is adjusted in real time and the closing status is periodically verified to ensure reliable closure of the bypass switch. At the same time, the capacitor connection link is cut off to prevent erroneous switching-in. After the capacitor is switched in, phase and current changes are continuously tracked. When exiting, switch closing confirmation, capacitor disconnection detection, and grounding continuity verification are strictly implemented, making the entire process closed-loop controllable. It can effectively suppress the electrochemical corrosion of the transformer by the DC component, ensure the stable operation of the neutral point grounding system, and improve the grid's adaptability to complex operating conditions and power supply reliability. Attached Figure Description

[0009] Figure 1 A schematic diagram of the steps in a DC blocking device control method; Figure 2 A comparison diagram of capacitor terminal voltage and loop current; Figure 3 This is the interface for the real-time monitoring and intelligent control platform of the DC blocking device control system; The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0010] The technical method of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0011] Furthermore, the accompanying drawings are merely illustrative of the invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor methods and / or microcontroller methods.

[0012] It should be understood that although the terms "first," "second," etc., may be used herein to describe various units, these units should not be limited by these terms. These terms are used merely to distinguish one unit from another. For example, without departing from the scope of the exemplary embodiments, a first unit may be referred to as a second unit, and similarly, a second unit may be referred to as a first unit. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0013] To achieve the above objectives, please refer to Figures 1 to 3 A method for controlling a DC blocking device, the method comprising the following steps: Preferably, step S1: collect the capacitor terminal voltage in the DC blocking device and the loop current at the neutral point of the transformer to obtain the loop current amplitude; In this embodiment, a combination of a high-precision voltage sensor and a current sensor is used for data acquisition. The voltage sensor is a capacitive voltage divider sensor with a range of 0-10kV and an accuracy class of 0.2. It is directly connected to the terminals of the capacitor in the DC blocking device. The sensor output is connected to the signal conditioning circuit through a shielded cable, with the cable shield grounded at one end to suppress electromagnetic interference. The current sensor is a Rogowski coil sensor with a range of 0-100A and an accuracy class of 0.2. It is connected in series in the loop between the transformer neutral point and ground. The sensor output signal is transmitted to the same signal conditioning circuit through the shielded cable.

[0014] It should be explained that the signal conditioning circuit performs differential amplification on the received original capacitor terminal voltage signal and the original transformer neutral point circuit current signal. The voltage signal amplification factor is set to 100 times, and the current signal amplification factor is set to 200 times. During the amplification process, a second-order low-pass filter circuit is used for filtering, and the filter cutoff frequency is set to 500Hz to eliminate high-frequency interference signals.

[0015] The filtered and amplified capacitor terminal voltage signal and transformer neutral point circuit current signal are synchronously input to an analog-to-digital converter. The converter uses a 16-bit resolution, a sampling frequency of 1kHz, and a sampling period of 1ms to strictly ensure that the sampling start times of the voltage and current signals are completely synchronized. The converter performs 10 consecutive samplings of the voltage and current signals in each sampling period to obtain 10 sets of capacitor terminal voltage sampling data and 10 sets of transformer neutral point circuit current sampling data. The voltage sampling data is uniformly expressed in V, and the current sampling data is uniformly expressed in A. All sampling data is stored in real time in a dedicated storage unit. The storage unit adopts a cyclic overwrite storage mode, and the storage depth is set to 1000 sets of sampling data.

[0016] Specifically, the effective value of the transformer neutral point loop current sampling data in the storage unit is calculated. In the calculation process, each group of current sampling data is first squared, then the arithmetic mean of the 10 squared data is taken, and finally the square root of the mean is taken to obtain the effective value of the transformer neutral point loop current in each sampling period, that is, the loop current amplitude. The unit of the calculation result is uniformly A. The capacitor terminal voltage sampling data is directly stored in the storage unit for subsequent phase difference calculation. The loop current amplitude calculation result is synchronously transmitted to the subsequent data processing stage. At the same time, the storage unit records the timestamp of each sampling. The timestamp accuracy is set to 1ms to ensure the time sequence correspondence between the capacitor terminal voltage sampling data, the transformer neutral point loop current sampling data and the loop current amplitude data.

[0017] Preferably, step S2: calculate the phase difference between the capacitor terminal voltage and the loop current to obtain the capacitive current phase difference; divide the DC component dominance feature and the AC component dominance feature based on the capacitive current phase difference; and calculate the stable duration of the capacitive current phase difference maintaining the DC component dominance feature. Optionally, in step S2, the phase difference between the capacitor terminal voltage and the loop current is calculated, and the capacitive current phase difference is obtained as follows: Synchronous, equally spaced time-domain sampling is performed on the capacitor terminal voltage signal and the transformer neutral point circuit current signal; Voltage and current sampling sequences of the same duration are extracted, and harmonic analysis is performed on the two sets of sampling sequences to extract the phase parameters of the fundamental voltage and fundamental current components. Calculate the difference between the fundamental phase of the voltage and the fundamental phase of the current, and remove abnormal data that exceed the reasonable phase range from the difference; define the processed difference as the capacitive current phase difference.

[0018] In this embodiment, synchronous, equally spaced time-domain sampling is performed on the capacitor terminal voltage sampling data and transformer neutral point circuit current sampling data stored in the dedicated storage unit. The sampling frequency remains at 1kHz, the sampling period is 1ms, consistent with the sampling parameters in step S1, and the sampling duration is set to 1s. 1000 sets of synchronously corresponding capacitor terminal voltage sampling data (unit: V) and transformer neutral point circuit current sampling data (unit: A) are obtained. All voltage sampling data within this 1s duration are extracted to form a voltage sampling sequence, and all current sampling data from the same period are extracted to form a current sampling sequence. Both sets of sequences have a length of 1000 data points to ensure complete time dimension matching.

[0019] In one embodiment, harmonic analysis is performed on the voltage sampling sequence and the current sampling sequence respectively. The fast Fourier transform algorithm is used to decompose the two sets of sequences in the frequency domain. The number of transform points is set to 1024 points and the frequency resolution is set to 1Hz. After decomposition, the phase parameters corresponding to the 50Hz fundamental component are extracted. The unit of the fundamental phase parameter of the capacitor terminal voltage is degrees (°), and the unit of the fundamental phase parameter of the transformer neutral point circuit current is also degrees (°). During the extraction process, the phase reference point of the fundamental component is determined based on the starting timestamp of the sampling sequence to ensure that the reference reference of the two sets of fundamental phase parameters is consistent and to avoid phase comparison deviation.

[0020] In another embodiment, the difference between the fundamental phase of the capacitor terminal voltage and the fundamental phase of the transformer neutral point circuit current is calculated. The calculation method is to subtract the fundamental phase of the current from the fundamental phase of the voltage, and the unit of the difference is degrees (°). A reasonable phase range is set to -180° to 180°. Difference data exceeding this range are identified as abnormal data and removed. The valid differences after removing abnormal data are normalized so that all valid differences fall within the -180° to 180° range. The normalized phase difference is defined as the capacitive-current phase difference, with the unit being degrees (°). It is synchronously associated with the timestamp of the corresponding sampling duration and stored in a dedicated storage unit for subsequent division of the dominant DC and AC components.

[0021] Optionally, the characteristics of distinguishing between DC component dominance and AC component dominance based on the capacitive phase difference in step S2 include: Retrieve the preset phase stability range corresponding to the DC component; The current phase difference is compared with the phase stability interval point by point, and the number of consecutive samples in which the current phase difference is within the interval is counted. If the number of consecutive samples equals the preset sampling threshold, it is determined to be a DC component dominant feature; if the current phase difference deviates from the range and the fluctuation amplitude is greater than the preset sampling threshold, it is determined to be an AC component dominant feature.

[0022] In this embodiment, a preset phase stability interval corresponding to the DC component is retrieved. This interval is calibrated based on the DC blocking device capacitance parameters and the transformer neutral point circuit impedance characteristics. The preset phase stability interval is 88° to 92°, with a tolerance range of ±2°. This preset interval is stored at a fixed address in a dedicated storage unit. During the retrieval process, the upper and lower limit values ​​of the interval and the tolerance parameters are read synchronously. After confirming that the parameters have not been tampered with, they are entered into the phase comparison stage. At the same time, the capacitive current phase difference data is retrieved. This capacitive current phase difference data contains the capacitive current phase difference values ​​of 1000 sampling points. Each sampling point is associated with a corresponding timestamp (accuracy: ms) to ensure the timing consistency of the comparison process.

[0023] It needs to be explained that the current-capacity phase difference is compared with the preset phase stability interval point by point. The comparison is performed sequentially from earliest to latest according to the timestamp. The comparison logic for a single sampling point is as follows: determine whether the current-capacity phase difference is greater than or equal to 88° and less than or equal to 92°. If this condition is met, the sampling point is marked as "within the interval"; otherwise, it is marked as "outside the interval". Simultaneously, continuous sampling count is started, beginning from the first sampling point marked as "within the interval". The count is incremented by 1 for each consecutive "within the interval" sampling point. If a single "outside the interval" sampling point appears, the count is immediately reset to zero and the count restarts. The statistical result is in units of timestamps and is stored synchronously with the timestamp of the corresponding sampling point.

[0024] The preset sampling threshold is 50 times, corresponding to a sampling duration of 50ms, which matches the sampling frequency of 1kHz (unit: Hz). This threshold is set based on the dynamic response characteristics of the loop, and the fluctuation amplitude judgment threshold is set to 5°. If the cumulative number of consecutive samples reaches 50 times and there is no "outside the interval" marker during the period, it is determined that the current flow phase difference is dominated by the DC component. If the current phase difference deviates from the stable phase range of 88° to 92°, and the fluctuation amplitude of the current phase difference between adjacent sampling points is greater than 5°, and this fluctuation state continues to occur for 10 or more sampling points, corresponding to a duration of 10ms, it is determined that the current flow phase difference is dominated by the AC component.

[0025] Optionally, the duration for which the statistical capacitive current phase difference maintains the stable characteristic of the DC component in step S2 is specifically as follows: Timing begins from the moment when the DC component is determined to be the dominant characteristic, and the characteristic state changes of the capacitive current phase difference are tracked in real time. If the characteristic state change continues to be dominated by the DC component, the timing duration will continue to accumulate; if the characteristic state change switches to be dominated by the AC component, the timing duration will be immediately reset to zero. When the timing reaches the preset stable duration threshold, the timing stops and the time of achievement is recorded; if the characteristic state changes during the timing process, the timing process is restarted.

[0026] In this embodiment, timing begins from the moment the current-capacitance phase difference is first determined to be dominated by the DC component. Timing relies on a clock module synchronized with the sampling system, with a timing accuracy set to 1ms. The timing start time is precisely aligned with the timestamp of the corresponding sampling point, and the starting timing timestamp is recorded synchronously. The characteristic state changes of the current-capacitance phase difference are tracked in real time, with the tracking frequency remaining consistent with the sampling frequency at 1kHz. The current-capacitance phase difference characteristic determination result for the current time period is extracted every 1ms. This result is derived based on a phase stability range of 88° to 92° and a threshold of 50 consecutive samplings.

[0027] It should be explained that the preset stabilization time threshold is 200ms. This threshold is based on the DC component attenuation characteristics of the transformer neutral point circuit and the capacitor response speed of the DC blocking device. At the same time, the characteristic state judgment interval is set to 1 sampling period (1ms). If the current extracted current phase difference characteristic judgment result is a DC component dominant feature, then 1ms is added to the accumulated time, and the accumulated time continues to accumulate. If the current extracted characteristic judgment result switches to an AC component dominant feature, that is, the current phase difference deviates from the 88° to 92° range or the fluctuation amplitude of adjacent sampling points is greater than 5°, then the current accumulated time is immediately cleared, and the timestamp of the clearing time and the reason for the characteristic state switch are recorded simultaneously.

[0028] Specifically, during the cumulative timing process, the current cumulative duration is compared with the stable duration threshold every 10ms to ensure timely capture of the target moment. When the cumulative timing duration reaches 200ms, timing is immediately stopped, the timestamp of the target moment is recorded, and the current cumulative timing duration is locked as the stable duration. This stable duration is stored in association with the original data of the current phase difference and the feature determination result. If the feature state changes from DC component dominance to AC component dominance during the timing process, after clearing the cumulative timing duration, it waits for the next determination of the DC component dominance feature. After the determination is successful again, the timing process is restarted, and the above tracking and accumulation operations are repeated.

[0029] Preferably, in step S3: if the phase difference of the capacitive current is dominated by the DC component, the current amplitude exceeds the standard, and the stable duration is up to the standard, the bypass switch of the DC blocking device is opened, and the capacitor of the DC blocking device is switched into the circuit between the neutral point of the transformer and the ground; if the phase difference of the capacitive current is dominated by the AC component, regardless of whether the current amplitude exceeds the standard, the bypass switch is kept closed and the capacitor is prohibited from being switched in. Optionally, step S3, checking whether the current amplitude exceeds the standard, includes: Retrieve the circuit current amplitude and determine the preset DC blocking switching reference amplitude; The loop current amplitude is compared with the DC blocking and switching reference amplitude. If the loop current amplitude is greater than the DC blocking and switching reference amplitude, it is marked as a single amplitude exceeding the standard. The system counts the number of consecutive instances of single current amplitude exceeding the limit. If the number of consecutive exceedances reaches the preset limit, the current amplitude is determined to be exceeding the limit; otherwise, the current amplitude is determined to be within the limit.

[0030] In this embodiment, the calculated and stored loop current amplitude of the transformer neutral point is retrieved. This loop current amplitude is the effective current value within each sampling period (1ms). During the retrieval process, the timestamp of the corresponding sampling point (with an accuracy of 1ms) is synchronously associated to ensure the time sequence of the current amplitude data is traceable. A preset DC blocking switching reference amplitude is determined. This DC blocking switching reference amplitude is calibrated based on the transformer's rated operating current, the neutral point grounding system's withstand capability, and the rated carrying current of the DC blocking device's capacitor. The preset DC blocking switching reference amplitude is 50A and is stored in the fixed parameter area of ​​a dedicated storage unit. When retrieving the reference amplitude, the parameter integrity is verified simultaneously. After confirming that there are no abnormalities, the numerical comparison step is entered.

[0031] The amplitude of the circuit current at the neutral point of the transformer is compared with the preset DC blocking switching reference amplitude in a sampling cycle. The comparison frequency is kept consistent with the sampling frequency at 1kHz. The comparison logic for a single sampling cycle is as follows: read the specific value of the circuit current amplitude in the current cycle and compare it with 50A. If the current circuit current amplitude is greater than 50A, then the sampling cycle is marked as a single amplitude exceeding the standard, and the timestamp and the specific value of the current amplitude in the cycle are recorded simultaneously. If the current circuit current amplitude is less than or equal to 50A, then a single amplitude exceeding the standard is not marked, and only the current current amplitude and the corresponding timestamp are recorded.

[0032] Specifically, the system initiates a count of consecutive exceedances, starting from the first sampling period marked as a single instance of amplitude exceeding the limit. For each consecutive sampling period with a single instance of amplitude exceeding the limit, the count is incremented by 1. If an unmarked single instance of amplitude exceeding the limit occurs, the current cumulative count is immediately reset to zero, and the count restarts. The unit of count is times. The preset number of exceedances is 60, corresponding to a cumulative duration of 60ms, matching the 1kHz sampling frequency. This threshold is set based on the loop current fluctuation characteristics to avoid misjudgments caused by instantaneous current surges. If the cumulative number of consecutive exceedances reaches 60, the transformer neutral point loop current amplitude is determined to be exceeding the limit during the current time period. If the cumulative number of consecutive exceedances does not reach 60, or if the count is reset during the statistical process, the transformer neutral point loop current amplitude is determined to be within the limit during the current time period.

[0033] Optionally, in step S3, if the current phase difference exhibits a DC component-dominated characteristic, the current amplitude exceeds the standard, and the stable duration exceeds the standard, the bypass switch of the DC blocking device is controlled to trip specifically as follows: If the three conditions of DC component dominating current phase difference, excessive current amplitude and stable duration are met simultaneously, a bypass switch tripping trigger signal is generated. Send the tripping trigger signal to the switch execution terminal and detect the signal reception status of the switch execution terminal; If the trip trigger signal is not successfully received, the trip trigger signal will be resent. If the tripping trigger signal is successfully received, the position change of the bypass switch is monitored in real time. When the switch position changes from the closed position to the open position, the tripping action is confirmed to be completed, and the time point when the switch tripping is completed is recorded.

[0034] In this embodiment, the status results of three judgment conditions are read synchronously in real time: the judgment result of the dominant characteristic of the capacitive current phase difference, the judgment result of the transformer neutral point circuit current amplitude exceeding the standard, and the judgment result of the stable duration of the capacitive current phase difference maintaining the dominant characteristic of the DC component. All three results are associated with the timestamp of the corresponding time period (accuracy 1ms). When the three conditions are met simultaneously, the capacitive current phase difference is continuously in the range of 88° to 92° (dominant characteristic of the DC component), the current amplitude is greater than 50A for 60 consecutive sampling periods (60ms) (current amplitude exceeding the standard), and the stable duration reaches 200ms cumulatively (stable duration reaches the standard), the trip signal generation process is triggered. The generated bypass switch trip trigger signal is a DC 24V level signal with a pulse width set to 200ms and the pulse rise and fall slopes both set to 1V / μs.

[0035] In one embodiment, the tripping trigger signal is transmitted to the bypass switch execution terminal via a shielded cable. The characteristic impedance of the transmission cable is matched to 50Ω (unit: ohms), and the transmission distance is controlled within 5 meters. Differential transmission is used to suppress electromagnetic interference during signal transmission. Signal detection nodes are set at both the signal transmission port and the switch execution terminal. The transmitting end immediately detects the output level after sending the signal, and the execution terminal sends back a DC 12V acknowledgment signal after receiving the signal. The feedback signal transmission delay is set to a threshold of 10ms. If the transmitting end does not receive the acknowledgment signal from the execution terminal within 10ms, it is determined that the tripping trigger signal has not been successfully received, and the tripping trigger signal is retransmitted after an interval of 50ms. The maximum number of retransmissions is set to 3.

[0036] In another embodiment, if the transmitting end receives a 12V acknowledgment signal from the executing end within 10ms, it is determined that the tripping trigger signal has been successfully received. Simultaneously, bypass switch position monitoring is initiated. A displacement sensor installed on the switch body collects switch position data in real time. The displacement sensor has a measurement range of 0 to 50 mm and a resolution of 0.1 mm, where the closed position corresponds to a displacement value of 0 mm and the open position corresponds to a displacement value of 30 mm. The position monitoring frequency is set to 100Hz, and switch displacement data is collected every 10ms. When the displacement value collected for three consecutive times stabilizes at 30 mm, it is determined that the switch position has switched from the closed position to the open position, confirming the completion of the tripping action. The timestamp of the tripping completion moment is recorded synchronously. This timestamp is stored in association with the tripping trigger signal transmission time, the period of current amplitude exceeding the standard, and the time of stabilization reaching the standard, providing a timing basis for subsequent capacitor switching operations.

[0037] Optionally, step S3, which involves connecting the capacitor of the DC blocking device into the circuit between the transformer neutral point and ground, includes: After confirming that the bypass switch has been opened, check the initial voltage across the capacitor; The initial voltage is compared with the preset safe voltage range. If the initial voltage is within the safe range, the capacitor connection process is started, and the continuity of the circuit between the transformer neutral point and ground is monitored in real time. After the circuit conductivity stabilizes, complete the series connection of the capacitor and the circuit; The voltage and current parameters of the circuit after connection are detected. If the voltage and current parameters are within the preset operating range, the capacitor connection is confirmed to be successful.

[0038] In this embodiment, after confirming that the bypass switch has been opened, a capacitive voltage divider sensor with a range of 0 to 20kV and an accuracy class of 0.2 is directly connected to the terminals of the DC blocking device capacitor to collect the initial voltage across the capacitor. The sampling frequency is set to 100Hz, and a set of initial voltage data is acquired every 10ms. Ten sets of data are continuously collected, and the arithmetic mean is taken as the final initial voltage value. This value is stored in association with the timestamp of the opening completion time (accuracy 1ms), and the timestamp is synchronized with the clock reference of the sampling system mentioned above.

[0039] The preset safe range for the initial capacitor voltage is determined to be 0 to 1000V. The calculated average initial voltage is compared with this safe range. If the average initial voltage is within the 0 to 1000V range, the capacitor connection process is initiated. Simultaneously, a loop continuity detection circuit based on Ohm's law is used to monitor the continuity of the loop between the transformer neutral point and ground. The input voltage of the monitoring circuit is set to DC 12V, and the output voltage threshold is set to 5V. When the output voltage of the monitoring circuit remains stable at 5V, the loop is considered to have a basis for conduction. The monitoring frequency is 100Hz, consistent with the initial voltage acquisition frequency, and a continuity status determination is performed every 10ms.

[0040] After 30 consecutive continuity tests (corresponding to a duration of 300ms), the circuit continuity is considered stable. At this point, the capacitor connection actuator is activated, driving the capacitor connection contact. The contact travel is set to 20mm, and the action completion time is controlled within 50ms. After the connection operation is completed, the same voltage sensor and Rogowski coil current sensor (range 0 to 100A, accuracy class 0.2) are used to collect the voltage and current parameters of the connected circuit. The monitoring frequency is set to 1kHz, acquiring one set of data every 1ms. The preset normal operating range of the circuit is voltage 0 to 12kV and current 0 to 80A. When the voltage parameters are all within the 0 to 12kV range and the current parameters are all within the 0 to 80A range for 50 consecutive tests, the parameters are considered to meet the requirements, confirming successful capacitor connection.

[0041] Optionally, in step S3, if the current phase difference is dominated by the AC component, the bypass switch is kept closed regardless of whether the current amplitude exceeds the limit, including: After determining that the AC component is the dominant characteristic, a bypass switch closing and holding signal is generated; The closing holding signal is continuously output to the bypass switch execution terminal, and the closing position feedback of the bypass switch execution terminal is detected in real time. If the feedback signal indicates that the switch is deviating from the closed position, adjust the signal output strength; if the feedback signal indicates that the switch is in the closed position, maintain a stable signal output. Regularly verify the effectiveness of the switch's closed state and keep the bypass switch always in the closed state.

[0042] In this embodiment, after determining that the phase difference of the current-capacitance circuit exhibits a dominant AC component, the bypass switch closing and holding signal generation process is immediately triggered. This determination is based on the previously preset phase stability range (88° to 92°), fluctuation amplitude threshold (5°), and continuous sampling count (10 times, corresponding to 10ms). The generated closing and holding signal is a continuous DC 24V signal with an output impedance set to 50Ω, matching the impedance of the bypass switch's execution coil. The signal generation circuit is powered by a voltage regulator module, and the power supply voltage fluctuation is controlled within ±0.5V to ensure signal amplitude stability.

[0043] The closing holding signal is continuously output to the bypass switch actuator via a differential shielded cable, with the transmission distance controlled within 5 meters. The cable shield is grounded at one end to suppress electromagnetic interference. Simultaneously, a displacement sensor (measuring range 0 to 50 mm, unit: millimeters, resolution 0.1 mm) installed on the switch body detects the closing position feedback at the bypass switch actuator in real time. The displacement value corresponding to the closing position is preset to 0 mm, and the position feedback signal transmission frequency is set to 100 Hz, with displacement data collected every 10 ms. If the collected displacement data is greater than 0.5 mm, it is determined that the feedback signal indicates the switch has deviated from the closing position. Immediately, signal output strength adjustment is initiated, gradually increasing the output voltage in increments of 0.5V until the displacement data falls back to the 0 mm to 0.5 mm range. If the displacement data stabilizes within the 0 mm to 0.5 mm range, the switch is determined to be in the closing position, maintaining the current 24V voltage output to ensure stable signal output.

[0044] It should be noted that the periodic verification cycle is set to 1 second. A verification of the switch closing status validity is performed every 1 second. The verification process involves briefly increasing the closing holding signal amplitude to 26V for 20ms, while simultaneously monitoring changes in displacement feedback data. If the displacement data remains within the 0mm to 0.5mm range during the verification process, the closing status is considered valid, and the output is restored to a stable 24V after verification. If the displacement data exceeds 0.5mm during verification, the signal output strength is immediately increased to 28V for 300ms until the displacement data returns to the acceptable range. The verification timestamp, signal adjustment parameters, and displacement feedback data are recorded simultaneously. Throughout the process, the closing holding signal amplitude, switch displacement data, and timestamp are recorded synchronously at a frequency of 1kHz to ensure traceability of all parameters and maintain the bypass switch in a closed state.

[0045] Most importantly, if the feedback signal indicates the switch is deviating from the closed position, the signal output strength is adjusted; if the feedback signal indicates the switch is in the closed position, a stable signal output is maintained. Specifically: Real-time analysis of feedback signals, extraction of switch position deviation values, and comparison with preset closing reference position differences; If the switch position deviation exceeds the preset closing reference position difference, the graded adjustment mechanism is activated, increasing the rated output amplitude by 5% for each grade according to the switch position deviation. Synchronously collect line voltage loss data and dynamically compensate output power according to the loss ratio to offset the signal attenuation caused by line impedance until the deviation value falls back to within the threshold and is maintained for 3 sampling cycles. If the switch is in the closed position, lock the current signal amplitude and frequency parameters, periodically superimpose a test signal whose signal amplitude fluctuation does not exceed 3% of the rated value, and monitor whether the switch position feedback deviation exceeds 0.5mm; If there is no deviation in the switch position feedback, the parameters remain unchanged. If the switch position feedback deviation exceeds the range, the signal phase is finely adjusted in 0.1° steps.

[0046] In this embodiment, the bypass switch position feedback signal receiving channel is activated. The feedback signal is output by the switch body displacement sensor (measuring range 0-50mm, resolution 0.1mm), and connected to the signal conditioning unit via a shielded cable. The conditioning unit utilizes a second-order low-pass filter circuit (filter cutoff frequency 500Hz) and a differential amplifier module (amplification factor 200x). The potentiometer in the conditioning unit is adjusted to calibrate the signal amplitude and filter high-frequency interference signals. The conditioned feedback signal is read in real time through the signal analysis interface, and the current displacement data of the transformer neutral point bypass switch is extracted. The difference between this data and the preset closing reference position (0mm) is calculated to obtain the switch position deviation value. The preset closing reference position difference threshold is 0.5mm. The deviation value and corresponding timestamp are recorded every 1ms (sampling period).

[0047] The real-time calculated switch position deviation is compared with a 0.5mm threshold. If the deviation is greater than 0.5mm, the graded adjustment relay in the signal conditioning unit is immediately closed, initiating graded adjustment of the signal output strength. The rated output amplitude of the closing holding signal is preset to 24V. Graded voltage boosting is achieved through the adjustable power supply (output range 0-30V, accuracy 0.1V) in the adjustment unit, with each stage increasing by 5% of the rated amplitude (single stage increase 1.2V). After each stage adjustment, a stable output is maintained for 10ms. During this period, the voltage across the line is collected by a voltage sensor (range 0-30V, accuracy 0.2) connected in series in the signal transmission line, and the voltage loss value is calculated (loss value = power supply output voltage - switch execution voltage). The power supply adjustment knob is adjusted according to the proportion of loss to rated voltage (loss proportion = loss value / 24V × 100%) to dynamically compensate the output power until the switch position deviation value falls back to the 0-0.5mm range, and this range is met for 3 consecutive samplings (1ms interval).

[0048] If the switch displacement data from three consecutive samplings are all within the 0-0.5mm range, the switch is determined to be in the closed position. Tighten the signal parameter locking knob to fix the current signal output amplitude (24V) and frequency (50Hz). The test signal is superimposed using the signal superposition unit at 200ms intervals. The amplitude adjustment knob of the superposition unit is adjusted to ensure that the test signal amplitude fluctuation is ≤3% of the rated output amplitude (maximum fluctuation amplitude 0.72V), with each superposition lasting 20ms. During the superposition of the test signal, the switch position feedback deviation is monitored in real time at a 1kHz frequency using the displacement sensor. If the deviation is consistently ≤0.5mm, the positions of all adjustment knobs remain unchanged. If the deviation is >0.5mm, the signal phase is fine-tuned in 0.1° steps using the phase adjustment knob, with monitoring maintained for 10ms after each adjustment, until the switch position feedback deviation returns to the 0-0.5mm range. The potentiometer position, phase value, deviation data, and timestamp are recorded simultaneously for each adjustment, completing the signal stabilization control operation.

[0049] Of particular importance is that step S3 prohibits capacitor switching in the following ways: While outputting the bypass switch closing and holding signal, a capacitor cut-in prohibition signal is generated; Transmit the capacitor cut-in disable signal to the capacitor access control link, cut off the signal transmission channel of the capacitor access control link, and detect the on / off status of the control link in real time. If the link is in the on state, the capacitor cut-in prohibition signal is sent again; if the link is in the off state, the prohibition command is confirmed to be effective, and the duration of the prohibition command is recorded.

[0050] In this embodiment, while the bypass switch closing and holding signal is being output, the capacitor insertion prohibition signal generation operation is simultaneously triggered. The closing and holding signal is a 24V DC continuous level signal, and the capacitor insertion prohibition signal is set to a DC 0V low level signal. The signal pulse width is set to 500ms, and the rise and fall slopes of the pulse are both set to 1V / μs. The signal output impedance is set to 50Ω to match the impedance of the capacitor access control link. After the prohibition signal is generated, it is transmitted through an independent shielded cable with the transmission distance controlled within 5 meters. The cable shield is grounded at one end and is laid parallel to the closing and holding signal transmission cable, with a spacing of more than 0.3 meters to avoid signal interference.

[0051] A capacitor is connected to the signal input terminal of the control link via a cut-off signal. A signal cut-off relay is installed within the link, with a relay trigger threshold set to 0.5V. When a cut-off signal (0V) is input, the relay immediately activates, cutting off the transmission channel of the capacitor-connected trigger signal in the control link. Simultaneously, voltage monitoring points are installed on both sides of the link cut-off node. Voltage sensors with a range of 0-30V (unit: volt) and an accuracy class of 0.2 are used to detect the on / off status of the control link in real time. The monitoring frequency is set to 1kHz, and voltage data from both monitoring points is collected every 1ms. The voltage difference (difference = input voltage - output voltage) is calculated. The preset link disconnection threshold is 20V, and the on / off threshold is 1V.

[0052] If the collected voltage difference is less than 1V, the capacitor access control link is determined to be in a conducting state, and the capacitor access prohibition signal is immediately resent. The resentment interval is set to 100ms, and monitoring continues for 20ms after each resentment. The maximum number of resentments is set to 5. If the collected voltage difference is greater than 20V, the link is determined to be in a disconnected state, the capacitor access prohibition command is confirmed to be effective, and the prohibition duration timer is started simultaneously with a timing accuracy of 1ms. During the period when the prohibition command is effective, the link on / off status is checked every 100ms, and voltage difference data is continuously collected. If the voltage difference drops below 1V during the check, the prohibition signal is repeatedly sent until the link is disconnected again. The time of each signal transmission, the link on / off status data, and the duration of the prohibition command are recorded simultaneously to ensure that the prohibition command remains effective.

[0053] Preferably, in step S4: after the capacitor of the DC blocking device is switched into the circuit between the transformer neutral point and ground, the capacitive current phase difference extraction, component dominance feature identification and current amplitude verification are continuously performed; when the capacitive current phase difference deviates from the DC component dominance feature or the current amplitude is lower than the preset DC blocking switching reference, the bypass switch is controlled to close and the capacitor is removed, and the transformer neutral point is restored to direct grounding.

[0054] Of particular importance is that, after the capacitor of the DC blocking device is connected to the circuit between the transformer neutral point and ground in step S4, the continuous execution of capacitive current phase difference extraction, component dominant feature identification, and current amplitude verification includes: After confirming that the capacitor is connected to the circuit and its operating state is stable, the dynamic sampling mechanism is activated. The adaptive sampling frequency is used to synchronously collect the capacitor terminal voltage and the transformer neutral point circuit current. When the current amplitude is abnormal, the sampling frequency is increased; when the current amplitude is normal, the sampling frequency is decreased. The acquired voltage and current signals are subjected to real-time noise reduction and filtering to preserve the fundamental frequency components; The phase difference between the current and the filtered voltage and current signals is calculated, and the dominance of the component is determined by the phase fluctuation amplitude. When the phase fluctuation amplitude is less than the preset fluctuation amplitude value, it is determined that the DC component is dominant. The effective value of the current signal is converted to obtain the real-time loop current amplitude.

[0055] In this embodiment, after confirming that the capacitor of the DC blocking device is connected to the circuit between the transformer neutral point and ground, and that the circuit voltage parameters (0-12kV) and current parameters (0-80A) of 50 consecutive samples (sampling period 1ms) are all within the preset operating range, the dynamic sampling mechanism is activated. A voltage sensor (range 0-20kV, accuracy class 0.2) and a current sensor (range 0-100A, accuracy class 0.2) are connected to the terminals at both ends of the capacitor and the transformer neutral point circuit, respectively, to synchronously collect the capacitor terminal voltage and the transformer neutral point circuit current. The preset abnormal current amplitude threshold is 80A, the normal operating threshold range is 0-80A, and the adaptive sampling frequency reference is set to 1kHz (unit: Hertz). Frequency adjustment is achieved through a sampling frequency switching switch. When the collected current amplitude is greater than 80A, the switching switch activates, increasing the sampling frequency to 2kHz; when the current amplitude falls back to the 0-80A range and stabilizes for 3 sampling periods (3ms), the switching switch resets, reducing the sampling frequency to 1kHz.

[0056] The dynamically acquired capacitor terminal voltage signal and transformer neutral point circuit current signal are subjected to real-time noise reduction and filtering. A noise reduction unit is built using a second-order low-pass filter circuit. The filter cutoff frequency is adaptively matched according to the sampling frequency; the cutoff frequency is adjusted to 500Hz for 1kHz sampling and to 1kHz for 2kHz sampling. The potentiometer on the filter circuit is adjusted to filter high-frequency interference signals and random noise, retaining only the 50Hz fundamental frequency component. The amplitude fluctuation of the filtered signal is controlled within 2% of the original signal amplitude. The signal data before and after filtering, as well as the corresponding timestamps (accuracy 1ms, unit: milliseconds), are recorded simultaneously.

[0057] Based on the filtered capacitor terminal voltage signal and the transformer neutral point circuit current signal, the capacitive-current phase difference is calculated. The calculation method follows the principle of subtracting the fundamental phase value of the current from the fundamental phase value of the voltage, with the difference range normalized to -180° to 180° (unit: degrees). The preset phase fluctuation amplitude judgment threshold is 5°. The phase difference value of adjacent sampling points is continuously collected by the phase monitoring unit to obtain the real-time phase fluctuation amplitude. When the phase fluctuation amplitude is less than 5° and lasts for 10 sampling cycles (10ms), it is judged as a DC component dominant feature. At the same time, the effective value of the filtered current signal is converted. The conversion process is to square the data of every 10 consecutive sampling points, take the arithmetic mean, and then take the square root of the mean to obtain the real-time transformer neutral point circuit current amplitude. The conversion result is uniformly expressed in amperes (A) and is stored synchronously in a dedicated storage unit with the capacitive-current phase difference and component dominant feature judgment results.

[0058] Optionally, in step S4, when the phase difference of the capacitive current deviates from the dominant characteristic of the DC component or the current amplitude is lower than the preset DC blocking switching reference, controlling the bypass switch to close and disconnect the capacitor, restoring the transformer neutral point to direct grounding includes: After determining that the phase difference of the current deviates from the dominant characteristic of the DC component or the current amplitude is lower than the preset DC blocking switching reference, a bypass switch closing trigger signal is generated. Send a closing trigger signal to the switch execution terminal and monitor the entire process of the switch execution terminal switching from the open position to the closed position; After confirming that the switch is closed, disconnect the power supply to the capacitor and check whether the capacitor is completely disconnected from the circuit. After confirming that the capacitor has been removed, check the grounding continuity of the transformer neutral point. If the grounding continuity is normal, confirm that the neutral point has been directly grounded.

[0059] In this embodiment, the determination result of the dominant characteristic of the capacitive current phase difference and the amplitude of the real-time transformer neutral point circuit current are read in real time. When the fluctuation amplitude of the capacitive current phase difference is greater than 5° and lasts for 10 sampling cycles (10ms), it is determined that the capacitive current phase difference has deviated from the dominant characteristic of the DC component. The preset DC blocking switching reference amplitude is 50A. When the real-time circuit current amplitude is less than 50A and lasts for 30 sampling cycles (30ms), it is determined that the current amplitude is lower than the reference. After any of the above determination conditions are met, the bypass switch closing trigger signal is immediately triggered. The signal type is a DC 24V level signal, the pulse width is set to 300ms, the pulse rise and fall slopes are both set to 1V / μs, and the output impedance is matched to 50Ω to adapt to the impedance of the bypass switch execution terminal.

[0060] The closing trigger signal is transmitted to the bypass switch actuator via a differential shielded cable, with the transmission distance controlled within 5 meters. The cable shield is grounded at one end to suppress electromagnetic interference. After the signal is sent, the switch position change is monitored in real time by a displacement sensor on the switch body (measuring range 0-50mm, resolution 0.1mm). The displacement value corresponds to 30mm for the open position and 0mm for the closed position. The monitoring frequency is set to 100Hz, and displacement data is collected every 10ms. The entire process of the switch switching from the open position to the closed position is tracked. When the displacement data collected for 5 consecutive times is stable in the 0-0.5mm range, the bypass switch is considered to have closed successfully. The timestamp of the closing completion moment is recorded synchronously (accuracy 1ms), and the timestamp is synchronized with the sampling system clock.

[0061] After confirming the bypass switch is closed, immediately operate the capacitor power supply disconnect switch to cut off the power supply to the DC blocking device capacitor. After a 200ms delay, the voltage across the capacitor is detected by a voltage sensor (range 0-20kV, accuracy 0.2). Simultaneously, the connection status between the capacitor and the transformer neutral point circuit is detected by a circuit continuity detection circuit at a frequency of 1kHz. When the voltage across the capacitor drops below 100V and the output voltage of the circuit continuity detection circuit is greater than 20V, it is determined that the capacitor is completely disconnected from the circuit. Subsequently, the transformer neutral point grounding continuity detection is initiated using a continuity detection circuit with an input voltage set to DC 12V and an output voltage threshold of 5V. When the output voltage of the detection circuit stabilizes at 5V for 50 sampling cycles (50ms), the grounding continuity status is determined to be normal, and the transformer neutral point is confirmed to be directly grounded. The timestamp of the grounding restoration completion is recorded synchronously and stored in association with the timestamps of the closing and capacitor disconnection.

[0062] Please see Figure 2 The figure shows the synchronous time-domain waveforms of the capacitor terminal voltage and the transformer neutral point loop current during the operation of the DC blocking device. The horizontal axis represents time (in seconds), the left vertical axis represents the capacitor terminal voltage (in V), and the right vertical axis represents the loop current (in V). Figure 2 The red curve represents the capacitor terminal voltage waveform, and the cyan curve represents the loop current waveform. Both exhibit a 50Hz power frequency periodic fluctuation characteristic, with the voltage phase leading the current phase, corresponding to the basis for calculating the capacitive-current phase difference in this invention. The phase shift relationship between voltage and current can be observed from the waveforms. Combined with the stable fluctuation of the waveform amplitude, this reflects that the capacitive-current phase difference is in the DC component-dominated characteristic range under the current operating conditions.

[0063] The present invention also provides a DC blocking device control system for executing the above-described DC blocking device control method, the DC blocking device control system comprising: The data acquisition module is used to acquire the capacitor terminal voltage and the loop current at the neutral point of the transformer in the DC blocking device, and to obtain the loop current amplitude. The phase analysis module is used to calculate the phase difference between the capacitor terminal voltage and the loop current to obtain the capacitive current phase difference; based on the capacitive current phase difference, it divides the DC component dominance feature into the AC component dominance feature; and it calculates the stable duration of the capacitive current phase difference maintaining the DC component dominance feature. The switching control module is used to control the bypass switch of the DC blocking device to open and switch the capacitor of the DC blocking device into the circuit between the transformer neutral point and ground if the phase difference of the capacitive current is dominated by the DC component, the current amplitude exceeds the standard and the stable time is up to the standard. If the phase difference of the capacitive current is dominated by the AC component, the bypass switch is kept closed and the capacitor is prohibited from being switched in, regardless of whether the current amplitude exceeds the standard. The monitoring and reset module is used to continuously perform capacitive current phase difference extraction, component dominance feature identification, and current amplitude verification after the capacitor of the DC blocking device is switched into the circuit between the transformer neutral point and ground. When the capacitive current phase difference deviates from the DC component dominance feature or the current amplitude is lower than the preset DC blocking switching reference, the bypass switch is controlled to close and the capacitor is removed, restoring the transformer neutral point to direct grounding.

[0064] Please see Figure 3 This is the real-time monitoring and intelligent control platform interface for the DC blocking device control system, fully presenting the operational status of the core control process of this invention. The data acquisition module displays the current capacitor terminal voltage as 8.13kV and the loop current amplitude as 57.6A (exceeding the 50A switching reference); the phase analysis module displays the capacitive current phase difference as 90.7°, which is within the phase stability range dominated by the DC component, and the dominant feature is determined to be the DC component; the switching control module displays that the bypass switch is in the open state, the capacitor is not connected, and switching is allowed; the monitoring and reset module displays that both phase and current monitoring are normal. The real-time curves below respectively show the stable fluctuation of the capacitive current phase difference and the changing trend of the loop current amplitude, intuitively reflecting that the current triggering conditions for capacitor switching are met.

[0065] Therefore, the embodiments should be considered as exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of the equivalents of the application are intended to be included within the invention.

[0066] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features of the invention herein.

Claims

1. A method for controlling a DC blocking device, characterized in that, Includes the following steps: Step S1: Collect the capacitor terminal voltage in the DC blocking device and the loop current at the neutral point of the transformer to obtain the loop current amplitude; Step S2: Calculate the phase difference between the capacitor terminal voltage and the loop current to obtain the capacitive current phase difference; based on the capacitive current phase difference, divide the DC component dominance characteristic and the AC component dominance characteristic. The duration during which the statistical capacitive phase difference maintains the stable characteristics dominated by the DC component; Step S3: If the phase difference of the capacitive current is dominated by the DC component, the current amplitude exceeds the standard, and the stable duration is up to the standard, control the bypass switch of the DC blocking device to open, and switch the capacitor of the DC blocking device into the circuit between the transformer neutral point and ground; if the phase difference of the capacitive current is dominated by the AC component, regardless of whether the current amplitude exceeds the standard, keep the bypass switch closed and prohibit the capacitor from being switched in. Step S4: After the capacitor of the DC blocking device is connected to the circuit between the transformer neutral point and ground, the capacitive current phase difference extraction, component dominance feature identification and current amplitude verification are continuously performed; when the capacitive current phase difference deviates from the DC component dominance feature or the current amplitude is lower than the preset DC blocking switching reference, the bypass switch is controlled to close and the capacitor is removed, and the transformer neutral point is restored to direct grounding.

2. The DC blocking device control method according to claim 1, characterized in that, In step S2, the phase difference between the capacitor terminal voltage and the loop current is calculated, and the capacitive current phase difference includes: Synchronous, equally spaced time-domain sampling is performed on the capacitor terminal voltage signal and the transformer neutral point circuit current signal; Voltage and current sampling sequences of the same duration are extracted, and harmonic analysis is performed on the two sets of sampling sequences to extract the phase parameters of the fundamental voltage and fundamental current components. Calculate the difference between the fundamental phase of the voltage and the fundamental phase of the current, and remove abnormal data that exceed the reasonable phase range from the difference; define the processed difference as the capacitive current phase difference.

3. The DC blocking device control method according to claim 1, characterized in that, The characteristics of distinguishing between DC-dominant and AC-dominant components based on the capacitive phase difference in step S2 include: Retrieve the preset phase stability range corresponding to the DC component; The current phase difference is compared with the phase stability interval point by point, and the number of consecutive samples in which the current phase difference is within the interval is counted. If the number of consecutive samples equals the preset sampling threshold, it is determined to be a DC component dominant feature; if the current phase difference deviates from the range and the fluctuation amplitude is greater than the preset sampling threshold, it is determined to be an AC component dominant feature.

4. The DC blocking device control method according to claim 1, characterized in that, The specific duration for which the statistical capacitive current phase difference maintains the stable characteristic of the DC component in step S2 is as follows: Timing begins from the moment when the DC component is determined to be the dominant characteristic, and the characteristic state changes of the capacitive current phase difference are tracked in real time. If the characteristic state change is dominated by the DC component, the timing duration will continue to accumulate. If the characteristic state changes to be dominated by the AC component, the timer duration is immediately reset to zero. When the timing reaches the preset stable duration threshold, the timing stops and the time of achievement is recorded; if the characteristic state changes during the timing process, the timing process is restarted.

5. The DC blocking device control method according to claim 1, characterized in that, Step S3, checking whether the current amplitude exceeds the standard, includes: Retrieve the circuit current amplitude and determine the preset DC blocking switching reference amplitude; The loop current amplitude is compared with the DC blocking and switching reference amplitude. If the loop current amplitude is greater than the DC blocking and switching reference amplitude, it is marked as a single amplitude exceeding the standard. The system counts the number of consecutive instances of single current amplitude exceeding the limit. If the number of consecutive exceedances reaches the preset limit, the current amplitude is determined to be exceeding the limit; otherwise, the current amplitude is determined to be within the limit.

6. The DC blocking device control method according to claim 1, characterized in that, In step S3, if the current phase difference exhibits a DC component-dominated characteristic, the current amplitude exceeds the standard, and the stable duration exceeds the standard, the bypass switch of the DC blocking device is controlled to trip as follows: If the three conditions of DC component dominating current phase difference, excessive current amplitude and stable duration are met simultaneously, a bypass switch tripping trigger signal is generated. Send the tripping trigger signal to the switch execution terminal and detect the signal reception status of the switch execution terminal; If the trip trigger signal is not successfully received, the trip trigger signal will be resent. If the tripping trigger signal is successfully received, the position change of the bypass switch is monitored in real time. When the switch position changes from the closed position to the open position, the tripping action is confirmed to be completed, and the time point when the switch tripping is completed is recorded.

7. The DC blocking device control method according to claim 1, characterized in that, Step S3, which involves connecting the capacitor of the DC blocking device into the circuit between the transformer neutral point and ground, includes: After confirming that the bypass switch has been opened, check the initial voltage across the capacitor; The initial voltage is compared with the preset safe voltage range. If the initial voltage is within the safe range, the capacitor connection process is started, and the continuity of the circuit between the transformer neutral point and ground is monitored in real time. After the circuit conductivity stabilizes, complete the series connection of the capacitor and the circuit; The voltage and current parameters of the circuit after connection are detected. If the voltage and current parameters are within the preset operating range, the capacitor connection is confirmed to be successful.

8. The DC blocking device control method according to claim 1, characterized in that, In step S3, if the phase difference of the capacitive current exhibits a dominant AC component, the bypass switch remains closed regardless of whether the current amplitude exceeds the limit, including: After determining that the AC component is the dominant characteristic, a bypass switch closing and holding signal is generated; The closing holding signal is continuously output to the bypass switch execution terminal, and the closing position feedback of the bypass switch execution terminal is detected in real time. If the feedback signal indicates that the switch is deviating from the closed position, adjust the signal output strength; if the feedback signal indicates that the switch is in the closed position, maintain a stable signal output. Regularly verify the effectiveness of the switch's closed state and keep the bypass switch always in the closed state.

9. The DC blocking device control method according to claim 1, characterized in that, In step S4, when the phase difference between the capacitive and current components deviates from the dominant characteristic of the DC component or the current amplitude is lower than the preset DC blocking switching reference, the bypass switch is closed to disconnect the capacitor and restore the transformer neutral point to direct grounding, including: After determining that the phase difference of the current deviates from the dominant characteristic of the DC component or the current amplitude is lower than the preset DC blocking switching reference, a bypass switch closing trigger signal is generated. Send a closing trigger signal to the switch execution terminal and monitor the entire process of the switch execution terminal switching from the open position to the closed position; After confirming that the switch is closed, disconnect the power supply to the capacitor and check whether the capacitor is completely disconnected from the circuit. After confirming that the capacitor has been removed, check the grounding continuity of the transformer neutral point. If the grounding continuity is normal, confirm that the neutral point has been directly grounded.

10. A DC blocking device control system, characterized in that, For performing the DC blocking device control method as described in claim 1, the DC blocking device control system includes: The data acquisition module is used to acquire the capacitor terminal voltage and the loop current at the neutral point of the transformer in the DC blocking device, and to obtain the loop current amplitude. The phase analysis module is used to calculate the phase difference between the capacitor terminal voltage and the loop current to obtain the capacitive current phase difference; based on the capacitive current phase difference, it divides the DC component dominance feature into the AC component dominance feature; and it calculates the stable duration of the capacitive current phase difference maintaining the DC component dominance feature. The switching control module is used to control the bypass switch of the DC blocking device to open and switch the capacitor of the DC blocking device into the circuit between the transformer neutral point and ground if the phase difference of the capacitive current is dominated by the DC component, the current amplitude exceeds the standard and the stable time is up to the standard. If the phase difference of the capacitive current is dominated by the AC component, the bypass switch is kept closed and the capacitor is prohibited from being switched in, regardless of whether the current amplitude exceeds the standard. The monitoring and reset module is used to continuously perform capacitive current phase difference extraction, component dominance feature identification, and current amplitude verification after the capacitor of the DC blocking device is switched into the circuit between the transformer neutral point and ground. When the capacitive current phase difference deviates from the DC component dominance feature or the current amplitude is lower than the preset DC blocking switching reference, the bypass switch is controlled to close and the capacitor is removed, restoring the transformer neutral point to direct grounding.

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