Short circuit and overload protection circuit and air conditioner

Abstract

The application discloses a short-circuit and overload protection circuit and an air conditioner. The short-circuit and overload protection circuit comprises a SiC MOSFET module, the SiC MOSFET module has a Kelvin source pin connected with a power source pin, a parasitic inductance is connected in series between the Kelvin source pin and the power source pin, the short-circuit and overload protection circuit at least comprises a current sampling unit for detecting a current change rate on the parasitic inductance, and a short-circuit detection unit connected with the current sampling unit, the short-circuit detection unit is used for judging whether the SiC MOSFET module has a short-circuit fault according to a sampling result of the current sampling unit. Compared with the prior art, the application relates to a metal oxide semiconductor field effect transistor, which utilizes the parasitic inductance as a current detection element, does not need to set a blanking time, and realizes a nanosecond-level fault response.

Description

Technical Field

[0001] This invention relates to metal-oxide-semiconductor field-effect transistors, and in particular to a short-circuit and overload protection circuit and an air conditioner. Background Technology

[0002] Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs), as representatives of third-generation wide-bandgap power semiconductor devices, have shown significant advantages in high-voltage, high-power, and high-frequency applications such as electric vehicles, smart grids, renewable energy inverters, and rail transportation due to their high switching frequency, low switching loss, high breakdown voltage, and excellent high-temperature stability. They are gradually replacing traditional silicon-based insulated-gate bipolar transistors (IGBTs).

[0003] However, the widespread application of SiC MOSFET modules poses serious challenges to their drive and protection circuits. First, the small chip area and high current density of SiC MOSFET modules result in extremely short short-circuit withstand times, typically only 2-7 microseconds, far lower than the 10 microseconds or more of silicon-based insulated-gate bipolar transistors. SiC MOSFET modules exhibit "soft saturation" characteristics during short circuits, with the drain current continuously rising during the fault period instead of saturating. This makes the traditional desaturation detection method (borrowed from IGBT protection) slow to respond and difficult to achieve fast protection. If the protection time exceeds its short-circuit withstand time, it may damage the SiC MOSFET module.

[0004] Furthermore, in addition to short-circuit faults, prolonged overload operation can lead to heat accumulation inside the device, eventually causing thermal escape failure. However, most existing protection schemes only focus on short-circuit protection and lack effective monitoring methods for overload failure.

[0005] Finally, when a short-circuit fault occurs in the SiC MOSFET module, the excessively high current drop rate will induce a huge voltage spike on the stray inductance of the loop, which may break down the SiC MOSFET module. At the same time, the fault signal may disappear during the turn-off process due to the drop in current, causing the protection circuit to repeatedly operate and the system to fall into oscillation.

[0006] Therefore, how to design a short-circuit and overload protection circuit and air conditioner that can solve the above problems is a technical problem that the industry urgently needs to solve. Summary of the Invention

[0007] To address the problem that existing desaturation detection methods have slow short-circuit protection response speeds and cannot adapt to the extremely short short-circuit withstand time of SiC MOSFET modules, this invention proposes a short-circuit and overload protection circuit and air conditioner. The aim is to use the parasitic inductance between the Kelvin source pin and the power source pin as a current sensing element, thereby eliminating the need to set a blanking time and achieving nanosecond-level fault response.

[0008] This invention proposes a short-circuit and overload protection circuit, including a SiC MOSFET module. The SiC MOSFET module has a Kelvin source pin connected to a power source pin, and a parasitic inductor is connected in series between the Kelvin source pin and the power source pin. The short-circuit and overload protection circuit includes at least a current sampling unit for detecting the current conversion rate on the parasitic inductor and a short-circuit detection unit connected to the current sampling unit. The short-circuit detection unit is used to determine whether there is a short-circuit fault in the SiC MOSFET module based on the sampling result of the current sampling unit.

[0009] Based on the above scheme, this invention uses the parasitic inductance between the Kelvin source pin and the power source pin as a current sensing element, thereby eliminating the need to set a blanking time and achieving nanosecond-level fault response.

[0010] Furthermore, the short-circuit and overload protection circuit of the present invention also includes a voltage sampling unit for detecting the drain-source voltage of the SiC MOSFET module, and an overload detection unit connected to the voltage sampling unit. The overload detection unit has an energy storage capacitor, and the energy storage capacitor is charged only when the SiC MOSFET module is overloaded. The overload detection unit determines whether to trigger overload protection based on the voltage on the energy storage capacitor.

[0011] Based on the above scheme, this invention charges the energy storage capacitor by collecting the drain-source voltage of the SiC MOSFET module and the current conversion rate collected by the current sampling unit. This physically simulates the energy accumulation process and achieves overload protection that is consistent with the physical nature of thermal failure of the SiC MOSFET module.

[0012] Furthermore, the short-circuit and overload protection circuit of the present invention also includes a fault latching and soft-shutdown circuit for performing short-circuit protection and overload protection. The fault latching and soft-shutdown circuit includes at least a logic circuit and a gate discharge circuit. The logic circuit is used to prevent the protection oscillation triggered by the SiC MOSFET module during the turn-off process. The gate discharge circuit is used to slow down the discharge rate of the gate capacitor in the SiC MOSFET module when a short-circuit fault occurs in the SiC MOSFET module.

[0013] Based on the above-mentioned solution, this invention can effectively suppress turn-off voltage spikes, avoid protection oscillations triggered by the SiC MOSFET module during turn-off, ensure stable locking of short-circuit fault states, and prevent the fault signal from disappearing due to current drop, thus avoiding the problem of repeated circuit operation.

[0014] Furthermore, the current sampling unit described in this invention includes: a capacitor Cf and a resistor Rf;

[0015] One end of the capacitor Cf is connected between the Kelvin source pin and one end of the parasitic inductor, and the other end of the capacitor Cf is connected to one end of the resistor Rf, and the other end of the resistor Rf is connected to the other end of the parasitic inductor.

[0016] Based on the above scheme, this invention can acquire the current transformation rate on the parasitic inductor and convert it into voltage through capacitor Cf, which can realize accurate detection of the current state on the SiC MOSFET module for short circuit fault judgment. Moreover, by acquiring the current transformation rate on the parasitic inductor, no blanking time needs to be set, and nanosecond-level fault response is achieved.

[0017] Furthermore, the short-circuit detection unit described in this invention includes a comparator A2;

[0018] The non-inverting input of comparator A2 is connected between capacitor Cf and resistor Rf, the inverting input of comparator A2 is connected to a first reference voltage, and the output of comparator A2 is used to output the judgment result of short circuit fault.

[0019] The first reference voltage is configured to be the voltage value that the capacitor Cf rises within a preset time due to the current conversion rate corresponding to the short-circuit fault of the SiC MOSFET module.

[0020] Based on the above scheme, this invention can determine whether a short circuit fault has occurred in a SiC MOSFET module by comparing a first reference voltage with the voltage on capacitor Cf, thus realizing short circuit detection of SiC MOSFET modules.

[0021] Furthermore, the voltage sampling unit in this invention includes: resistor R1 and resistor R2;

[0022] One end of resistor R1 is connected to the drain of the SiC MOSFET module to obtain the drain-source voltage, and the other end of resistor R1 is connected to resistor R2, with the other end of resistor R2 grounded.

[0023] Based on the above scheme, this invention can accurately acquire the drain-source voltage of the SiC MOSFET module. It can work with the current conversion rate acquired by the current sampling unit to control the conduction state of the switch M1 in the delayed charging control circuit, thereby ensuring that the energy storage capacitor is charged only when the SiC MOSFET module is overloaded. This physically simulates the energy accumulation process and achieves overload protection that is consistent with the physical nature of thermal failure of the SiC MOSFET module.

[0024] Furthermore, the overload detection unit in this invention also includes a delayed charging control circuit, which is used to control the energy storage capacitor to charge only when the SiC MOSFET module is overloaded, and the delayed charging control circuit includes: switching transistor M1, switching transistor M2, and switching transistor M3;

[0025] The gate of the switching transistor M1 is connected between the resistor R1 and the resistor R2. The source of the switching transistor M1 is connected between the capacitor Cf and the resistor Rf in the current sampling unit. The drain of the switching transistor M1 is connected to the source of the switching transistor M2. The drain of the switching transistor M2 is connected to the power supply voltage. The gate of the switching transistor M2 is connected to the gate of the switching transistor M3. The drain of the switching transistor M3 is connected to the power supply voltage. The source of the switching transistor M3 is connected in series with the energy storage capacitor and then grounded.

[0026] The present invention, through the above solution, enables the energy storage capacitor to be charged only when the SiC MOSFET module is overloaded, thus avoiding the problem that the SiC MOSFET module charges the energy storage capacitor when it is not overloaded, causing the energy storage capacitor voltage to continuously rise and misleading the comparator A1, affecting the judgment result of the overload protection.

[0027] Furthermore, the overload detection unit in this invention also includes a comparator A1 for determining whether overload protection is triggered;

[0028] The non-inverting input of the comparator A1 is connected between the source of the switching transistor M3 and the energy storage capacitor. The inverting input of the comparator A1 is connected to the second reference voltage. The output of the comparator A1 is used to output the judgment result of the overload protection.

[0029] The second reference voltage is configured as the overload protection voltage of the SiC MOSFET module.

[0030] The present invention, through the above-described scheme, can compare the voltage on the energy storage capacitor with the second reference voltage to determine whether overload protection is required, thereby avoiding the problem of thermal failure of the SiC MOSFET module leading to abnormal circuit operation.

[0031] Furthermore, the logic circuit described in this invention consists of an OR gate and a Schmitt trigger. The two input terminals of the OR gate are respectively connected to the output terminals of the short-circuit detection unit and the overload detection unit. The output terminal of the OR gate is connected to the input terminal of the Schmitt trigger, and the output terminal of the Schmitt trigger is connected to the gate discharge circuit.

[0032] The present invention, through the above-described scheme, can utilize the characteristics of a Schmitt trigger to lock the fault state of a SiC MOSFET module when a short-circuit fault or overload abnormality occurs, thereby preventing the current of the SiC MOSFET module from dropping during the turn-off process, which would cause the protection circuit to repeatedly activate and the system to fall into oscillation.

[0033] Furthermore, the gate discharge circuit described in this invention includes: resistor RG, resistor Rg, and switching transistor M5;

[0034] One end of the resistor RG is connected to the gate of the SiC MOSFET module, and the other end of the resistor RG is connected to a PWM wave used to control the operation of the SiC MOSFET module.

[0035] One end of the resistor Rg is connected between the resistor RG and the gate of the SiC MOSFET module, the other end of the resistor Rg is connected to the drain of the switching transistor M5, the source of the switching transistor M5 is grounded, and the gate of the switching transistor M5 is connected to the output of the logic circuit.

[0036] The present invention, through the above-described solution, can slow down the discharge rate of the gate capacitance of the SiC MOSFET module, thereby reducing the current conversion rate and thus reducing the overshoot voltage generated therefrom, avoiding the problem of overshoot voltage damaging the SiC MOSFET module.

[0037] The present invention also proposes an air conditioner having a controller, wherein the controller employs the aforementioned short-circuit and overload protection circuit.

[0038] This invention relates to metal-oxide-semiconductor field-effect transistors (MOSFETs). Compared with the prior art, this invention has at least the following advantages:

[0039] 1. This invention uses the parasitic inductance between the Kelvin source pin and the power source pin as a current sensing element, eliminating the need to set a blanking time and achieving nanosecond-level fault response;

[0040] 2. This invention charges the energy storage capacitor by collecting the drain-source voltage of the SiC MOSFET module and combining it with the current conversion rate collected by the current sampling unit. This physically simulates the energy accumulation process and achieves overload protection that is consistent with the physical nature of thermal failure of the SiC MOSFET module.

[0041] 3. This invention can prevent the current drop of the SiC MOSFET module during the turn-off process from causing the protection circuit to repeatedly activate and the system to fall into oscillation through the logic circuit. It can also reduce the overshoot voltage through the gate discharge circuit, thus avoiding the problem of the overshoot voltage breaking down the SiC MOSFET module. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a block diagram of the overall modules of the present invention;

[0044] Figure 2 This is a circuit diagram of the current sampling unit in this invention;

[0045] Figure 3 This is a circuit diagram of the short-circuit detection unit in this invention;

[0046] Figure 4 This is a schematic diagram of the overall circuit of the short-circuit detection section in this invention;

[0047] Figure 5 This is a circuit diagram of the voltage sampling unit in this invention;

[0048] Figure 6 This is a circuit diagram of the delayed charging control circuit in this invention;

[0049] Figure 7 This is a circuit diagram of the overload detection unit in this invention;

[0050] Figure 8 This is a schematic diagram of the overall circuit of the overload detection section in this invention;

[0051] Figure 9 This is a circuit diagram of the logic circuit in this invention;

[0052] Figure 10 This is a circuit diagram of the gate discharge circuit in this invention;

[0053] Figure 11 This is a circuit diagram of the short-circuit protection and overload protection sections of the present invention;

[0054] Figure 12 This is a schematic diagram of the overall circuit connection of the present invention. Detailed Implementation

[0055] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0056] Therefore, a feature pointed out in this specification is used to describe one feature of one embodiment of the invention, and does not imply that every embodiment of the invention must have the described feature. Furthermore, it should be noted that this specification describes many features. Although certain features may be combined to illustrate possible system designs, these features may also be used in other combinations not explicitly stated. Therefore, unless otherwise stated, the described combinations are not intended to be limiting.

[0057] The principles and structure of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0058] In the existing technology, the driving and protection circuits of SiC MOSFET modules have the following problems:

[0059] 1. Traditional desaturation detection methods (adapted from IGBT protection) have a slow response and are difficult to achieve fast protection. If the protection time exceeds the short-circuit withstand time of the SiC MOSFET module, it may damage the SiC MOSFET module.

[0060] 2. In addition to short-circuit faults, prolonged overload operation can lead to heat accumulation inside the device, eventually causing thermal escape failure. However, most existing protection schemes only focus on short-circuit protection and lack effective monitoring methods for overload failure.

[0061] 3. When a short circuit fault occurs in the SiC MOSFET module, the excessively high current drop rate will induce a huge voltage spike on the stray inductance of the loop, which may break down the SiC MOSFET module. At the same time, the fault signal may disappear during the turn-off process due to the current drop, causing the protection circuit to operate repeatedly and the system to fall into oscillation.

[0062] To solve the above problem 1, the present invention proposes a short circuit and overload protection circuit, which includes a SiC MOSFET module, namely the silicon carbide metal oxide semiconductor field-effect transistor mentioned above. In order to reduce the coupling interference between the drive circuit and the power circuit of the SiC MOSFET module, the SiC MOSFET module is specially provided with a Kelvin source pin, which is connected to the power source pin of the SiC MOSFET module, and a parasitic inductor is connected in series between the Kelvin source pin and the power source pin.

[0063] In this invention, the parasitic inductor is used as a current sensing element for short-circuit fault detection. Specifically, the short-circuit and overload protection circuit proposed in this invention includes at least a current sampling unit for detecting the current conversion rate on the parasitic inductor and a short-circuit detection unit connected to the current sampling unit. The short-circuit detection unit is used to determine whether there is a short-circuit fault in the SiC MOSFET module based on the sampling results of the current sampling unit.

[0064] Please see the appendix Figure 2 The SiC MOSFET is the SiC MOSFET module mentioned earlier. Vss is the Kelvin source pin, and Ls is the parasitic inductance. One end of the parasitic inductance is connected to the Kelvin source pin, and the other end is connected to the power source pin. In this invention, the parasitic inductance is used as a current sensing element, which can achieve nanosecond-level fault response without setting a blanking time. This can solve the problem in Problem 1 above where the response time is lagging and exceeds the short-circuit withstand time of the SiC MOSFET module, which may cause damage to the SiC MOSFET module.

[0065] To solve the above problem 2, the short circuit and overload protection circuit proposed in this invention is further provided with a voltage sampling unit for detecting the drain-source voltage of the SiC MOSFET module and an overload detection unit connected to the voltage sampling unit. The overload detection unit has an energy storage capacitor, and the energy storage capacitor is charged only when the SiC MOSFET module is overloaded. The overload detection unit can determine whether to trigger overload protection based on the voltage on the energy storage capacitor.

[0066] Overload failure is essentially the accumulation of energy under the combined action of voltage and current over a long period of time. Simply detecting current or voltage cannot accurately reflect the thermal stress state of SiC MOSFET modules. In this invention, by charging the energy storage capacitor when the SiC MOSFET module is overloaded, the energy accumulation process can be physically simulated. Then, by detecting the voltage on the energy storage capacitor, an overload protection scheme that is relatively consistent with the physical nature of thermal failure of SiC MOSFET modules can be obtained, thus solving the two problems mentioned above: lack of effective monitoring means for overload failure.

[0067] To address the aforementioned problem 3, the short-circuit and overload protection circuit proposed in this invention also includes a fault latching and soft-shutdown circuit, which consists of a logic circuit and a gate discharge circuit. The logic circuit is used to prevent the SiC MOSFET module from triggering protective oscillations during the turn-off process, and the gate discharge circuit is used to slow down the discharge rate of the gate capacitor in the SiC MOSFET module when a short-circuit fault occurs.

[0068] Specifically, the gate discharge circuit is controlled by a Schmitt trigger in the logic circuit. This Schmitt trigger acts as a latch, and its logic function is as follows: once the Schmitt trigger is triggered, its output is locked at a high level. Even if the input signal of the Schmitt trigger disappears, its output will not change; it will only be reset when the rising edge of the next PWM cycle arrives. Based on this characteristic, when a fault signal is detected, the Schmitt trigger can remain triggered continuously, and the fault will not be determined to have disappeared due to the current drop during the SiC MOSFET module shutdown, causing the recovery circuit to trigger the fault again and repeatedly activate the protection circuit. This solves the problem in issue 3 mentioned above, where the fault signal may disappear during the shutdown process due to the current drop, causing the protection circuit to repeatedly activate and the system to oscillate.

[0069] For the gate discharge circuit, it can slow down the discharge rate of the gate capacitor in the SiC MOSFET module, thereby reducing the current conversion rate of the SiC MOSFET module during the turn-off process. This reduces the overshoot voltage caused by the reduced current conversion rate, lowering it from the original 800V for hard turn-off to 620~710V. This can prevent the overshoot voltage from damaging the SiC MOSFET module. Here, the overshoot voltage is the huge voltage spike induced on the stray inductance of the circuit due to the excessively high current drop rate mentioned above. In other words, the present invention can solve the problem in problem 3 above, where the excessively high current drop rate induces a huge voltage spike on the stray inductance of the circuit when a short-circuit fault occurs in the SiC MOSFET module, which may damage the SiC MOSFET module.

[0070] In summary, this invention mainly relates to short-circuit protection and overload protection for metal-oxide-semiconductor field-effect transistors, and it has the following beneficial effects:

[0071] 1. This invention uses the parasitic inductance between the Kelvin source pin and the power source pin as a current sensing element, eliminating the need to set a blanking time and achieving nanosecond-level fault response;

[0072] 2. This invention charges the energy storage capacitor by collecting the drain-source voltage of the SiC MOSFET module and combining it with the current conversion rate collected by the current sampling unit. This physically simulates the energy accumulation process and achieves overload protection that is consistent with the physical nature of thermal failure of the SiC MOSFET module.

[0073] 3. This invention can prevent the current drop of the SiC MOSFET module during the turn-off process from causing the protection circuit to repeatedly activate and the system to fall into oscillation through the logic circuit. It can also reduce the overshoot voltage through the gate discharge circuit, thus avoiding the problem of the overshoot voltage breaking down the SiC MOSFET module.

[0074] The above setup will be explained in detail below with reference to the accompanying drawings. For the current sampling circuit used to detect the voltage slew rate across the parasitic inductor, please refer to the attached diagram. Figure 2 and appendix Figure 12 It includes: capacitor Cf and resistor Rf;

[0075] One end of capacitor Cf is connected between the power source pin and one end of the parasitic inductor, and the other end of capacitor Cf is connected to one end of resistor Rf, and the other end of resistor Rf is connected to the other end of the parasitic inductor.

[0076] In this design, the capacitor Cf and resistor Rf are essentially connected in series and then in parallel across the parasitic inductor. This parasitic inductor is used as a current sensing element, and its operation is as follows:

[0077] When the SiC MOSFET module is normally turned on, the current conversion efficiency (dI_D / dt) is a limited value (typically 0.1-0.5A / ns), the capacitor Cf charges, and the voltage rise (V_O) between the capacitor Cf and the resistor Rf is limited.

[0078] When a short-circuit fault occurs in the SiC MOSFET module, the current conversion rate (dI_D / dt) rises sharply (up to several kA / μs), the capacitor Cf charges, and the voltage (V_O) between the capacitor Cf and the resistor Rf rises to a high level within about 120-150 ns.

[0079] Then, by detecting the voltage (V_O) between capacitor Cf and resistor Rf through the short-circuit detection unit, it can be determined whether a short-circuit fault has occurred. Under the above scheme, the present invention can achieve accurate detection of the current state on the SiC MOSFET module for the judgment of short-circuit faults. Moreover, by collecting the current change rate on the parasitic inductor, no blanking time needs to be set, and nanosecond-level fault response is achieved.

[0080] Please see the appendix Figure 3 and appendix Figure 12 The short-circuit detection unit in this invention includes a comparator A2;

[0081] The non-inverting input of comparator A2 is connected between capacitor Cr and resistor Rf, the inverting input of comparator A2 is connected to the first reference voltage, and the output of comparator A2 is used to output the judgment result of short circuit fault.

[0082] The first reference voltage is configured as the voltage value that capacitor Cr rises within a preset time due to the current change rate corresponding to a short-circuit fault in the SiC MOSFET module.

[0083] In the appendix Figure 3In this circuit, the "+" terminal of comparator A2 represents the non-inverting input terminal, and the "-" terminal of comparator A2 represents the inverting input terminal. Generally, when the voltage at the non-inverting input terminal is greater than the voltage at the inverting input terminal, comparator A2 will output a high-level signal, and vice versa.

[0084] Vref1 is the first reference voltage, which is configured to be the voltage value that capacitor Cr rises within a preset time due to the current change rate corresponding to the short-circuit fault of the SiC MOSFET module. In other words, when the SiC MOSFET module is normally turned on, the voltage (V_O) between capacitor Cf and resistor Rf is less than the first reference voltage, and comparator A2 outputs a low-level signal.

[0085] When a short circuit fault occurs in the SiC MOSFET module, the voltage (V_O) between capacitor Cf and resistor Rf is higher than the first reference voltage, and comparator A2 outputs a high-level signal;

[0086] Here, the preset time can correspond to the time it takes for the voltage (V_O) between capacitor Cf and resistor Rf to rise to a higher level, which is about 120-150ns. The high-level signal and the low-level signal are the short-circuit fault judgment results output by the output terminal of comparator A2 in the previous text.

[0087] Under the above-described design, the present invention can realize short-circuit detection of SiC MOSFET modules.

[0088] Please see the appendix Figure 4 and appendix Figure 12 Based on the above-mentioned current sampling unit and short-circuit detection unit, the working principle of the short-circuit detection section of this invention is as follows:

[0089] When the SiC MOSFET module is turned on normally, the current conversion rate (dI_D / dt) is a limited value (usually between 0.1-0.5A / ns), the capacitor Cf is charged, and the voltage (V_O) between the capacitor Cf and the resistor Rf rises by a limited amount, which is less than the first reference voltage. The comparator A2 outputs a low-level signal, indicating that there is no short circuit fault.

[0090] When a short circuit fault occurs in the SiC MOSFET module, the current conversion rate (dI_D / dt) rises sharply (up to several kA / μs), the capacitor Cf charges, and the voltage (V_O) between the capacitor Cf and the resistor Rf rises to a high level within about 120-150ns, which is greater than the first reference voltage. The comparator A2 outputs a high-level signal, indicating that a short circuit fault exists.

[0091] Please see the appendix Figure 5 and appendix Figure 12 In this invention, the voltage sampling unit includes: resistor R1 and resistor R2;

[0092] One end of resistor R1 is connected to the drain of the SiC MOSFET module to obtain the drain-source voltage, and the other end of resistor R1 is connected to resistor R2, and the other end of resistor R2 is grounded.

[0093] Here, the voltage sampling circuit is mainly used to sample the drain-source voltage V_DS of the SiC MOSFET module. The voltage between resistor R1 and resistor R2 is the output of the voltage sampling unit, which is used to provide the subsequent circuit. Due to the voltage division of resistor R1 and resistor R2, the actual voltage output by the voltage sampling circuit is V_DS' = V_DS×R2 / (R1+R2).

[0094] The values ​​of resistors R1 and R2 can be adaptively adjusted to change the ratio of the output voltage to the drain-source voltage V_DS, thereby meeting the control requirements of the subsequent circuit.

[0095] The detection of the drain-source voltage V_DS is mainly used to determine whether the SiC MOSFET module is overloaded. As mentioned above, the energy storage capacitor needs to simulate the energy accumulation process when the SiC MOSFET module is overloaded. Therefore, it is necessary to first detect whether the SiC MOSFET module is overloaded, and then control the energy storage capacitor to charge in order to achieve the simulation effect of the above energy accumulation process.

[0096] This invention, through the setting of the voltage sampling circuit, can accurately acquire the drain-source voltage of the SiC MOSFET module. It can work in conjunction with the current change rate acquired by the current sampling unit to control the conduction state of the switch M1 in the delayed charging control circuit, thereby ensuring that the energy storage capacitor is charged only when the SiC MOSFET module is overloaded. This physically simulates the energy accumulation process and achieves overload protection that is consistent with the physical nature of thermal failure of the SiC MOSFET module.

[0097] To prevent the SiC MOSFET module from charging the energy storage capacitor when it is not overloaded, this invention also includes a delayed charging control circuit to ensure that the energy storage capacitor is charged only when the SiC MOSFET module is overloaded. Please refer to the appendix. Figure 6 and appendix Figure 12 The delayed charging control circuit in this invention includes: switch M1, switch M2, and switch M3;

[0098] The gate of switch M1 is connected between resistors R1 and R2. The source of switch M1 is connected between capacitor Cr and resistor Rf in the current sampling unit. The drain of switch M1 is connected to the source of switch M2. The drain of switch M2 is connected to the power supply voltage. The gate of switch M2 is connected to the gate of switch M3. The drain of switch M3 is connected to the power supply voltage. The source of switch M3 is connected to the energy storage capacitor in series and then grounded.

[0099] Here, connecting the gate of switch M1 between resistors R1 and R2 is used to obtain the drain-source voltage V_DS of the SiC MOSFET module. Connecting the source of switch M1 between capacitor Cr and resistor Rf in the current sampling unit is used to obtain the rise of the voltage (V_O) between capacitor Cr and resistor Rf caused by the current conversion rate (dI_D / dt). The on / off state of switch M1 is simultaneously controlled by the drain-source voltage V_DS of the SiC MOSFET module and the voltage (V_O) between capacitor Cr and resistor Rf. Its specific working principle is as follows:

[0100] As an energy storage capacitor, capacitor Ce is used when the SiC MOSFET module is in the on state during normal operation. The drain-source voltage V_DS of the SiC MOSFET module is small (about 2-3V), and the corresponding voltage V_DS' = V_DS×R2 / (R1+R2) output to the gate of switch M1 is very small. At the same time, the voltage (V_O) between capacitor Cf and resistor Rf is also very small. At this time, the gate-source voltage V_GS1 = V_DS' - V_O of switch M1 is much lower than its turn-on threshold voltage. At this time, switch M1 is turned off, and no current charges capacitor Ce.

[0101] Conversely, when a short circuit fault occurs in the SiC MOSFET module, the switching transistor M1 turns on, and the capacitor Ce begins to charge.

[0102] The present invention, through the above solution, enables the energy storage capacitor to be charged only when the SiC MOSFET module is overloaded, thus avoiding the problem that the SiC MOSFET module charges the energy storage capacitor when it is not overloaded, causing the energy storage capacitor voltage to continuously rise and misleading the comparator A1, affecting the judgment result of the overload protection.

[0103] Please see the appendix Figure 8 and appendix Figure 12 To further reduce the voltage on capacitor Ce when the SiC MOSFET module is working normally, the present invention also includes a switching transistor M4, which is connected to a discharge pin R_DIS, which is used to provide discharge current to maintain the voltage on capacitor Ce at around 0V and prevent comparator A1 from being mis-turned on.

[0104] Please see the appendix Figure 7 and appendix Figure 12 The overload detection unit in this invention also includes a comparator A1 for determining whether overload protection is triggered;

[0105] The non-inverting input of comparator A1 is connected between the source of the switching transistor M3 and the energy storage capacitor. The inverting input of comparator A1 is connected to the second reference voltage. The output of comparator A1 is used to output the judgment result of overload protection.

[0106] The second reference voltage is configured as the overload protection voltage for the SiC MOSFET module.

[0107] In the appendix Figure 7 In this circuit, the "+" terminal of comparator A1 represents the non-inverting input terminal, and the "-" terminal of comparator A1 represents the inverting input terminal. Generally, when the voltage at the non-inverting input terminal is greater than the voltage at the inverting input terminal, comparator A1 will output a high-level signal, and vice versa.

[0108] Vref2 is the second reference voltage, which is configured as the overload protection voltage of the SiC MOSFET module (this overload protection voltage is set according to the performance of the SiC MOSFET module, or according to the voltage corresponding to the historical overload thermal failure). When the energy storage capacitor does not reach the overload protection voltage during the overload charging of the SiC MOSFET module, it outputs a low-level signal, indicating that there is no need to trigger the overload protection.

[0109] When the SiC MOSFET module is overcharged and reaches the overload protection voltage, the energy storage capacitor outputs a high-level signal, indicating that overload protection needs to be triggered.

[0110] The high-level and low-level signals are the overload protection judgment results output by the comparator A1 mentioned earlier.

[0111] Through the above-described scheme, this invention can physically simulate the energy accumulation process by charging the energy storage capacitor, and determine the potential overload thermal failure of the SiC MOSFET module based on the voltage on the energy storage capacitor, and execute relevant protection, thus achieving overload protection that is consistent with the physical nature of thermal failure of the SiC MOSFET module.

[0112] Please see the appendix Figure 8 and appendix Figure 12 Based on the aforementioned voltage sampling unit, delayed charging control circuit, and overload detection unit, the working principle of the overload detection section of this invention is as follows:

[0113] As an energy storage capacitor, capacitor Ce is used when the SiC MOSFET module is in the on state during normal operation. The drain-source voltage V_DS of the SiC MOSFET module is small (about 2-3V), and the corresponding voltage V_DS' = V_DS×R2 / (R1+R2) output to the gate of switch M1 is very small. At the same time, the voltage (V_O) between capacitor Cf and resistor Rf is also very small. At this time, the gate-source voltage V_GS1 = V_DS' - V_O of switch M1 is much lower than its turn-on threshold voltage. At this time, switch M1 is turned off, and no current charges capacitor Ce. Switch M4 provides discharge current to maintain the voltage on capacitor Ce at around 0V.

[0114] When the SiC MOSFET module is overloaded, the switch M1 turns on and the capacitor Ce begins to charge. At this time, the capacitor Ce simulates the energy accumulation process of the SiC MOSFET module. When the energy storage capacitor has not reached the overload protection voltage, the comparator A1 outputs a low-level signal, indicating that there is no need to trigger the overload protection. When the energy storage capacitor has reached the overload protection voltage, the comparator A1 outputs a high-level signal, indicating that the overload protection needs to be triggered.

[0115] As mentioned above, this invention essentially requires short-circuit protection and overload protection. Specifically, it needs to be able to trigger the corresponding protection action when either a short-circuit protection or overload protection occurs in the SiCMOSFET module. For this purpose, this invention includes a logic circuit, which can be found in the appendix. Figure 9 and appendix Figure 12 In this invention, the logic circuit consists of an OR gate and a Schmitt trigger. The two inputs of the OR gate are connected to the outputs of the short-circuit detection unit and the overload detection unit, respectively. The output of the OR gate is connected to the input of the Schmitt trigger, and the output of the Schmitt trigger is connected to the gate discharge circuit.

[0116] Appendix Figure 9 U1 is the AND gate, and U2 is the Schmitt trigger.

[0117] Here, the purpose of setting up the OR gate is to trigger the corresponding protection action when either short-circuit protection or overload protection occurs in the SiC MOSFET module, as mentioned earlier. The logic symbol of the OR gate is OR, and it can output signal 1 (high-level signal) when the signal at either input terminal is 1 (corresponding to a high-level signal). By connecting the two input terminals of the OR gate to the output terminals of the short-circuit detection unit and the overload detection unit respectively, it is possible to achieve the effect that when either short-circuit protection or overload protection occurs in the SiC MOSFET module, a high-level signal can be output through the OR gate, thereby triggering the protection action.

[0118] The Schmitt trigger is used to address the issue of fault signals disappearing during turn-off due to current drops, causing repeated activation of the protection circuit and system oscillation. The output of the OR gate is set to V_fault and fed into the Schmitt trigger, which acts as a latch, clocked by an externally input PWM signal. Its logic function is as follows: it is only sensitive to V_fault when the PWM signal is high (corresponding to the SiC MOSFET module being turned on). Once the Schmitt trigger is activated, its output is locked high. Even if the V_fault signal disappears, the output of the Schmitt trigger remains unchanged until the rising edge of the next PWM signal arrives, effectively preventing protection oscillations caused by the disappearance of V_fault due to current drops during SiC MOSFET module turn-off.

[0119] Please see the appendix Figure 10 and appendix Figure 12 The gate discharge circuit in this invention includes: resistor RG, resistor Rg, and switching transistor M5;

[0120] One end of resistor RG is connected to the gate of the SiC MOSFET module, and the other end of resistor RG is connected to the PWM wave used to control the operation of the SiC MOSFET module.

[0121] One end of resistor Rg is connected between resistor RG and the gate of the SiC MOSFET module, and the other end of resistor Rg is connected to the drain of switching transistor M5. The source of switching transistor M5 is grounded, and the gate of switching transistor M5 is connected to the output of the logic circuit.

[0122] Here, the resistance of resistor RG is relatively small, about 1Ω, and it is mainly used to quickly discharge the SiC MOSFET module when the SiC MOSFET module is normally turned off.

[0123] The resistor Rg has a relatively large resistance, approximately 10Ω. Its main purpose is to reduce the current drop rate dI_D / dt of the SiC MOSFET module, that is, to slow down the discharge speed of the gate capacitor in the SiC MOSFET module. Whether it is connected or not is directly controlled by the switching transistor M5. Only when the SiC MOSFET module triggers short circuit protection or overload protection will the logic circuit output a high-level signal to turn on the switching transistor M5, thereby reducing the current drop rate dI_D / dt of the SiC MOSFET module and preventing overshoot voltage from breaking down the SiC MOSFET module.

[0124] The present invention, through the above-described solution, can slow down the discharge rate of the gate capacitance of the SiC MOSFET module, thereby reducing the current conversion rate and thus reducing the overshoot voltage generated therefrom, avoiding the problem of overshoot voltage damaging the SiC MOSFET module.

[0125] Please see the appendix Figure 11 and appendix Figure 12 Regarding the above-mentioned logic circuit and gate discharge circuit, the working principle of the short circuit protection and overload protection section of this invention is as follows: when the SiC MOSFET module does not trigger short circuit protection or overload protection, the logic circuit outputs a low-level signal. At this time, the switching transistor M5 is turned off, the resistor Rg is not connected to the circuit, the SiC MOSFET module is normally controlled by its drive signal (PWM wave), and the gate of the SiC MOSFET module discharges quickly through a small resistor RG (approximately 1Ω).

[0126] When the SiC MOSFET module triggers short-circuit protection or overload protection, the logic circuit outputs a high-level signal. Due to the presence of the Schmitt trigger, this high-level signal is locked and will not be pulled low to turn off the switching transistor M5. Switch M5 remains in the on state. A relatively large resistor Rg (approximately 10Ω) is connected to the gate of the SiC MOSFET module to slow down the discharge rate of the SiC MOSFET module, thereby reducing the current drop rate dI_D / dt and the resulting overshoot voltage V_DS. In this invention, through the above design, the overshoot voltage V_DS can be reduced from approximately 800V during hard turn-off to 620-710V, and dI_D / dt is reduced by approximately 40%, thus avoiding the problem of overshoot voltage damaging the SiC MOSFET module.

[0127] Based on the above-mentioned short-circuit and overload protection circuit, the present invention also proposes an air conditioner having a controller having the above-mentioned overload protection circuit.

[0128] As mentioned above, this invention is mainly used to solve a series of problems existing in SiC MOSFET modules, belongs to the field of metal-oxide-semiconductor field-effect transistors, and compared with the prior art, this invention has at least the following beneficial effects:

[0129] 1. This invention uses the parasitic inductance between the Kelvin source pin and the power source pin as a current sensing element, eliminating the need to set a blanking time and achieving nanosecond-level fault response;

[0130] 2. This invention charges the energy storage capacitor by collecting the drain-source voltage of the SiC MOSFET module and combining it with the current conversion rate collected by the current sampling unit. This physically simulates the energy accumulation process and achieves overload protection that is consistent with the physical nature of thermal failure of the SiC MOSFET module.

[0131] 3. This invention can prevent the current drop of the SiC MOSFET module during the turn-off process from causing the protection circuit to repeatedly activate and the system to fall into oscillation through the logic circuit. It can also reduce the overshoot voltage through the gate discharge circuit, thus avoiding the problem of the overshoot voltage breaking down the SiC MOSFET module.

[0132] It should be noted that the terminology used above is for describing specific embodiments only and is not intended to limit the exemplary embodiments of the present invention. When the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof. The order of execution of actions, steps, etc., in the apparatus and methods in the specification and drawings can be implemented in any order unless a specific express order is specified, and as long as the output of a previous process is not used in a subsequent process. Similar sequential terms used for ease of description do not imply that such an order must be followed.

[0133] Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, they should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as constraints. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0134] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A short-circuit and overload protection circuit, comprising a SiC MOSFET module, the SiC MOSFET module having a Kelvin source pin connected to a power source pin, and a parasitic inductance connected in series between the Kelvin source pin and the power source pin, characterized in that, The short-circuit and overload protection circuit includes at least a current sampling unit for detecting the current conversion rate on the parasitic inductor and a short-circuit detection unit connected to the current sampling unit. The short-circuit detection unit is used to determine whether the SiC MOSFET module has a short-circuit fault based on the sampling result of the current sampling unit.

2. The short-circuit and overload protection circuit according to claim 1, characterized in that, The short-circuit and overload protection circuit further includes a voltage sampling unit for detecting the drain-source voltage of the SiC MOSFET module, and an overload detection unit connected to the voltage sampling unit. The overload detection unit has an energy storage capacitor, and the energy storage capacitor is charged only when the SiC MOSFET module is overloaded. The overload detection unit determines whether to trigger overload protection based on the voltage on the energy storage capacitor.

3. The short-circuit and overload protection circuit according to claim 2, characterized in that, The short-circuit and overload protection circuit also includes a fault latching and soft-shutdown circuit for performing short-circuit protection and overload protection. The fault latching and soft-shutdown circuit includes at least a logic circuit and a gate discharge circuit. The logic circuit is used to prevent protection oscillations triggered by the SiC MOSFET module during the turn-off process. The gate discharge circuit is used to slow down the discharge rate of the gate capacitor in the SiC MOSFET module when a short-circuit fault occurs in the SiC MOSFET module.

4. The short-circuit and overload protection circuit according to claim 1, characterized in that, The current sampling unit includes: a capacitor Cf and a resistor Rf; One end of the capacitor Cf is connected between the Kelvin source pin and one end of the parasitic inductor, and the other end of the capacitor Cf is connected to one end of the resistor Rf, and the other end of the resistor Rf is connected to the other end of the parasitic inductor.

5. The short-circuit and overload protection circuit according to claim 4, characterized in that, The short-circuit detection unit includes a comparator A2; The non-inverting input of comparator A2 is connected between capacitor Cf and resistor Rf, the inverting input of comparator A2 is connected to a first reference voltage, and the output of comparator A2 is used to output the judgment result of short circuit fault. The first reference voltage is configured to be the voltage value that the capacitor Cf rises within a preset time due to the current conversion rate corresponding to the short-circuit fault of the SiC MOSFET module.

6. The short-circuit and overload protection circuit according to claim 2, characterized in that, The voltage sampling unit includes: resistor R1 and resistor R2; One end of resistor R1 is connected to the drain of the SiC MOSFET module to obtain the drain-source voltage, and the other end of resistor R1 is connected to resistor R2, with the other end of resistor R2 grounded.

7. The short-circuit and overload protection circuit according to claim 6, characterized in that, The overload detection unit further includes a delayed charging control circuit, which controls the energy storage capacitor to charge only when the SiC MOSFET module is overloaded, and the delayed charging control circuit includes: switching transistor M1, switching transistor M2, and switching transistor M3. The gate of the switching transistor M1 is connected between the resistor R1 and the resistor R2. The source of the switching transistor M1 is connected between the capacitor Cf and the resistor Rf in the current sampling unit. The drain of the switching transistor M1 is connected to the source of the switching transistor M2. The drain of the switching transistor M2 is connected to the power supply voltage. The gate of the switching transistor M2 is connected to the gate of the switching transistor M3. The drain of the switching transistor M3 is connected to the power supply voltage. The source of the switching transistor M3 is connected in series with the energy storage capacitor and then grounded.

8. The short-circuit and overload protection circuit according to claim 7, characterized in that, The overload detection unit also includes a comparator A1 for determining whether overload protection has been triggered; The non-inverting input of the comparator A1 is connected between the source of the switching transistor M3 and the energy storage capacitor. The inverting input of the comparator A1 is connected to the second reference voltage. The output of the comparator A1 is used to output the judgment result of the overload protection. The second reference voltage is configured as the overload protection voltage of the SiC MOSFET module.

9. The short-circuit and overload protection circuit according to claim 3, characterized in that, The logic circuit consists of an OR gate and a Schmitt trigger. The two inputs of the OR gate are connected to the outputs of the short-circuit detection unit and the overload detection unit, respectively. The output of the OR gate is connected to the input of the Schmitt trigger, and the output of the Schmitt trigger is connected to the gate discharge circuit.

10. The short-circuit and overload protection circuit according to claim 3, characterized in that, The gate discharge circuit includes: resistor RG, resistor Rg, and switching transistor M5; One end of the resistor RG is connected to the gate of the SiC MOSFET module, and the other end of the resistor RG is connected to a PWM wave used to control the operation of the SiC MOSFET module. One end of the resistor Rg is connected between the resistor RG and the gate of the SiC MOSFET module, the other end of the resistor Rg is connected to the drain of the switching transistor M5, the source of the switching transistor M5 is grounded, and the gate of the switching transistor M5 is connected to the output of the logic circuit.

11. An air conditioner, the air conditioner having a controller, characterized in that, The controller is provided with a short-circuit and overload protection circuit as described in any one of claims 1 to 10.

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