A hybrid DC circuit breaker based on hierarchical current limiting, multi-energy-level LC forced zero-crossing and fault persistence discrimination and a breaking method thereof

Abstract

This invention discloses a hybrid DC circuit breaker and its interruption method based on graded current limiting, multi-level LC forced zero crossing, and fault persistence discrimination, belonging to the field of DC power distribution protection and DC interruption technology. The circuit breaker includes a main current channel unit (1), an auxiliary commutator current limiting branch (2), a multi-level LC forced zero crossing commutator unit (3), an energy buffer and absorption unit (4), and a detection and control unit (5). After a fault occurs, an auxiliary channel is established and the main channel is deactivated. Based on the current before current limiting, a state of no additional current limiting, first current limiting, or second current limiting is selected. Before the LC branch is triggered, it is determined whether the fault is persistent. For non-persistent faults, the main current is restored; for persistent faults, the corresponding LC branch is selected based on the commutator selection sampling current, causing the second ultra-fast mechanical switch branch to generate an artificial zero crossing. In the state of no additional current limiting, the auxiliary branch current decays naturally. In the first and second current limiting states, the remaining energy is buffered by the first commutation capacitor and absorbed by the surge arrester. This invention can reduce the normal loss of the main circuit and improve the adaptability of current limiting and interruption under a wide range of fault currents.

Description

Technical Field

[0001] This invention relates to the field of DC power distribution protection and DC interruption technology, specifically to a hybrid DC circuit breaker and its interruption method based on graded current limiting, multi-level LC forced zero crossing and fault persistence discrimination, which is applicable to fault current limiting, fast interruption and transient fault recovery in medium and high voltage DC power distribution systems and bidirectional DC transmission and distribution systems. Background Technology

[0002] With the development of new energy power generation, DC distribution networks, rail transit, data centers, and integrated ship power systems, the voltage level and power supply capacity of DC systems are constantly increasing. Since DC fault current does not have a natural zero-crossing point, the fault current usually rises rapidly in a short period of time after a short-circuit fault occurs on the line. This requires DC circuit breakers to simultaneously possess the capabilities of rapid fault detection, fault current limiting, artificial zero-crossing establishment, recovery voltage withstand, and fault energy absorption.

[0003] Existing DC circuit breakers mainly include mechanical DC circuit breakers, solid-state DC circuit breakers, and hybrid DC circuit breakers. Mechanical DC circuit breakers have low operating losses, but are limited by the mechanical operating speed and the lack of a natural zero-crossing point for DC current, typically requiring auxiliary commutator branches to establish artificial zero-crossing conditions. Solid-state DC circuit breakers have fast operating speeds, but the power semiconductor devices are connected in series in the main circuit for extended periods, resulting in higher conduction losses, higher heat dissipation requirements, and higher device costs. Hybrid DC circuit breakers, through the coordinated operation of mechanical switches and power electronic devices, can balance low operating losses with rapid fault interruption, and have therefore attracted widespread attention.

[0004] To limit the rise rate of DC short-circuit current, some existing technologies connect a current-limiting inductor in series in the main circuit. This method can suppress the increase of fault current, but the current-limiting inductor continuously carries current during normal operation, which increases line voltage drop, power loss, equipment size, and manufacturing cost. Other solutions place the current-limiting inductor in the fault handling branch, activating it only after a fault occurs; however, these typically use a single current-limiting parameter, making it difficult to simultaneously handle different breaking conditions such as weak current, medium fault current, and large fault current.

[0005] During DC current interruption, a pre-charge capacitor and an oscillating inductor are often used to form an LC commutation circuit, injecting reverse commutation current into the mechanical switch branch to reduce the mechanical switch branch current to zero or near zero. Since the peak value of the reverse commutation current, the oscillation duration, and the commutation energy requirements differ for different fault current levels, using a single LC commutation branch with a fixed capacitor, fixed pre-charge voltage, and fixed oscillating inductor can easily lead to excessive commutation energy under low current conditions and insufficient commutation capacity under medium to high current conditions. This is not conducive to balancing device stress, commutation reliability, and interruption range.

[0006] Some existing DC circuit breakers perform a complete current limiting and interruption process immediately upon detecting a fault. When the fault is a short-duration transient fault, a self-recovering fault, or a detected disturbance, the LC forced zero-crossing branch and mechanical switch are still triggered to complete the entire interruption action. This increases the number of mechanical switch operations, the number of charging and discharging cycles of the commutator capacitor, and the current and voltage stress on power electronic devices. Existing fault persistence discrimination schemes are usually independent of the selection of the current limiting branch, the mechanical switch operation process, and the LC commutation level selection, making it difficult to fully utilize the discrimination time window formed during the controlled fault current phase.

[0007] Furthermore, existing hybrid DC circuit breakers typically employ single-function mechanical switches, or lack clear phased functional divisions among multiple mechanical switches, making it difficult to simultaneously achieve rapid isolation of the upstream main current path and manual zero-crossing interruption of downstream fault currents. If the connection positions and operating sequences of the auxiliary converter branches are improperly configured, the upstream mechanical switches may still have to withstand significant tripping currents, or the downstream mechanical switches may fail to achieve stable manual zero-crossing conditions.

[0008] In the later stages of the interruption, significant energy may still be stored in the current-limiting inductor, line inductance, and DC power supply. Some existing solutions rely primarily on surge arresters to directly absorb the remaining energy, or to first transfer the energy to the commutation capacitor before discharging it. If there is a lack of coordinated control between the commutation capacitor, surge arrester, and energy transfer switch, problems such as overvoltage of the commutation capacitor, excessive current in the energy transfer circuit, and uneven energy absorption by the surge arrester may occur.

[0009] Therefore, a hybrid DC circuit breaker and its interruption method are needed. Without increasing the normal operating loss of the main circuit, different current limiting states are selected according to the initial fault current. After the current limiting state is established, a fault persistence discrimination window is formed. The corresponding energy level LC forced zero-crossing commutation branch is selected according to the actual current. At the same time, the near-zero current isolation of the front-stage mechanical switch, the manual zero-crossing interruption of the rear-stage mechanical switch, and the coordinated buffering and absorption of the remaining energy are achieved. Summary of the Invention

[0010] The purpose of this invention is to provide a hybrid DC circuit breaker and its interruption method based on graded current limiting, multi-level LC forced zero crossing and fault persistence discrimination, so as to solve the problems of large normal operation losses caused by long-term series connection of current limiting inductors in existing DC circuit breakers, difficulty in adapting to a wide range of fault currents by a single current limiting parameter and a single LC converter branch, easy triggering of transient faults leading to unnecessary complete interruption, and uncoordinated residual energy processing.

[0011] To achieve the above objectives, the present invention provides a hybrid DC circuit breaker based on graded current limiting, multi-level LC forced zero crossing and fault persistence discrimination, including a main current channel unit (1), an auxiliary commutation current limiting branch (2), a multi-level LC forced zero crossing commutation unit (3), an energy buffer and absorption unit (4), and a detection and control unit (5).

[0012] Optionally, the main current channel unit (1) includes a first ultra-fast mechanical switch UFD1, a load commutator switch LCS, and a second ultra-fast mechanical switch UFD2 connected in series in the DC main circuit. During normal operation, the DC system current flows through the main current channel formed by the first ultra-fast mechanical switch UFD1, the load commutator switch LCS, and the second ultra-fast mechanical switch UFD2. One end of the auxiliary commutator current limiting branch (2) is connected to the side of the first ultra-fast mechanical switch UFD1 closest to the DC power supply, and the other end is connected to the node between the load commutator switch LCS and the second ultra-fast mechanical switch UFD2, so that the auxiliary commutator current limiting branch (2) is connected across the two ends of the series segment formed by the first ultra-fast mechanical switch UFD1 and the load commutator switch LCS, and does not bypass the second ultra-fast mechanical switch UFD2. After a fault occurs, the auxiliary converter current limiting branch (2) establishes an auxiliary current channel, and the load converter switch LCS is turned off under control, so that the current flowing through the first ultra-fast mechanical switch UFD1 and the load converter switch LCS is transferred to the auxiliary converter current limiting branch (2), thereby providing the first ultra-fast mechanical switch UFD1 with zero current or near-zero current tripping conditions; the current to be interrupted after being processed by the auxiliary converter current limiting branch (2) continues to flow through the second ultra-fast mechanical switch UFD2, and the multi-level LC forced zero-crossing converter unit (3) establishes artificial zero-crossing conditions.

[0013] Optionally, the auxiliary commutation current limiting branch (2) includes a first commutation thyristor T1, a first commutation capacitor C1, and a first auxiliary thyristor T1. 2a Second auxiliary thyristor T 2b , commutation diode D a To D d And an optional current limiting unit. The first commutation thyristor T1 is used to establish an auxiliary current path after a fault occurs, and the first auxiliary thyristor T... 2a Second auxiliary thyristor T 2b The first commutation capacitor C1 is used to form a reverse commutation circuit for the first commutated thyristor T1, so that the current of the first commutated thyristor T1 is reduced to zero and reverse biased.

[0014] Optionally, the auxiliary commutation current limiting branch (2) further includes a first pre-charge voltage regulating capacitor C4, a first pre-charge voltage regulating resistor R1, and a first pre-charge voltage regulating thyristor T. 11The first pre-charge regulating capacitor C4, the first pre-charge regulating resistor R1, and the first pre-charge regulating thyristor T 11 This forms the first pre-charge voltage regulation branch, used to adjust the pre-charge voltage of the first commutation capacitor C1 before disconnection.

[0015] Optionally, the optional current limiting unit includes a first current limiting branch and a second current limiting branch. The first current limiting branch includes a first current limiting inductor L1 and a first current limiting branch selection thyristor T connected in series. 3a The second current-limiting branch includes a second current-limiting inductor L2 connected in series and a second current-limiting branch selection thyristor T. 3b Furthermore, the inductance value of the second current-limiting inductor L2 is greater than the inductance value of the first current-limiting inductor L1.

[0016] Optionally, the optional current limiting unit has a state without additional current limiting, a first current limiting state, and a second current limiting state. The sampling current I obtained before the current limiting branch is activated is... pre When the current is less than the first grade threshold, neither the first current-limiting branch nor the second current-limiting branch is activated; when the sampling current I before current limiting is... pre When the current is greater than or equal to the first-level threshold and less than the second-level threshold, the first current-limiting branch is activated; when the sampling current I before current limiting is... pre When the threshold value is greater than or equal to the second level threshold, the second current-limiting branch is activated.

[0017] Optionally, the multi-level LC forced zero-crossing commutation unit (3) is connected across the two ends of the second ultra-fast mechanical switch UFD2, and includes a first LC forced zero-crossing commutation branch and a second LC forced zero-crossing commutation branch. The first LC forced zero-crossing commutation branch has a first available initial oscillation energy, and the second LC forced zero-crossing commutation branch has a second available initial oscillation energy, and the second available initial oscillation energy is greater than the first available initial oscillation energy.

[0018] Optionally, the multi-level LC forced zero-crossing commutation unit (3) includes a first oscillation capacitor C2, a second oscillation capacitor C3, an LC oscillation inductor L3, and a first LC commutation thyristor T. 4a Second LC commutator thyristor T 4b and commutator thyristors T5 to T 10 The first oscillation capacitor C2 and the first LC commutator thyristor T 4a The LC oscillating inductor L3 and the corresponding commutation thyristor constitute the first LC forced zero-crossing commutation branch; the second oscillating capacitor C3 and the second LC commutation thyristor T... 4b The LC oscillating inductor L3 and the corresponding commutation thyristor constitute the second LC forced zero-crossing commutation branch.

[0019] Optionally, the first available initial oscillation energy E1 of the first LC forced zero-crossing commutation branch and the second available initial oscillation energy E2 of the second LC forced zero-crossing commutation branch respectively satisfy:

[0020]

[0021] Among them, U C2 U is the pre-charge voltage of the first oscillating capacitor C2. C3 This is the pre-charge voltage of the second oscillating capacitor C3, and it satisfies E2 > E1.

[0022] Optionally, the commutation selection sampling current I obtained after the current limiting state is established. post When the energy level is less than the LC level selection threshold, the first LC forced zero-crossing commutation branch is selected; when the commutation selection sampling current I... post When the threshold value is greater than or equal to the LC level selection threshold, the second LC forced zero-crossing commutation branch is selected. The selected LC forced zero-crossing commutation branch injects a commutation current in the opposite direction to the current to be interrupted into the second ultra-fast mechanical switch UFD2 branch, so that the current in the second ultra-fast mechanical switch UFD2 branch generates an artificial zero crossing.

[0023] Optionally, the multi-level LC forced zero-crossing commutation unit (3) further includes a second pre-charge voltage regulating capacitor C5, a second pre-charge voltage regulating resistor R2, and a second pre-charge voltage regulating thyristor T. 12 First pre-charged thyristor T 4c Second precharged thyristor T 4d The second pre-charge regulating capacitor C5, the second pre-charge regulating resistor R2, and the second pre-charge regulating thyristor T 12 This forms the second pre-charge voltage regulating branch; the first pre-charge conducting thyristor T 4c The pre-charge path for establishing the first oscillation capacitor C2 is used, and the second pre-charge thyristor T is turned on. 4d This is used to establish a pre-charge path for the second oscillating capacitor C3.

[0024] Optionally, commutation diode D a To D d and commutator thyristors T5 to T 10 The circuit is configured according to the conduction directions of the forward fault current and the reverse fault current to form corresponding bidirectional commutation and forced zero-crossing commutation paths, making the hybrid DC circuit breaker suitable for bidirectional DC systems.

[0025] Optionally, the energy buffer and absorption unit (4) includes an energy transfer thyristor T. 13The surge arrester (MOV) and energy discharge switch (S) are included. The first commutation capacitor C1 also serves as the commutation capacitor of the first commutator thyristor T1 and the transient energy buffer capacitor in the first and second current-limiting states. When in the first or second current-limiting state, after the current in the second ultra-fast mechanical switch UFD2 branch artificially crosses zero, the first commutator thyristor T1 is turned off, and the current in the LC oscillation branch decays to zero or below a preset threshold, the energy transfer thyristor T... 13 The circuit is turned on, transferring the energy stored in the current-limiting inductor already in the current-limiting branch and the remaining energy in the DC system to the first commutation capacitor C1. When the voltage of the first commutation capacitor C1 reaches the preset access threshold, the energy discharge switch S is turned on to connect to the surge arrester MOV. Without additional current limiting, the energy transfer thyristor T... 13 With the energy discharge switch S remaining untriggered, the auxiliary branch current naturally decays.

[0026] Optionally, the detection and control unit (5) is connected to the load commutation switch LCS, the first ultra-fast mechanical switch UFD1, the second ultra-fast mechanical switch UFD2, the first commutation thyristor T1, and the first auxiliary thyristor T1, respectively. 2a Second auxiliary thyristor T 2b The first current-limiting branch selects thyristor T. 3a The second current-limiting branch selects thyristor T. 3b First LC commutator thyristor T 4a Second LC commutator thyristor T 4b First pre-charged thyristor T 4c Second pre-charged thyristor T 4d , commutator thyristors T5 to T 10 First pre-charged voltage regulating thyristor T 11 Second pre-charge voltage regulating thyristor T 12 Energy transfer thyristor T 13 It is connected to the energy discharge switch S, which is used to collect the current, voltage and switching status of the DC main circuit and corresponding branches, and control the operation of each switching device according to the preset control sequence.

[0027] Optionally, the detection and control unit (5) is configured to: establish an auxiliary current channel and exit the main current channel after a fault is detected; and sample the current I before current limiting. preSelect the state without additional current limiting, the first current limiting state, or the second current limiting state; after the selected current processing state is established and before the LC forced zero-crossing commutation branch is triggered, set the fault persistence discrimination window and determine whether the fault is persistent. When the fault is determined to be a non-persistent fault, the detection and control unit (5) stops the triggering of the multi-level LC forced zero-crossing commutation unit (3), restores the first ultra-fast mechanical switch UFD1 and the second ultra-fast mechanical switch UFD2 to the state that meets the main current requirements, and then controls the load commutation switch LCS to resume conduction, so that the current in the auxiliary commutation current limiting branch (2) is transferred back to the main current path. When the fault is determined to be a persistent fault, the detection and control unit (5) acquires the commutation selection sampling current I. post Select sampling current I based on commutation post Select either the first LC forced zero-crossing commutation branch or the second LC forced zero-crossing commutation branch, and trigger the selected LC forced zero-crossing commutation branch after the contact gap of the second ultra-fast mechanical switch UFD2 reaches the preset withstand voltage opening distance.

[0028] Optionally, during a fault handling cycle, once the first or second current-limiting branch is selected, the selected current-limiting state is maintained until the current of the corresponding current-limiting branch drops to zero or below a preset exit threshold. At least one of the first-level threshold, the second-level threshold, and the LC level selection threshold is provided with a hysteresis range to avoid repeated branch selection caused by current fluctuations near the corresponding threshold.

[0029] Another aspect of the present invention provides a breaking method using the above-mentioned hybrid DC circuit breaker, comprising the following steps:

[0030] Before disconnection, the first commutation capacitor C1, the first oscillation capacitor C2, and the second oscillation capacitor C3 are pre-charged, and the current and voltage parameters in the DC main circuit are detected.

[0031] After a fault is detected, the first commutator thyristor T1 is triggered to establish an auxiliary current channel, the load commutator switch LCS is controlled to turn off, and a trip command is issued to the first ultra-fast mechanical switch UFD1 and the second ultra-fast mechanical switch UFD2, so that the main current is transferred from the main current channel to the auxiliary commutator current limiting branch (2).

[0032] Obtain the pre-current limiting sampling current I before the current limiting branch is put into operation. pre And based on the current I sampled before current limiting pre Choose between the following modes: no additional current limiting, first current limiting, or second current limiting. When the no additional current limiting mode is selected, neither the first nor the second current limiting branch is activated, and the first auxiliary thyristor T... 2a Second auxiliary thyristor T 2bThe first commutator thyristor T1 remains on while in the untriggered state. When either the first or second current-limiting state is selected, a corresponding current-limiting branch is established, and the first auxiliary thyristor T1 is triggered after the contact gap of the first ultra-fast mechanical switch UFD1 reaches the preset withstand voltage opening distance. 2a Second auxiliary thyristor T 2b This causes the first commutation capacitor C1 to reverse the phase of the first commutation thyristor T1, thereby transferring the current to the selected current-limiting branch.

[0033] After the selected current processing state is established and before the LC forced zero-crossing commutation branch is triggered, a fault persistence discrimination window is set to obtain at least two parameters from the fault current amplitude, fault current change rate, fault duration, and bus voltage recovery status to determine whether the fault persists.

[0034] When the fault is determined to be a non-persistent fault, subsequent LC forced zero-crossing commutation operations are stopped, and the main current path is restored; when the fault is determined to be a persistent fault, the commutation selection sampling current I is acquired. post Select sampling current I based on commutation post Choose either the first LC forced zero-crossing commutation branch or the second LC forced zero-crossing commutation branch to artificially generate zero-crossing current in the second ultra-fast mechanical switch UFD2 branch.

[0035] After the current in the second ultra-fast mechanical switch UFD2 branch generates an artificial zero crossing, when in a state without additional current limiting, the first auxiliary thyristor T is kept in place. 2a Second auxiliary thyristor T 2b Energy transfer thyristor T 13 When the energy discharge switch S is in an untriggered state, the current in the first commutator thyristor T1 and the LC oscillation branch naturally decays under the equivalent damping effect of the circuit. When the current of the first commutator thyristor T1 decreases below its holding current and remains below a preset turn-off time, and the current in the LC oscillation branch decreases to zero or below a preset threshold, the interruption is determined to be complete. When in the first current limiting state or the second current limiting state, after the first commutator thyristor T1 completes turn-off and the current in the LC oscillation branch decays to zero or below a preset threshold, the energy transfer thyristor T is triggered. 13 This allows the equivalent inductance of the line, the remaining energy in the DC system, and the energy stored in the current-limiting inductor to be transferred to the first commutation capacitor C1. When the voltage of the first commutation capacitor C1 reaches the preset access threshold, the energy discharge switch S is turned on to connect to the surge arrester MOV.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] The present invention sets the current limiting inductor in the auxiliary converter current limiting branch (2). During normal operation, neither the first current limiting branch nor the second current limiting branch is connected to the main current channel, which can avoid the additional voltage drop and power loss caused by the long-term series connection of the current limiting inductor.

[0038] This invention is based on the pre-current limiting sampling current I before the current limiting branch is put into operation. pre Choosing between no additional current limiting state, first current limiting state, or second current limiting state allows current limiting branches with different inductance values ​​to adapt to different fault current levels, which is beneficial for balancing rapid action under low current conditions and current rise rate limitation under high fault current conditions.

[0039] The present invention uses an auxiliary converter current limiting branch (2) to connect the series segment consisting of the first ultra-fast mechanical switch UFD1 and the load converter switch LCS, so that the first ultra-fast mechanical switch UFD1 can complete isolation under zero current or near-zero current conditions, while retaining the second ultra-fast mechanical switch UFD2 as the subsequent manual zero-crossing switch, thereby realizing the phased coordinated operation of the two mechanical switches.

[0040] This invention sets a fault persistence discrimination window after the current limiting state is established and before the LC forced zero-crossing commutation branch is triggered. For non-persistent faults, it can avoid subsequent LC forced zero-crossing commutation and the complete energy absorption process, reducing the number of LC commutation branch triggers and the stress on power electronic devices; for mechanical mechanisms that allow mid-term cancellation of tripping, it can also reduce the number of times the mechanical switch completes full-stroke tripping and re-closing.

[0041] This invention selects the sampling current I based on the commutation. post By selecting LC forced zero-crossing commutation branches with different available initial oscillation energies, the reverse commutation current can be matched with the actual interrupting current, which can reduce the excess commutation energy under weak current conditions and improve the reliability of artificial zero-crossing under medium and large fault current conditions.

[0042] This invention utilizes the first commutation capacitor C1 to perform both reverse commutation of the first commutation thyristor T1 and transient buffering of residual energy under the first and second current limiting states. When the voltage of the first commutation capacitor C1 reaches the preset access threshold, the surge arrester MOV is connected, so that the first commutation capacitor C1 and the surge arrester MOV work together to process the residual energy in the later stage of the interruption under the corresponding operating conditions. This is beneficial to limit the overvoltage of the energy transfer circuit and reduce the energy stress of a single energy-absorbing device.

[0043] This invention can form a commutation and forced zero-crossing path suitable for both forward and reverse fault currents, and can be extended to DC distribution networks, new energy DC collection systems, rail transit DC power supply systems, ship DC systems and other bidirectional DC power transmission and distribution applications. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0045] Figure 1 A schematic diagram of the circuit topology and functional unit division of the hybrid DC circuit breaker provided by the present invention;

[0046] In the diagram, 1 is the main current channel unit; 2 is the auxiliary commutation current limiting branch; 3 is the multi-level LC forced zero-crossing commutation unit; 4 is the energy buffer and absorption unit; 5 is the detection and control unit; UFD1 is the first ultra-fast mechanical switch; UFD2 is the second ultra-fast mechanical switch; LCS is the load commutation switch; T1 is the first commutation thyristor; T 2a T 2b For auxiliary thyristors; T 3a T 3b Select a thyristor for the current-limiting branch; T 4a For the first LC commutator thyristor; T 4b For the second LC commutator thyristor; T 4c T 4d For pre-charged conduction thyristors; T5 to T 10 For commutator thyristors; T 11 T 12 For pre-charged voltage regulating thyristors; T 13 C1 to C5 are energy transfer thyristors; L1 to L3 are capacitors; R1 and R2 are pre-charge voltage regulating resistors; Da to Dd are commutation diodes; S is an energy discharge switch; MOV is a surge arrester.

[0047] Figure 2 A schematic diagram of the overall structure of the hybrid DC circuit breaker provided by the present invention;

[0048] Figure 3 A flowchart of the interruption control of a hybrid DC circuit breaker provided by the present invention;

[0049] Figure 4 This is a schematic diagram of the switching path of the present invention under weak current conditions;

[0050] Figure 5 This is a schematic diagram of the interruption path of the present invention under medium fault current conditions.

[0051] Figure 6 This is a schematic diagram of the interruption path under high fault current conditions according to the present invention. Detailed Implementation

[0052] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. It should be understood that the following embodiments are only used to illustrate the present invention and are not intended to limit the scope of protection of the present invention. Equivalent substitutions or adaptive adjustments made by those skilled in the art to the component types, parameters, connection forms, and control timing without departing from the concept of the present invention can all be included within the scope of protection of the present invention.

[0053] This implementation method is based on Figure 1 The diagram primarily illustrates the forward operating condition where the DC current flows from left to right. For the reverse operating condition where the DC current flows from right to left, the bidirectional current-carrying structure of the load commutation switch LCS and the commutation diode D can be used. a To D d and commutator thyristors T5 to T 10 It forms a commutation and forced zero-crossing path corresponding to the forward operating condition, and its control principle is the same as that of the forward operating condition.

[0054] Example 1: Overall Structure of Hybrid DC Circuit Breaker

[0055] like Figure 1 and Figure 2 As shown, this embodiment provides a hybrid DC circuit breaker based on graded current limiting, multi-level LC forced zero crossing and fault persistence discrimination, including a main current channel unit (1), an auxiliary commutation current limiting branch (2), a multi-level LC forced zero crossing commutation unit (3), an energy buffer and absorption unit (4), and a detection and control unit (5).

[0056] The main current channel unit (1) includes a first ultra-fast mechanical switch UFD1, a load commutator switch LCS, and a second ultra-fast mechanical switch UFD2 connected in series in the DC main circuit. The first ultra-fast mechanical switch UFD1 is mainly used to form front-end electrical isolation after current transfer, and the second ultra-fast mechanical switch UFD2 is mainly used to interrupt the fault current of the second stage under the action of the multi-level LC forced zero-crossing commutator unit (3).

[0057] In this embodiment, the load commutation switch (LCS) is composed of two insulated-gate bipolar transistors (IGBTs) connected in reverse series. Each IGBT has an anti-parallel diode, enabling the LCS to conduct current bidirectionally and be controlled to turn off. The LCS can also be an IGBT module, an integrated gate commutated thyristor module, a power MOSFET module, or other fully controllable power semiconductor devices that meet the voltage, current, and turn-off speed requirements.

[0058] One end of the auxiliary converter current limiting branch (2) is connected to the side of the first ultra-fast mechanical switch UFD1 closest to the DC power supply, and the other end is connected to the node between the load converter switch LCS and the second ultra-fast mechanical switch UFD2. Therefore, the auxiliary converter current limiting branch (2) is connected across the two ends of the series segment formed by the first ultra-fast mechanical switch UFD1 and the load converter switch LCS, but does not bypass the second ultra-fast mechanical switch UFD2.

[0059] Through the above connection, after a fault occurs, the current flowing through the first ultra-fast mechanical switch UFD1 and the load converter switch LCS can be transferred to the auxiliary converter current limiting branch (2), so that the first ultra-fast mechanical switch UFD1 can be tripped under zero current or near-zero current conditions; at the same time, the current to be interrupted after being processed by the auxiliary converter current limiting branch (2) still flows through the second ultra-fast mechanical switch UFD2, so that the second ultra-fast mechanical switch UFD2 branch can generate artificial zero crossing by using the LC reverse converter current in the subsequent stage.

[0060] The auxiliary commutation current limiting branch (2) includes a fast commutation unit and an optional current limiting unit. The fast commutation unit includes a first commutation thyristor T1, a first commutation capacitor C1, and a first auxiliary thyristor T1. 2a Second auxiliary thyristor T 2b , commutation diode D a To D d The first pre-charge regulating capacitor C4, the first pre-charge regulating resistor R1, and the first pre-charge regulating thyristor T 11 .

[0061] The first commutator thyristor T1 is used to quickly establish an auxiliary current path after a fault is detected. The first auxiliary thyristor T... 2a Second auxiliary thyristor T 2b Used to turn on the first commutation capacitor C1 at a specified time, so that the first commutation capacitor C1 applies a reverse commutation voltage to the first commutation thyristor T1, thereby reducing the current of the first commutation thyristor T1 and enabling it to obtain sufficient reverse bias time.

[0062] The first pre-charge voltage regulating capacitor C4, the first pre-charge voltage regulating resistor R1, and the first pre-charge voltage regulating thyristor T 11 This forms the first pre-charge voltage regulating branch. The detection and control unit (5) controls the first pre-charge voltage regulating thyristor T... 11 The conduction time or conduction number is determined so that the first commutation capacitor C1 obtains a pre-charge voltage with a preset polarity and preset amplitude before being switched off.

[0063] The optional current limiting unit includes a first current limiting branch and a second current limiting branch. The first current limiting branch includes a first current limiting inductor L1 and a first current limiting branch selection thyristor T connected in series. 3aThe second current-limiting branch includes a second current-limiting inductor L2 connected in series and a second current-limiting branch selection thyristor T. 3b The inductance value of the second current-limiting inductor L2 is greater than the inductance value of the first current-limiting inductor L1.

[0064] The first current-limiting branch is used for medium fault current conditions, and the second current-limiting branch is used for larger fault current conditions. Within a single fault handling cycle, the first current-limiting branch selects thyristor T. 3a Or select thyristor T for the second current-limiting branch 3b Once triggered, the corresponding current limiting state remains locked until the current in that branch naturally decreases to zero or falls below the preset exit threshold.

[0065] The multi-level LC forced zero-crossing commutation unit (3) is connected across the two ends of the second ultra-fast mechanical switch UFD2, and includes a first oscillating capacitor C2, a second oscillating capacitor C3, an LC oscillating inductor L3, and a first LC commutation thyristor T. 4a Second LC commutator thyristor T 4b First pre-charged thyristor T 4c Second pre-charged thyristor T 4d , commutator thyristors T5 to T 10 The second pre-charge regulating capacitor C5, the second pre-charge regulating resistor R2, and the second pre-charge regulating thyristor T 12 .

[0066] First oscillation capacitor C2, first LC commutation thyristor T 4a LC oscillating inductor L3 and commutation thyristors T5 to T 10 The corresponding devices in the circuit form the first LC forced zero-crossing commutation branch; the second oscillation capacitor C3 and the second LC commutation thyristor T 4b LC oscillating inductor L3 and commutation thyristors T5 to T 10 The corresponding devices in the circuit constitute the second LC forced zero-crossing commutation branch.

[0067] The first LC forced zero-crossing commutation branch has a smaller available initial oscillation energy and is used for weak current or low current conditions after current limiting; the second LC forced zero-crossing commutation branch has a larger available initial oscillation energy and is used for medium and large current conditions after processing by the first or second current limiting branch.

[0068] The second precharge voltage regulating capacitor C5, the second precharge voltage regulating resistor R2, and the second precharge voltage regulating thyristor T 12 This forms the second pre-charge voltage regulating branch. The first pre-charge conducting thyristor T... 4c The second pre-charge thyristor T4d is used to establish the pre-charge path for the first oscillating capacitor C2, and the second pre-charge thyristor T4d is used to establish the pre-charge path for the second oscillating capacitor C3.

[0069] The energy buffer and absorption unit (4) includes an energy transfer thyristor T. 13 The system includes a first commutation capacitor C1, an energy discharge switch S, and a surge arrester MOV. The first commutation capacitor C1 is used both for the reverse commutation of the first commutator thyristor T1 and for storing energy in the current-limiting inductor and the remaining energy of the line in the transient receiving section during the later stages of the interruption in the first or second current-limiting state.

[0070] The energy discharge switch S is connected in series in the input branch of the surge arrester MOV. The energy discharge switch S can be a thyristor, insulated gate bipolar transistor, integrated gate commutated thyristor, or other switching devices that meet the withstand voltage and pulse current requirements. The surge arrester MOV is used to limit the overvoltage of the first commutation capacitor C1 and the energy transfer circuit and absorb the remaining energy after connection.

[0071] The detection and control unit (5) includes a main circuit current detection module, a branch current detection module, a bus voltage detection module, a capacitor voltage detection module, a mechanical switch position detection module, a controller, and a drive module. The controller may be a digital signal processor, a field-programmable gate array, a microcontroller, or a combined control platform composed of the above devices.

[0072] The main circuit current detection module is used to acquire the main circuit current after a fault occurs and the pre-limiting sampling current I before the current-limiting branch is activated. pre The branch current detection module is used to acquire the commutation selection sampling current I after the current limiting state is established. post The system includes LC oscillation branch current and energy transfer branch current; a bus voltage detection module to determine whether the bus voltage has recovered; a capacitor voltage detection module to detect the voltage of the first commutation capacitor C1, the first oscillation capacitor C2, and the second oscillation capacitor C3; and a mechanical switch position detection module to obtain the contact position or opening distance of the first ultra-fast mechanical switch UFD1 and the second ultra-fast mechanical switch UFD2.

[0073] The detection and control unit (5) is connected to the load commutation switch LCS, the first ultra-fast mechanical switch UFD1, the second ultra-fast mechanical switch UFD2, the first commutation thyristor T1, and the first auxiliary thyristor T1, respectively. 2a Second auxiliary thyristor T 2b The first current-limiting branch selects thyristor T. 3a The second current-limiting branch selects thyristor T. 3b First LC commutator thyristor T 4a Second LC commutator thyristor T 4b First pre-charged thyristor T 4c Second pre-charged thyristor T 4d , commutator thyristors T5 to T 10 First pre-charged voltage regulating thyristor T 11Second pre-charge voltage regulating thyristor T 12 Energy transfer thyristor T 13 Connect to the energy discharge switch S.

[0074] Example 2: Normal Operation and Pre-charge Process

[0075] During normal operation, the first ultra-fast mechanical switch UFD1, the load converter switch LCS, and the second ultra-fast mechanical switch UFD2 are all in the ON or OFF state, and the DC system current flows along the main current path. The first converter thyristor T1 and the first auxiliary thyristor T... 2a Second auxiliary thyristor T 2b The first current-limiting branch selects thyristor T. 3a The second current-limiting branch selects thyristor T. 3b First LC commutator thyristor T 4a Second LC commutator thyristor T 4b , commutator thyristors T5 to T 10 Energy transfer thyristor T 13 Both the energy discharge switch S and the energy release switch S are in an untriggered state.

[0076] During normal operation, neither the first current-limiting inductor L1 nor the second current-limiting inductor L2 is connected in series in the main current path, so there will be no additional voltage drop and copper loss caused by the long-term current flow of the large inductor. The auxiliary commutation current-limiting branch (2) only bears the corresponding static voltage, and its current-carrying device does not bear the normal load current.

[0077] Before the switching operation, the detection and control unit (5) controls the first pre-charge voltage regulation branch to pre-charge the first commutation capacitor C1, so that the first commutation capacitor C1 has a polarity that can apply a reverse voltage to the first commutation thyristor T1. The detection and control unit (5) determines whether the pre-charging is completed by detecting the voltage value of the first commutation capacitor C1.

[0078] Simultaneously, the detection and control unit (5) controls the second pre-charge voltage regulating branch, and respectively cooperates with the first pre-charge conducting thyristor T 4c Second precharged thyristor T 4d The first oscillating capacitor C2 and the second oscillating capacitor C3 are pre-charged. The pre-charge polarity of the first oscillating capacitor C2 and the second oscillating capacitor C3 is set so that after the corresponding LC branch is triggered, a commutation current opposite to the direction of the current to be interrupted is injected into the second ultra-fast mechanical switch UFD2 branch.

[0079] The available initial oscillation energy E1 of the first LC forced zero-crossing commutation branch and the available initial oscillation energy E2 of the second LC forced zero-crossing commutation branch are respectively:

[0080]

[0081] Among them, U C2 U is the pre-charge voltage of the first oscillating capacitor C2. C3 This is the pre-charge voltage for the second oscillation capacitor C3. By setting C3 to be greater than C2, U... C3 Greater than U C2 Alternatively, the capacitor value and precharge voltage can be adjusted simultaneously to make the second available initial oscillation energy E2 greater than the first available initial oscillation energy E1.

[0082] To prevent commutation failure due to insufficient precharge voltage, the detection and control unit (5) only allows the circuit breaker to enter the interruption ready state after the voltages of the first commutation capacitor C1, the first oscillation capacitor C2, and the second oscillation capacitor C3 all reach the corresponding allowable range. If the voltage of any capacitor is lower than the minimum allowable value or higher than the maximum allowable value, the corresponding interruption action is blocked and an abnormal signal is output.

[0083] Example 3: Fault Detection and Main Current Transfer Process

[0084] like Figure 3 As shown, when the main circuit current, bus voltage, or current change rate meets the preset fault criteria, the detection and control unit (5) determines that the DC system has entered the fault handling state. The fault criteria may include at least one of the following: the main circuit current exceeds the start-up threshold, the current change rate exceeds the change rate threshold, and the bus voltage is lower than the undervoltage threshold. Alternatively, a multi-parameter joint criterion may be used.

[0085] After a fault is detected, the detection and control unit (5) triggers the first commutator thyristor T1 to establish an auxiliary current channel; then controls the load commutator switch LCS to turn off, and simultaneously issues a trip command to the first ultra-fast mechanical switch UFD1 and the second ultra-fast mechanical switch UFD2.

[0086] Since the auxiliary converter current limiting branch (2) is connected across the two ends of the series segment formed by the first ultra-fast mechanical switch UFD1 and the load converter switch LCS, after the first converter thyristor T1 is turned on and the load converter switch LCS is turned off, the main current that originally flowed through the first ultra-fast mechanical switch UFD1 and the load converter switch LCS is transferred to the auxiliary converter current limiting branch (2).

[0087] After the main current completes the transfer to the auxiliary converter current-limiting branch (2), and before the first and second current-limiting branches are put into operation, the detection and control unit (5) acquires the sampling current I before current limiting. pre The sampling current I before current limiting pre The instantaneous current, short-time window average current, or digitally filtered current value at the sampling moment can be used to select the state without additional current limiting, the first current limiting state, or the second current limiting state.

[0088] After the branch current of the first ultra-fast mechanical switch UFD1 drops to zero or below the first preset current threshold, its contacts continue to separate under lower current stress. The detection and control unit (5) can directly determine the contact opening distance based on the mechanical switch position sensor, or it can estimate the contact opening distance based on the calibrated opening time-stroke characteristics.

[0089] The second ultra-fast mechanical switch UFD2 begins to disconnect after receiving the tripping command, but the current to be interrupted still passes through the second ultra-fast mechanical switch UFD2 before the LC forced zero-crossing commutator unit is triggered. The contact gap of the second ultra-fast mechanical switch UFD2 gradually increases to establish insulation conditions for the recovery voltage withstand after the subsequent artificial zero-crossing.

[0090] Sampled current I before current limiting pre The sampling time should be after the main current has completed its transfer to the auxiliary converter current-limiting branch (2), and before the first current-limiting branch or the second current-limiting branch is put into operation. In order to reduce the error caused by the delay of the switch action, several points can be sampled continuously after the fault starts, and the predicted current at the actual time of the current-limiting branch is obtained by linear extrapolation or state observation.

[0091] Example 4: Graded Current Limiting and Fault Persistence Determination

[0092] The detection and control unit (5) sets the first grade threshold I. th1 Second grade threshold I th2 , and I th2 Greater than I th1 When the current I is sampled before current limiting pre Less than the first grade threshold I th1 When I is selected, the state without additional current limiting is chosen; when I pre Greater than or equal to I th1 And less than I th2 When I... pre Greater than or equal to I th2 When that happens, select the second current limiting state.

[0093] Without additional current limiting, the first current limiting branch selects thyristor T. 3a Second current limiting branch selects thyristor T 3b Neither of them triggers, and the auxiliary converter current limiting branch (2) carries a weak current through the short-time low-inductance converter holding path formed by the fast converter unit. Since the current to be interrupted is small under this condition, the fault persistence judgment window and the subsequent LC trigger delay are set to be short.

[0094] In the first current-limiting state, the detection and control unit (5) triggers the first current-limiting branch selection thyristor T. 3aThis allows the first current-limiting inductor L1 to enter the fault current path. The first current-limiting inductor L1 is used to limit the rise rate of the moderate fault current and to provide a controlled current holding phase for fault persistence determination.

[0095] In the second current-limiting state, the detection and control unit (5) triggers the second current-limiting branch selection thyristor T. 3b This allows the second current-limiting inductor L2 to enter the fault current path. Since L2 is larger than L1, the second current-limiting branch has a stronger ability to suppress the rise rate of large fault currents.

[0096] To avoid current path interruption during the turn-off of the first commutator thyristor T1, in either the first or second current-limiting state, the triggering of the corresponding current-limiting branch thyristor should be no later than that of the first auxiliary thyristor T1. 2a Second auxiliary thyristor T 2b The triggering occurs. After the corresponding current-limiting branch is established, the first commutation capacitor C1 is connected to the first auxiliary thyristor T. 2a Second auxiliary thyristor T 2b A reverse voltage is applied to the first commutator thyristor T1, causing the current to gradually transfer from the first commutator thyristor T1 to the selected current-limiting branch.

[0097] After the selected current limiting state is established, the detection and control unit (5) enters the fault persistence discrimination window. For the state without additional current limiting, the start time of the fault persistence discrimination window can be set to the moment when the main current completes the transfer to the auxiliary commutation current limiting branch (2); for the first current limiting state or the second current limiting state, the start time can be set to the moment when the current of the selected current limiting branch reaches the preset ratio of the current of the auxiliary commutation current limiting branch (2), or the moment when the current of the first commutation thyristor T1 decreases to the preset value; the end time is earlier than the planned trigger time of the selected LC forced zero crossing commutation branch.

[0098] Within the fault persistence determination window, the detection and control unit (5) acquires at least two parameters from the fault current amplitude, fault current change rate, fault duration, and bus voltage recovery status. To suppress measurement noise, moving average, low-pass filtering, or multi-point consistency judgment can be applied to each parameter.

[0099] In one discrimination method, when the fault current is continuously lower than the current recovery threshold and the bus voltage is continuously higher than the voltage recovery threshold and remains above the preset confirmation time, the fault is determined to be a non-continuous fault; when the above conditions are not met simultaneously before the end of the discrimination window, the fault is determined to be a continuous fault.

[0100] Hysteresis can be set for the current recovery threshold and the bus voltage recovery threshold. For example, the current initiation threshold for entering a fault state is higher than the current recovery threshold for exiting a fault state, and the bus voltage threshold for entering an undervoltage state is lower than the voltage recovery threshold for exiting an undervoltage state, thereby avoiding repeated changes in the judgment result caused by fluctuations in current or voltage around the threshold.

[0101] When the fault is determined to be a non-continuous fault, the detection and control unit (5) prohibits the triggering of the first LC forced zero-crossing commutation branch and the second LC forced zero-crossing commutation branch, and executes the main current recovery process. If the mechanisms of the first ultra-fast mechanical switch UFD1 and the second ultra-fast mechanical switch UFD2 allow the opening to be cancelled midway, the opening command is cancelled and the switch is controlled to return to the closing position; if the mechanical mechanism does not allow the return midway, the switch is made to complete the opening and then re-execute the closing.

[0102] After both the first ultra-fast mechanical switch UFD1 and the second ultra-fast mechanical switch UFD2 reach the state that meets the main current requirement, the detection and control unit (5) controls the load converter switch LCS to resume conduction, so that the current in the auxiliary converter current limiting branch (2) is transferred back to the main current path. The thyristor in the auxiliary converter current limiting branch (2) is turned off after the branch current naturally crosses zero.

[0103] Once the first or second current-limiting state is selected within a fault handling cycle, it will not switch to another current-limiting state based on instantaneous current fluctuations. First grade threshold I th1 Second grade threshold I th2 The hysteresis intervals can be set separately to avoid duplicate selections near the threshold.

[0104] Example 5: Forced zero-crossing process of multi-level LC under persistent fault

[0105] When the fault is determined to be a persistent fault, the detection and control unit (5) acquires the commutation selection sampling current I of the second ultra-fast mechanical switch UFD2 branch after the selected current processing state is established and before the LC branch is triggered. post The commutation selection sampling current I post It reflects the actual interrupt current of the grade and is used to select the first LC forced zero-crossing commutation branch or the second LC forced zero-crossing commutation branch.

[0106] The detection and control unit (5) sets the LC energy level selection threshold I. LC When the commutation selects the sampling current I post Less than the LC level selection threshold I LC When I is selected, the first LC forced zero-crossing commutation branch is chosen; when I post Greater than or equal to I LC When selecting the second LC forced zero-crossing commutation branch.

[0107] To ensure the reliability of artificial zero crossing, the peak reverse commutation current generated by the selected LC branch should be greater than the commutation selection sampling current I. post And retain commutation margin. Under the approximate condition of neglecting branch resistance and device voltage drop, the peak oscillating currents of the first LC branch and the second LC branch can be expressed as:

[0108]

[0109] Let the commutation margin factor be K. s K s If the value is greater than 1, then the selected LC branch should satisfy I. LC，pk ≥K s ·I post The commutation margin factor can be determined based on device parameter deviations, branch resistances, arcing characteristics of mechanical switches, and control errors.

[0110] exist Figure 1 Under the forward current condition shown, when the first LC forced zero-crossing commutation branch is selected, the detection and control unit (5) triggers the ninth commutation thyristor T9 and the first LC commutation thyristor T after the contact gap of the second ultra-fast mechanical switch UFD2 reaches the preset withstand voltage opening distance. 4a Together with the eighth commutator thyristor T8, the first oscillation capacitor C2 and the LC oscillation inductor L3 form an oscillation circuit.

[0111] exist Figure 1 Under the forward current condition shown, when the second LC forced zero-crossing commutation branch is selected, the detection and control unit (5) triggers the ninth commutation thyristor T9 and the second LC commutation thyristor T1. 4b Together with the eighth commutator thyristor T8, the second oscillation capacitor C3 and the LC oscillation inductor L3 form an oscillation circuit.

[0112] The aforementioned oscillation circuit injects a commutation current into the second ultra-fast mechanical switch UFD2 branch in the opposite direction to the forward interrupted current. When the instantaneous value of the reverse commutation current reaches or exceeds the interrupted current in the second ultra-fast mechanical switch UFD2 branch, the combined current of the second ultra-fast mechanical switch UFD2 branch drops to zero and reverses in a short time, thereby forming a reliable artificial zero-crossing condition.

[0113] Under reverse fault current conditions, artificial zero crossing can be achieved through a commutation path symmetrical to that under forward conditions. Figure 1 Under the device orientation shown, the tenth commutator thyristor T can be used in the reverse weak current condition. 10 First LC commutator thyristor T 4a The corresponding path is formed by the seventh commutator thyristor T7; for medium and large reverse current conditions, the tenth commutator thyristor T1 can be used. 10 Second LC commutator thyristor T 4bThe seventh commutator thyristor T7 forms the corresponding path.

[0114] The fifth commutator thyristor T5 and the sixth commutator thyristor T6, together with the seventh commutator thyristor T7 and the eighth commutator thyristor T8, are used to provide corresponding conduction paths during the stages of oscillation current direction change, branch freewheeling, or energy feedback. The specific triggering combination can be set according to the precharge polarity of the first oscillation capacitor C2 and the second oscillation capacitor C3 and the actual device orientation.

[0115] When the current in the branch of the second ultra-fast mechanical switch UFD2 generates an artificial zero crossing, its contact gap bears the recovery voltage. The detection and control unit (5) determines whether the artificial zero crossing is successful based on the opening distance of the second ultra-fast mechanical switch UFD2, the zero-crossing state of the branch current, and the change in the bus voltage.

[0116] If the current of the second ultra-fast mechanical switch UFD2 branch does not cross zero within the specified time, the detection and control unit (5) can block the subsequent energy transfer action according to the preset protection strategy and output a commutation failure signal; if the device allows, a backup commutation trigger or redundant energy absorption branch can also be configured.

[0117] Example 6: Energy buffering and absorption process in the later stage of the interruption

[0118] After the current in the second ultra-fast mechanical switch UFD2 branch generates an artificial zero crossing, in the absence of additional current limiting, the detection and control unit (5) maintains the first auxiliary thyristor T. 2a Second auxiliary thyristor T 2b Energy transfer thyristor T 13 With the energy discharge switch S in an untriggered state, the current in the first commutator thyristor T1 and the LC oscillation branch naturally decays under the equivalent damping effect of the circuit.

[0119] The detection and control unit (5) continuously detects the current of the first commutator thyristor T1, the current of the LC oscillation branch, and the voltage of related devices. When the current of the first commutator thyristor T1 drops below its holding current and remains at or above the preset turn-off time, the first commutator thyristor T1 turns off naturally. When the current of the LC oscillation branch drops to zero or below the preset threshold, and the voltage of related devices does not exceed the preset overvoltage threshold, it is determined that the interruption process under the condition of no additional current limiting is completed. In the above process, the first commutation capacitor C1 does not undertake the function of forcibly absorbing all remaining energy. When the voltage of the first commutation capacitor C1 does not reach the preset MOV access threshold, the energy discharge switch S remains off, and the surge arrester MOV does not participate in this weak current interruption process.

[0120] For both the first and second current-limiting states, the first commutator thyristor T1 has completed reverse commutation during the preceding current-limiting process. When it is confirmed that the first commutator thyristor T1 has been turned off, the LC oscillation branch current has decayed to zero or below a preset threshold, and the second ultra-fast mechanical switch UFD2 has a contact gap capable of withstanding the recovery voltage, the energy transfer thyristor T is triggered. 13 Energy transfer thyristor T 13 After conduction, the remaining energy in the equivalent inductance of the line, part of the energy continuously fed into the fault point by the DC system, and the energy stored in the first current-limiting inductor L1 or the second current-limiting inductor L2 that has been put into operation are transferred to the first commutation capacitor C1, causing the voltage of the first commutation capacitor C1 to rise.

[0121] The first commutation capacitor C1 only serves as a transient buffer during the initial stage of energy transfer and is not required to independently absorb all the energy stored in the current-limiting inductor and the remaining energy in the line. The detection and control unit (5) detects the voltage U of the first commutation capacitor C1 in real time. C1 .

[0122] When the voltage U of the first commutation capacitor C1 C1 Reaching the preset MOV access threshold U on At this time, the detection and control unit (5) controls the energy discharge switch S to turn on, connecting the surge arrester MOV to the energy transfer circuit. The preset MOV connection threshold U... on The voltage is lower than the main clamping voltage of the surge arrester MOV to ensure that the surge arrester MOV is connected before the first commutation capacitor C1 reaches a dangerous overvoltage.

[0123] As energy transfer continues, the surge arrester MOV enters the nonlinear conduction region, clamping the voltage of the first commutation capacitor C1 and the energy transfer circuit, and absorbing the remaining energy. Thus, the first commutation capacitor C1 acts as a fast transient buffer, while the surge arrester MOV undertakes the main absorption of remaining energy. Together, they reduce the voltage and energy stress of individual components.

[0124] Energy coordination design can be checked according to the following formula:

[0125]

[0126] In the formula, L k For the first current-limiting inductor L1 or the second current-limiting inductor L2, I E0 E is the branch current before energy transfer. line U represents the equivalent residual energy in the line and system. C1,0 E is the voltage across the first commutation capacitor C1 at the start of energy transfer. MoV,allow The energy that the MOV surge arrester is allowed to absorb during a single interruption.

[0127] When the current limiting branch current, the energy transfer branch current, and the surge arrester MOV current all decrease to the corresponding end threshold, the detection and control unit (5) determines that a single interruption process is complete. Subsequently, the application of trigger pulses to the relevant thyristors is stopped, and they naturally turn off after the branch current crosses zero; for fully controlled switching devices, they are controlled to turn off, and the pre-charge voltage of the first commutation capacitor C1, the first oscillation capacitor C2, and the second oscillation capacitor C3 is restored through the first pre-charge voltage regulating branch and the second pre-charge voltage regulating branch.

[0128] Example 7: Parameter Configuration, Threshold Design, and Action Timing

[0129] In one exemplary parameter configuration, the DC system has a rated voltage of 10kV, a rated current of 500A, and a line equivalent resistance R. line The resistance is 0.12Ω, and the equivalent inductance of the line is L. line The load resistance is 0.6mH, and the load resistance is R. load The resistance is 20Ω. The above parameters are only used to illustrate the parameter coordination method of the present invention and do not constitute a limitation on the applicable voltage and current levels.

[0130] The first current-limiting inductor L1 can be 2mH, and the second current-limiting inductor L2 can be 5mH. The selection of the first current-limiting inductor L1 and the second current-limiting inductor L2 can be determined based on the DC voltage, the allowable rate of rise of the fault current, the length of the fault duration discrimination window, and the peak reverse commutation current that the LC branch can provide.

[0131] Under the approximate condition of neglecting resistance and internal resistance of the power supply, in order to ensure that the current does not exceed the allowable current I within the discrimination time Δt. allow The selected current-limiting inductor L k It is advisable to satisfy:

[0132]

[0133] In the formula, U dc L1 represents the DC system voltage, and I0 represents the initial current when the current-limiting branch is switched on. In actual design, the effects of line inductance, fault resistance, load branch, and power supply equivalent impedance should also be considered, and L1 and L2 should be verified through electromagnetic transient simulation.

[0134] In an exemplary multi-level LC parameter configuration, the LC oscillation inductor L3 is 160μH, the first oscillation capacitor C2 is 6.4μF, the second oscillation capacitor C3 is 100μF, and the pre-charge voltage of both the first oscillation capacitor C2 and the second oscillation capacitor C3 is 5kV.

[0135] Based on the approximation formula for peak oscillation current, the theoretical peak reverse commutation current of the first LC forced zero-crossing commutation branch is approximately 1.0 kA, and the theoretical peak reverse commutation current of the second LC forced zero-crossing commutation branch is approximately 3.95 kA. Considering branch resistance, device voltage drop, and parameter deviations, the LC energy level selection threshold should be lower than the corresponding theoretical peak value, while retaining the specified commutation margin.

[0136] For example, the first classification threshold I can be... th1 Set near the rated current, and set the second grade threshold I th2 Set to higher than I th1 Fault current level; LC level selection threshold I LC Then the sampling current I is selected according to the commutation. post The effective reverse current available from the first LC branch is determined. Each threshold can be set within a hysteresis range of 5% to 15%.

[0137] The first commutation capacitor C1 can be determined based on the reverse bias time required by the first commutation thyristor T1, the allowable voltage change rate of the first commutation capacitor C1, and the buffering requirements at the initial stage of energy transfer. The pre-charge voltage of the first commutation capacitor C1 and the MOV access threshold U... on The clamping voltage of the surge arrester MOV should meet the dual requirements of reliable commutation of the first commutator thyristor T1 and overvoltage limitation in the later stage of interruption.

[0138] In one action timing example, after fault detection is completed, the first commutator thyristor T1 is first triggered and the load commutator switch LCS is turned off. At the same time, a tripping command is issued to the first ultra-fast mechanical switch UFD1 and the second ultra-fast mechanical switch UFD2; then, based on the sampled current I before current limiting... pre When selecting the current limiting state, if no additional current limiting state is selected, the first commutator thyristor T1 remains on and the first auxiliary thyristor T1 is not triggered before the LC forced zero-crossing commutation branch is triggered. 2a Second auxiliary thyristor T 2b When the first current limiting state or the second current limiting state is selected, the corresponding current limiting branch is established, and after the first ultra-fast mechanical switch UFD1 reaches the specified opening distance, the reverse commutation of the first commutation thyristor T1 is completed through the first commutation capacitor C1.

[0139] After the selected current-limiting state is established, the detection and control unit (5) performs fault persistence determination. If the fault disappears, the LC branch triggering is disabled and the main current is restored; if the fault persists, the commutation selection sampling current I is acquired. post Then select the corresponding LC forced zero-crossing commutation branch. The selected LC branch is triggered after the second ultra-fast mechanical switch UFD2 reaches the specified opening distance.

[0140] After the artificial zero-crossing occurs in the second ultra-fast mechanical switch UFD2 branch, in the absence of additional current limiting, the first auxiliary thyristor T is maintained. 2a Second auxiliary thyristor T 2b Energy transfer thyristor T 13 With the energy discharge switch S in an untriggered state, the current in the first commutator thyristor T1 and the LC oscillation branch naturally decays. When the current in the first commutator thyristor T1 drops below the sustaining current and remains off for a preset time, and the current in the LC oscillation branch drops to zero or below a preset threshold, the weak current interruption is considered complete. For the first current limiting state and the second current limiting state, after confirming that the first commutator thyristor T1 has completed its turn-off and the current in the LC oscillation branch has decayed to zero or below a preset threshold, the energy transfer thyristor T is triggered. 13 When the voltage of the first commutation capacitor C1 reaches the preset MOV connection threshold, the energy discharge switch S is turned on, instead of waiting for all the energy to be transferred to the first commutation capacitor C1 before connecting the surge arrester MOV.

[0141] The timing of each action is not limited to a fixed time value, but is determined by the fault detection result and the sampled current I before current limiting. pre commutation selection sampling current I post The operating distance is determined by the mechanical switch contact gap, the LC oscillation branch current, and the voltage of the first commutation capacitor C1. By combining event triggering with time protection, the reliability of operation under different system parameters and different fault conditions can be improved.

[0142] When simulating or testing this embodiment, weak current, medium fault current and large fault current conditions can be set respectively, and the main circuit current, the branch current of the first ultra-fast mechanical switch UFD1, the branch current of the second ultra-fast mechanical switch UFD2, the current of the first current limiting inductor L1 or the second current limiting inductor L2, the LC reverse commutation current, the voltage of the first commutation capacitor C1 and the energy absorbed by the surge arrester MOV can be recorded.

[0143] The verification results should at least satisfy the following: the first ultra-fast mechanical switch UFD1 forms isolation under zero or near-zero current conditions; the selected current-limiting branch can select the commutation sampling current I. post The effective commutation capacity of the selected LC branch is limited; the second ultra-fast mechanical switch UFD2 branch forms a reliable artificial zero crossing; the peak voltage of the first commutation capacitor C1 does not exceed the allowable value; and the single-time energy absorption of the surge arrester MOV does not exceed its allowable range.

[0144] Other implementation methods

[0145] The number of current limiting stages in this invention is not limited to two stages. Depending on the DC system capacity and fault current range, three or more selectable current limiting branches with different inductance values ​​can be set, and the current limiting stages can be based on the sampled current I before current limiting.pRe Choose one or more of the branch roads.

[0146] The LC commutation levels of this invention are not limited to two levels. Three or more selectable LC forced zero-crossing commutation levels can be formed by setting different oscillating capacitors, different pre-charge voltages, different oscillating inductors, or combinations thereof.

[0147] The first ultra-fast mechanical switch UFD1 and the second ultra-fast mechanical switch UFD2 can employ electromagnetic repulsion mechanisms, permanent magnet mechanisms, residual magnet mechanisms, or other high-speed mechanical mechanisms that can meet the requirements for operating time and opening distance. The arc-extinguishing medium of the second ultra-fast mechanical switch UFD2 can be selected from vacuum, gas, or air insulation forms according to the voltage level and application environment.

[0148] Fault persistence determination is not limited to current and bus voltage criteria; it can also be combined with the differential current at both ends of the line, fault direction, impedance estimation, optical signal, temperature signal, or superior protection command for comprehensive judgment.

[0149] The above embodiments illustrate the structure, operation process, and parameter coordination relationships of the present invention. Equivalent substitutions, combinations, and modifications made by those skilled in the art without departing from the essence of the present invention should all fall within the protection scope of the present invention.

Claims

1. A hybrid DC circuit breaker based on graded current limiting, multi-level LC forced zero crossing, and fault persistence discrimination, characterized in that, It includes a main current channel unit (1), an auxiliary commutation current limiting branch (2), a multi-level LC forced zero-crossing commutation unit (3), an energy buffer and absorption unit (4), and a detection and control unit (5); The main current channel unit (1) includes a first ultra-fast mechanical switch UFD1, a load converter switch LCS, and a second ultra-fast mechanical switch UFD2 connected in series in the DC main circuit. One end of the auxiliary converter current limiting branch (2) is connected to the side of the first ultra-fast mechanical switch UFD1 near the DC power supply, and the other end is connected to the node between the load converter switch LCS and the second ultra-fast mechanical switch UFD2, so that the auxiliary converter current limiting branch (2) is connected across the two ends of the series segment formed by the first ultra-fast mechanical switch UFD1 and the load converter switch LCS, and does not bypass the second ultra-fast mechanical switch UFD2; The auxiliary commutation current limiting branch (2) includes a first commutation thyristor T1, a first commutation capacitor C1, and a first auxiliary thyristor T1. 2a Second auxiliary thyristor T 2b And an optional current limiting unit, the optional current limiting unit includes a first current limiting branch and a second current limiting branch, the first current limiting branch includes a first current limiting inductor L1, the second current limiting branch includes a second current limiting inductor L2, and the inductance value of the second current limiting inductor L2 is greater than the inductance value of the first current limiting inductor L1; The multi-level LC forced zero-crossing commutation unit (3) is connected across the two ends of the second ultra-fast mechanical switch UFD2, and includes a first LC forced zero-crossing commutation branch with a first available initial oscillation energy and a second LC forced zero-crossing commutation branch with a second available initial oscillation energy, wherein the second available initial oscillation energy is greater than the first available initial oscillation energy. The energy buffer and absorption unit (4) includes an energy transfer thyristor T. 13 The surge arrester MOV and the energy discharge switch S, the first commutation capacitor C1 are also used to reverse the phase of the first commutation thyristor T1, and in the first current limiting state or the second current limiting state, the energy transfer thyristor T 13 After conduction, at least some of the remaining energy is buffered; The detection and control unit (5) is configured as follows: After a fault is detected, the first commutator thyristor T1 is triggered to establish an auxiliary current path, the load commutator switch LCS is controlled to turn off, and a tripping command is issued to the first ultra-fast mechanical switch UFD1 and the second ultra-fast mechanical switch UFD2, so that the main current is transferred from the main current path to the auxiliary commutator current limiting branch (2). Obtain the pre-current limiting sampling current I before the current limiting branch is put into operation. pre And based on the current sampling current I before current limiting pre Choose either the no-addition-current-limiting state, the first-current-limiting state of the first-current-limiting branch, or the second-current-limiting state of the second-current-limiting branch. After the selected current processing state is established and before the multi-level LC forced zero-crossing commutation unit (3) is triggered, it is determined whether the fault continues; When the fault is determined to be a non-continuous fault, the triggering of the multi-level LC forced zero-crossing converter unit (3) is stopped and the main current path is restored. When the fault is determined to be a persistent fault, the commutation selection sampling current I is obtained. post And select the sampling current I according to the commutation. post Choose either the first LC forced zero-crossing commutation branch or the second LC forced zero-crossing commutation branch to artificially generate zero-crossing current in the second ultra-fast mechanical switch UFD2 branch; After the artificial zero crossing is generated, when there is no additional current limiting, the first auxiliary thyristor T is kept in the state of no additional current limiting. 2a Second auxiliary thyristor T 2b Energy transfer thyristor T 13 When the energy discharge switch S is in an untriggered state, the current in the first commutator thyristor T1 and the LC oscillation branch naturally decays until the first commutator thyristor T1 naturally turns off and the current in the LC oscillation branch decreases to zero or below a preset threshold. When in the first current limiting state or the second current limiting state, after the current in the first commutator thyristor T1 decreases to zero and the current in the LC oscillation branch decays to zero or below a preset threshold, the energy transfer thyristor T is controlled. 13 The circuit is turned on, allowing the remaining energy in the equivalent inductance of the line and the DC system, as well as the energy stored in the first current-limiting inductor L1 or the second current-limiting inductor L2, to be transferred to the first commutation capacitor C1. When the voltage of the first commutation capacitor C1 reaches the preset access threshold, the energy discharge switch S is turned on to connect to the surge arrester MOV and absorb the remaining energy and limit the overvoltage of the energy transfer circuit.

2. The hybrid DC circuit breaker according to claim 1, characterized in that, The load switching circuit LCS includes a first insulated-gate bipolar transistor and a second insulated-gate bipolar transistor arranged in reverse series. The first insulated-gate bipolar transistor and the second insulated-gate bipolar transistor are respectively provided with anti-parallel diodes to form a bidirectional current-carrying and controllable turn-off semiconductor switching branch.

3. The hybrid DC circuit breaker according to claim 1, characterized in that, The first commutator thyristor T1 is used to establish an auxiliary current path after a fault occurs; when the sampling current I before current limiting is used... pre When the no additional current limiting state is selected, the first auxiliary thyristor T 2a Second auxiliary thyristor T 2b The first commutator thyristor T1 remains on while in the untriggered state to maintain the auxiliary current path. After the artificial zero-crossing occurs in the second ultra-fast mechanical switch UFD2 branch, the current in the first commutator thyristor T1 decays naturally. l When the current in the circuit drops below its sustaining current and remains for a period not less than the preset turn-off time, the first commutator thyristor T1 turns off naturally. When either the first or second current-limiting state is selected, the first auxiliary thyristor T is triggered after the contact gap of the first ultra-fast mechanical switch UFD1 reaches the preset withstand voltage opening distance. 2a Second auxiliary thyristor T 2b This causes the first commutation capacitor C1 to form a reverse commutation circuit with the first commutation thyristor T1, thereby reducing the current of the first commutation thyristor T1 to zero and obtaining reverse bias. The auxiliary commutation current limiting branch (2) also includes a first pre-charge voltage regulating capacitor C4, a first pre-charge voltage regulating resistor R1, and a first pre-charge voltage regulating thyristor T. 11 The first pre-charge regulating capacitor C4, the first pre-charge regulating resistor R1, and the first pre-charge regulating thyristor T 11 This forms the first pre-charge voltage regulating branch, used to regulate the pre-charge voltage of the first commutation capacitor C1.

4. The hybrid DC circuit breaker according to claim 1, characterized in that, The first current-limiting branch also includes a first current-limiting branch selection thyristor T connected in series with the first current-limiting inductor L1. 3a The second current-limiting branch also includes a second current-limiting inductor. L2 The second current-limiting branch in series selects thyristor T. 3b ; When the current-limiting sampling current I pre When the current is less than the first grade threshold, neither the first current-limiting branch nor the second current-limiting branch is activated; When the current-limiting sampling current I pre When the threshold value is greater than or equal to the first-level threshold and less than the second-level threshold, the first current-limiting branch selector thyristor T is triggered. 3a This causes the first current-limiting inductor L1 to be connected to the fault current path. When the current-limiting sampling current I pre When the threshold value is greater than or equal to the second-level threshold, the second current-limiting branch selector thyristor T is triggered. 3b This causes the second current-limiting inductor L2 to be connected to the fault current path.

5. The hybrid DC circuit breaker according to claim 1, characterized in that, The multi-level LC forced zero-crossing commutation unit (3) includes a first oscillation capacitor C2, a second oscillation capacitor C3, an LC oscillation inductor L3, and a first LC commutation thyristor T. 4a Second LC commutator thyristor T 4b and commutator thyristors T5 to T 10 ; The first oscillation capacitor C2 and the first LC commutator thyristor T 4a LC oscillating inductor L3 and commutation thyristors T5 to T 10 The corresponding commutation thyristors in the circuit constitute the first LC forced zero-crossing commutation branch; The second oscillation capacitor C3 and the second LC commutator thyristor T 4b LC oscillating inductor L3 and commutation thyristors T5 to T 10 The corresponding commutator thyristors in the circuit constitute the second LC forced zero-crossing commutation branch; The first LC forced zero-crossing commutation branch and the second LC forced zero-crossing commutation branch are respectively used to inject commutation current in the opposite direction to the current to be interrupted into the second ultra-fast mechanical switch UFD2 branch.

6. The hybrid DC circuit breaker according to claim 5, characterized in that, The first available initial oscillation energy E1 of the first LC forced zero-crossing commutation branch and the second available initial oscillation energy E2 of the second LC forced zero-crossing commutation branch respectively satisfy: And E2 is greater than E1; When the commutation selection sampling current I post When the energy level is less than the LC level selection threshold, the first LC forced zero-crossing commutation branch is selected; when the commutation selection sampling current I... post When the value is greater than or equal to the LC level selection threshold, the second LC forced zero-crossing commutation branch is selected.

7. The hybrid DC circuit breaker according to claim 5, characterized in that, The multi-level LC forced zero-crossing commutation unit (3) also includes a second pre-charge voltage regulating capacitor C5, a second pre-charge voltage regulating resistor R2, and a second pre-charge voltage regulating thyristor T. 12 First pre-charged thyristor T 4c Second precharged thyristor T 4d ; The second pre-charge regulating capacitor C5, the second pre-charge regulating resistor R2, and the second pre-charge regulating thyristor T 12 This constitutes the second pre-charge voltage regulating branch; The first pre-charged thyristor T 4c The pre-charge path is used to establish the first oscillation capacitor C2 during the pre-charge phase, and the second pre-charge conducting thyristor T... 4d Used to establish a pre-charge path for the second oscillating capacitor C3 during the pre-charge phase; commutation diode D a To D d and commutator thyristors T5 to T 10 The circuit is set according to the conduction direction of the forward fault current and the reverse fault current to form the corresponding bidirectional commutation and forced zero-crossing commutation path.

8. The hybrid DC circuit breaker according to claim 1, characterized in that, During a fault handling cycle, once the first current-limiting branch or the second current-limiting branch is selected, it will maintain the selected current-limiting state until the current of the selected current-limiting branch drops to zero or below the preset exit threshold. At least one of the first and second graded thresholds for selecting the no-addition-current-limiting state, the first current-limiting state, and the second current-limiting state, and the LC level selection threshold for selecting the first LC forced zero-crossing commutation branch and the second LC forced zero-crossing commutation branch, is provided with a threshold hysteresis range to avoid repeated selection of the current-limiting branch or the LC forced zero-crossing commutation branch when the current fluctuates near the corresponding threshold.

9. A method for interrupting circuits using the hybrid DC circuit breaker according to any one of claims 1 to 8, characterized in that, Includes the following steps: S1. Before disconnection, precharge the first commutation capacitor C1, the first oscillation capacitor C2, and the second oscillation capacitor C3, and detect the current and voltage parameters of the DC main circuit. S2. After a fault is detected, the first commutator thyristor T1 is triggered to establish an auxiliary current channel, the load commutator switch LCS is controlled to turn off, and a tripping command is issued to the first ultra-fast mechanical switch UFD1 and the second ultra-fast mechanical switch UFD2, so that the main current is transferred from the main current channel to the auxiliary commutator current limiting branch (2). S3. Obtain the pre-current limiting sampling current I before the current-limiting branch is put into operation. pre And based on the current sampling current I before current limiting pre Choose from no additional rate limiting, first rate limiting, or second rate limiting; When the no-additional-current-limiting state is selected, before the LC forced zero-crossing commutation branch is triggered, neither the first nor the second current-limiting branch is activated, keeping the first commutation thyristor T1 on and not triggering the first auxiliary thyristor T1. 2a Second auxiliary thyristor T 2b ; When the first current limiting state or the second current limiting state is selected, the corresponding first current limiting branch selector thyristor T is triggered. 3a Alternatively, the second current-limiting branch can select thyristor T. 3b This enables the establishment of flow-limiting routes on the corresponding flow-limiting branches; After the contact gap of the first ultra-fast mechanical switch UFD1 reaches the preset withstand voltage opening distance, the first auxiliary thyristor T is triggered. 2a Second auxiliary thyristor T 2b This causes the first commutation capacitor C1 to reverse the phase of the first commutation thyristor T1, thereby transferring the current to the established corresponding current-limiting branch. S4. After the selected current processing state is established and before the LC forced zero-crossing commutation branch is triggered, a fault persistence determination window is set, and the fault persistence determination window is used to determine whether the fault persists. When the fault is determined to be a non-continuous fault, the subsequent LC forced zero-crossing commutation operation is stopped, and the main current state of the first ultra-fast mechanical switch UFD1, the second ultra-fast mechanical switch UFD2, and the load commutation switch LCS is restored. When the fault is determined to be a persistent fault, the commutation selection sampling current I is obtained. post And select the sampling current I according to the commutation. post Choose either the first LC forced zero-crossing commutation branch or the second LC forced zero-crossing commutation branch; S5. After the contact gap of the second ultra-fast mechanical switch UFD2 reaches the preset withstand voltage opening distance, the selected LC forced zero-crossing commutation branch is triggered to inject reverse commutation current into the branch of the second ultra-fast mechanical switch UFD2, so that the current of the branch of the second ultra-fast mechanical switch UFD2 generates artificial zero crossing. S6. After the current in the second ultra-fast mechanical switch UFD2 branch generates an artificial zero crossing, when in a state without additional current limiting, maintain the first auxiliary thyristor T. 2a Second auxiliary thyristor T 2b Energy transfer thyristor T 13 When the energy discharge switch S is in an untriggered state, the current in the first commutator thyristor T1 and the LC oscillation branch naturally decays under the equivalent damping of the circuit. When the current of the first commutator thyristor T1 decreases below its holding current for a duration not less than a preset turn-off time, the current in the LC oscillation branch decreases to zero or below a preset threshold, and the monitored voltage does not exceed a preset overvoltage threshold, the interruption process under the no-addition-current-limiting state is considered complete. When in the first current-limiting state or the second current-limiting state, after the current of the first commutator thyristor T1 decreases to zero and the current in the LC oscillation branch decays to zero or below a preset threshold, the energy transfer thyristor T is triggered. 13 This allows the equivalent inductance of the line and the remaining energy in the DC system, as well as the energy stored in the current-limiting inductor, to be transferred to the first commutation capacitor C1. When the voltage of the first commutation capacitor C1 reaches the preset access threshold, the energy discharge switch S is controlled to be turned on to connect to the surge arrester MOV, which absorbs the remaining energy and limits the overvoltage of the energy transfer circuit.

10. The interruption method according to claim 9, characterized in that, Within the fault persistence determination window, the fault current and DC bus voltage are continuously acquired; when the fault current is continuously lower than the current recovery threshold and the DC bus voltage is continuously reached or higher than the voltage recovery threshold, and this is maintained for a preset confirmation time, the fault is determined to be a non-persistent fault; when the above conditions are not simultaneously met before the end of the fault persistence determination window, the fault is determined to be a persistent fault. After determining that the fault is a non-continuous fault, the subsequent LC forced zero-crossing commutation action is stopped. First, the second ultra-fast mechanical switch UFD2 and the first ultra-fast mechanical switch UFD1 are restored to the state that meets the main current requirements. Then, the load commutation switch LCS is restored to conduction, and the current in the auxiliary commutation current limiting branch (2) is transferred back to the main current channel, so that the thyristor in the auxiliary commutation current limiting branch (2) is naturally turned off after its branch current crosses zero.

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