A relay protection logic path visual analysis method, device and system

Abstract

The present application belongs to the technical field of relay protection, and particularly relates to a relay protection logic path visual analysis method, device and system. The method comprises: S1, after a fault occurs, obtaining an intermediate state recording file and a standard recording file; extracting the logic execution path main information of the fault in the pre-constructed relay protection logic graph model; S2, using a pre-set causal rule library to output the causal reasoning chain of the relay protection action according to the intermediate state recording file and the standard recording file; judging the type of the relay protection action behavior according to the logic execution path main information, and giving the judgment basis; the causal rule library is compiled by experts according to the relay protection standard principle. The present application solves the technical problem that the visual analysis of the relay protection action in the prior art relies on manual reasoning by the analysis personnel's own experience.

Description

Technical Field

[0001] This invention belongs to the field of relay protection technology, specifically relating to a method, device, and system for visual analysis of relay protection logic paths. Background Technology

[0002] Relay protection devices are the first line of defense for ensuring the safe and stable operation of power systems. When a power system fault occurs, the protection device, based on collected electrical quantity information, uses internally preset logic criteria to determine the fault and outputs a trip command. Accurately reconstructing the logical execution path of the protection device during a fault is crucial for evaluating protection behavior, diagnosing the causes of incorrect actions, optimizing protection settings, and conducting device research and development testing. However, existing technologies suffer from the following technical bottlenecks: 1. The logic execution process is invisible. Traditional relay protection devices only record the input electrical quantities and output results. The intermediate execution process of the protection logic—including the satisfaction of various criteria, the input and output states of logic gates, and the timing of the fulfillment of timing conditions—is not recorded, resulting in the protection action process exhibiting a "black box" characteristic.

[0003] 2. Fault path is difficult to trace. When the protection device malfunctions or fails to operate, technicians need to manually deduce possible logical execution paths from complex recorded waveforms, which is highly dependent on personal experience and has a success rate of less than 60%.

[0004] A Chinese invention patent application with publication number CN103853807A and publication date of June 11, 2014, discloses a method for visual analysis of power faults. This method, when a relay protection device sends fault records after operation or startup, sends an intermediate state file of its internal logic judgment and a corresponding protection principle logic diagram file. A backend server performs visual playback analysis of the files sent by the relay protection device, and the analysis results can be optionally sent to the operation and maintenance center. However, the above solution has the following problems: (1) The analysis conclusions rely on manual guesswork. Even if the node state changes are observed through waveform-logic diagram linkage, the analyst still needs to rely on his own experience to manually deduce the cause of the fault (such as "why the A phase current change caused the differential protection to operate"), lacking the system-level automatic cause-effect analysis capability.

[0005] (2) The interaction method has a high professional threshold. Existing visualization playback tools require users to manually drag the timeline and hover the mouse to view node information. The operation is cumbersome and requires users to have in-depth knowledge of protection principles, which is not conducive to rapid popularization and use by on-site operation and maintenance personnel. Summary of the Invention

[0006] The purpose of this invention is to provide a method, device, and system for visual analysis of relay protection logic paths, in order to solve the technical problem that the visual analysis of relay protection actions in the prior art relies on the analyst's own experience for manual reasoning.

[0007] To address the aforementioned technical problems, the first aspect of this invention provides a method for visual analysis of relay protection logic paths, the method comprising: S1. After a fault occurs, obtain intermediate state waveform files and standard waveform files; extract the main logic execution path information of this fault from the pre-constructed relay protection logic diagram model; The intermediate state waveform file is used to store the node status data of the key logic nodes of the relay protection when a fault occurs. The relay protection logic diagram model is a directed graph model with logic elements as nodes and signal flow direction as directed edges. S2. Using a pre-set causal rule base, output the causal reasoning chain of this relay protection action based on the intermediate state waveform file and the standard waveform file; determine the type of relay protection action behavior based on the main information of the logical execution path, and provide the basis for the determination; The causal rule base was compiled by experts based on the principles of relay protection standards.

[0008] In one possible implementation, the process by which the causal rule base in S2 outputs the causal inference chain for this relay protection action based on the intermediate state waveform file and the standard waveform file includes: S21. Extract electrical quantity features from the standard waveform recording file, and align the time when each electrical quantity feature appears with the state reversal time of the key logic node in the intermediate state waveform recording file. S22. Each rule in the causal rule base includes a precondition and a conclusion. The aligned electrical quantity features and the state sequence of the key logic nodes are matched with the precondition of each rule respectively. The conclusions of the successfully matched rules are concatenated in time to obtain the causal reasoning chain.

[0009] In one possible implementation, the intermediate state waveform file is obtained by inserting a probe at the location of a state change in a critical logic node of the source code of the relay protection device; writing the node identifier, state value, and timestamp of the critical logic node into a memory buffer through the probe; and encapsulating the data in the memory buffer within a set time window before and after the fault occurs into an intermediate state waveform file when a relay protection start signal is detected.

[0010] In one possible implementation, the intermediate state waveform file includes a description file, a data file, and an index file; the description file is used to store metadata of key logical nodes; the data file is used to store the state of key logical nodes in a time series; and the index file is used to store a node state snapshot index with key timestamps.

[0011] In one possible implementation, the type of relay protection action behavior is determined by searching the active subgraph of the relay protection logic diagram model at the current moment for the shortest connected path from the protection initiation node to the output action node as the main logic execution path for the type of relay protection action behavior, which is either normal action or maloperation. Otherwise, it is indicated that the type of relay protection action behavior is failure to operate. The active subgraph consists of active nodes and directed edges between them, where an active node is a node whose current state value is true.

[0012] In one possible implementation, the method further includes: S3, generating an answer to the question based on the user-input question, intermediate state waveform file, standard waveform file, logic execution path backbone information, and a knowledge base in the field of relay protection.

[0013] In one possible implementation, S3 includes: S31. Identify the user's query intent based on the question entered by the user; S32. Retrieve knowledge entries that match the user's query intent from the knowledge base in the field of relay protection; the knowledge entries are structured question-and-answer pairs including description templates. S33. Fill in the description template of the matching knowledge entries according to the intermediate state waveform file, the standard waveform file and the logical execution path backbone; S34. Output the completed description template as the answer to the question.

[0014] In one possible implementation, the memory buffer is a circular buffer.

[0015] To address the aforementioned technical problems, a second aspect of the present invention provides a relay protection logic path visualization analysis device, comprising a processor for executing a computer program to implement the steps of the method in any possible implementation of the first aspect of the present invention.

[0016] To address the aforementioned technical problems, a third aspect of the present invention provides a relay protection logic path visualization analysis system, comprising: Intermediate state waveform recording file generation module: used to obtain intermediate state waveform recording files after a fault occurs. The intermediate state waveform recording files are used to store the node status data of key logic nodes of the relay protection when the fault occurs. Logic graph model loading and path extraction module: used to extract the main logic execution path information of the current fault from the pre-constructed relay protection logic graph model; the relay protection logic graph model is a directed graph model with logic elements as nodes and signal flow direction as directed edges; Multimodal intelligent analysis engine: It is used to output the causal reasoning chain of the current relay protection action based on the intermediate state waveform file and the standard waveform file using a pre-set causal rule base; it determines the type of the relay protection action behavior based on the main information of the logical execution path and provides the judgment basis; the causal rule base is compiled by experts based on the principles of relay protection standards.

[0017] The beneficial effects of this invention are: the system automatically associates electrical quantity waveform characteristics (standard waveform recording files) with logical node state changes (intermediate state waveform recording files), directly outputting the fault cause reasoning chain, transforming the traditional manual guessing process into automatic system analysis, generating fault reports in seconds, and significantly reducing reliance on expert experience. All intelligent analyses are based on pre-set causal rules and a structured knowledge base, do not involve black-box models, and the analysis conclusions are traceable and verifiable. This invention solves the technical problem in existing technologies where the visual analysis of relay protection actions relies on manual reasoning based on the analyst's own experience. Attached Figure Description

[0018] Figure 1 This is the overall flowchart of the implementation of the relay protection logic path visualization analysis system of the present invention; Figure 2 This is a schematic diagram of the intermediate state waveform recording file structure and the principle of logic path trunk extraction in the implementation of the relay protection logic path visualization analysis system of the present invention. Figure 3 This is a system interaction timing diagram in the implementation of the relay protection logic path visualization analysis system of the present invention; Figure 4 This is a schematic diagram of the visualization playback interface and natural language question-and-answer interface in the implementation of the relay protection logic path visualization analysis system of the present invention. Figure 5 This is a flowchart of the multimodal intelligent causal analysis process in the implementation of the relay protection logic path visualization analysis system of the present invention. Figure 6 This is a flowchart of the natural language question-and-answer module in the implementation of the relay protection logic path visualization analysis system of the present invention; Figure 7 This is a schematic diagram of the main logic execution path extraction in the implementation of the relay protection logic path visualization analysis system of the present invention; Figure 8 This is a schematic diagram of the device architecture in an embodiment of the relay protection logic path visualization analysis device of the present invention. Detailed Implementation

[0019] This invention automatically associates electrical quantity waveform characteristics (standard waveform recordings) with logical node state changes (intermediate state waveform recordings), directly outputting the fault cause reasoning chain. This transforms the traditional manual guessing process into automatic system analysis, generating fault reports in seconds and significantly reducing reliance on expert experience. All intelligent analyses are based on pre-set causal rules and a structured knowledge base, avoiding black-box models, and the analysis conclusions are traceable and verifiable. This invention solves the technical problem in existing technologies where the visual analysis of relay protection actions relies on manual reasoning based on the analyst's own experience.

[0020] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings.

[0021] Implementation method of relay protection logic path visualization analysis system: Taking a 220kV transmission line differential protection as an example, this paper fully demonstrates the implementation process of the present invention, including the correctness analysis of the transmission line differential protection operation and intelligent question answering, such as... Figure 1 As shown, it includes the following steps and software modules: Step 1: Native capture of logical path (probe implantation and status capture module).

[0022] The probe implantation of this invention does not add any hardware. Instead, it inserts a piece of state capture code (i.e., a probe function) into the software source code of the relay protection device at the code location of a key logic node. This probe function is compiled integrally with the logic node code during compilation and is automatically executed as the device runs. It does not change the original logic path of the protection criteria, but only adds a state recording function on top of it. The specific implementation consists of the following four sub-steps.

[0023] Sub-step 1.1: Identify key logic nodes. The software logic of relay protection devices is usually written in C / C++, and key logic nodes correspond to specific variables or function exits in the source code. This invention pre-selects the key logic nodes to be captured based on the protection principle (such as differential protection, distance protection) and assigns a unique identifier to each node.

[0024] This embodiment takes the differential protection of a 220kV transmission line as an example. The selected key logic nodes include: protection start node, differential relay node, zone / internal / external discrimination node, phase selection element node, and output relay node. Each node has a clearly defined corresponding location in the source code.

[0025] Sub-step 1.2: Code instrumentation to implant probes. This invention employs code instrumentation technology, requiring only one line of probe recording macro call to be added at each critical logic node location in the original business code. This macro receives a node identifier and a conditional expression representing the node's state as parameters, and internally performs the following tasks: checks the global enable switch of the probe; evaluates the truth value of the conditional expression (true indicates the node is valid, false indicates it is invalid); obtains the current system timestamp; and calls the core probe recording function.

[0026] The macro call does not change the execution path of the original decision logic; it only adds a status recording function. For function-type logic nodes, a probe recording macro is inserted before the function's return statement, passing the node identifier and the function's return value as parameters. The probe code and protection logic code are compiled together during compilation, and the final generated binary firmware contains probe instructions.

[0027] Sub-step 1.3: Probe runtime behavior. The probe core recording function is designed as a very lightweight operation. It takes three parameters: node identifier, node state value (0 or 1), and system timestamp, packs them into a fixed-length data structure, and then writes it without locking to a pre-allocated circular buffer in memory.

[0028] The circular buffer is a contiguous memory region with a configurable size; in this embodiment, it is configured to store 4096 records. The system maintains a write pointer, which increments by 1 after each write operation. When the pointer exceeds the end of the buffer, it automatically returns to the beginning and continues writing, overwriting old data with new data. This achieves lock-free, continuous recording with a fixed time overhead. This operation does not involve mutexes or dynamic memory allocation, has an extremely short execution time (average measured at 0.8 microseconds), and has less than 1% impact on the overall execution time of the protection logic.

[0029] The system timestamp is directly provided by the device's internal hardware timer. The probe function directly reads the current value of the timer counter as the timestamp, ensuring low latency and high accuracy in time acquisition.

[0030] Sub-step 1.4: Fault Triggering and Retention. When the protection device detects a fault disturbance (i.e., the protection start node state changes from 0 to 1), the system enters fault recording mode. At this time, the current position of the circular buffer write pointer is recorded, this position is marked as the reference point where the fault occurred, and a retention flag is set.

[0031] In the device's main loop or idle task, a background thread periodically checks the hardening flag. When the flag is detected as set, the background thread calculates the range of circular buffer entries to be hardened based on a preset pre-fault time window (e.g., 2 cycles before the fault) and post-fault time window (e.g., 8 cycles after the fault), combined with the known sampling rate and write pointer position. Probe data within this range is copied to a linear buffer and then written to the data portion of the intermediate state waveform file via the file system interface. After hardening is complete, the hardening flag is cleared, and the device awaits the next trigger.

[0032] Through the above four steps, native-level, low-intrusion, and high-performance capture of the logic node status on the relay protection device side is achieved. Probe insertion employs code instrumentation technology, with the probe code and logic node code compiled together at compile time.

[0033] Step 2: Generation of intermediate state waveform recording files (intermediate state waveform recording file generation module).

[0034] This step encapsulates the captured key logic node state data into an intermediate state waveform file. For example... Figure 2 On the left, the file contains three parts: Description file: Uses XML text format to store logical node metadata. Each node corresponds to one record, which includes node identifier, node name, node type, associated protection function, criterion expression, and coordinate position information in the visualization interface.

[0035] Data file: Stores the state values ​​of each node in a continuous time sequence, using a hybrid compression algorithm of bit compression encoding and run-length encoding.

[0036] The hybrid compression algorithm is as follows: First, bit compression is performed on the m node states of each sampling point, with each node state occupying 1 bit, and the compression is performed to the number of bytes that are m divided by 8 and then rounded up; then, run-length encoding is used to perform secondary compression on the continuous repeating state value sequence.

[0037] Index file: Stores a snapshot index of node status with key timestamps, facilitating quick location and random access. Each index entry records the timestamp and its corresponding data file offset.

[0038] The aforementioned description file, data file, and index file are strictly aligned with the configuration file, data file, and header file of the standard COMTRADE waveform recording file (i.e., the standard waveform recording file) using a globally unified timestamp. Both types of files share the same time base, ensuring a precise correspondence between electrical quantity waveforms and logic node states on the time axis, forming a joint dataset of electrical quantity and logic quantity domains, such as... Figure 3 As shown.

[0039] After the device generates the intermediate waveform recording file, it uploads the intermediate waveform recording file (including the description file, data file, and index file) and the accompanying COMTRADE file to the backend (PC or server) via a communication interface (such as IEC61850). Upon receiving the file, the visualization analysis software on the backend performs file parsing, logic diagram model matching, and data loading to prepare for subsequent analysis.

[0040] Step 3: Extraction of the main logical execution path (logic graph model loading and path extraction module).

[0041] A protection logic graph model is constructed, prefabricating the logical structures of various protection functions as a directed graph model. This directed graph model consists of a set of nodes and a set of directed edges, where nodes represent logic elements and directed edges represent signal flow directions. The node state values ​​at each sampling time in the data file are mapped to corresponding nodes in the logic graph model according to their node identifiers. In the logic graph model, a connected path is calculated from the protection initiation node to the exit action node, where all node states are true. This connected path is the main logical execution path for this fault. Figure 7 As shown, N302, N201, and N102 are all nodes with a true state.

[0042] Furthermore, when extracting the main logical execution path in step 3, an active node set and an active subgraph are defined. The active node set consists of nodes whose state value is true at the current sampling time, and the active subgraph consists of the active node set and the directed edges between them. The shortest connected path is searched in the active subgraph. If the path exists, it is determined that the protection logic is connected at that time.

[0043] The background software pre-loads the protection logic diagram model. At each sampling time, an active node set is defined. The shortest path algorithm searches only the active subgraph for a connected path from the protection initiation node to the exit action node. If such a connected path exists, it is the main logical execution path for this fault; if it does not exist, it is determined that the protection logic failed to reach the exit during the fault process, which can be used for subsequent failure-to-operate cause analysis.

[0044] Step 4: Multimodal intelligent causal analysis (multimodal intelligent analysis engine).

[0045] This step is executed automatically by the multimodal intelligent analysis engine, which has a built-in causal rule library. For example... Figure 5As shown, firstly, the system automatically extracts key features from the electrical quantity waveforms, including: current abrupt changes, harmonic content (ratio of second harmonic to fundamental frequency), zero-sequence voltage amplitude, zero-sequence current amplitude, calculated differential current value, calculated braking current value, and measured impedance value. These feature values ​​are obtained through traditional signal processing methods such as Fourier transform and sequence component calculation. Then, the system aligns the times when these features appear with the times when the logic node states flip, recorded by the probes, to confirm causal timing relationships.

[0046] The causal rule base is stored in the form of production rules. Each rule includes preconditions (combinations of electrical quantity characteristics and logical node states) and a conclusion (causal explanation text). The rule base content is derived from the principles of relay protection standards and is pre-compiled by experts.

[0047] The system matches the extracted feature values ​​and node state sequences item by item with the rules in the rule base. If a match is successful, the corresponding causal explanation text is output. The outputs of multiple rules are concatenated in chronological order to form a complete causal reasoning chain. At the same time, based on the integrity of the main logical execution path and the state of the final exit node, the system automatically determines whether the protection action is "correct action," "no action," or "false action," and provides the basis for the determination.

[0048] Step 5: Natural Language Interactive Question Answering (Natural Language Question Answering Module).

[0049] This step corresponds to Figure 6 The flowchart shown illustrates the execution by the natural language question-answering module, which does not rely on a large language model and is entirely based on rules and templates. Users can directly ask questions through text input boxes. The system response process is as follows: Semantic parsing: Using keyword matching and template mapping methods, user questions are parsed into query intents.

[0050] Contextual association: Automatically obtain contextual data such as the fault time, main logic execution path, electrical quantity characteristic values, and relevant node status during the current playback.

[0051] Knowledge Base Retrieval: Retrieves knowledge entries matching the query intent from a pre-built knowledge base in the field of relay protection. The knowledge base includes explanations of protection principles, a library of common fault modes, setting rules, etc., and is stored in a structured question-and-answer pair format.

[0052] Answer generation: Based on the retrieved knowledge entries and current context data, a natural language answer is generated using a template-filling method.

[0053] Specifically, in the third display area of ​​the visual playback interface, the system provides a natural language question-and-answer input box. Users can enter questions in everyday language in this box. After receiving a user's question, the system first performs semantic parsing: identifying the user's query intent through keyword matching and predefined template mapping. Then, the system calls the context management unit to automatically obtain the following context data at the current playback moment. Next, the system retrieves knowledge entries matching the query intent from a pre-set knowledge base in the field of relay protection. This knowledge base is stored in the form of structured question-and-answer pairs, covering various protection principle explanations, common fault mode libraries, setting rules, etc. All knowledge entries are pre-compiled by experts. Finally, the system generates answers using a template-filling method: combining the descriptive templates from the retrieved knowledge entries with the specific values ​​in the current context data to fill in and generate a natural language answer. The generated answer is displayed in the question-and-answer area, and the system can also highlight nodes related to the answer in the logic diagram model to help users understand it intuitively. In addition, the question-and-answer module supports continuous contextual dialogue; users can continue to ask follow-up questions based on the previous question-and-answer result, and the system updates the query context according to the dialogue history to generate progressive answers.

[0054] Step 6, Visual Replay and Interaction (Visual Replay and Interaction Module).

[0055] This step corresponds to Figure 4 The graphical user interface (GUI) is shown below. The protection logic diagram model is displayed in the first display area, and the fault waveform curve is displayed in the second display area. When the user operates the timeline, the waveform cursor in the second display area moves accordingly, and the status coloring of the logic nodes in the first display area is updated synchronously. Nodes belonging to the main logic execution path and their connections are highlighted, while inactive nodes are displayed in gray. The GUI also includes a natural language question-and-answer input box and an intelligent analysis results display area.

[0056] The first display area presents the protection logic diagram model in the form of a directed graph. Nodes belonging to the main logic execution path and their connections are highlighted in a color (e.g., red), while inactive nodes are displayed in gray. The second display area displays fault recording waveforms in COMTRADE format. The third display area displays the natural language question-and-answer results, the intelligent causal analysis chain, and the final action conclusion.

[0057] Users can browse the fault process by dragging the timeline cursor. As the cursor moves, the waveform cursor in the second display area moves accordingly, and the coloring of the logic nodes in the first display area updates synchronously based on the node's state value at that moment. When the user hovers the mouse over any node in the logic diagram, an information window automatically pops up, displaying the node's name, type, criterion expression, current state value, and the time of its state change.

[0058] The three display areas respond in unison, enabling users to fully understand the fault process from three dimensions: electrical quantity waveforms, logical state changes, and causal semantic interpretation.

[0059] The system supports integration with automated testing platforms for protection devices, receiving intermediate state waveform files in batches, automatically generating logic coverage heatmaps and test blind spot reports, and outputting intelligent analysis conclusions in batches. During factory testing or version iterations of protection devices, it can batch replay historical fault waveforms, statistically analyze the probability of each node in the logic graph model being triggered in the test set, generate a logic coverage heatmap, identify node sets with trigger probabilities below a preset threshold as test blind spots, and generate supplementary test case suggestions.

[0060] Implementation method of visual analysis of relay protection logic path: A method for visual analysis of relay protection logic paths, such as Figure 1 As shown, the method includes the following steps: S1. After a fault occurs, obtain intermediate state waveform files and standard waveform files; extract the main logic execution path information of this fault from the pre-constructed relay protection logic diagram model; Intermediate state waveform recording files are used to store node state data of key logic nodes of relay protection when a fault occurs; the relay protection logic graph model is a directed graph model with logic elements as nodes and signal flow direction as directed edges. Intermediate state waveform files are obtained as follows: probes are inserted at the locations of state changes in critical logic nodes of the relay protection device's source code; the node identifiers, state values, and timestamps of the critical logic nodes are written to a memory buffer via these probes; when a relay protection start signal is detected, the data within a set time window before and after the fault in the memory buffer is encapsulated into an intermediate state waveform file. The intermediate state waveform file includes a description file, a data file, and an index file; the description file stores metadata for the critical logic nodes; the data file stores the states of the critical logic nodes in a time sequence; and the index file stores a snapshot index of the node states at key timestamps.

[0061] The memory buffer is a circular buffer.

[0062] S2. Using a pre-set causal rule base, output the causal reasoning chain of this relay protection action based on the intermediate state waveform file and the standard waveform file; determine the type of relay protection action behavior based on the main information of the logical execution path, and provide the judgment basis; the causal rule base is compiled by experts based on the principles of relay protection standards.

[0063] Specifically, the causal reasoning chain is obtained according to the following process: S21. Extract electrical quantity features from the standard waveform recording file, and align the time when each electrical quantity feature appears with the state reversal time of the key logic node in the intermediate state waveform recording file. S22. Each rule in the causal rule base includes a precondition and a conclusion. The aligned electrical quantity features and the state sequence of the key logic nodes are matched with the precondition of each rule respectively. The conclusions of the successfully matched rules are concatenated in time to obtain the causal reasoning chain.

[0064] The method for determining the type of relay protection action behavior is to search for the shortest connected path from the protection start node to the exit action node in the active subgraph of the relay protection logic graph model at the current moment. This path serves as the main logic execution path for determining whether the relay protection action behavior is a normal action or a malfunction. Otherwise, it indicates that the type of relay protection action behavior is a failure to operate. The active subgraph consists of active nodes and the directed edges between them. The active nodes are those whose current state value is true.

[0065] S3. Generate the answer to the question based on the user-input question, intermediate state waveform file, standard waveform file, logic execution path backbone information, and knowledge base in the field of relay protection.

[0066] S31. Identify the user's query intent based on the question entered by the user; S32. Retrieve knowledge entries that match the user's query intent from the knowledge base in the field of relay protection; the knowledge entries are structured question-and-answer pairs including description templates. S33. Fill in the description template of the matching knowledge entries according to the intermediate state waveform file, the standard waveform file and the logical execution path backbone; S34. Output the completed description template as the answer to the question.

[0067] The relay protection logic path visualization analysis method in this embodiment has the same functions as the software modules in the above-described relay protection logic path visualization analysis system embodiment. For detailed implementation of each step of this method, please refer to the above-described overall implementation of relay protection logic path visualization analysis.

[0068] Implementation method of relay protection logic path visualization analysis device: The schematic diagram of the architecture of the relay protection logic path visualization analysis device in this embodiment is shown below. Figure 8 As shown, it specifically includes a memory, a processor, a system bus, and a computer program stored in the memory. The processor and the memory communicate and interact with each other via the system bus. The processor executes the computer program to implement the steps of the relay protection logic path visualization analysis method described in the embodiments of the present invention. The specific relay protection logic path visualization analysis method has been described in sufficient detail in the above embodiments and will not be repeated here. The processor can be a microprocessor (MCU) or other processing device; the memory can be any type of memory that stores information using electrical energy, such as non-volatile storage media (including computer programs, databases), or other types of memory.

[0069] This invention has the following characteristics: This invention discloses a method and system for native capture and visualization playback of relay protection logic paths. At key logic nodes in the software source code of the relay protection device, this invention natively implants state capture probes through code instrumentation to acquire the state values ​​and timestamps of each logic node in real time, generating intermediate state waveform files containing description files, data files, and index files. These files are then time-aligned with standard COMTRADE files to form a joint dataset of electrical and logical quantities. A protection logic graph model is constructed, and a graph-based shortest path algorithm is used to extract the main logical execution path from the start node to the exit node. Based on a pre-built causal rule base, electrical quantity features are automatically associated with logic node states to generate a structured fault cause reasoning chain and action judgment conclusion. Natural language question-and-answer interaction is provided, allowing users to obtain intuitive answers based on the current playback context through text-based questions, supporting continuous follow-up questions. A three-zone linkage visualization playback of waveform, logic graph, and semantic answer is achieved. This invention elevates protection action analysis from black-box speculation to deterministic evidence chain analysis and intelligent question answering, significantly reducing reliance on experts and improving the efficiency and accuracy of fault diagnosis.

[0070] Compared with the prior art, the present invention has the following significant advantages: (1) The logic execution process is made white-box. By directly capturing the state of all key logic nodes through natively implanted probes, the analysis of relay protection actions is elevated from black-box speculation to the level of deterministic evidence chain tracing for the first time.

[0071] (2) Multimodal intelligent causal analysis. The system automatically associates the characteristics of electrical quantity waveforms with the changes in the state of logic nodes, and directly outputs the fault cause reasoning chain, transforming the traditional manual guessing process into automatic system analysis. Fault reports are generated in seconds, greatly reducing the reliance on expert experience.

[0072] (3) Natural Language Interactive Question and Answer. Users no longer need to manually drag the timeline or hover to view node information; they can simply enter everyday questions to get intuitive answers. This transforms complex graphical professional analysis into a conversational experience, allowing non-expert users to quickly understand fault logic, which aligns with the trend of humanized interaction in industrial software.

[0073] (4) Knowledge base and rule-driven, with strong interpretability. All intelligent analyses are based on pre-set causal rules and structured knowledge bases, without involving black box models, and the analysis conclusions are traceable and verifiable.

[0074] (5) Lightweight deployment with no additional hardware costs. The multimodal intelligent analysis and natural language question answering modules run on the background computer, requiring no modification to the protection device hardware, and can be seamlessly integrated with existing visualization playback systems.

[0075] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Numerous specific details in this specification are for illustrative purposes only, and embodiments of the present invention can be implemented without relying on these details. Well-known methods, structures, and techniques are not described in detail to avoid obscuring the understanding of the present invention. Features in different embodiments can be arbitrarily combined, and these combinations all fall within the scope of protection of the present invention and constitute different embodiments. The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any equivalent substitutions or modifications made to the embodiments within the technical solution and inventive concept of the present invention shall still fall within the scope of protection of the present invention.

Claims

1. A method for visual analysis of relay protection logic paths, characterized in that, The method includes: S1. After a fault occurs, obtain intermediate state waveform files and standard waveform files; extract the main logic execution path information of this fault from the pre-constructed relay protection logic diagram model; The intermediate state waveform file is used to store the node status data of the key logic nodes of the relay protection when a fault occurs. The relay protection logic diagram model is a directed graph model with logic elements as nodes and signal flow direction as directed edges. S2. Using a pre-set causal rule base, output the causal reasoning chain of this relay protection action based on the intermediate state waveform file and the standard waveform file; determine the type of relay protection action behavior based on the main information of the logical execution path, and provide the basis for the determination; The causal rule base was compiled by experts based on the principles of relay protection standards.

2. The method for visual analysis of relay protection logic paths according to claim 1, characterized in that, The process by which the causal rule base in S2 outputs the causal reasoning chain for this relay protection action based on the intermediate state waveform file and the standard waveform file includes: S21. Extract electrical quantity features from the standard waveform recording file, and align the time when each electrical quantity feature appears with the state reversal time of the key logic node in the intermediate state waveform recording file. S22. Each rule in the causal rule base includes a precondition and a conclusion. The aligned electrical quantity features and the state sequence of the key logic nodes are matched with the precondition of each rule respectively. The conclusions of the successfully matched rules are concatenated in time to obtain the causal reasoning chain.

3. The method for visual analysis of relay protection logic paths according to claim 1, characterized in that, The intermediate state waveform file is obtained as follows: a probe is inserted at the location of the state change of the key logic node in the source code of the relay protection device; the node identifier, state value and timestamp of the key logic node are written into the memory buffer through the probe; when the relay protection start signal is detected, the data in the memory buffer within a set time window before and after the fault occurs is encapsulated into an intermediate state waveform file.

4. The method for visual analysis of relay protection logic paths according to claim 1 or 3, characterized in that, The intermediate state waveform file includes a description file, a data file, and an index file; the description file is used to store metadata of key logical nodes; the data file is used to store the state of key logical nodes in a time series; and the index file is used to store a snapshot index of node state at key timestamps.

5. The method for visual analysis of relay protection logic paths according to claim 1, characterized in that, The method to determine the type of relay protection action behavior is to search for the shortest connected path from the protection start node to the output action node in the active subgraph of the relay protection logic diagram model at the current moment. This path serves as the main logic execution path for determining whether the relay protection action behavior is a normal action or a malfunction. Otherwise, it indicates that the type of relay protection action behavior is a failure to operate. The active subgraph consists of active nodes and directed edges between them, where an active node is a node whose current state value is true.

6. The method for visual analysis of relay protection logic paths according to claim 1, characterized in that, The method also includes: S3, generating the answer to the question based on the user-input question, intermediate state waveform file, standard waveform file, logic execution path backbone information, and knowledge base in the field of relay protection.

7. The method for visual analysis of relay protection logic paths according to claim 6, characterized in that, S3 include: S31. Identify the user's query intent based on the question entered by the user; S32. Retrieve knowledge entries that match the user's query intent from the knowledge base in the field of relay protection; the knowledge entries are structured question-and-answer pairs including description templates. S33. Fill in the description template of the matching knowledge entries according to the intermediate state waveform file, the standard waveform file and the logical execution path backbone; S34. Output the completed description template as the answer to the question.

8. The method for visual analysis of relay protection logic paths according to claim 3, characterized in that, The memory buffer is a circular buffer.

9. A relay protection logic path visualization analysis device, comprising a processor, characterized in that, The processor is used to execute a computer program to implement the steps of the relay protection logic path visualization analysis method as described in any one of claims 1 to 8.

10. A relay protection logic path visualization analysis system, characterized in that, include: Intermediate state waveform recording file generation module: used to obtain intermediate state waveform recording files after a fault occurs. The intermediate state waveform recording files are used to store the node status data of key logic nodes of the relay protection when the fault occurs. Logic graph model loading and path extraction module: used to extract the main logic execution path information of the current fault from the pre-constructed relay protection logic graph model; the relay protection logic graph model is a directed graph model with logic elements as nodes and signal flow direction as directed edges; Multimodal intelligent analysis engine: used to output the causal reasoning chain of the current relay protection action based on the intermediate state waveform file and the standard waveform file using a pre-set causal rule base; The type of relay protection action is determined based on the main information of the logical execution path, and the basis for the determination is given; the causal rule base is compiled by experts based on the principles of relay protection standards.

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