A two-terminal wide-temperature surge suppression circuit and device

Abstract

The application discloses a two-terminal wide-temperature surge suppression circuit and device, and belongs to the technical field of power supply starting circuits. The circuit comprises a first conduction sub-circuit, a first PNP triode, a second PNP triode and a first stabilizing tube. When the temperature of the first PNP triode and the second PNP triode changes in normal operation, the first PNP triode generates a first temperature drift deviation, the second PNP triode generates a second temperature drift deviation, the first temperature drift deviation is the same in size as the second temperature drift deviation but opposite in direction to the two-terminal wide-temperature surge suppression circuit, so the first temperature drift deviation will offset the second temperature drift deviation, thereby eliminating the influence of temperature change on the first PNP triode and the second PNP triode, and further improving the stability of the surge suppression circuit in the full-temperature range.

Description

Technical Field

[0001] This invention relates to the field of power-starting circuit technology, and in particular to a two-terminal wide-temperature surge suppression circuit and device. Background Technology

[0002] With the widespread application of switching power supplies in communication equipment, industrial control, automotive electronics, and aerospace, the requirements for power supply system startup reliability, environmental adaptability, and short-circuit withstand capability are becoming increasingly stringent. At the moment of power supply startup, the initial charging current (i.e., surge current) of the large bus capacitor can be several times or even tens of times higher than the steady-state operating current. Without limitation, this could burn out the rectifier bridge, blow fuses, or even cause system failure. Therefore, surge suppression devices are typically inserted in series in the charging circuit to achieve a soft start.

[0003] Common existing solutions include: First, the NTC thermistor solution, but it suffers from hot-start failure and significant characteristic drift with ambient temperature; second, the linear constant current solution, but the power transistor experiences extremely high instantaneous power consumption during startup and typically requires at least three external terminals, making it impossible to directly replace the two-terminal passive device; existing technology proposes a surge startup circuit based on differential voltage feedback, which can achieve near-constant power control, but the constant current setpoint drifts significantly with temperature, resulting in inconsistent protection performance across the entire temperature range; and existing temperature compensation solutions require auxiliary power supplies and complex ICs, increasing cost and potential failure points. Therefore, the above solutions cannot achieve high stability of the surge suppression circuit across the entire temperature range without the possibility of directly replacing the two-terminal passive device. Summary of the Invention

[0004] The present invention aims to provide a two-terminal wide-temperature surge suppression circuit and device to solve the above-mentioned technical problems and improve the stability of the surge suppression circuit in the full temperature range.

[0005] To solve the above-mentioned technical problems, the present invention provides a two-terminal wide-temperature surge suppression circuit, including a first conducting sub-circuit, a first PNP transistor, a second PNP transistor, and a first Zener diode; The emitter of the second PNP transistor serves as the positive power supply interface, the base and collector of the second PNP transistor are electrically connected, and the collector of the second PNP transistor is electrically connected to the input terminal of the first conducting sub-circuit. The cathode of the first Zener diode is electrically connected to the emitter of the second PNP transistor, and the anode of the first Zener diode is electrically connected to the emitter of the first PNP transistor. The base of the first PNP transistor is electrically connected to the feedback terminal of the first conducting sub-circuit, and the collector of the first PNP transistor is electrically connected to the control terminal of the first conducting sub-circuit. The output terminal of the first conducting sub-circuit serves as the positive terminal interface of the load. During normal operation, when the temperatures of the first PNP transistor and the second PNP transistor change, the first PNP transistor generates a first temperature drift deviation, and the second PNP transistor generates a second temperature drift deviation. The first temperature drift deviation and the second temperature drift deviation are of the same magnitude but opposite in direction to the two-terminal wide-temperature surge suppression circuit. Therefore, the first temperature drift deviation will cancel out the second temperature drift deviation, thereby eliminating the influence of temperature changes on the first PNP transistor and the second PNP transistor.

[0006] This invention uses a special connection between two transistors. During normal operation, when the temperature changes, the two transistors will produce temperature drift deviations of the same magnitude but opposite directions relative to the circuit. These two temperature drift deviations will cancel each other out, thereby eliminating the influence of temperature changes on the two transistors and thus improving the stability of the surge suppression circuit across the entire temperature range.

[0007] Furthermore, the first conducting sub-circuit includes a first feedback module, a PMOS transistor, a third resistor, and a fourth resistor, wherein: The first end of the third resistor serves as the input terminal of the first conducting sub-circuit, and the second end of the third resistor is electrically connected to the source of the PMOS transistor. The gate of the PMOS transistor serves as the control terminal of the first conduction sub-circuit, and the drain of the PMOS transistor serves as the output terminal of the first conduction sub-circuit. The first end of the fourth resistor is electrically connected to the gate of the PMOS transistor, and the second end of the fourth resistor is electrically connected to the drain of the PMOS transistor. The first terminal of the first feedback module is electrically connected to the source of the PMOS transistor, the second terminal of the first feedback module serves as the feedback terminal of the first conduction sub-circuit, and the third terminal of the first feedback module is electrically connected to the drain of the PMOS transistor.

[0008] It should be noted that the first PNP transistor acts as the driving transistor, and the second PNP transistor acts as the compensation transistor; let the voltage regulation value of the first Zener diode be... The Vbe of the drive transistor is The Vbe of the compensation tube is The resistance of the third resistor is R1, and the voltage difference across R1 is V(R1). The conduction threshold of the driving transistor is determined by the following voltage loop: (Equation 1) The first PNP transistor and the second PNP transistor are of the same type, have the same conduction threshold temperature coefficient (approximately -2mV / ℃), and drift in the same direction with equal amplitude when the temperature changes. (Equation 2) The constant current reference is determined solely by the voltage of the first Zener diode: (Equation 3) in, The constant current reference of this circuit is the magnitude of the current that is finally output to the positive terminal of the load. The temperature coefficient of the Zener diode (such as a 1.24V Zener diode) is usually less than 50ppm / ℃, which is much smaller than the Vbe temperature coefficient of the transistor. The constant current reference remains stable throughout the entire temperature range.

[0009] It should also be noted that this circuit has two operating phases: During the constant current stage, the circuit will operate in this stage when it starts normally or when the voltage difference between the positive power supply interface and the positive load interface is small. The driving transistor controls the gate voltage of the PMOS transistor to keep the conduction current constant. Two transistors of the same type ensure that the constant current value does not change with temperature. During the differential voltage reduction phase, when the load is short-circuited or heavily loaded, resulting in a large voltage difference between the positive terminal of the power supply and the positive terminal of the load, this phase will be activated. The first feedback module samples the differential voltage signal from the drain and source terminals of the PMOS transistor and generates a feedback potential that is sent to the base of the driver transistor. When the differential voltage increases, the change in the feedback potential alters the conduction level of the driver transistor, controlling the PMOS transistor to tend to turn off, and the charging current automatically decreases. The "differential voltage reduction" characteristic, where the current decreases as the differential voltage increases, limits the instantaneous power consumption of the PMOS transistor to a safe range, presenting an approximately constant power parabolic power consumption curve.

[0010] In this process, regardless of whether it's the constant current stage or the differential voltage reduction stage, the Vbe of the compensation transistor and the Vbe of the driving transistor are always connected in series in the voltage loop, continuously canceling out temperature drift and maintaining highly consistent power consumption limiting characteristics across the entire temperature range. The collector currents of the driving transistor and the compensation transistor can be unequal. Although the current difference results in a fixed difference (approximately tens of millivolts) in the absolute value of Vbe between the two transistors, the temperature coefficient of Vbe remains essentially constant over a wide current range. This fixed difference does not change with temperature and does not affect the compensation effect. This characteristic reduces device matching requirements and enhances engineering feasibility.

[0011] This two-terminal wide-temperature surge suppression circuit does not require a separate grounding terminal. The internal reference potential is established at the low potential end of the third resistor. The power supply of the entire circuit is multiplexed with the main circuit circuit connected to the two terminals of this circuit, and it draws power from the voltage difference between the two terminals to operate.

[0012] The above solution has only two external connection terminals, which are equivalent to power resistors or NTC thermistors in electrical connection. It can directly replace the existing two-terminal passive surge suppression devices without changing the circuit board layout. The module draws power from the two terminals, solving the problem that traditional active circuits require independent grounding terminals. Moreover, it achieves the "differential current reduction" characteristic through the differential voltage feedback mechanism. Under short-circuit extreme conditions, the current automatically folds back to an extremely low level, and the instantaneous power consumption of the power transistor is always limited to the preset safety range. The power consumption curve is parabolic, which fundamentally solves the problem of traditional constant current solutions being prone to burnout during short circuits.

[0013] Furthermore, the first feedback module includes a first resistor and a second resistor, wherein: The first end of the first resistor serves as the first end of the first feedback module, and the second end of the first resistor serves as the second end of the first feedback module. The first end of the second resistor is electrically connected to the second end of the first resistor, and the second end of the second resistor serves as the third end of the first feedback module.

[0014] Furthermore, the two-terminal wide-temperature surge suppression circuit also includes a first diode, wherein: The anode of the first diode serves as the positive power supply interface, and the cathode of the first diode is electrically connected to the emitter of the second PNP transistor.

[0015] In the above scheme, the first diode acts as a reverse connection protection diode, which can prevent the circuit from being damaged due to reverse polarity connection, and at the same time block the capacitor at the positive terminal of the load from discharging in reverse to the positive terminal of the power supply.

[0016] The present invention also provides a two-terminal wide-temperature surge suppression circuit, including a second conducting sub-circuit, a first NPN transistor, a second NPN transistor, and a second Zener diode; The emitter of the second NPN transistor serves as the positive terminal of the load, the base of the second NPN transistor is electrically connected to the collector, and the collector of the second NPN transistor is electrically connected to the output terminal of the second conducting sub-circuit. The anode of the second Zener diode is electrically connected to the emitter of the second NPN transistor, and the cathode of the second Zener diode is electrically connected to the emitter of the first NPN transistor. The base of the first NPN transistor is electrically connected to the feedback terminal of the second conduction sub-circuit, and the collector of the first NPN transistor is electrically connected to the control terminal of the second conduction sub-circuit. The input terminal of the second conducting sub-circuit serves as the positive power supply interface; During normal operation, when the temperatures of the first NPN transistor and the second NPN transistor change, the first NPN transistor generates a first temperature drift deviation, and the second NPN transistor generates a second temperature drift deviation. The first temperature drift deviation and the second temperature drift deviation are of the same magnitude but opposite in direction to the two-terminal wide-temperature surge suppression circuit. Therefore, the first temperature drift deviation will cancel out the second temperature drift deviation, thereby eliminating the influence of temperature changes on the first NPN transistor and the second NPN transistor.

[0017] This invention uses a special connection between two transistors. During normal operation, when the temperature changes, the two transistors will produce temperature drift deviations of the same magnitude but opposite directions relative to the circuit. These two temperature drift deviations will cancel each other out, thereby eliminating the influence of temperature changes on the two transistors. The remaining components have very low temperature sensitivity, thus improving the stability of the surge suppression circuit across the entire temperature range.

[0018] Furthermore, the second conducting sub-circuit includes a second feedback module, an NMOS transistor, a seventh resistor, and an eighth resistor, wherein: The drain of the NMOS transistor serves as the input terminal of the second conduction sub-circuit, the gate of the NMOS transistor serves as the control terminal of the second conduction sub-circuit, and the source of the NMOS transistor is electrically connected to the first terminal of the seventh resistor. The second end of the seventh resistor serves as the output end of the second conducting sub-circuit. The first end of the eighth resistor is electrically connected to the drain of the NMOS transistor, and the second end of the eighth resistor is electrically connected to the gate of the NMOS transistor. The first terminal of the second feedback module is electrically connected to the drain of the NMOS transistor, the second terminal of the second feedback module serves as the feedback terminal of the second conduction sub-circuit, and the third terminal of the second feedback module is electrically connected to the source of the NMOS transistor.

[0019] It should be noted that the first NPN transistor acts as the driver transistor, and the second NPN transistor acts as the compensation transistor; let the voltage regulation value of the second Zener diode be... The Vbe of the drive transistor is The Vbe of the compensation tube is The resistance of the third resistor is R1, and the voltage difference across R1 is V(R1). The conduction threshold of the driving transistor is determined by the following voltage loop: (Equation 4) The first NPN transistor and the second NPN transistor are of the same type, have the same on-threshold temperature coefficient (approximately -2mV / ℃), and drift in the same direction with equal amplitude when the temperature changes. (Equation 5) The constant current reference is determined solely by the voltage of the second Zener diode: (Equation 6) in, The constant current reference of this circuit is the magnitude of the current that is finally output to the positive terminal of the load. The temperature coefficient of the Zener diode (such as a 1.24V Zener diode) is usually less than 50ppm / ℃, which is much smaller than the Vbe temperature coefficient of the transistor. The constant current reference remains stable throughout the entire temperature range.

[0020] It should also be noted that this circuit has two operating phases: During the constant current stage, the circuit will operate in this stage when it starts normally or when the voltage difference between the positive power supply interface and the positive load interface is small. The driving transistor controls the gate voltage of the NMOS transistor to keep the conduction current constant. Two transistors of the same type ensure that the constant current value does not change with temperature. During the differential voltage reduction phase, when the load is short-circuited or heavily loaded, resulting in a large voltage difference between the positive terminal of the power supply and the positive terminal of the load, this phase will be activated. The second feedback module samples the differential voltage signal from the drain and source terminals of the NMOS transistor and generates a feedback potential that is sent to the base of the driver transistor. When the differential voltage increases, the change in the feedback potential alters the conduction level of the driver transistor, controlling the NMOS transistor to tend to turn off, and the charging current automatically decreases. The "differential voltage reduction" characteristic, where the current decreases as the differential voltage increases, limits the instantaneous power consumption of the NMOS transistor to a safe range, presenting an approximately constant power parabolic power consumption curve.

[0021] In this process, regardless of whether it's the constant current stage or the differential voltage reduction stage, the Vbe of the compensation transistor and the Vbe of the driving transistor are always connected in series in the voltage loop, continuously canceling out temperature drift and maintaining highly consistent power consumption limiting characteristics across the entire temperature range. The collector currents of the driving transistor and the compensation transistor can be unequal. Although the current difference results in a fixed difference (approximately tens of millivolts) in the absolute value of Vbe between the two transistors, the temperature coefficient of Vbe remains essentially constant over a wide current range. This fixed difference does not change with temperature and does not affect the compensation effect. This characteristic reduces device matching requirements and enhances engineering feasibility.

[0022] This two-terminal wide-temperature surge suppression circuit does not require a separate grounding terminal. The internal reference potential is established at the low potential end of the seventh resistor. The power supply of the entire circuit is multiplexed with the main circuit circuit connected to the two terminals of this circuit, and it draws power from the voltage difference between the two terminals to operate.

[0023] Based on this floating ground characteristic, this two-terminal wide-temperature surge suppression circuit can be directly applied to high-end scenarios. When the circuit is connected in series between the positive terminal of the power supply and the positive terminal of the load, the internal reference potential of the circuit will float adaptively. When applied to external circuits, the source of the NMOS transistor is not fixedly grounded, but is a floating internal reference point, which completely eliminates the dependence on high-voltage PMOS devices and significantly reduces the difficulty and cost of device selection in high-voltage applications.

[0024] The above solution has only two external connection terminals, which are equivalent to power resistors or NTC thermistors in electrical connection. It can directly replace the existing two-terminal passive surge suppression devices without changing the circuit board layout. The module draws power from the two terminals, solving the problem that traditional active circuits require independent grounding terminals. Moreover, it achieves the "differential current reduction" characteristic through the differential voltage feedback mechanism. Under short-circuit extreme conditions, the current automatically folds back to an extremely low level, and the instantaneous power consumption of the power transistor is always limited to the preset safety range. The power consumption curve is parabolic, which fundamentally solves the problem of traditional constant current solutions being prone to burnout during short circuits.

[0025] Furthermore, the second feedback module includes a fifth resistor and a sixth resistor, wherein: The first end of the fifth resistor serves as the first end of the second feedback module, and the second end of the fifth resistor serves as the second end of the second feedback module. The first end of the sixth resistor is electrically connected to the second end of the fifth resistor, and the second end of the sixth resistor serves as the third end of the second feedback module.

[0026] In the above scheme, a conventional NMOS transistor circuit would connect a clamping diode in parallel between the gate and source of the NMOS transistor. However, in this scheme, this clamping diode can be omitted because when the voltage difference across the NMOS transistor is large, the first NPN transistor automatically adjusts the gate-source voltage of the NMOS transistor to a moderate level (usually far below the 20V gate oxide breakdown threshold) through closed-loop feedback, and the NMOS transistor operates in the linear region. When the voltage difference decreases to a level insufficient to maintain constant current, the NMOS transistor jumps out of the linear region and enters full conduction, but at this point the voltage difference is already far below the safety threshold. Therefore, by reasonably setting the parameters of the fifth, sixth, and seventh resistors, the gate-source voltage of the NMOS transistor remains within a safe range throughout the entire operation, without the need for additional clamping protection.

[0027] Furthermore, the two-terminal wide-temperature surge suppression circuit also includes a second diode, wherein: The anode of the second diode is electrically connected to the emitter of the second NPN transistor, and the cathode of the second diode serves as the positive terminal interface of the load.

[0028] In the above scheme, the second diode serves as a reverse connection protection diode, which can prevent the circuit from being damaged due to reverse polarity connection, and at the same time block the capacitor at the positive terminal of the load from discharging in reverse to the positive terminal of the power supply.

[0029] The present invention also provides a two-terminal wide-temperature surge suppression device, comprising a housing and a two-terminal wide-temperature surge suppression circuit as described in claim 4 disposed inside the housing; the housing is provided with a power positive interface and a load positive interface; the power positive interface is electrically connected to the anode of the first diode in the two-terminal wide-temperature surge suppression circuit; the load positive interface is electrically connected to the output terminal of the first conducting sub-circuit in the two-terminal wide-temperature surge suppression circuit.

[0030] The present invention also provides a two-terminal wide-temperature surge suppression device, comprising a housing and a two-terminal wide-temperature surge suppression circuit as described in claim 8 disposed inside the housing; the housing is provided with a power positive interface and a load positive interface; the power positive interface is electrically connected to the input terminal of the second conducting sub-circuit in the two-terminal wide-temperature surge suppression circuit; the load positive interface is electrically connected to the cathode of the second diode in the two-terminal wide-temperature surge suppression circuit.

[0031] The invention utilizes a special connection between two transistors in a two-terminal wide-temperature surge suppression circuit. During normal operation, when the temperature changes, the two transistors will generate temperature drift deviations of the same magnitude but opposite directions relative to the circuit. These two temperature drift deviations will cancel each other out, thereby eliminating the influence of temperature changes on the two transistors and thus improving the stability of the surge suppression circuit over the entire temperature range. Attached Figure Description

[0032] Figure 1 A structural diagram of a PMOS high-side solution for a two-terminal wide-temperature surge suppression circuit provided in a certain embodiment of the present invention; Figure 2 A structural diagram of a PMOS high-side solution for a two-terminal wide-temperature surge suppression circuit provided in a certain embodiment of the present invention; Figure 3 A structural diagram of an NMOS high-side solution for a two-terminal wide-temperature surge suppression circuit provided in a certain embodiment of the present invention; Figure 4 This is a structural diagram of an NMOS low-end solution for a two-terminal wide-temperature surge suppression circuit provided in a certain embodiment of the present invention; Figure 5 An electrical connection diagram illustrating a high-end application of a two-terminal wide-temperature surge suppression circuit according to a certain embodiment of the present invention; Figure 6An electrical connection diagram illustrating a low-end application of a two-terminal wide-temperature surge suppression circuit according to a certain embodiment of the present invention; Figure 7 This is a comparison chart of measured power consumption at three temperatures provided for a certain embodiment of the present invention. Detailed Implementation

[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] Please see Figure 1 and Figure 2 This embodiment provides a two-terminal wide-temperature surge suppression circuit as a PMOS high-side solution. The circuit includes a first conducting sub-circuit, a first PNP transistor, a second PNP transistor, and a first Zener diode. The emitter of the second PNP transistor serves as the positive power supply interface, the base and collector of the second PNP transistor are electrically connected, and the collector of the second PNP transistor is electrically connected to the input terminal of the first conducting sub-circuit. The cathode of the first Zener diode is electrically connected to the emitter of the second PNP transistor, and the anode of the first Zener diode is electrically connected to the emitter of the first PNP transistor. The base of the first PNP transistor is electrically connected to the feedback terminal of the first conducting sub-circuit, and the collector of the first PNP transistor is electrically connected to the control terminal of the first conducting sub-circuit. The output terminal of the first conducting sub-circuit serves as the positive terminal interface of the load. During normal operation, when the temperatures of the first PNP transistor and the second PNP transistor change, the first PNP transistor generates a first temperature drift deviation, and the second PNP transistor generates a second temperature drift deviation. The first temperature drift deviation and the second temperature drift deviation are of the same magnitude but opposite in direction to the two-terminal wide-temperature surge suppression circuit. Therefore, the first temperature drift deviation will cancel out the second temperature drift deviation, thereby eliminating the influence of temperature changes on the first PNP transistor and the second PNP transistor.

[0035] This embodiment uses a special connection between two transistors. During normal operation, when the temperature changes, the two transistors will produce temperature drift deviations of the same magnitude but opposite directions relative to the circuit. These two temperature drift deviations will cancel each other out, thereby eliminating the influence of temperature changes on the two transistors and improving the stability of the surge suppression circuit across the entire temperature range.

[0036] In one embodiment, the first conducting sub-circuit includes a first feedback module, a PMOS transistor, a third resistor, and a fourth resistor, wherein: The first end of the third resistor serves as the input terminal of the first conducting sub-circuit, and the second end of the third resistor is electrically connected to the source of the PMOS transistor. The gate of the PMOS transistor serves as the control terminal of the first conduction sub-circuit, and the drain of the PMOS transistor serves as the output terminal of the first conduction sub-circuit. The first end of the fourth resistor is electrically connected to the gate of the PMOS transistor, and the second end of the fourth resistor is electrically connected to the drain of the PMOS transistor. The first terminal of the first feedback module is electrically connected to the source of the PMOS transistor, the second terminal of the first feedback module serves as the feedback terminal of the first conduction sub-circuit, and the third terminal of the first feedback module is electrically connected to the drain of the PMOS transistor.

[0037] It should be noted that the first PNP transistor acts as the driving transistor, and the second PNP transistor acts as the compensation transistor; let the voltage regulation value of the first Zener diode be... The Vbe of the drive transistor is The Vbe of the compensation tube is The resistance of the third resistor is R1, and the voltage difference across R1 is V(R1). The conduction threshold of the driving transistor is determined by the following voltage loop: (Equation 7) The first PNP transistor and the second PNP transistor are of the same type, have the same conduction threshold temperature coefficient (approximately -2mV / ℃), and drift in the same direction with equal amplitude when the temperature changes. (Equation 8) The constant current reference is determined solely by the voltage of the first Zener diode: (Equation 9) in, The constant current reference of this circuit is the magnitude of the current that is finally output to the positive terminal of the load. The temperature coefficient of the Zener diode (such as a 1.24V Zener diode) is usually less than 50ppm / ℃, which is much smaller than the Vbe temperature coefficient of the transistor. The constant current reference remains stable throughout the entire temperature range.

[0038] It should also be noted that this circuit has two operating phases: During the constant current stage, the circuit will operate in this stage when it starts normally or when the voltage difference between the positive power supply interface and the positive load interface is small. The driving transistor controls the gate voltage of the PMOS transistor to keep the conduction current constant. Two transistors of the same type ensure that the constant current value does not change with temperature. During the differential voltage reduction phase, when the load is short-circuited or heavily loaded, resulting in a large voltage difference between the positive terminal of the power supply and the positive terminal of the load, this phase will be activated. The first feedback module samples the differential voltage signal from the drain and source terminals of the PMOS transistor and generates a feedback potential that is sent to the base of the driver transistor. When the differential voltage increases, the change in the feedback potential alters the conduction level of the driver transistor, controlling the PMOS transistor to tend to turn off, and the charging current automatically decreases. The "differential voltage reduction" characteristic, where the current decreases as the differential voltage increases, limits the instantaneous power consumption of the PMOS transistor to a safe range, presenting an approximately constant power parabolic power consumption curve.

[0039] In both the constant current stage and the differential current reduction stage, the Vbe of the compensation tube and the Vbe of the drive tube are always connected in series in the voltage circuit, and the temperature drift is continuously canceled out, resulting in highly consistent power consumption limiting characteristics across the entire temperature range.

[0040] This two-terminal wide-temperature surge suppression circuit does not require a separate grounding terminal. The internal reference potential is established at the low potential end of the third resistor. The power supply of the entire circuit is multiplexed with the main circuit circuit connected to the two terminals of this circuit, and it draws power from the voltage difference between the two terminals to operate.

[0041] This embodiment has only two external connection terminals, which are equivalent to power resistors or NTC thermistors in electrical connection. It can directly replace existing passive surge suppression devices with two terminals without changing the circuit board layout. The module draws power from the two terminals, solving the problem that traditional active circuits require independent grounding terminals. Moreover, it achieves the "differential current reduction" characteristic through differential voltage feedback mechanism. Under short-circuit extreme conditions, the current automatically folds back to an extremely low level, and the instantaneous power consumption of the power transistor is always limited to a preset safe range. The power consumption curve is parabolic, which fundamentally solves the problem of easy burnout of traditional constant current solutions during short circuits.

[0042] Please see Figure 5 One terminal of this two-terminal wide-temperature surge suppression circuit serves as the positive power supply interface, and the other terminal serves as the positive load interface, connected to the high end of the external circuit.

[0043] In one embodiment, the first feedback module includes a first resistor and a second resistor, wherein: The first end of the first resistor serves as the first end of the first feedback module, and the second end of the first resistor serves as the second end of the first feedback module. The first end of the second resistor is electrically connected to the second end of the first resistor, and the second end of the second resistor serves as the third end of the first feedback module.

[0044] Specifically, the recommended model for the first PNP transistor is 2N3906, and the model for the second PNP transistor should be the same as that of the first. The recommended model for the first Zener diode is LM385-1.2 or TL431 (1.24V), with a selection temperature coefficient of less than 50ppm / ℃. The third resistor should be selected from 0.1Ω to 100Ω, determined based on the constant current value required in the actual application. The first resistor should be selected from 500Ω to 10kΩ, with 5.11kΩ being a typical choice. The second resistor should be selected from 100kΩ to 2MΩ. The fourth resistor should also be selected from 100kΩ to 2MΩ. Preferably, the first and second PNP transistors are integrated dual PNP transistors (such as BC857BD or MMDT3906 in an SOT-363 package), with the same die and process parameters, ensuring good thermal coupling and further improving compensation accuracy.

[0045] In one embodiment, the two-terminal wide-temperature surge suppression circuit further includes a first diode, wherein: The anode of the first diode serves as the positive power supply interface, and the cathode of the first diode is electrically connected to the emitter of the second PNP transistor.

[0046] In this embodiment, the first diode serves as a reverse connection protection diode, which can prevent the circuit from being damaged due to reverse polarity connection, and at the same time block the capacitor at the positive terminal of the load from discharging in reverse to the positive terminal of the power supply.

[0047] Please see Figure 3 This embodiment also provides a two-terminal wide-temperature surge suppression circuit as an NMOS high-side solution, including a second conduction sub-circuit, a first NPN transistor, a second NPN transistor, and a second Zener diode; The emitter of the second NPN transistor serves as the positive terminal of the load, the base of the second NPN transistor is electrically connected to the collector, and the collector of the second NPN transistor is electrically connected to the output terminal of the second conducting sub-circuit. The anode of the second Zener diode is electrically connected to the emitter of the second NPN transistor, and the cathode of the second Zener diode is electrically connected to the emitter of the first NPN transistor. The base of the first NPN transistor is electrically connected to the feedback terminal of the second conduction sub-circuit, and the collector of the first NPN transistor is electrically connected to the control terminal of the second conduction sub-circuit. The input terminal of the second conducting sub-circuit serves as the positive power supply interface; During normal operation, when the temperatures of the first NPN transistor and the second NPN transistor change, the first NPN transistor generates a first temperature drift deviation, and the second NPN transistor generates a second temperature drift deviation. The first temperature drift deviation and the second temperature drift deviation are of the same magnitude but opposite in direction to the two-terminal wide-temperature surge suppression circuit. Therefore, the first temperature drift deviation will cancel out the second temperature drift deviation, thereby eliminating the influence of temperature changes on the first NPN transistor and the second NPN transistor.

[0048] This embodiment uses a special connection between two transistors. During normal operation, when the temperature changes, the two transistors will produce temperature drift deviations of the same magnitude but opposite directions relative to the circuit. These two temperature drift deviations will cancel each other out, thereby eliminating the influence of temperature changes on the two transistors. The remaining components have very low temperature sensitivity, thus improving the stability of the surge suppression circuit across the entire temperature range.

[0049] In one embodiment, the second conducting sub-circuit includes a second feedback module, an NMOS transistor, a seventh resistor, and an eighth resistor, wherein: The drain of the NMOS transistor serves as the input terminal of the second conduction sub-circuit, the gate of the NMOS transistor serves as the control terminal of the second conduction sub-circuit, and the source of the NMOS transistor is electrically connected to the first terminal of the seventh resistor. The second end of the seventh resistor serves as the output end of the second conducting sub-circuit. The first end of the eighth resistor is electrically connected to the drain of the NMOS transistor, and the second end of the eighth resistor is electrically connected to the gate of the NMOS transistor. The first terminal of the second feedback module is electrically connected to the drain of the NMOS transistor, the second terminal of the second feedback module serves as the feedback terminal of the second conduction sub-circuit, and the third terminal of the second feedback module is electrically connected to the source of the NMOS transistor.

[0050] It should be noted that the first NPN transistor acts as the driver transistor, and the second NPN transistor acts as the compensation transistor; let the voltage regulation value of the second Zener diode be... The Vbe of the drive transistor is The Vbe of the compensation tube is The resistance of the seventh resistor is R1, and the voltage difference across R1 is V(R1). The conduction threshold of the driving transistor is determined by the following voltage loop: (Equation 10) The first NPN transistor and the second NPN transistor are of the same type, have the same on-threshold temperature coefficient (approximately -2mV / ℃), and drift in the same direction with equal amplitude when the temperature changes. (Equation 11) The constant current reference is determined solely by the voltage of the second Zener diode: (Equation 12) in, The constant current reference of this circuit is the magnitude of the current that is finally output to the positive terminal of the load. The temperature coefficient of the Zener diode (such as a 1.24V Zener diode) is usually less than 50ppm / ℃, which is much smaller than the Vbe temperature coefficient of the transistor. The constant current reference remains stable throughout the entire temperature range.

[0051] Please see Figure 7 The data in the figure shows the power consumption measurements of the MOSFET at different input voltages at -60℃, 25℃, and 100℃. The horizontal axis represents the input voltage in volts (V), and the vertical axis represents the MOSFET power consumption in watts (W). The left table shows the circuit without temperature compensation, and the right table shows the circuit with temperature compensation. It is clear that the MOSFET power consumption in the temperature-compensated circuit maintains high stability at all three temperatures and voltage levels, showing a significant improvement compared to the uncompensated circuit.

[0052] Specifically, the test data on the power consumption of the MOSFET as a function of temperature without temperature compensation is shown in Table 1, and the test data on the power consumption of the MOSFET as a function of temperature after temperature compensation is shown in Table 2, as follows: Table 1: Power consumption of MOSFETs as a function of temperature without temperature compensation Table 2: Power dissipation of MOSFET with temperature after temperature compensation A comparison of the data in the two tables shows that without compensation, the maximum power consumption deviation under the three temperature conditions reaches 2.72W; after adding temperature compensation, the maximum deviation is less than 0.23W, verifying the effectiveness of the temperature compensation scheme of the present invention.

[0053] It should also be noted that this circuit has two operating phases: During the constant current stage, the circuit will operate in this stage when it starts normally or when the voltage difference between the positive power supply interface and the positive load interface is small. The driving transistor controls the gate voltage of the NMOS transistor to keep the conduction current constant. Two transistors of the same type ensure that the constant current value does not change with temperature. During the differential voltage reduction phase, when the load is short-circuited or heavily loaded, resulting in a large voltage difference between the positive terminal of the power supply and the positive terminal of the load, this phase will be activated. The second feedback module samples the differential voltage signal from the drain and source terminals of the NMOS transistor and generates a feedback potential that is sent to the base of the driver transistor. When the differential voltage increases, the change in the feedback potential alters the conduction level of the driver transistor, controlling the NMOS transistor to tend to turn off, and the charging current automatically decreases. The "differential voltage reduction" characteristic, where the current decreases as the differential voltage increases, limits the instantaneous power consumption of the NMOS transistor to a safe range, presenting an approximately constant power parabolic power consumption curve.

[0054] In both the constant current stage and the differential current reduction stage, the Vbe of the compensation tube and the Vbe of the drive tube are always connected in series in the voltage circuit, and the temperature drift is continuously canceled out, resulting in highly consistent power consumption limiting characteristics across the entire temperature range.

[0055] This two-terminal wide-temperature surge suppression circuit does not require a separate grounding terminal. The internal reference potential is established at the low potential end of the seventh resistor. The power supply of the entire circuit is multiplexed with the main circuit circuit connected to the two terminals of this circuit, and it draws power from the voltage difference between the two terminals to operate.

[0056] Based on this floating ground characteristic, this two-terminal wide-temperature surge suppression circuit can be directly applied to high-end scenarios. When the circuit is connected in series between the positive terminal of the power supply and the positive terminal of the load, the internal reference potential of the circuit will float adaptively. When applied to external circuits, the source of the NMOS transistor is not fixedly grounded, but is a floating internal reference point, which completely eliminates the dependence on high-voltage PMOS devices and significantly reduces the difficulty and cost of device selection in high-voltage applications.

[0057] This embodiment has only two external connection terminals, which are equivalent to power resistors or NTC thermistors in electrical connection. It can directly replace existing passive surge suppression devices with two terminals without changing the circuit board layout. The module draws power from the two terminals, solving the problem that traditional active circuits require independent grounding terminals. Moreover, it achieves the "differential current reduction" characteristic through differential voltage feedback mechanism. Under short-circuit extreme conditions, the current automatically folds back to an extremely low level, and the instantaneous power consumption of the power transistor is always limited to a preset safe range. The power consumption curve is parabolic, which fundamentally solves the problem of easy burnout of traditional constant current solutions during short circuits.

[0058] Please see Figure 5 One terminal of this two-terminal wide-temperature surge suppression circuit serves as the positive power supply interface, and the other terminal serves as the positive load interface, connected to the high end of the external circuit.

[0059] In one embodiment, the second feedback module includes a fifth resistor and a sixth resistor, wherein: The first end of the fifth resistor serves as the first end of the second feedback module, and the second end of the fifth resistor serves as the second end of the second feedback module. The first end of the sixth resistor is electrically connected to the second end of the fifth resistor, and the second end of the sixth resistor serves as the third end of the second feedback module.

[0060] In this embodiment, a conventional NMOS transistor circuit would connect a clamping diode in parallel between the gate and source of the NMOS transistor. However, this clamping diode can be omitted in this solution because when the voltage difference across the NMOS transistor is large, the first NPN transistor automatically adjusts the gate-source voltage of the NMOS transistor to a moderate level (usually far below the 20V gate oxide breakdown threshold) through closed-loop feedback, and the NMOS transistor operates in the linear region. When the voltage difference decreases to an insufficient level to maintain constant current, the NMOS transistor jumps out of the linear region and enters full conduction, but at this point the voltage difference is already far below the safety threshold. Therefore, by reasonably setting the resistance parameters of the fifth, sixth, and seventh resistors, the gate-source voltage of the NMOS transistor remains within a safe range throughout the entire operation, without the need for additional clamping protection.

[0061] Specifically, the recommended model for the first NPN transistor is 2N3904, and the model of the second NPN transistor should be consistent with that of the first NPN transistor. The recommended model for the second Zener diode is LM385-1.2 or TL431 (1.24V), with a temperature coefficient of less than 50ppm / ℃. The third resistor should be selected from 0.1Ω to 100Ω, depending on the constant current value required in the application. The first resistor should be selected from 100Ω to 10kΩ, with a typical selection of 5.11kΩ. The second resistor should be selected from 100kΩ to 2MΩ. The fourth resistor should be selected from 100kΩ to 500kΩ. Ideally, the first and second PNP transistors should be integrated dual NPN transistors (such as BC847BD or MMDT3904 in an SOT-363 package), with the same die and process parameters, ensuring good thermal coupling.

[0062] In one embodiment, the two-terminal wide-temperature surge suppression circuit further includes a second diode, wherein: The anode of the second diode is electrically connected to the emitter of the second NPN transistor, and the cathode of the second diode serves as the positive terminal interface of the load.

[0063] In this embodiment, the second diode serves as a reverse connection protection diode, which can prevent the circuit from being damaged due to reverse polarity connection, and at the same time block the capacitor at the positive terminal of the load from discharging in reverse to the positive terminal of the power supply.

[0064] Please see Figure 4 This embodiment also provides a two-terminal wide-temperature surge suppression circuit as a low-end NMOS solution, including a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a second NMOS transistor, a third NPN transistor, a fourth NPN transistor, a third Zener diode, and a third diode. The cathode of the third diode serves as the negative terminal interface of the load, and the anode of the third diode is electrically connected to the emitter of the fourth NPN transistor. The base and collector of the fourth NPN transistor are electrically connected, and the collector of the fourth NPN transistor is electrically connected to the first end of the eleventh resistor. The second end of the eleventh resistor is electrically connected to the source of the second NMOS transistor; The gate of the second NMOS transistor is electrically connected to the first end of the twelfth resistor, and the drain of the second NMOS transistor serves as the negative power supply interface. The second end of the twelfth resistor is electrically connected to the drain of the second NMOS transistor; The anode of the third Zener diode is electrically connected to the anode of the third diode, and the cathode of the third Zener diode is electrically connected to the emitter of the third NPN transistor. The base of the third NPN transistor is electrically connected to the first end of the ninth resistor, and the collector of the third NPN transistor is electrically connected to the gate of the second NMOS transistor. The second terminal of the ninth resistor is electrically connected to the source of the second NMOS transistor; The first end of the tenth resistor is electrically connected to the first end of the ninth resistor, and the second end of the tenth resistor is electrically connected to the drain of the second NMOS transistor. During normal operation, when the temperatures of the third NPN transistor and the fourth NPN transistor change, the third NPN transistor generates a third temperature drift deviation, and the fourth NPN transistor generates a fourth temperature drift deviation. The third temperature drift deviation and the fourth temperature drift deviation are of the same magnitude but in opposite directions relative to the two-terminal wide-temperature surge suppression circuit. Therefore, the third temperature drift deviation cancels out the fourth temperature drift deviation, thereby eliminating the influence of temperature changes on the third NPN transistor and the fourth NPN transistor.

[0065] This embodiment is a low-end NMOS solution, and its circuit structure is exactly the same as that of the high-end NMOS solution, except that the circuit is connected in series in the application.

[0066] Please see Figure 6 One terminal of this two-terminal wide-temperature surge suppression circuit serves as the negative power supply interface, and the other terminal serves as the negative load interface, connected to the low end of the external circuit.

[0067] This embodiment uses a special connection between two transistors. During normal operation, when the temperature changes, the two transistors will produce temperature drift deviations of the same magnitude but opposite directions relative to the circuit. These two temperature drift deviations will cancel each other out, thereby eliminating the influence of temperature changes on the two transistors. The remaining components have very low temperature sensitivity, thus improving the stability of the surge suppression circuit across the entire temperature range.

[0068] This embodiment also provides a two-terminal wide-temperature surge suppression device, including a housing and a two-terminal wide-temperature surge suppression circuit as a PMOS high-side solution disposed inside the housing; the housing is provided with a power supply positive interface and a load positive interface; the power supply positive interface is electrically connected to the anode of the first diode in the two-terminal wide-temperature surge suppression circuit; the load positive interface is electrically connected to the output terminal of the first conducting sub-circuit in the two-terminal wide-temperature surge suppression circuit.

[0069] This embodiment also provides a two-terminal wide-temperature surge suppression device, including a housing and a two-terminal wide-temperature surge suppression circuit as an NMOS high-side solution disposed inside the housing; the housing is provided with a power supply positive interface and a load positive interface; the power supply positive interface is electrically connected to the input terminal of the second conducting sub-circuit in the two-terminal wide-temperature surge suppression circuit; the load positive interface is electrically connected to the cathode of the second diode in the two-terminal wide-temperature surge suppression circuit.

[0070] This embodiment also provides a two-terminal wide-temperature surge suppression device, including a housing and a two-terminal wide-temperature surge suppression circuit as a low-end NMOS scheme disposed inside the housing; the housing is provided with a power supply negative interface and a load negative interface; the power supply negative interface is electrically connected to the drain of the second NMOS transistor in the two-terminal wide-temperature surge suppression circuit; the load negative interface is electrically connected to the cathode of the third diode in the two-terminal wide-temperature surge suppression circuit.

[0071] The above three device embodiments use two transistors in a special connection in a two-terminal wide-temperature surge suppression circuit. During normal operation, when the temperature changes, the two transistors will produce temperature drift deviations of the same magnitude but opposite directions relative to the circuit. These two temperature drift deviations will cancel each other out, thereby eliminating the influence of temperature changes on the two transistors, thus improving the stability of the surge suppression circuit over the entire temperature range.

[0072] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A two-terminal wide-temperature surge suppression circuit, characterized in that, It includes a first conducting sub-circuit, a first PNP transistor, a second PNP transistor, and a first Zener diode; The emitter of the second PNP transistor serves as the positive power supply interface, the base and collector of the second PNP transistor are electrically connected, and the collector of the second PNP transistor is electrically connected to the input terminal of the first conducting sub-circuit. The cathode of the first Zener diode is electrically connected to the emitter of the second PNP transistor, and the anode of the first Zener diode is electrically connected to the emitter of the first PNP transistor. The base of the first PNP transistor is electrically connected to the feedback terminal of the first conducting sub-circuit, and the collector of the first PNP transistor is electrically connected to the control terminal of the first conducting sub-circuit. The output terminal of the first conducting sub-circuit serves as the positive terminal interface of the load. During normal operation, when the temperatures of the first PNP transistor and the second PNP transistor change, the first PNP transistor generates a first temperature drift deviation, and the second PNP transistor generates a second temperature drift deviation. The first temperature drift deviation and the second temperature drift deviation are of the same magnitude but opposite in direction to the two-terminal wide-temperature surge suppression circuit. Therefore, the first temperature drift deviation will cancel out the second temperature drift deviation, thereby eliminating the influence of temperature changes on the first PNP transistor and the second PNP transistor.

2. The two-terminal wide-temperature surge suppression circuit according to claim 1, characterized in that, The first conducting sub-circuit includes a first feedback module, a PMOS transistor, a third resistor, and a fourth resistor, wherein: The first end of the third resistor serves as the input terminal of the first conducting sub-circuit, and the second end of the third resistor is electrically connected to the source of the PMOS transistor. The gate of the PMOS transistor serves as the control terminal of the first conduction sub-circuit, and the drain of the PMOS transistor serves as the output terminal of the first conduction sub-circuit. The first end of the fourth resistor is electrically connected to the gate of the PMOS transistor, and the second end of the fourth resistor is electrically connected to the drain of the PMOS transistor. The first terminal of the first feedback module is electrically connected to the source of the PMOS transistor, the second terminal of the first feedback module serves as the feedback terminal of the first conduction sub-circuit, and the third terminal of the first feedback module is electrically connected to the drain of the PMOS transistor.

3. A two-terminal wide-temperature surge suppression circuit according to claim 2, characterized in that, The first feedback module includes a first resistor and a second resistor, wherein: The first end of the first resistor serves as the first end of the first feedback module, and the second end of the first resistor serves as the second end of the first feedback module. The first end of the second resistor is electrically connected to the second end of the first resistor, and the second end of the second resistor serves as the third end of the first feedback module.

4. A two-terminal wide-temperature surge suppression circuit according to claim 1, characterized in that, It also includes a first diode, wherein: The anode of the first diode serves as the positive power supply interface, and the cathode of the first diode is electrically connected to the emitter of the second PNP transistor.

5. A two-terminal wide-temperature surge suppression circuit, characterized in that, It includes a second conducting sub-circuit, a first NPN transistor, a second NPN transistor, and a second Zener diode; The emitter of the second NPN transistor serves as the positive terminal of the load, the base of the second NPN transistor is electrically connected to the collector, and the collector of the second NPN transistor is electrically connected to the output terminal of the second conducting sub-circuit. The anode of the second Zener diode is electrically connected to the emitter of the second NPN transistor, and the cathode of the second Zener diode is electrically connected to the emitter of the first NPN transistor. The base of the first NPN transistor is electrically connected to the feedback terminal of the second conduction sub-circuit, and the collector of the first NPN transistor is electrically connected to the control terminal of the second conduction sub-circuit. The input terminal of the second conducting sub-circuit serves as the positive power supply interface; During normal operation, when the temperatures of the first NPN transistor and the second NPN transistor change, the first NPN transistor generates a first temperature drift deviation, and the second NPN transistor generates a second temperature drift deviation. The first temperature drift deviation and the second temperature drift deviation are of the same magnitude but opposite in direction to the two-terminal wide-temperature surge suppression circuit. Therefore, the first temperature drift deviation will cancel out the second temperature drift deviation, thereby eliminating the influence of temperature changes on the first NPN transistor and the second NPN transistor.

6. A two-terminal wide-temperature surge suppression circuit according to claim 5, characterized in that, The second conducting sub-circuit includes a second feedback module, an NMOS transistor, a seventh resistor, and an eighth resistor, wherein: The drain of the NMOS transistor serves as the input terminal of the second conduction sub-circuit, the gate of the NMOS transistor serves as the control terminal of the second conduction sub-circuit, and the source of the NMOS transistor is electrically connected to the first terminal of the seventh resistor. The second end of the seventh resistor serves as the output end of the second conducting sub-circuit. The first end of the eighth resistor is electrically connected to the drain of the NMOS transistor, and the second end of the eighth resistor is electrically connected to the gate of the NMOS transistor. The first terminal of the second feedback module is electrically connected to the drain of the NMOS transistor, the second terminal of the second feedback module serves as the feedback terminal of the second conduction sub-circuit, and the third terminal of the second feedback module is electrically connected to the source of the NMOS transistor.

7. A two-terminal wide-temperature surge suppression circuit according to claim 6, characterized in that, The second feedback module includes a fifth resistor and a sixth resistor, wherein: The first end of the fifth resistor serves as the first end of the second feedback module, and the second end of the fifth resistor serves as the second end of the second feedback module. The first end of the sixth resistor is electrically connected to the second end of the fifth resistor, and the second end of the sixth resistor serves as the third end of the second feedback module.

8. A two-terminal wide-temperature surge suppression circuit according to claim 5, characterized in that, It also includes a second diode, wherein: The anode of the second diode is electrically connected to the emitter of the second NPN transistor, and the cathode of the second diode serves as the positive terminal interface of the load.

9. A two-terminal wide-temperature surge suppression device, characterized in that, The device includes a housing and a two-terminal wide-temperature surge suppression circuit as described in claim 4 disposed inside the housing; the housing is provided with a power positive interface and a load positive interface; the power positive interface is electrically connected to the anode of the first diode in the two-terminal wide-temperature surge suppression circuit; the load positive interface is electrically connected to the output terminal of the first conducting sub-circuit in the two-terminal wide-temperature surge suppression circuit.

10. A two-terminal wide-temperature surge suppression device, characterized in that, The device includes a housing and a two-terminal wide-temperature surge suppression circuit as described in claim 8 disposed inside the housing; the housing is provided with a power positive interface and a load positive interface; the power positive interface is electrically connected to the input terminal of the second conducting sub-circuit in the two-terminal wide-temperature surge suppression circuit; the load positive interface is electrically connected to the cathode of the second diode in the two-terminal wide-temperature surge suppression circuit.

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