Photovoltaic direct current arc prevention method based on multi-thread processor

Abstract

The application relates to the field of photovoltaic power generation safety, and provides a photovoltaic direct-current arc defense method based on a multi-thread processor, which comprises the following steps: over-sampling a photovoltaic direct-current bus current based on an ADC of the multi-thread processor, synchronously calling an adaptive trap wave algorithm, filtering out frequency point interference of a dynamic switch of a photovoltaic inverter, and obtaining initial sampling data; dividing hardware threads of the multi-thread processor into a first thread domain and a second thread domain which are isolated from each other; performing MPPT power operation based on the first thread domain, adjusting the dynamic switch of the photovoltaic inverter based on an operation result, and generating a trigger signal after single-period MPPT power operation; in response to the trigger signal, the second thread domain determines an arc recognition result based on the initial sampling data; if the arc recognition result is an arc alarm, the first thread domain controls the photovoltaic direct-current loop to be cut off. Power control and arc detection are parallel, the arc false alarm rate is reduced, the arc failure response speed is fast, stable power generation is realized, and photovoltaic power generation income is improved.

Description

Technical Field

[0001] This application relates to the fields of photovoltaic power generation safety and power electronic control technology, and in particular to a photovoltaic DC arc protection method based on a multi-threaded processor. This application also relates to a photovoltaic DC arc protection device based on a multi-threaded processor, a computing device, and a computer-readable storage medium. Background Technology

[0002] Photovoltaic DC arc detection, or AFCI, is currently a necessity in the photovoltaic industry because DC arcing is the most critical factor causing distributed photovoltaic fires. Existing AFCI solutions mainly rely on simple Fourier transform (FFT) and energy threshold determination.

[0003] However, the switching actions of the photovoltaic inverter itself, the disturbances caused by shading, and the feedback noise from the grid side can easily overlap with the actual electric arc in the frequency domain, resulting in excessively high false alarms. This leads to frequent false shutdowns of the inverter, severely impacting power generation revenue. Furthermore, the instantaneous temperature of a DC arc can reach 3000°C, requiring the circuit to be cut off within 100 ms or even less. Traditional cloud-based or low-speed microcontroller (MCU) solutions suffer from large computational delays and cannot meet the instantaneous shutdown requirements. Summary of the Invention

[0004] In view of this, embodiments of this application provide a photovoltaic DC arc defense method based on a multi-threaded processor to address the technical deficiencies in the prior art. Embodiments of this application also provide a photovoltaic DC arc defense device based on a multi-threaded processor, a computing device, and a computer-readable storage medium.

[0005] According to a first aspect of the embodiments of this application, a photovoltaic DC arc defense method based on a multi-threaded processor is provided, comprising: The ADC based on the multi-threaded processor performs oversampling on the photovoltaic DC bus current and synchronously calls the adaptive notch filter algorithm of the multi-threaded processor to filter out the frequency interference of the dynamic switching of the photovoltaic inverter in real time and obtain the initial sampling data. The hardware threads of the multi-threaded processor are divided into a first thread domain and a second thread domain that are isolated from each other. The first thread domain is used to control maximum power point tracking, and the second thread domain is used for arc detection. MPPT power calculation is performed based on the first thread domain, and the dynamic switch of the photovoltaic inverter is adjusted based on the calculation result. A trigger signal is generated after a single cycle of MPPT power calculation. In response to the trigger signal, the second thread domain determines the arc identification result based on the initial sampling data. If the arc identification result is an arc alarm, the first thread domain operates the built-in PWM emergency block register of the multi-threaded processor to cut off the photovoltaic DC circuit.

[0006] Optionally, in response to the trigger signal, the second thread domain determines the arc identification result based on the initial sampling data, including: In response to the trigger signal, the second thread domain extracts the feature vector of the initial sampled data to obtain an arc multidimensional feature vector containing abrupt entropy, temporal kurtosis, and broadband energy flatness; The arc multidimensional feature vector is input into the on-chip lightweight Tiny-CNN model through the second thread domain to perform arc recognition, and the arc recognition result is obtained, wherein the arc recognition result includes normal operation or arc alarm.

[0007] Optionally, the lightweight Tiny-CNN used for photovoltaic arc recognition binarized weights are pre-stored in off-chip flash memory or on-chip shared memory in a packaged bitstream format; when the second thread domain performs the current network layer inference operation through the current arc multidimensional feature vector, the weight DMA engine configured in the second thread domain asynchronously and in parallel reads and unpacks the bitstream of the next layer binarized weights.

[0008] Optionally, dividing the hardware threads of the multi-threaded processor into mutually isolated first thread domains and second thread domains includes: The controllable dynamic multithreaded architecture based on the multithreaded processor adds a mark to each instruction, wherein the mark contains the thread domain identifier to which the corresponding instruction belongs and the execution priority; Based on the thread domain identifier carried by the mark, MPPT control instructions belonging to the first thread domain and arc detection instructions belonging to the second thread domain are distinguished. At the same time, the processor hardware computing resources are dynamically allocated in combination with the execution priority recorded by the mark.

[0009] Optionally, the MPPT control instructions include MPPT operation instructions, and the arc detection instructions include arc feature extraction instructions and Tiny-CNN inference instructions. The execution priority of the marks corresponding to the MPPT control instructions is uniformly configured as high priority, and the execution priority of the marks corresponding to the arc detection instructions is uniformly configured as low priority. During the instruction issuance phase, the processor hardware prioritizes scheduling the MPPT control instructions to occupy the computational units based on the difference in execution priority of the marks.

[0010] Optionally, when the first thread domain generates a high-priority MPPT emergency calculation requirement, the arc-related calculation process currently being executed by the second thread domain is paused, and the intermediate calculation data of the process is saved. During the pause, no calculation resources are allocated to the second thread domain, and read and write operations of the second thread domain to the storage area are blocked. Only the first thread domain is allowed to read and write to the storage area to perform MPPT calculations. Until the first thread domain completes all the MPPT emergency calculations, the resource and storage access restrictions on the second thread domain are lifted, and the second thread domain retrieves the pre-saved intermediate calculation data and continues to execute the paused arc-related calculation process.

[0011] Optionally, the multi-threaded processor is configured with a phase-shiftable on-chip memory clock, and the on-chip memory clock operates at a frequency lower than the processor core main clock frequency. During the process of the first thread domain performing MPPT power calculation and / or the second thread domain determining the arc identification result based on the initial sampling data, the on-chip memory clock synchronously and dynamically adjusts the output clock phase to adapt to the processor core read and write timing, and the multi-threaded processor performs gated clock stop operation on idle memory modules whose read and write channels are not occupied by the first thread domain and the second thread domain.

[0012] Optionally, when the arc identification result output by the second thread domain is an arc alarm, the second thread domain synchronously outputs the arc fault confidence level; The first thread domain classifies the fault level based on the arc fault confidence level; When the confidence level of the arc fault is less than or equal to the first confidence threshold, the fault level is a low-confidence suspected arc. The first thread domain stops operating the PWM emergency block register, reports an alarm log locally, and continuously collects bus current for re-judgment. When the confidence level of the arc fault is greater than the first confidence threshold and less than or equal to the second confidence threshold, the fault level is a high confidence confirmed arc, the PWM emergency lockout register is continuously latched, and an arc fault message is synchronously output to the peripheral fault communication interface. When the confidence level of the arc fault is greater than the second confidence threshold, the fault level is an ultra-high confidence strong arc, the PWM is blocked and the hardware switch drive signal is triggered to disconnect the DC circuit breaker at the front end of the photovoltaic string.

[0013] Optionally, the multi-threaded processor is configured with a multi-level pipelined parallel execution architecture, and maps the MPPT power calculation task belonging to the first thread domain and the arc identification task belonging to the second thread domain to two mutually isolated pipeline execution stages within the multi-level pipelined parallel execution architecture.

[0014] Optionally, the two sets of pipeline execution stages are equipped with independent computing paths and dedicated computing storage spaces; each computing path can only perform read and write operations on its own dedicated computing storage space, and the computing processes of the first thread domain and the second thread domain are completed in their respective pipeline execution stages.

[0015] According to a second aspect of the embodiments of this application, a photovoltaic DC arc protection device based on a multi-threaded processor is provided, comprising: The sampling module is configured to oversample the photovoltaic DC bus current based on the ADC of the multi-threaded processor, and synchronously call the adaptive notch filter algorithm of the multi-threaded processor to filter out the frequency interference of the dynamic switching of the photovoltaic inverter in real time to obtain the initial sampling data. The partitioning module is configured to divide the hardware threads of the multi-threaded processor into a first thread domain and a second thread domain that are isolated from each other, wherein the first thread domain is used to control maximum power point tracking and the second thread domain is used for arc detection. The MPPT power calculation module is configured to perform MPPT power calculation based on the first thread domain, adjust the dynamic switch of the photovoltaic inverter based on the calculation result, and generate a trigger signal after a single cycle of MPPT power calculation. The photovoltaic DC arc detection and defense module is configured to respond to the trigger signal, wherein the second thread domain determines the arc detection result based on the initial sampling data, and if the arc detection result is an arc alarm, the first thread domain operates the built-in PWM emergency block register of the multi-threaded processor to cut off the photovoltaic DC circuit.

[0016] According to a third aspect of the embodiments of this application, a computing device is provided, comprising: Memory and processor; The memory is used to store computer-executable instructions, and the processor executes the computer-executable instructions to implement the steps of the photovoltaic DC arc defense method based on a multi-threaded processor.

[0017] According to a fourth aspect of the embodiments of this application, a computer-readable storage medium is provided that stores computer-executable instructions, which, when executed by a processor, implement the steps of the photovoltaic DC arc defense method based on a multi-threaded processor.

[0018] According to a fifth aspect of the embodiments of this application, a chip is provided that stores a computer program, which, when executed by the chip, implements the steps of the photovoltaic DC arc defense method based on a multi-threaded processor.

[0019] This application provides a photovoltaic DC arc protection method based on a multi-threaded processor. The method involves oversampling the photovoltaic DC bus current using the ADC of the multi-threaded processor, synchronously calling the adaptive notch filter algorithm of the multi-threaded processor to filter out frequency interference from the dynamic switching of the photovoltaic inverter in real time, and obtaining initial sampling data. The hardware threads of the multi-threaded processor are divided into a first thread domain and a second thread domain, which are isolated from each other. The first thread domain is used to control maximum power point tracking (MPPT), and the second thread domain is used for arc detection. MPPT power calculation is performed based on the first thread domain, and the dynamic switching of the photovoltaic inverter is adjusted based on the calculation result. A trigger signal is generated after a single cycle of MPPT power calculation. In response to the trigger signal, the second thread domain determines the arc identification result based on the initial sampling data. If the arc identification result is an arc alarm, the first thread domain operates the built-in PWM emergency lockout register of the multi-threaded processor to cut off the photovoltaic DC circuit. This invention relates to a method that utilizes an edge-side AI processing chip to identify the characteristics of high-frequency noise on a DC bus, thereby achieving accurate determination of DC arcs, parallel power control and arc detection, reducing the false alarm rate of arcs, and providing fast response to arc faults. This enables stable power generation while improving the revenue of photovoltaic power generation. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart of a photovoltaic DC arc defense method based on a multi-threaded processor provided in an embodiment of this application; Figure 2 This is a schematic diagram of the hardware architecture for thread domain partitioning and storage space isolation of a photovoltaic DC arc defense method based on a multi-threaded processor, provided in an embodiment of this application. Figure 3 This is a schematic diagram of a phase-movable on-chip memory clock architecture for a photovoltaic DC arc defense method based on a multi-threaded processor, provided in an embodiment of this application. Figure 4 This is a schematic diagram of the structure of a photovoltaic DC arc defense device based on a multi-threaded processor, provided in one embodiment of this application; Figure 5 This is a structural block diagram of a computing device provided in one embodiment of this application. Detailed Implementation

[0022] Many specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below.

[0023] The terminology used in one or more embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of one or more embodiments of this application. The singular forms “a,” “the,” and “the” used in one or more embodiments of this application and in the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” used in one or more embodiments of this application refers to and includes any or all possible combinations of one or more associated listed items.

[0024] It should be understood that although the terms first, second, etc., may be used to describe various information in one or more embodiments of this application, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, first may also be referred to as second without departing from the scope of one or more embodiments of this application, and similarly, second may also be referred to as first.

[0025] This application provides a photovoltaic DC arc protection method based on a multi-threaded processor. This application also relates to a photovoltaic DC arc protection device based on a multi-threaded processor, a computing device, and a computer-readable storage medium, which will be described in detail in the following embodiments.

[0026] Figure 1 The flowchart illustrates a photovoltaic DC arc defense method based on a multi-threaded processor according to an embodiment of this application, which specifically includes the following steps: Step S102: The ADC based on the multi-threaded processor oversamples the photovoltaic DC bus current, and synchronously calls the adaptive notch filter algorithm of the multi-threaded processor to filter out the frequency interference of the dynamic switching of the photovoltaic inverter in real time, so as to obtain the initial sampling data. Step S104: Divide the hardware threads of the multi-threaded processor into a first thread domain and a second thread domain that are isolated from each other, wherein the first thread domain is used to control maximum power point tracking and the second thread domain is used for arc detection. Step S106: Perform MPPT power calculation based on the first thread domain, adjust the dynamic switch of the photovoltaic inverter based on the calculation result, and generate a trigger signal after a single cycle of MPPT power calculation; Step S108: In response to the trigger signal, the second thread domain determines the arc identification result based on the initial sampling data. If the arc identification result is an arc alarm, the first thread domain operates the built-in PWM emergency block register of the multi-threaded processor to cut off the photovoltaic DC circuit.

[0027] The multi-threaded processor employs a controllable dynamic multi-threaded digital signal processor (DSP), equipped with four independent hardware threads, a VPU vector processing unit, an on-chip analog-to-digital converter (ADC), adaptive notch filtering hardware logic, a phase-shifting clock storage module, and a hardware PWM blocking register. PWM stands for Pulse Width Modulation, and it features a Mark instruction scheduling architecture to support parallel operation of maximum power point tracking (MPPT) real-time control and arc AI inference. The ADC oversampling uses a built-in 4Msps high-speed analog-to-digital converter to acquire the photovoltaic DC bus current at a sampling rate far exceeding the arc characteristic frequency band, preferably between 10kHz and 100kHz. Oversampling improves the signal-to-noise ratio of weak arc noise and captures subtle waveform changes in arc pink noise. The adaptive notch filtering algorithm is a real-time filtering logic integrated into the system-on-a-chip (SoC) hardware link. It continuously tracks the dynamic switching frequency of the photovoltaic inverter from 16kHz to 32kHz, generates corresponding notch frequencies, and directly filters out switching harmonic interference in the sampling hardware path.

[0028] Furthermore, the frequency interference of the dynamic switching of the photovoltaic inverter is due to the periodic switching of the MOSFETs / IGBTs in the photovoltaic DC / DC and DC / AC power conversion units. The switching frequency fluctuates in real time with the illumination and load, generating fixed frequency harmonic noise, which is the biggest source of interference for photovoltaic arc detection. The hardware threads are divided into two threads, the first and the second, which rely on two groups of hardware execution resources defined by a controllable dynamic multi-threading Mark. Each group has its own independent pipeline, registers, and memory access paths, with physical resource isolation and no thread preemption or blocking conflicts. The first thread domain is dedicated to executing maximum power point tracking real-time closed-loop control, outputting a PWM drive waveform to adjust the photovoltaic output power and ensure the power plant's power generation efficiency. This is a core hard real-time task of the photovoltaic inverter, requiring millisecond-level response. The second thread domain is dedicated to executing current feature extraction and lightweight CNN arc inference. It only gains scheduling authority after completing a single cycle of MPPT calculation and does not preempt power control hardware resources. The MPPT power calculation uses a maximum power point tracking closed-loop algorithm to collect the photovoltaic panel voltage and current in real time, calculate the optimal operating point using the perturbation observation method / conductivity increment method, and output a proportionally adjustable PWM signal to control the inverter's switching transistors to maximize the photovoltaic output power.

[0029] Furthermore, the trigger signal generated after a single-cycle MPPT operation is a level-synchronous trigger pulse generated by the hardware directly accessing the DMA channel after the first thread domain completes a full round of voltage-current sampling, power calculation, and PWM output closed loop. This pulse serves as the sole enable signal for the second thread domain to start arc detection. The initial sampled data is a clean 10kHz~100kHz current waveform data stream after ADC oversampling and adaptive notch filtering to remove inverter switching harmonics, grid noise, and component shadow disturbances. Only the arc-specific pink noise feature is retained as the original input for subsequent arc identification. The arc identification result is a binary judgment label output by the second thread domain using multi-dimensional features and a Tiny-CNN binary classification model. This label indicates whether the operation is normal or an arc alarm, and is the sole basis for determining the protection action. The built-in PWM emergency lockout register is a SoC hardware-level latch register. The lockout flag is directly written to the first thread domain, and the hardware circuit instantly shuts off all inverter power switch drive signals, cutting off the photovoltaic DC power circuit in milliseconds without requiring software to issue instructions step by step, meeting the mandatory 100ms arc shutdown standard.

[0030] Traditional photovoltaic AFCI arc detection uses low-speed single-point sampling with a general-purpose MCU and relies solely on software FFT filtering. The inverter's dynamic switching harmonics and cloud cover cause current disturbances that highly overlap with the pink noise spectrum of the arc. Fixed energy thresholds can easily mistake normal operating conditions for arcs, leading to frequent shutdowns and direct losses in photovoltaic power generation. A single erroneous shutdown in a small or medium-sized distributed power station can result in the loss of several hours of power generation revenue. At the same time, low-speed sampling cannot capture the high-frequency, subtle waveforms of weak initial arcs, posing a fire hazard and failing to meet the national standard for arc detection accuracy. Furthermore, in traditional single-threaded MCU architectures, MPPT power control and arc detection are executed sequentially. This results in a longer arc detection cycle if MPPT is prioritized, requiring hundreds of milliseconds to identify the arc after it occurs. A 3000℃ arc can easily ignite cables and junction boxes. If arc detection is prioritized, MPPT computation is delayed, preventing photovoltaic systems from tracking maximum power in real time, leading to a long-term decrease in power generation efficiency. These two tasks cannot be performed in parallel to balance real-time performance and power generation benefits. Arc recognition computational inference can preempt MPPT computation units, causing power control jitter, unstable output voltage, and grid connection failures.

[0031] Furthermore, when the inverter's PWM duty cycle is adjusted significantly, the bus current fluctuates violently, making arc detection highly susceptible to misjudgment. The detection results cannot be fed back to the power control logic in real time; even if an arc is identified, multiple software layers are required to issue a shutdown command, resulting in multi-level software delays. This prevents millisecond-level active circuit breaker protection, allowing only passive shutdown after a fault, lacking proactive defense capabilities. After an arc alarm, the shutdown command needs to be transmitted through multiple software layers—operating system, application layer, and driver layer—resulting in a long overall response time. A DC arc can ignite the insulation sheath within 100ms, posing a clear fire safety vulnerability. There is no direct hardware connection for the PWM blocking path; protection functions fail directly when the software crashes or the program malfunctions, resulting in insufficient safety redundancy.

[0032] Based on this, pure initial sampling data is generated by combining SoC hardware synchronous oversampling with adaptive hardware notch filtering; based on controllable dynamic multi-threaded Mark markers, hardware divides into dual isolated thread domains; the first thread domain performs MPPT single-cycle closed-loop operation to generate hardware trigger signal; the second thread domain responds to the trigger signal to perform arc recognition, and when an alarm occurs, it links the hardware PWM to block the circuit, thus solving the above problems.

[0033] Specifically, after the system is powered on, the first thread domain starts the MPPT basic sampling link and simultaneously enables the chip's built-in 4Msps high-speed ADC hardware module. The ADC collects the real-time current of the photovoltaic DC bus, and the sampling bandwidth covers the full frequency band of arc characteristics from 10kHz to 100kHz. The oversampling factor can be freely set, preferably 16 times. Through multi-cycle sampling superposition and averaging, the ambient electromagnetic random white noise is filtered, and the weak arc current fluctuation signal is amplified, solving the defects of insufficient signal-to-noise ratio of low-speed MCU sampling and inability to identify weak arcs. The raw current data stream output by the ADC is directly connected to the on-chip integrated adaptive notch filter hardware path. The hardware internally analyzes the duty cycle and switching cycle of the current MPPT output PWM register in real time, calculates the current dynamic switching frequency range of the inverter (16kHz~32kHz) in real time, and automatically generates the corresponding single-order / multi-order digital notch filter core. The hardware accurately filters out the harmonic components corresponding to the switching frequency from the raw sampled data stream. At the same time, the hardware has built-in dynamic noise threshold logic to distinguish between low-frequency current disturbances caused by cloud shading of photovoltaic modules and continuous broadband pink noise from the electric arc. It automatically shields low-frequency interference components and retains only the continuous high-frequency noise waveform specific to the electric arc. After filtering, standardized initial sampled data is generated and stored in the dual-port L1 high-speed memory.

[0034] This stage is entirely parallel to MPPT basic sampling. Sampling and filtering can be performed independently by the chip's peripheral hardware without occupying any thread domain computing resources. This eliminates false alarms caused by inverter switching noise. The pipeline completes sampling and filtering synchronously with zero software latency. The sampled data stream is stored in shared on-chip storage in real time and without interruption, providing interference-free raw data support for subsequent arc detection in the second thread domain. While the sampling and filtering hardware continuously outputs data, the processor core loads a VLIW (Very Long Instruction Set) with Mark markers. The compiler pre-embeds independent Mark markers for the two types of task instructions. At this time, the priority of the first thread domain and the second thread domain can be set through the Mark markers. For example, the Mark markers of MPPT control instructions are configured with high priority, and the Mark markers of arc detection instructions are configured with low priority. The processor instruction fetch unit cyclically scans the valid instructions in the I-Cache and automatically divides the hardware computing resources into completely isolated first and second thread domains based on the thread domain ID and priority information built into the Mark markers.

[0035] The isolation mechanisms include pipelined isolation, memory isolation, and clock-gated isolation. Specifically, in pipelined isolation, the two sets of threads occupy independent ALU arithmetic units, VPU vector operation units, and register files, respectively, with physical separation of the computational hardware. Large vector operations for AI inference will not preempt real-time computational resources for MPPT addition, subtraction, multiplication, and division. In memory isolation, the L1 memory is divided into independent address segments. The first thread domain can only read and write MPPT voltage, current, and PWM parameter storage areas, while the second thread domain can only read and write initial sampling data and feature vector storage areas. Hardware address filters intercept illegal access across memory areas, preventing data from being tampered with between the two types of tasks. In clock-gated isolation, the system dynamically allocates clock paths. The high-priority first thread domain is always allocated a stable kernel clock, while the second thread domain is only fully allocated the computational clock after the first thread domain completes a single cycle of computation and outputs a trigger pulse. In the event of an MPPT emergency interrupt, the clock of the second thread domain can be directly cut off, completely releasing hardware resources to the power control task. The entire thread domain partitioning is completed automatically by the hardware, without the need for operating system kernel scheduling. There is no clock overhead for saving thread switching context, which solves the technical problems of multi-threaded switching latency and resource contention jitter. After the dual thread domains are ready to run in parallel, the processor enters the main process of cyclic scheduling. The first thread domain continuously executes MPPT closed-loop control, while the second thread domain remains in sleep mode waiting for trigger signals, ensuring that power control takes priority and arc detection wakes up on demand.

[0036] If the first thread domain continuously runs a complete MPPT single cycle relying on high-priority Mark instructions, the fixed timing of the single cycle is as follows: read the photovoltaic DC bus voltage and the low-frequency average value of the initial sampled data in L1 storage to obtain the current real-time photovoltaic output power; execute the conductance incremental MPPT algorithm VPU vector parallel operation to quickly calculate the optimal output voltage operating point. The entire operation process exclusively uses the dedicated VPU vector unit of the first thread domain and is not affected by any task in the second thread domain; write the optimal operating point parameters into the on-chip PWM generation module register, adjust the inverter's dynamic switching duty cycle and switching period, and adjust the photovoltaic output power in real time to ensure that the module always operates at the maximum power point; synchronously update the switching frequency tracking parameters of the adaptive notch filter hardware. The inverter switching frequency changes in real time with the MPPT adjustment, and the notch filter hardware synchronously updates the filter core; after all MPPT operations, PWM output, and filter parameter updates are completed in a single cycle, the kernel hardware DMA controller automatically generates a hardware trigger pulse signal. The pulse level is latched into the cross-thread hardware mailbox register as a wake-up enable flag for the second thread domain. The pulse duration is a preset number of system clock cycles to ensure that the instruction decoding unit of the second thread domain stably captures the trigger signal.

[0037] Arc detection is only initiated after each complete power control closed loop is completed, avoiding false alarms caused by dynamic PWM adjustment of the inverter and severe fluctuations in bus current. Through hardware-triggered timing binding, arc identification is performed only at the end of a single cycle with stable power, significantly reducing the probability of false alarms from a timing perspective. Simultaneously, the MPPT operation exclusively uses high-priority hardware resources throughout, ensuring no power tracking delay regardless of the computational power of the arc detection task, balancing power generation efficiency and detection accuracy. The second-thread domain instruction decoding unit continuously polls the trigger pulse flag in the hardware mailbox. Upon capturing the hardware trigger signal output from the first-thread domain, it automatically de-gated the clock, allocates dedicated VPU and DMA computing resources, reads the complete initial sampling data from the previous cycle (adaptive notch filtering) from the phase-shifted clock-driven L1 shared memory, and initiates arc identification. First, multi-dimensional arc features are extracted and fed into the Tiny-CNN model for binary classification inference. After inference, the arc identification result is written to the dedicated status register of the hardware mailbox, simultaneously releasing the second-thread domain clock resources and re-entering sleep mode to await the next trigger pulse. Before the first thread domain starts the next round of MPPT calculation, it first reads the arc identification result stored in the hardware mailbox. If the identification result is normal operation, the first thread domain directly executes the new cycle of MPPT power calculation, outputs the PWM drive signal normally, and the photovoltaic continues to generate full power without any shutdown action. If the identification result is an arc alarm, the first thread domain stops the MPPT parameter iteration calculation and directly writes to the SoC's built-in PWM emergency block register through the hardware bus. After the register is set, the hardware logic instantly cuts off all inverter power switch drive signals, the DC bus has no power input, the arc loses its sustaining current and quickly extinguishes, and the physical disconnection of the photovoltaic DC circuit is completed in milliseconds without the need for software to issue shutdown commands in layers.

[0038] Therefore, hardware adaptive notch filtering cancels out inverter dynamic switching interference in real time, and MPPT timing binding avoids detection during current fluctuation periods, jointly eliminating mainstream interference sources, reducing the false arc alarm rate, significantly reducing the inverter's unexplained downtime, increasing the annual power generation of distributed photovoltaics, and directly improving the economic benefits of the power station. The controllable dynamic multi-threaded hardware resource isolation architecture ensures that high-priority MPPT operations are not preempted by AI inference computing power, maximum power point tracking has no delay, and photovoltaic power generation efficiency is not affected by arc detection tasks; simultaneously, arc detection is executed synchronously on demand, eliminating serial waiting time and balancing the dual needs of real-time power generation control and high-frequency arc monitoring. After an arc alarm, the hardware directly connects to the PWM blocking register, and the circuit breaker response is far below the national standard's 100ms mandatory time limit, preventing the DC arc from continuing to burn and avoiding the risk of fire in photovoltaic junction boxes and cables. Sampling filtering, thread scheduling, trigger signal generation, and hardware circuit breaker can all be implemented using on-chip hardware peripherals; the MCU core software is only responsible for basic parameter configuration, reducing the computational load and overall SoC power consumption, adapting to the low-power design requirements of small residential photovoltaic inverters, and extending equipment lifespan. Hardware-triggered power control and arc detection timing are bound together. Storage, computation, and clock are all hardware isolated, eliminating issues such as thread preemption, data tampering, and timing errors. Under complex outdoor conditions such as high and low temperatures and strong electromagnetic fields, the inverter operates continuously and stably without crashes or malfunctions, significantly reducing equipment maintenance costs.

[0039] Furthermore, the process of dividing the hardware threads of a multi-threaded processor into mutually isolated first thread domains and second thread domains is specifically implemented in this embodiment as follows: The controllable dynamic multithreaded architecture based on the multithreaded processor adds a mark to each instruction, wherein the mark contains the thread domain identifier to which the corresponding instruction belongs and the execution priority; based on the thread domain identifier carried by the mark, MPPT control instructions belonging to the first thread domain and arc detection instructions belonging to the second thread domain are distinguished, and the processor hardware computing resources are dynamically allocated in combination with the execution priority recorded in the mark.

[0040] Furthermore, the MPPT control instructions include MPPT operation instructions, and the arc detection instructions include arc feature extraction instructions and Tiny-CNN inference instructions. The execution priority of the marks corresponding to the MPPT control instructions is uniformly configured as high priority, and the execution priority of the marks corresponding to the arc detection instructions is uniformly configured as low priority. During the instruction issuance phase, the processor hardware prioritizes scheduling the MPPT control instructions to occupy the computational units based on the difference in execution priority of the marks.

[0041] Furthermore, when the first thread domain generates a high-priority MPPT emergency calculation request, the arc-related calculation process currently being executed by the second thread domain is paused, and the intermediate calculation data of the process is saved. During the pause, no computing resources are allocated to the second thread domain, and read and write operations of the second thread domain to the storage area are blocked. Only the first thread domain is allowed to read and write to the storage area to execute MPPT calculations. Until the first thread domain completes all the aforementioned MPPT emergency calculations, the resource and storage access restrictions on the second thread domain are lifted, and the second thread domain retrieves the pre-saved intermediate calculation data and continues to execute the paused arc-related calculation process.

[0042] The controllable dynamic multithreaded architecture includes a VLIW (Very Long Instruction) pipeline, supporting multiple independent hardware threads. Hardware resources are dynamically scheduled based on instruction-attached Mark markers. The Mark is a 64-bit header identifier field embedded in each VLIW instruction, containing a thread domain ID distinguishing the first and second thread domains, as well as a priority level. This is automatically embedded during compiler compilation and parsed in real-time during hardware fetch and decode stages, eliminating the need for software-configured thread priorities. The thread domain identifier is the thread domain ID field within the Mark. After hardware decoding, the instruction is automatically assigned and allocated corresponding pipeline and register resources. The execution priority is the priority level field within the Mark, divided into high and low priorities. The processor's fetch unit prioritizes high-priority instructions to occupy ALU and VPU computing hardware, while low-priority instructions are only allocated resources when no high-priority instructions are available. During dynamic hardware resource allocation, the processor's I-Cache fetch unit cyclically scans all valid instructions, parsing the Mark marker ID and priority of each instruction, and dynamically allocates computing pipelines, vector units, and memory access buses. High-priority MPPT instructions always have priority in obtaining hardware usage rights.

[0043] Furthermore, the MPPT operation instructions are a set of VLIW instructions specific to the first thread domain, covering arithmetic and vector operation instructions such as photovoltaic voltage and current sampling and reading, conductance increment / disturbance observation power iteration, PWM duty cycle calculation, adaptive notch parameter update, and bus closed-loop regulation. These instructions directly determine the real-time photovoltaic power generation efficiency and are key hard real-time instructions of the system. The arc feature extraction instructions are vector operation instructions specific to the second thread domain, relying on the VPU to calculate abrupt entropy, temporal kurtosis, and wideband energy flatness in parallel. They include FFT hardware acceleration instructions and sliding window statistical instructions, consuming a large amount of computing power but with relaxed real-time requirements. The Tiny-CNN inference instructions are convolution, pooling, and fully connected vector multiplication and addition instructions in the second thread domain, accompanied by weight DMA read and write operations, batch vector... The computation takes a few milliseconds per round of inference, with no hard deadline at the millisecond level. High priority indicates that the instruction has hardware preemption rights. Low priority indicates that the instruction can only be issued and executed when the high priority instruction queue is empty, and has no hardware preemption rights. The instruction issuance stage is the second stage of a controllable dynamic multi-threaded pipeline, corresponding to the hardware arbitration stage after instruction fetching and before arithmetic unit allocation. Each system clock cycle scans the Mark priority of all instructions to be issued to complete the hardware resource allocation decision. The priority scheduling mechanism corresponds to the fixed priority judgment logic built into the hardware arbitration unit. When high and low priority valid instructions exist in the same cycle, the low priority instruction's issuance opportunity in this round is directly discarded, and the high priority MPPT instruction is allocated to the ALU / VPU first. The low priority instruction is cached in the thread queue to wait for the next cycle.

[0044] Furthermore, the MPPT emergency computation requirement characterization involves high-priority forced computations triggered by dynamic disturbances in the photovoltaic system, including iterative power changes due to sudden irradiance fluctuations, bus overvoltage / overcurrent closed-loop protection, grid harmonic suppression, and inverter switching frequency dynamic correction. These are hardware control tasks that must be executed without delay. The arc-related computation process corresponds to a continuous pipeline in the second thread domain, including sampling feature extraction and Tiny-CNN multi-layer convolution / pooling inference. During operation, it generates temporary intermediate computation data such as multi-dimensional features, intermediate convolution feature maps, and weight caches. The intermediate computation data consists of unfinished temporary computation data generated by the VPU and DMA when the arc computation is paused, including sliding window sampling caches, three-dimensional feature vectors, intermediate feature matrices of each CNN layer, and ununpacked weight bitstreams, stored in the second thread domain. The second thread domain has a dedicated isolated cache. During the process of blocking computational resource allocation, a hardware-gated clock mechanism is used to pause the system clock of the second thread domain's ALU, VPU, DMA, and vector register group. The hardware unit stops powering on and no longer consumes computing power or power. During the process of blocking memory access, a hardware address filter locks the second thread domain's memory read / write bus, prohibiting read / write instructions from the L1 sampling cache and inference weight cache, thus preventing MPPT operations from modifying stored data and causing arc calculation errors. After the MPPT emergency operation ends, the hardware releases the clock and memory gating, and the second thread domain directly reads the intermediate data that was completely saved before the power failure and continues the operation from the paused pipeline level. There is no need to reread the original sampled data, repeat the feature calculation, or consume computing power repeatedly.

[0045] Because the high-computational task of arc detection inference continuously occupies hardware, the MPPT real-time control thread is frequently blocked, causing photovoltaic output power to fluctuate, grid harmonics to exceed the standard, and inverter protection shutdown. Relying on software to mark task ownership, when the program runs away or the stack overflows, the instructions of the two types of tasks are confused. MPPT parameters are tampered with by the arc detection program, or the sampled data is overwritten by power calculation, resulting in system data disorder and loss of control. In addition, a single thread is fixedly allocated for each clock cycle in a fixed time-sharing manner. If low-priority AI tasks have no effective instructions, the hardware computing unit is idle, resulting in wasted computing power. At the same time, high-priority MPPT tasks cannot preempt hardware in time, resulting in poor real-time performance.

[0046] Based on this, during the compilation of the photovoltaic inverter firmware, a dedicated compiler automatically identifies two types of functional subroutines and embeds corresponding Mark fields for each VLIW (Very Long Instruction) instruction. The first type of functional subroutines are MPPT control subroutines, which include all related instructions such as bus voltage / current sampling, power calculation, PWM output, and adaptive notch filter parameter update. The compiler automatically assigns Mark values ​​to these instructions, corresponding to the first thread domain and high level. The second type of functional subroutines are arc detection subroutines, which include all instructions such as sampling feature extraction, Tiny-CNN weight DMA read / write, AI inference, and feature vector calculation. Mark values ​​are assigned to these subroutines, corresponding to the second thread domain and low level. Each 64-bit VLIW instruction has a dedicated Mark bit segment in its header, independent of the opcode. It does not occupy the encoding space of arithmetic or vector instructions. A single instruction can carry up to three sub-operations simultaneously, namely branch, integer, and vector instructions. Each sub-instruction shares the same Mark tag, ensuring that all instruction threads and priorities within the same task are consistent. After compilation, the firmware is burned to the on-chip I-Cache instruction cache of the SoC. When the processor powers on and fetches instructions, it reads the opcode and Mark tag simultaneously. The Mark information flows with the instruction throughout the entire pipeline of instruction fetching, decoding, and execution. Each level of hardware unit can read it in real time without the need for additional storage to record task attributes, avoiding defects such as software tag loss or corruption.

[0047] After the processor powers on, the instruction fetch unit circularly traverses all valid instructions in the I-Cache, fetching a set of VLIW instructions each system clock cycle. Simultaneously, it removes the Mark flag from the instruction header, separates the thread domain ID field and the priority field, and performs two parallel hardware checks. The first check distinguishes instruction affiliation based on the thread domain ID and pre-distributes instructions to the corresponding thread domain instruction queue. For example, ID=0 is sent to the first thread domain's high-priority instruction queue, and ID=1 is sent to the second thread domain's low-priority instruction queue. The two instruction queues are physically isolated and have completely independent storage addresses, preventing instruction mixing. The second check extracts the Mark priority level, marking the scheduling weight of each instruction. The hardware arbitration unit permanently follows the rule of issuing high-priority instructions first. If a valid MPPT instruction exists in the high-priority queue in the current clock cycle, the low-priority arc detection instruction is skipped, and the computation pipeline is allocated preferentially. Only when the high-priority queue is empty and there are no MPPT instructions to be executed is the second thread domain arc detection instruction scheduled to occupy hardware resources. The instruction fetch unit synchronously parses the Mark every cycle, and can complete the mark recognition and instruction queueing in a single cycle. The parsing delay is only one clock cycle, and there is no operating system scheduling time. At the same time, the Mark is permanently bound to the instruction. When the program crashes or the stack overflows, the illegal instruction Mark remains unchanged, and the hardware can still identify the thread ownership, so there will be no confusion between the two types of task resources.

[0048] After the instruction is read, it is sent to the hardware decoding circuit. The decoding unit reads the Mark again and dynamically allocates the entire set of processor hardware resources in combination with the ID and priority to achieve physical isolation of the thread domain. The resource allocation includes arithmetic unit allocation, register file allocation, memory bus allocation, DMA channel allocation, and pipeline allocation.

[0049] Specifically, the arithmetic unit allocation is as follows: the high-priority first thread domain instruction exclusively uses the main ALU arithmetic unit and the high-frequency main VPU vector unit to meet the real-time multiplication and addition and vector power calculation of MPPT; the low-priority second thread domain is only allocated to the spare VPU vector unit, so that AI inference does not preempt the main arithmetic hardware and the computing power of MPPT power calculation is not squeezed throughout the process; if the high-priority instruction is suddenly interrupted, the decoding unit immediately cuts off the clock gating of the spare VPU in the second thread domain, and completely releases the vector computing power to MPPT. The register file allocation is as follows: independent general-purpose register groups are allocated according to the Mark thread ID. For example, ID=0 accesses the MPPT-dedicated register file to store voltage, current, and PWM duty cycle parameters; ID=1 accesses the arc detection-dedicated register file to store sampled waveforms, 3D features, and CNN weight cache. Hardware address filters intercept cross-register read and write operations to prevent mutual tampering of parameters. The storage bus allocation is as follows: the Mark marks distinguish storage access permissions. The first thread domain can read and write the power parameter storage partition and the adaptive notch configuration partition; the second thread domain can only read the sampled shared storage and read and write the inference weight cache partition, and cannot modify MPPT control parameters. Hardware blocks illegal cross-partition write operations, and data is physically isolated. DMA channel allocation is as follows: high-priority MPPT tasks are allocated dedicated DMA for ADC sampling and PWM output; low-priority arc tasks are only allocated weighted preload DMA. The two types of DMA buses are physically separated, and batch read / write of weights will not interfere with current and voltage sampling data transmission. Pipeline allocation is as follows: the processor's multi-stage execution pipeline is segmented according to Mark priority. High-priority instructions enter the preceding high-speed pipeline first, and low-priority instructions fill the idle subsequent pipelines. When a high-priority instruction arrives, it can directly preempt the pipeline without waiting for the low-priority task to complete.

[0050] Furthermore, during the firmware compilation phase, the compiler automatically and uniformly configures Mark priorities for both types of instructions in batches. First, it performs lexical and syntax scanning to identify all MPPT control function code, including code segments such as bus ADC sampling and reading, power difference iterative calculation, PWM cycle / duty cycle refresh, inverter switching frequency tracking, adaptive notch filter parameter refresh, and overvoltage / overcurrent closed-loop protection calculations. For each VLIW instruction generated from this code segment, the thread field and priority field are uniformly filled with Mark markers. All MPPT-related operation instructions and hardware configuration instructions are uniformly marked with high priority, with no exceptions, ensuring that power control-related operations always have the highest scheduling authority. Simultaneously, the compiler identifies arc detection-specific code segments, including code for sampling data sliding window buffering, mutation entropy / kurtosis / energy flatness vector statistics, FFT frequency domain decomposition, Tiny-CNN convolution multiplication and addition, weight DMA read / write, and feature vector buffer read / write. For all instructions generated from this type of code, the thread field and priority are uniformly filled with Mark markers. All AI feature extraction and neural network inference instructions are uniformly marked with low priority, with no priority skipping. After compilation, the Mark field of all instructions is automatically traversed globally. If any MPPT instruction with low priority or an arc instruction with high priority is detected, a compilation error is thrown directly, firmware generation is terminated, and developers are forced to correct the code logic. Priority configuration errors are intercepted during the compilation stage to prevent field failures caused by incorrect firmware being flashed to the device. The compiled 64-bit VLIW instructions with uniformly graded Marks are stored in the I-Cache instruction cache. The cache is divided into two independent storage areas according to the thread domain: all high-priority MPPT instructions are stored in the high-priority instruction bank, and low-priority arc instructions are stored in the low-priority bank. The hardware instruction fetch unit can read these instructions in blocks for fast access, reducing instruction retrieval cycles.

[0051] For the hardware arbitration priority determination logic in the processor instruction issue phase, after the processor pipeline completes instruction fetching and decoding, it enters the instruction issue arbitration phase. This phase is purely hardware logic with no software involvement. A complete priority determination is performed once every 600MHz system clock cycle. The determination process is standardized, fixed, and cannot be modified. The hardware arbitration unit has a built-in dual instruction queue buffer, namely a high-priority MPPT queue and a low-priority arc queue. During the complete determination, the hardware synchronously reads the valid flag bits of both instruction queues and performs scheduling under three working conditions. In the first working condition, there are valid instructions waiting to be issued in the high-priority MPPT instruction queue. The hardware arbitration unit directly blocks the issuance permission of all low-priority arc instructions in this cycle, cuts off the clock allocation path of the second thread domain VPU and ALU arithmetic units, and only allocates computing resources, buses, and registers to high-priority MPPT instructions. Low-priority arc instructions are retained in the low-priority queue. The processor caches the low-priority thread and waits for the next clock cycle to re-evaluate the priority. Even if the low-priority thread is currently executing multi-layer CNN convolution vector operations, as long as the high-priority queue has MPPT instructions to be executed, the hardware immediately gates and freezes the low-priority operation pipeline, prioritizing power control requirements and completely solving the priority inversion problem of traditional RTOS. The second scenario is when the high-priority MPPT instruction queue is empty and the low-priority arc queue has valid instructions. The arbitration unit releases the spare VPU and DMA hardware resources to the second thread domain, allowing arc feature extraction and CNN inference instructions to be issued and executed. This fully utilizes the idle hardware computing power of MPPT without computational tasks, without wasting processor hardware resources and improving chip utilization. The third scenario is when neither the high-priority nor the low-priority queue has valid instructions. The processor enters a global low-power clock gating mode, shutting down all arithmetic unit and memory bus clocks to reduce overall power consumption until a valid instruction is generated in any queue to wake up the hardware.

[0052] The system supports concurrent multi-instruction issuance. VLIW issues a maximum of three sub-instructions per cycle. If multiple MPPT instructions exist in the high-priority queue within the same cycle, the arbitration unit prioritizes and issues all MPPT sub-instructions in parallel, occupying all computational pathways. Only after all high-priority instructions have been issued and the queue is cleared will a portion of the spare computational pathways be allocated to low-priority arc instructions. For example, if MPPT power calculation instructions and arc entropy calculation instructions exist simultaneously in a single cycle, the hardware directly allocates the main 256-bit VPU to MPPT, while arc entropy calculation only allocates idle small vector auxiliary units, tilting computational resources towards power control. For interrupt-linked enhanced scheduling, when photovoltaic grid disturbances or sudden changes in illumination trigger an emergency closed-loop interrupt of MPPT, the interrupt hardware signal directly raises the high-priority queue's Valid flag. Regardless of the low-priority thread's inference stage, the arbitration unit immediately switches hardware resources to MPPT, with an interrupt response delay of only 2-5 system clock cycles, ensuring rapid stabilization of the photovoltaic bus voltage.

[0053] For the entire process of time-sharing linkage of high and low priority instructions, in normal steady-state conditions (i.e., stable illumination and long MPPT iteration cycles), the high-priority MPPT queue only generates one set of power calculation instructions every 100 clock cycles, while the queue is empty in the remaining cycles. The hardware arbitration unit continuously allocates spare VPUs to the second thread domain to fully execute sampling feature extraction, Tiny-CNN multi-layer inference, and after completing arc identification, it sleeps and waits for the next round of MPPT trigger signal, making full use of idle computing power to continuously monitor bus arc noise and ensure continuous safety monitoring. In dynamic conditions (i.e., cloud cover, sudden changes in illumination, and drastic fluctuations in photovoltaic output power), the MPPT iterates at high frequency, and the high-priority queue is continuously filled with valid high-priority instructions. In each clock cycle, the hardware prioritizes MPPT operations, and the arc detection CNN inference pipeline is continuously gated and paused, only buffering intermediate feature data to prevent loss, until the illumination stabilizes, the MPPT iteration frequency decreases, and the high-priority queue is cleared. Then, the hardware resumes the second thread domain computing power allocation, retrieves the buffered sampling data, and continues to complete arc detection without losing a single frame of bus sampling waveform, eliminating the risk of missed detections. For fault conditions, such as inverter overcurrent or grid harmonic impact, the hardware triggers MPPT protection operation instructions, the high-priority queue remains at full load, the low-priority arc detection task is paused for a long time, and all processor computing power is devoted to photovoltaic closed-loop protection to prioritize the grid connection safety of the equipment. After the fault is cleared, the arc detection process is automatically restored.

[0054] Finally, if there is a high-priority MPPT emergency calculation requirement, and the photovoltaic system experiences dynamic disturbances due to cloud cover, grid distortion, sudden changes in component temperature, overcurrent alarms, etc., the MPPT hardware sampling module detects that the bus voltage / current deviates from the optimal operating range and immediately sends a hardware emergency interrupt pulse to the processor instruction arbitration unit. The pulse directly pulls up the high-priority instruction queue Valid flag and generates a second thread domain pause latch signal. This signal does not require software response and the hardware takes effect directly. Upon receiving the pause latch signal, the hardware arbitration unit simultaneously executes two parallel hardware operations. The first hardware operation involves sending clock gating shutdown instructions to all arithmetic units in the second thread domain, namely VPU, ALU, and multi-channel DMA, cutting off the system clock supply to all arithmetic hardware. Vector operations and weight transfers immediately cease, and the instantaneous values ​​of all hardware registers remain latched unchanged, preventing the loss of temporary arithmetic values ​​due to clock interruptions. The second hardware operation involves activating the on-chip hardware address filter and writing a storage access blocking mask to the second thread domain. The mask locks the read / write bus channels of the arc task's dedicated sampling buffer, weight buffer, and feature buffer. At this point, any read or write storage instructions in the second thread domain will be intercepted and discarded by the hardware filter, preventing modification or reading of any on-chip storage data. This completely isolates the storage resources of MPPT operations and arc operations, preventing data from being overwritten or tampered with.

[0055] One system clock cycle before clock gating is disabled and the memory bus is blocked, the processor's built-in dedicated field-saving DMA automatically starts, batch-transferring all intermediate computation data from the second thread domain to a dedicated isolated power-off buffer. This buffer is an independent SRAM partition, accessible only during arc task pauses / resumptions. The first thread domain of MPPT has no access rights to this buffer. Data storage includes intermediate time-domain sampling data, intermediate feature data, and intermediate CNN inference data. The intermediate time-domain sampling data includes the original waveforms of the 2048-point bus current before the sliding window statistics are completed, and the temporarily calculated window segment entropy values. The intermediate feature data includes the calculated abrupt entropy, time-domain kurtosis, broadband energy flatness temporary variables, and incompletely concatenated feature vectors. The intermediate CNN inference data includes the output feature maps of each convolutional layer, the partially unpacked bitstream preloaded by the weight DMA, the temporary operation matrix of the pooling layer, and the incomplete multiplication and addition values ​​in the VPU vector register. After data is stored in the isolated buffer, a hardware valid verification flag is added. During computation recovery, the hardware automatically verifies data integrity to prevent data corruption due to storage interference.

[0056] After the second thread's resources and storage are completely blocked, the processor arbitration unit allocates all computing hardware, including the main VPU, ALU, ADCDMA, PWM register bus, and L1 main memory partition, to the first thread domain without any resource contention. It then executes the MPPT emergency closed-loop operation at full speed. This operation includes: high-speed reading of isolated bus voltage and current sampling data; VPU parallel calculation of multi-channel power difference; rapid iteration of the optimal maximum power operating point; real-time correction of PWM duty cycle and inverter switching frequency; synchronous update of the adaptive notch filter core to match the new switching frequency and continuously filter out interference; and triggering overvoltage / overcurrent hardware protection logic to adjust the DC bus output amplitude and stabilize the photovoltaic power within a safe range. Throughout the emergency operation, no arc tasks preempt hardware. All computing power is invested in the power closed loop in a single cycle, and the bus adjustment delay is controlled at the level of hundreds of nanoseconds. In the face of sudden changes in light, voltage fluctuations can be quickly suppressed to avoid inverter protection shutdown. The MPPT emergency operation has multiple rounds of iterative cycles. As long as all closed-loop adjustments are not completed, the clock gating and storage blocking mask of the second thread domain remain effective, and the arc tasks are always in a paused and locked state.

[0057] Once the first thread domain completes all power iterations and the bus voltage and current return to a stable and safe range, the MPPT hardware module sends a completion release pulse to the arbitration unit. The hardware then sequentially releases the restrictions on the second thread domain in a step-by-step manner, ensuring orderly timing and preventing data corruption. Specifically, the first step clears the storage blocking mask of the hardware address filter and reopens the read / write bus of the second thread domain's dedicated cache, allowing the arc task to access the sampling and weight storage areas. The second step removes the clock gating of the VPU, DMA, and ALU, restoring the system clock supply to all computational hardware in the second thread domain, and the hardware unit re-enters the computational state. The third step activates the on-site recovery DMA, batch-reading all previously saved intermediate arc computation data from the independent isolated power-off cache and backfilling it into the VPU vector register, feature cache, and weight DMA buffer as is. The hardware automatically verifies the data verification flag, and after confirming that the data is neither lost nor tampered with, sets the arc thread ready flag.

[0058] After the hardware backfills the intermediate data, the second-thread instruction pipeline directly resumes the arc operation from the paused / interrupted level. If paused at the feature extraction stage, it directly reads the cached sliding window temporary entropy value and incomplete waveform data to continue calculating the 3D feature vector without rereading the entire frame of ADC sampling data. If paused at the Tiny-CNN inference convolutional layer, it directly loads the cached previous layer's convolutional feature map and semi-unpacked weight bitstream, continuing multiply-accumulate operations from the current convolutional layer, skipping previously completed network layers and saving multiple layers of redundant calculations. After resuming the operation, the arc recognition result is generated and written to the cross-thread hardware mailbox for the next MPPT cycle to read, eliminating the risk of missed detections or misjudgments. This significantly reduces the computational overhead of repeated sampling, repeated feature extraction, and repeated CNN inference under frequent lighting disturbances, resulting in a decrease in the processor's average load and a significant reduction in chip power consumption.

[0059] Furthermore, the multi-threaded processor is configured with a multi-level pipelined parallel execution architecture, and maps the MPPT power calculation task belonging to the first thread domain and the arc identification task belonging to the second thread domain to two mutually isolated pipeline execution stages within the multi-level pipelined parallel execution architecture.

[0060] Furthermore, the two sets of pipeline execution stages are equipped with independent computing paths and dedicated computing storage spaces; each computing path can only perform read and write operations on its own dedicated computing storage space, and the computing processes of the first thread domain and the second thread domain are completed in their respective pipeline execution stages.

[0061] The multi-stage pipelined parallel execution architecture refers to the pipeline being divided into multiple independent hardware execution stages, supporting physical partitioning and parallelism of multi-threaded tasks. Each pipeline execution stage is a complete segmented hardware unit for pipelined computation, including a dedicated ALU, VPU, register pathway, and memory access bus. Each execution stage is completely independent, with separate power supply and clock control. The first isolated pipeline execution stage is allocated to all MPPT computation instructions for the first thread domain, with a dedicated high-speed arithmetic operation pathway, high-frequency memory access bus, and high-priority hardware resources. The second isolated pipeline execution stage is allocated to arc feature and CNN inference instructions for the second thread domain, with a dedicated backup vector operation pathway and low-priority resources, which are only fully activated when the high-priority pipeline is idle. The task mapping process is as follows: during compilation, the compiler automatically distributes and binds the two types of instructions to the corresponding pipeline execution stages through Mark markers. The hardware instruction fetching stage is automatically split, and the two types of tasks will not enter the same pipeline hardware path.

[0062] Furthermore, each pipeline's EX computing stage has its own dedicated hardware computing link, including an independent ALU arithmetic unit, a 256-bit VPU vector unit, and multiple DMA data transfer channels. The hardware circuitry is completely separate, with no shared computing resources. Dedicated computing storage space is provided for each pipeline, with an independent on-chip SRAM cache partition. The MPPT pipeline's dedicated storage stores voltage, current, and PWM parameters, while the arc pipeline's dedicated storage stores sampled waveforms, 3D features, and CNN weights. The address spaces are physically isolated. Hardware address filters bind the computing path to the corresponding storage partition. The first pipeline can only read and write to the MPPT dedicated storage, and the second pipeline can only read and write to the arc dedicated storage. Cross-partition read / write instructions are directly intercepted and discarded by the hardware, ensuring hardware-forced isolation. All MPPT sampling, power iteration, and PWM output are completed in the first pipeline path and its associated storage; arc sampling, feature extraction, and CNN inference are completed in the second pipeline path and its associated storage. The two types of computing processes are physically closed loops without overlap.

[0063] Based on this, such as Figure 2The schematic diagram of the thread domain partitioning and memory space isolation hardware architecture of a photovoltaic DC arc defense method based on a multi-threaded processor is provided. The processor's multi-stage VLIW pipeline physically partitions the EX operation level and MEM memory access level, dividing them into two completely independent pipeline execution hardware paths. The two paths share the first two pipeline stages: IF instruction fetch and ID decoding. Hardware isolation begins from the DIS transmitter level. Specifically, the first MPPT-dedicated pipeline execution stage has an independent main VPU, a high-performance ALU, a high-speed L1 memory access bus, and a dedicated general-purpose register file. It runs at full clock speed, and all MPPT power calculation, PWM control, and notch filter parameter update instructions can only be assigned to this stage. The second arc-dedicated pipeline execution stage has an independent backup small VPU, an auxiliary ALU, a weighted DMA memory access bus, and an independent vector cache register. Its clock can be dynamically gated and reduced. Arc feature extraction and Tiny-CNN convolution inference instructions can only be assigned to this stage. The two execution stages are completely independent in terms of power supply, clock, bus, and registers, with no hardware resource sharing. One set of pipelined operations will not occupy any hardware path of the other set, physically eliminating task computational power contention and data overwriting. The first two stages of the pipeline have built-in Mark-based flow distribution units in the IF / ID shared modules. After decoding, the flow is automatically distributed to the corresponding execution stage based on the thread ID. The flow distribution hardware completes in a single cycle with no delay.

[0064] When generating VLIW instructions, the compiler writes a pipeline mapping identifier based on the Mark thread ID of the MPPT / arc instruction. During the hardware decoding stage, the instructions are automatically routed according to the identifier. For example, if MarkID=0, it corresponds to the MPPT high-priority instruction, and the first pipeline mapping identifier is appended. After the ID is decoded, it is directly sent to the MPPT-dedicated execution level DIS emitter unit. If MarkID=1, it corresponds to the arc low-priority instruction, and the second pipeline mapping identifier is appended. After the ID is decoded, it is routed to the arc-dedicated execution level DIS emitter unit. The compiler performs global verification to prevent cross-pipeline mapping instructions. If a mapping conflict occurs, a compilation error is directly reported to avoid two types of tasks entering the same pipeline path and to prevent hardware resources from being mixed.

[0065] During steady-state operation, the entire pipeline operates synchronously and in parallel. The complete timing chain includes the IF fetch stage, ID decode stage, DIS issue stage, EX operation stage, MEM memory access stage, and WB write-back stage. Specifically, the IF fetch stage reads all VLIW instructions from the I-Cache and sends them to the ID decode stage. The ID decode stage synchronously parses the Mark flag of each instruction, and the hardware splitting unit outputs instructions in two paths. The first path, A, corresponds to MPPT instructions and is sent to the first high-priority pipeline DIS issue stage, which prioritizes 600MHz full-speed computing hardware. The second path corresponds to arc instructions and is sent to the second low-priority pipeline DIS issue stage. The full clock power is only released when the first pipeline has no instructions to execute. The DIS issue stage arbitrates the two pipelines independently. One pipeline group permanently prioritizes high-priority MPPT instructions, while the second group only processes the offloaded arc instructions. The EX arithmetic stage synchronously processes the two pipelines' independent VPUs / ALUs, iterating power parameters at full speed during MPPT, and performing parallel calculations of arc features and convolutions, with no hardware interference. The MEM memory access stage stores MPPT path access power parameters in a bank, and arc path access sampling and weights in a bank, with physical bus isolation ensuring read and write operations do not block each other. The WB write-back stage writes the calculation results to the independent register files of the two pipelines, storing MPPT parameters and arc features separately to avoid overwriting each other. Under stable illumination conditions, the first pipeline operates at low load with sufficient idle computing power, while the second arc pipeline continuously executes bus arc monitoring at full speed. Under sudden cloud cover changes, the first pipeline performs emergency MPPT adjustment at full load, while the second pipeline uses clock gating to reduce its frequency and pause inference. The two pipelines are completely independently scheduled without mutual blocking.

[0066] Furthermore, independent clock gating, register physical isolation, memory access bus isolation, and interrupt preemption adaptation are implemented. Specifically, independent clock gating means that the two pipeline execution stages have independent clock switches, with the MPPT pipeline permanently operating at full speed of 600MHz; the arc pipeline can reduce its frequency or stop clocking as needed, reducing power consumption during idle periods; register physical isolation means that the two pipelines are equipped with completely independent general-purpose registers and vector registers, MPPT operation results are not written to the arc cache, and intermediate arc values ​​cannot overwrite power control parameters; memory access bus isolation means that the MEM memory access paths of the two pipelines are respectively connected to dedicated storage banks, and address filters block cross-bank access, ensuring complete isolation of data read and write; interrupt preemption adaptation means that MPPT emergency interrupts only preempt the hardware of the first pipeline group and do not interfere with the register cache of the second pipeline group, and interrupt save and restore only operate on the local registers of the first pipeline group, eliminating the need to save a large amount of intermediate data from the arc pipeline, significantly improving interrupt response speed.

[0067] For the two sets of completely independent computational pathways, each execution stage has its own complete and non-shared computational hardware pathway, with hardware resources permanently and exclusively allocated. The first MPPT pipeline computational pathway is equipped with a main VPU vector computation unit, a high-performance multi-cycle ALU, multiple dedicated ADC / PWMDMA channels, and an independent branch jump BRU unit. It is dedicated to performing voltage and current vector sampling, parallel iteration of conductance increment MPPT, batch calculation of PWM duty cycle, adaptive notch filter kernel update, and bus closed-loop protection operations. All power-related vector and arithmetic operations exclusively occupy this pathway, and no computational hardware is released to the second set. The second arc pipeline computational pathway is equipped with an auxiliary VPU unit, a lightweight AL, two weight / sampling DMA channels, and an independent feature statistics computation unit. It only performs sampling waveform sliding window calculation, parallel solution of mutation entropy / kurtosis vectors, Tiny-CNN convolution / pooling multiplication and addition, and weight bitstream unpacking and transport. AI inference-related operations only occupy this pathway and will not preempt the MPPT main vector unit. The two computing paths have physically independent hardware circuits, with completely separate power supply, clock, and input / output buses. During the same system clock cycle, the two paths can execute vector operations synchronously and in parallel. MPPT batch power iteration and arc multi-layer CNN inference run simultaneously without hardware queuing. The hardware arbitration unit permanently prohibits one set of pipeline instructions from being scheduled to another set of computing paths, eliminating computing power contention from the bottom layer.

[0068] For the two pipelines, dedicated physically isolated computational storage spaces are provided. The on-chip L1 SRAM memory is divided into two non-overlapping address segments according to the pipeline grouping. The address intervals have no overlap, and the hardware address buses are wired separately to form dedicated computational storage spaces. The MPPT dedicated storage address segment only connects to the memory access path of the first pipeline, and is subdivided into voltage and current sampling cache, MPPT power iteration cache, PWM register mirror, and adaptive notch filter coefficient cache; only the first pipeline MEM memory access stage can initiate read and write operations. The arc dedicated storage address segment only connects to the memory access path of the second pipeline, and is subdivided into 2048-point bus waveform cache, three-dimensional feature vector cache, CNN weight bitstream cache, and convolution intermediate feature map cache; only the second pipeline MEM memory access stage can initiate read and write operations. The two storage segments are physically isolated with no overlapping intervals, and the hardware address decoding circuits are separate, so data written to one storage segment will not physically overwrite the memory cells of the other storage segment. The memory phase-shifting clock circuits are configured with independent phase adjustment signals for the two storage segments to adapt to the different memory access timing requirements of the two pipelines, achieving zero-wait read and write for each storage segment.

[0069] For hardware address filters that lock the path and bind read / write permissions to storage, each pipeline MEM memory access path entry point has a built-in dedicated hardware address filter. The filter has a fixed address access whitelist, forcibly restricting the operation path to read and write only to its own dedicated storage. Read / write instructions that cross address ranges are directly intercepted and discarded by the hardware. The first pipeline address filter whitelist only includes the MPPT dedicated storage address range. If the pipeline generates a read / write address that exceeds this range, the filter directly blocks the memory access bus, invalidates the instruction, generates a hardware anomaly flag, and will not access the arc storage. The second pipeline address filter whitelist only includes the arc dedicated storage address range. Any memory access instruction pointing to MPPT storage is directly intercepted, and power control parameters cannot be modified. During the overall system cycle operation, the MPPT and arc recognition operations form independent closed loops within their respective pipeline paths and dedicated storage. Data interaction is achieved through a single compliant channel via a cross-thread hardware mailbox, which only transmits the final arc recognition result and does not transmit intermediate sampling or power data. Specifically, the first pipeline ADCDMA reads the bus voltage and current from the MPPT dedicated sampling buffer; the main VPU path executes MPPT power iteration calculations in parallel, storing intermediate power variables in the MPPT dedicated iteration buffer; after the calculation is completed, the PWM buffer and notch filter coefficient buffer are updated; at the end of the single-cycle closed loop, a hardware trigger pulse is generated and stored in the cross-thread hardware mailbox; upon receiving the hardware trigger pulse, the second pipeline DMA reads the initial sampling data from the arc dedicated waveform buffer; the auxiliary VPU path calculates the three-dimensional feature vector in parallel and stores it in the arc feature buffer; the weight DMA preloads the binary bit stream from the arc weight buffer, and the VPU executes Tiny-CNN multi-layer inference; after inference is completed, the arc recognition result and confidence score are written to the cross-thread hardware mailbox. Both types of tasks transmit the final judgment / trigger signal only through a hardware mailbox. The intermediate calculation waveforms, characteristics, and power parameters are all enclosed in their respective pipeline's dedicated storage, eliminating the cross-use of intermediate data and completely eliminating the root cause of data tampering and computing power competition.

[0070] Therefore, MPPT and arc detection are executed synchronously in two separate isolated pipelines. AI inference will not block power regulation, there is no queuing delay when there are sudden changes in light intensity, and the accuracy of dynamic tracking of photovoltaic power generation is greatly improved. The two types of tasks are physically separated in terms of computation and storage. Intermediate data of arc detection cannot cover MPPT control parameters, the inverter output voltage is stable, and there are no harmonic oscillations or grid disconnection faults. There is no need to clear pipeline registers to switch tasks, saving dozens of cycles of context refresh time and reducing the average latency of the whole machine. When there is no need for arc detection, the second pipeline clock can be turned off separately, and the power consumption of the whole machine is significantly reduced during nighttime standby and midday stable operation. The compiler automatically distributes tasks by relying on Mark markers, and developers do not need to manually allocate pipeline resources, simplifying the development of photovoltaic inverter firmware. Furthermore, MPPT and CNN convolution can perform large-scale vector multiplication and addition simultaneously without preempting a single VPU, doubling the overall computing power utilization. The two types of tasks are completed synchronously without delay. Software code overflow and pointer out-of-bounds errors cannot cross-partition read / write, the electric arc will not tamper with power parameters, and MPPT will not overwrite the sampled waveform, significantly reducing false alarms and power oscillation faults. The data and computing hardware for the two types of tasks are completely separated, allowing for individual pipeline debugging when inverter anomalies occur, improving firmware fault troubleshooting efficiency. The two storage segments have independent phase-shifted clock phases adapted to the memory access timing of the two sets of pipelines, with no waiting period for MPPT batch parameter writing and large-scale electric arc waveform reading, further compressing the overall recognition and control latency.

[0071] Furthermore, in response to the trigger signal, the process by which the second thread domain determines the arc identification result based on the initial sampling data is specifically implemented as follows in this embodiment: In response to the trigger signal, the second thread domain extracts the feature vector of the initial sampled data to obtain a multidimensional feature vector of the arc that includes abrupt entropy, temporal kurtosis, and broadband energy flatness; through the second thread domain, the multidimensional feature vector of the arc is input into an on-chip lightweight Tiny-CNN model for arc recognition to obtain the arc recognition result, wherein the arc recognition result includes normal operation or arc alarm.

[0072] Furthermore, the lightweight Tiny-CNN used for photovoltaic arc recognition has its binarized weights pre-stored in off-chip flash memory or on-chip shared memory in a packaged bitstream format; when the second thread domain performs the current network layer inference operation through the current arc multidimensional feature vector, the weight DMA engine configured in the second thread domain asynchronously and in parallel reads and unpacks the bitstream of the next layer's binarized weights.

[0073] Among them, mutation entropy is the core fingerprint feature of the arc in the time domain, quantifying the degree of random mutation of the bus current waveform within a short time window, and is used to monitor the sudden increase in uncertainty of the current waveform in a very short time. The normal inverter switching waveform has a regular and orderly entropy value with low value, while the arc ionizes the air and produces random spikes, resulting in a sudden sharp increase in entropy value, distinguishing steady-state harmonics from instantaneous arc disturbances. Time-domain kurtosis is used to describe the sharpness of the current waveform pulses, identify the flatness of the energy distribution in a wide frequency band, and distinguish it from the steep peak value of inverter harmonics. That is, the inverter harmonics are smooth periodic waveforms with low kurtosis, while the arc produces a large number of narrow-amplitude sharp pulses with significantly increased kurtosis, identifying intermittent weak arcing signals. Wideband energy flatness is the core fingerprint in the frequency domain, capturing the sharp pulse pattern generated by the arc. The inverter switching energy is concentrated at a single fixed frequency point, and the energy distribution is steep. The arc pink noise is uniformly distributed across the entire frequency band from 10 to 100 kHz, and the energy flatness value is close to 1, distinguishing single harmonics from continuous arc noise. The multidimensional feature vector of the electric arc is formed by sequentially concatenating three dimensionless feature values: mutation entropy, temporal kurtosis, and broadband energy flatness. This concatenation serves as the sole input to Tiny-CNN, and the three-dimensional fingerprint is used for joint judgment to avoid misclassification based on a single feature. The on-chip lightweight Tiny-CNN model is a binary classification convolutional neural network optimized for embedded DSPs. After offline training, it is stored on-chip in the SoC. The network has ≤5 layers, no floating-point operations, and uses fixed-point / binarization computation throughout. It is adapted for parallel inference by VPU vector units and is specifically designed for binary classification of photovoltaic electric arcs and normal operating conditions, outputting a single-bit recognition result.

[0074] Furthermore, the binarized weights, after offline training, compress the CNN convolutional kernel weights into 0 / 1 binary values, replacing the 32-bit floating-point weights. This reduces storage capacity to 1 / 32, adapting to embedded low-storage SoCs. The VPU can quickly complete multiplication and addition operations via XOR logic, significantly reducing computational overhead. The packaged bitstream format represents the multi-layer binary weights as a continuous binary data stream, adding segment headers to identify the start and length of each layer's weights. This simplifies DMA batch read addressing logic and reduces storage address jump overhead. The weight DMA engine is a dedicated hardware direct memory access controller in the second thread domain, independent of the kernel ALU. It can read and write on-chip / off-chip storage weight data without CPU intervention, achieving fully asynchronous parallelism between inference computation and weight loading. The asynchronous parallel read / write representation means that while the VPU of the current convolutional layer performs feature inference, the DMA background synchronously reads and unpacks the weights of the next layer. The computation and data loading times overlap, masking storage read latency and eliminating weight loading wait cycles. Bit stream unpacking involves DMA's built-in hardware unpacking logic. After reading the packaged bit stream, it automatically strips the segment headers and restores the continuous binary bit stream to a standard binary weight array of the convolution kernel. No software decoding is required, resulting in zero CPU overhead.

[0075] Based on this, after being triggered and woken up, the VPU extracts the three-dimensional arc multi-dimensional feature vector in parallel. Specifically, after the second thread domain captures the hardware trigger pulse and allocates dedicated VPU vector operation resources, it reads a window-length initial sampled pure current waveform from the phase-shifted clock L1 memory in batches via the DMA channel. The waveform has been filtered to remove inverter switching interference, retaining only the 10~100kHz high-frequency current data, which is stored in the dedicated vector register file of the second thread domain without occupying any storage resources in the first thread domain. Feature extraction is all performed in parallel batches by the VPU vector unit, with the three features solved synchronously in parallel, shortening the computation time. The hardware calculations include parallel calculation of abrupt entropy, parallel calculation of time-domain kurtosis, and parallel calculation of broadband energy flatness.

[0076] Specifically, in the parallel calculation of mutation entropy, the VPU divides the sampled data into multiple sliding sub-windows. Each window simultaneously calculates the probability distribution of current amplitude and solves for the information entropy value. By comparing the entropy difference between adjacent windows, the entropy mutation amplitude of the short window is extracted as a mutation entropy feature value. The entropy difference of the normal inverter periodic waveform is stable within a very small range. When arc spikes occur, the entropy mutation amplitude increases significantly. This indicator captures instantaneous sudden arc signals, solving the problem of missed detection of intermittent weak arcing. The vector unit completes the entropy calculation of multiple windows in parallel in a single operation. In the parallel calculation of time-domain kurtosis, the VPU batch-solves the ratio of the fourth-order central moment to the variance of the sampled data and outputs the time-domain kurtosis. The inverter switching waveform is periodically smooth with a kurtosis value less than 3. Arcs generate a large number of spike pulses with a kurtosis value greater than 8. This indicator specifically identifies intermittent short arcs caused by loose photovoltaic module joints. These arcs have weak frequency domain characteristics, with only obvious time-domain pulse characteristics, making them easily missed by single-frequency domain detection. During the parallel calculation of wideband energy flatness, the VPU has built-in hardware FFT acceleration instructions to complete the fast Fourier transform of the data in parallel, decomposing the energy of all frequency points from 10kHz to 100kHz; it also calculates the full-band energy variance, and the smaller the variance, the flatter the energy distribution, and outputs the wideband energy flatness; the inverter energy is concentrated at a single switching frequency point, with a large variance and low flatness, while the arc pink noise is evenly distributed across the entire frequency band, with a very small variance and flatness close to 1.

[0077] After the three features are processed synchronously, the VPU automatically concatenates the three standardized dimensionless values ​​of mutation entropy, temporal kurtosis, and broadband energy flatness in a fixed order to generate a one-dimensional arc multi-dimensional feature vector, which is stored in the dedicated on-chip cache for inference. The vector has a fixed length of 3 dimensions and no redundant data, reducing the computational overhead of subsequent CNN input. The entire feature extraction process only occupies the hardware resources of the second thread domain, and the MPPT first thread domain operation is completely unaffected.

[0078] After the multidimensional feature vectors are generated, the second-thread domain DMA engine automatically feeds the feature vectors into the input layer of the on-chip lightweight Tiny-CNN model. This model is trained offline using massive photovoltaic field samples containing various inverter switching interferences, cloud disturbances, and real arcing samples. After training, all weights are binarized and fixed-point compressed, and then stored in the SoC's on-chip Flash memory, requiring no external DDR loading and eliminating external storage access latency. The model consists of only 4 convolutional layers and 1 fully connected layer for output, with no floating-point multiplication or addition. The inference process is executed in four parallel stages, including parallel computation of convolutional layers, hardware dimensionality reduction of pooling layers, and mapping of classification and binary classification decision units in fully connected layers.

[0079] Specifically, during the parallel computation of the convolutional layer, the VPU loads feature vectors and binary convolutional kernels, completing 16 sets of 16-bit parallel multiply-accumulate operations in a single cycle. This batch extracts deep-seated correlation features within the feature vectors, fusing the coupling relationship between time-domain and frequency-domain three-dimensional indicators to avoid errors caused by single features. For example, under certain special conditions where only abrupt entropy increases and kurtosis remains normal, a single threshold might lead to false alarms. The CNN, by fusing three-dimensional features, can accurately distinguish between interference and genuine electric arcs. During the hardware dimensionality reduction process of the pooling layer, the built-in hardware max-pooling unit compresses the convolutional output features, reducing computational load without losing core electric arc discrimination information, balancing inference speed and recognition accuracy. During the mapping and classification process of the fully connected layer, the pooled fused features are mapped to the binary output space, outputting matching probability values ​​for the two types of conditions. The binary classification unit directly compares the probabilities of normal and electric arc conditions using a hardware comparator, outputting a unique electric arc identification result identifier, including either normal operation or electric arc alarm. The determination result is latched into a cross-thread hardware mailbox register for the first thread domain to read and execute protection actions. The entire inference process is exclusively handled by the second thread domain using the VPU and DMA hardware. If the first thread domain generates a high-priority MPPT interrupt during inference, the hardware-gated clock can immediately freeze the CNN pipeline, save intermediate feature caches, prioritize power control, and resume inference after the interrupt ends without discarding the current frame sampling data.

[0080] In addition, weight pre-deployment and asynchronous inference loading are set up. During the offline weight packaging and storage pre-deployment stage at the device factory, after the model is trained offline, the PC training tool quantizes and compresses the floating-point weights of each convolution and fully connected layer of Tiny-CNN into binary 0 / 1 data, and packages them into continuous bit stream data packets in the order of network forward inference. Each bit stream is marked with a packet header, which contains three types of identifiers: the current network layer number, the weight array length, and the storage offset address. After packaging, the overall file is divided into multiple continuous binary data streams. During deployment, the weight packaged bit stream can be burned into the shared L1 memory on the Hongxin SoC. The shared storage is driven by a phase-shifting clock circuit. The storage clock is lower than the core clock frequency. Dynamic phase adjustment realizes zero-wait read and write of weight DMA, without accessing the low-speed external Flash, and the loading speed is the fastest. Alternatively, the packaged bit stream can be stored in the inverter's external SPI high-speed flash memory. The external Flash is equipped with independent hardware chip select and read bus, which does not occupy the bandwidth of the ADC and PWM peripheral bus. It is suitable for enhanced Tiny-CNN models with more layers and meets the storage requirements of high-precision arc recognition scenarios. After the weights are pre-deployed, the second thread domain DMA engine initializes the storage addressing table, pre-records the storage start offset and data length of each layer of packed bit stream, and loads the addressing parameters into the DMA hardware register once before inference starts. The entire inference process does not require the CPU to participate in address calculation, and the hardware is completely autonomous in addressing, eliminating the latency and computing power consumption caused by software address calculation.

[0081] During inference, the DMA asynchronous parallel preloading and hardware unpacking pipeline process, the second thread domain acquires the three-dimensional electric arc feature vector and sends it into the Tiny-CNN input layer. When starting the first layer inference, the hardware pipeline synchronously triggers dual parallel tasks. The two hardware paths are completely independent and do not compete for resources. Specifically, for the current layer inference mainline, the first task executed by the VPU is to read the unpacked binary weight array of the current layer by the VPU vector unit, perform convolution operation with the arc multidimensional feature vector, and complete 16-channel 16-bit binary multiplication and addition in parallel. The convolution feature result of this layer is then output to the on-chip inference cache. This task exclusively uses the second thread domain VPU computing hardware and is not affected by DMA storage read and write operations, ensuring continuous and uninterrupted inference computation. For the next layer weight preloading auxiliary line, the second task executed by the dedicated weight DMA engine is to asynchronously initiate storage read instructions based on the pre-stored hardware address table. The DMA engine reads the complete packaged bit stream of the next layer in batches from the on-chip shared storage / off-chip SPI flash memory. The reading process completely overlaps with the inference computation of task A, and there is no serial waiting. The DMA hardware has a built-in bit stream hardware unpacking unit that strips the segment header identifier and filters redundant information such as layer number and offset while reading the packaged data stream. The continuous binary bit stream is directly restored to a regular binary weight array and automatically stored in the dedicated inference weight cache.

[0082] The hardware timing synchronization logic for the two-layer task is as follows: the entire clock cycle of the current layer VPU inference exactly covers the total time consumed by the next layer's weight DMA read + hardware unpacking. When the VPU completes the current layer's convolution operation and prepares to switch to the next layer's computation, the fully unpacked weights of the next layer have already been pre-stored in the cache. The inference pipeline has no storage waiting gap, realizing a deep parallel pipeline that pre-fetches the next layer's weights during computation. The cyclic scheduling logic for the multi-layer network is as follows: Tiny-CNN has a multi-level structure with convolutional layers, pooling layers, and fully connected layers. Only the convolutional and fully connected layers require weight data, while the pooling layers have no weights and do not require DMA loading. When inference reaches the pooling layer, the VPU only performs dimensionality reduction operations, resulting in low computational load. The DMA engine synchronously preloads the weight data packets of the next two layers, making full use of the idle computational window of the pooling layer to pre-cache the weights, further compressing the loading time of subsequent convolutional layers. When inference reaches the last fully connected layer, the DMA stops the preloading operation, releases the storage bus resources, and only retains the VPU to complete the final binary classification output. With the hardware resource isolation mechanism in place, the weighted DMA engine is a dedicated peripheral for the second thread domain. The bus access path is physically separated from the ADC and PWM storage bus of the MPPT in the first thread domain. When the DMA performs batch read and write of weights, it will not preempt the MPPT voltage and current sampling data storage bandwidth, and will not cause power control data read and write delays. When the first thread domain triggers a high-priority MPPT interrupt, the hardware gating can temporarily pause the DMA storage read to prioritize MPPT storage access. After the interrupt ends, the DMA automatically resumes reading the weight bit stream from the paused address. The unpacked cached data will not be lost, and there is no need to reread the entire data packet. The breakpoint resume hardware logic greatly reduces the inference delay loss caused by interrupts.

[0083] Furthermore, the multi-threaded processor is configured with a phase-movable on-chip memory clock, and the operating clock frequency of the on-chip memory clock is lower than the processor core main clock frequency; when the first thread domain performs MPPT power calculation and / or the second thread domain determines the arc identification result based on the initial sampling data, the on-chip memory clock synchronously and dynamically adjusts the output clock phase to adapt to the processor core read and write timing, and the multi-threaded processor performs gated clock stop operation on idle memory modules whose read and write channels are not occupied by the first thread domain and the second thread domain.

[0084] The on-chip clock with a movable phase relies on a phase-shift clock generator hardware, independent of the processor core's main clock. It can dynamically adjust the rising / falling edge phase of the output clock, while the memory operating frequency is fixed at low frequencies such as 1 / 2 or 1 / 3 of the main clock, reducing storage power consumption. The core main clock is the DSP's core reference system clock, used for ALU, VPU, and instruction pipeline operation, with a processing speed far exceeding that of the on-chip L1 memory. Dynamic phase adjustment is characterized by the phase-shift generator synchronously shifting the memory clock phase when the core initiates a memory read / write instruction, ensuring complete alignment between the memory read / write data and the core's processing timing, eliminating low-speed memory read / write wait cycles. During the gated clock-stop process for idle memory modules, the memory bank consists of multiple parallel storage banks. Banks not accessed by MPPT or arc threads automatically have their clock supply cut off by hardware, resulting in zero dynamic power consumption for idle modules. The storage read / write channels are configured with independent address, data, and control bus channels for each storage bank, allocated to the first thread domain's MPPT parameter storage and the second thread's sampling / feature storage, respectively. These channels are physically separated and do not interfere with each other.

[0085] Based on this, such as Figure 3 The diagram illustrates a phase-movable on-chip memory clock architecture for a photovoltaic DC arc defense method based on a multi-threaded processor. For the phase-movable storage clock, the SoC incorporates an independent memory phase-shifting clock generator, which is frequency-divided from the main clock with a fixed division factor of 2. The storage reference clock is half the main clock frequency; for example, if the main clock is 600MHz, the storage reference clock is 300MHz. The hardware supports continuous phase offset adjustment from 0 to 180 degrees. It is equipped with an L1 memory cluster consisting of eight parallel banks, each bank having an independent clock gating switch and an independent read / write channel. For the clock signal link, the system main clock is sent to the ALU / ... The VPU processing core receives another signal, which is then fed into a phase-shifting PLL circuit to generate a storage reference clock. The phase-shifting generator receives the core's storage read / write control signal, dynamically shifts the phase of the storage clock in real time, and outputs Clk_M to the target storage bank. The storage bank is partitioned into two functional areas: one functional area is allocated to the first thread domain MPPT, storing voltage and current samples, PWM parameters, and notch filter coefficients; the other functional area is allocated to the second thread domain arc detection, storing the ADC's original sampled waveform, three-dimensional feature vector, and Tiny-CNN weight bitstream. The two types of thread read / write channels are physically completely isolated. In addition, each storage bank has an independently configured clock enable CE signal. A high CE level enables the clock, and a low CE level disables it. The hardware arbitration unit monitors the read / write bus activity of each bank in real time, and automatically pulls the CE signal low to stop the clock when there is no read / write access. The entire storage hardware architecture is factory-partitioned, and the compiler automatically allocates MPPT and arc data to the corresponding banks during compilation.

[0086] When the first thread domain performs MPPT power calculations, or the second thread domain extracts features / reads / writes CNN weights, the kernel LSU memory access unit synchronously sends a phase adjustment control signal to the phase-shift clock generator. The hardware matches the memory clock phase in real time, eliminating read / write wait cycles. If only the first thread domain performs MPPT read / write on its dedicated bank, the LSU sends an MPPT read / write timing flag, and the phase-shift generator shifts the memory clock phase forward by 180 degrees, ensuring that the rising edge of the low-speed 300MHz memory data output is perfectly aligned with the 600MHz kernel data sampling edge. After the kernel initiates a read command, there is no waiting period; it immediately reads the effective voltage, current, and power parameters. MPPT iterative calculations have no memory delay. When writing PWM duty cycle and notch filter parameters, the phase shift ensures sufficient memory write setup time and prevents data write distortion. If only the second thread, the arc thread, reads and writes to the Bank, the LSU sends an arc sampling read / write flag, and the phase shifter switches the phase offset to 90 degrees to adapt to the timing of continuous read / write of large batches of waveforms. When the DMA batch transfers sampled data and weighted bitstreams, the storage and DMA timings are perfectly matched, and there is no interruption in batch data transfer. Feature extraction and weight preloading do not generate waiting gaps. If the two threads read and write to their respective dedicated storage Banks simultaneously, the phase shifter outputs two independent phase offset clocks: one offset of 180 degrees for the MPPTBank and one offset of 90 degrees for the arc Bank. The phases of the two storage clocks are independently adjustable and do not interfere with each other. The two threads synchronously and in parallel read and write to their respective storage partitions, and the data read / write timings meet the hardware setup and hold requirements, without any errors in the reading of sampled waveforms or power parameters.

[0087] The hardware storage arbitration unit continuously monitors the address and data bus read / write activity flags of all storage banks in real time. It scans the access status of all banks once per system clock cycle, and immediately performs clock gating and shutdown operations on idle banks without read / write access. Specifically, if no read, write, or chip select (CE) signals are received for 16 consecutive core main clock cycles, the storage bank is determined to be idle. After being determined to be idle, the arbitration unit immediately pulls down the independent clock enable signal for that bank, cuts off the 300MHz clock output from the phase-shift clock generator to that bank, and the storage array and address decoding circuit synchronously stop switching operations. When a thread needs to read or write to the idle bank again, the LSU read / write instruction pulls up the CE enable signal one clock cycle in advance, the phase-shift clock resumes outputting the storage clock of the corresponding phase, and the read / write operation is performed only after the storage circuit has powered on and stabilized. The hardware has a built-in fixed one-cycle stabilization wait to ensure the validity of the first read / write data.

[0088] If the midday sunlight is stable, MPPT only iterates a few times. Of the Banks 0-3 allocated to the first thread domain, only Bank 0 is continuously read and written, while Banks 1-3 are idle and automatically clocked out. For continuous arc sampling and inference, all Banks 4-7 allocated to the second thread domain are clocked on. Only half of the storage modules are powered, halving storage power consumption. At night, with no solar illumination, the MPPT thread goes to sleep, and all MPPT-dedicated Banks 0-3 are permanently clocked out. Arc detection operates at a low frequency, with only Bank 4 clocked on, and the remaining arc banks clocked out. With frequent cloud disturbances, MPPT performs high-frequency reads and writes in all dedicated banks, arc synchronous reads and writes in sampling banks, and all storage banks are clocked on to ensure maximum real-time performance.

[0089] Furthermore, when the arc identification result output by the second thread domain is an arc alarm, the second thread domain synchronously outputs the arc fault confidence level; the first thread domain classifies the fault level based on the arc fault confidence level; when the arc fault confidence level is less than or equal to the first confidence threshold, the fault level is a low-confidence suspected arc, the first thread domain stops operating the PWM emergency block register, reports the alarm log locally, and continuously collects bus current for re-judgment; when the arc fault confidence level is greater than the first confidence threshold and less than or equal to the second confidence threshold, the fault level is a high-confidence confirmed arc, the PWM emergency block register is continuously latched, and an arc fault message is synchronously output to the external fault communication interface; when the arc fault confidence level is greater than the second confidence threshold, the fault level is an ultra-high-confidence strong arc, the PWM is blocked and the hardware switch drive signal is triggered to disconnect the DC circuit breaker at the front end of the photovoltaic string.

[0090] Herein, the arc fault confidence corresponds to the binary classification probability value output by the Tiny-CNN model, where a higher value indicates a higher probability that the current waveform is a real DC arc, and a lower value indicates a high probability of being inverter interference or sampling noise. The first confidence threshold is a firmware preset judgment boundary: values below this threshold are only suspected interference, and shutdown protection is not executed. The second confidence threshold is a firmware preset high-risk arc boundary: values above this threshold are determined as severe arcing with an immediate fire risk. The low-confidence suspected arc means that the model determines a low probability, which is most likely a short-term current disturbance; only log recording and continuous multi-frame re-judgment are performed, and the power generation circuit is not cut off, so as to avoid mis-shutdown and power generation loss. The high-confidence confirmed arc means that the model determines a high probability of a real arc, continuously latches PWM blocking, cuts off the power conversion circuit, and uploads a fault message to the operation and maintenance platform at the same time. The ultra-high-confidence strong arc refers to severe DC arcing with an extremely fast temperature rise rate; in addition to blocking PWM, the hardware DC circuit breaker is additionally driven to completely disconnect the photovoltaic module strings and isolate the fault source. The local alarm log is non-volatile storage in the on-chip Flash, which records the occurrence time of the suspected arc, bus waveform, and confidence value, facilitating operation and maintenance personnel to trace the on-site working conditions. The peripheral fault communication interface is the 485 / CAN / WiFi communication hardware of the inverter, which sends standardized fault messages to the external operation and maintenance gateway and cloud platform, including the fault level, occurrence time, and bus parameters.

[0091] Based on this, after the VPU in the second thread domain completes the inference of the multi-dimensional feature vector, the fully connected layer of the CNN outputs two sets of results simultaneously, which are stored in two independent registers of the hardware mailbox in parallel, wherein one register stores a binary alarm identifier; the other register stores the quantified arc fault confidence value, and the value represents the model probability that the current bus waveform belongs to a real DC arc.

[0092] If the identifier is 0, it indicates normal operation, the confidence register is directly cleared, and the first thread domain reads it and normally executes MPPT operation without any protection action; if the identifier is 1, it indicates an arc alarm, and the confidence value is synchronously latched to the mailbox register for the hardware threshold comparison unit in the first thread domain to read and perform hierarchical judgment. The confidence is output by quantifying the native classification probability of the CNN, and is synchronously calculated and output by hardware after the VPU inference is completed, which does not increase the operation overhead of the second thread domain. One inference outputs both the judgment result and the fault severity index, providing a quantitative basis for hierarchical protection.

[0093] The first thread domain has a built-in dual-channel hardware threshold comparator, and a fixed first threshold Th1 and a second threshold Th2 are programmed in the firmware at the factory, where Th1<Th2. If the confidence ≤ Th1, the low-confidence suspected arc flag is set; if Th1 < confidence ≤ Th2, the high-confidence confirmed arc flag is set; if confidence > Th2, the ultra-high-confidence strong arc flag is set. After the judgment is completed, the three-level fault flags are latched into independent hardware status registers to trigger differentiated protection logic respectively.

[0094] For suspected arcing with low confidence, the hardware does not operate the PWM emergency block register, the inverter continues to output PWM drive normally, and the photovoltaic power generation is uninterrupted. At the same time, local log storage and background tasks triggered by multi-frame continuous review are executed in parallel. During local log storage, DMA automatically writes the current bus sampling waveform, confidence value, and system timestamp to the on-chip Flash non-volatile log partition. Data is not lost when power is off, and maintenance personnel can read it locally to trace back the suspected disturbance conditions. During multi-frame continuous review, the first thread domain adjusts the ADC oversampling buffer length and continuously collects multiple frames of bus current waveforms and sends them to the second thread domain to repeatedly perform arc identification. If the confidence of all frames for a preset number of consecutive frames is higher than Th1, it is upgraded to confirm arcing. Low confidence alarms in a single frame are directly ignored, completely eliminating false shutdowns caused by instantaneous electromagnetic interference and sampling glitches, and significantly reducing power generation losses.

[0095] For high-confidence confirmed arcs, a latch flag is immediately written to the PWM emergency block register, continuously cutting off the inverter power switch drive, disconnecting the DC power conversion circuit, and causing the arc to lose its sustaining current. Simultaneously, the fault communication peripheral hardware is activated: CAN / 485 / WiFi interfaces package standardized fault messages, including the fault level, current bus voltage and current, confidence level, device number, and fault timestamp, which are automatically uploaded to the local maintenance gateway and the cloud-based photovoltaic monitoring platform. The maintenance backend receives a medium-level arc fault alarm in real time and arranges personnel for on-site repair. The latch register remains in a blocked state, and the block flag is only cleared after the inverter is manually reset to prevent the arc from reigniting.

[0096] For ultra-high confidence strong arcing, dual hardware circuit breaker protection is triggered simultaneously. The first layer of protection is to immediately set the PWM emergency block register and cut off the inverter drive signal. The second layer of protection is to output a high level of hardware GPIO to drive the DC circuit breaker drive circuit, disconnect the DC bus at the front end of the photovoltaic module, completely isolate the residual high voltage DC on the photovoltaic panel side, and eliminate the risk of violent combustion of cables and junction boxes. At the same time, the highest priority emergency fault message is sent to the cloud, and the platform pushes SMS and APP alarms to notify the operation and maintenance personnel to rush to the scene for emergency handling. The dual hardware circuit breaker is a pure hardware signal output with no software forwarding delay, and the two-level isolation is completed in milliseconds to deal with high-risk and violent arcing scenarios and meet the highest standards of photovoltaic fire safety.

[0097] For low-confidence suspected arcs, if the confidence level falls below the threshold after multiple consecutive frames of reassessment, the alarm log flag is automatically cleared and the normal sampling cycle is restored, requiring no manual intervention throughout the process. For high / ultra-high confidence arcs, hardware blocking is implemented and the circuit breaker drive signal is continuously latched. The inverter hardware must be manually powered off and reset to clear the PWM blocking flag and reset the circuit breaker drive signal, preventing automatic restart and secondary arcing if the fault is not eliminated. It has a fault self-locking safety mechanism.

[0098] Corresponding to the above method embodiments, this application also provides an embodiment of a photovoltaic DC arc defense device based on a multi-threaded processor. Figure 4 A schematic diagram of a photovoltaic DC arc protection device based on a multi-threaded processor, according to an embodiment of this application, is shown. Figure 4 As shown, the device includes: The sampling module 402 is configured to oversample the photovoltaic DC bus current based on the ADC of the multi-threaded processor, and synchronously call the adaptive notch filter algorithm of the multi-threaded processor to filter out the frequency interference of the dynamic switching of the photovoltaic inverter in real time to obtain the initial sampling data. The partitioning module 404 is configured to divide the hardware threads of the multi-threaded processor into a first thread domain and a second thread domain that are isolated from each other, wherein the first thread domain is used to control maximum power point tracking and the second thread domain is used for arc detection. MPPT power calculation module 406 is configured to perform MPPT power calculation based on the first thread domain, adjust the dynamic switch of the photovoltaic inverter based on the calculation result, and generate a trigger signal after a single cycle of MPPT power calculation. The photovoltaic DC arc detection and defense module 408 is configured to respond to the trigger signal, wherein the second thread domain determines the arc detection result based on the initial sampling data, and if the arc detection result is an arc alarm, the first thread domain operates the built-in PWM emergency block register of the multi-threaded processor to cut off the photovoltaic DC circuit.

[0099] In an optional embodiment, the photovoltaic DC arc detection and defense module 408 is further configured to: In response to the trigger signal, the second thread domain extracts the feature vector of the initial sampled data to obtain a multidimensional feature vector of the arc that includes abrupt entropy, temporal kurtosis, and broadband energy flatness; through the second thread domain, the multidimensional feature vector of the arc is input into an on-chip lightweight Tiny-CNN model for arc recognition to obtain the arc recognition result, wherein the arc recognition result includes normal operation or arc alarm.

[0100] In an optional embodiment, the photovoltaic DC arc detection and defense module 408 is further configured to: The lightweight Tiny-CNN used for photovoltaic arc recognition has its binarized weights pre-stored in off-chip flash memory or on-chip shared memory in a packaged bitstream format. When the second thread domain performs the current network layer inference operation through the current arc multidimensional feature vector, the weight DMA engine configured in the second thread domain asynchronously and in parallel reads and unpacks the bitstream of the next layer's binarized weights.

[0101] In an optional embodiment, the partitioning module 404 is further configured to: The controllable dynamic multithreaded architecture based on the multithreaded processor adds a mark to each instruction, wherein the mark contains the thread domain identifier to which the corresponding instruction belongs and the execution priority; based on the thread domain identifier carried by the mark, MPPT control instructions belonging to the first thread domain and arc detection instructions belonging to the second thread domain are distinguished, and the processor hardware computing resources are dynamically allocated in combination with the execution priority recorded in the mark.

[0102] In an optional embodiment, the partitioning module 404 is further configured to: The MPPT control instructions include MPPT operation instructions, and the arc detection instructions include arc feature extraction instructions and Tiny-CNN inference instructions. The execution priority of the marks corresponding to the MPPT control instructions is uniformly configured as high priority, and the execution priority of the marks corresponding to the arc detection instructions is uniformly configured as low priority. During the instruction issuance phase, the processor hardware prioritizes scheduling the MPPT control instructions to occupy the computational units based on the difference in execution priority of the marks.

[0103] In an optional embodiment, the partitioning module 404 is further configured to: When the first thread domain generates a high-priority MPPT emergency calculation request, the arc-related calculation process currently being executed by the second thread domain is paused, and the intermediate calculation data of the process is saved. During the pause, no computing resources are allocated to the second thread domain, and read and write operations of the second thread domain to the storage area are blocked. Only the first thread domain is allowed to read and write to the storage area to execute MPPT calculations. After the first thread domain completes all the MPPT emergency calculations, the resource and storage access restrictions on the second thread domain are lifted, and the second thread domain retrieves the pre-saved intermediate calculation data and continues to execute the paused arc-related calculation process.

[0104] In an optional embodiment, the photovoltaic DC arc protection device based on a multi-threaded processor further includes: A clock phase adjustment module is used to dynamically adjust the output clock phase of the on-chip memory clock during the MPPT power calculation performed by the first thread domain and / or the arc identification result determined by the second thread domain based on the initial sampling data, to adapt to the processor core read / write timing. The multi-threaded processor performs gated clock-stop operations on idle memory modules whose read / write channels are not occupied by the first thread domain and the second thread domain. The multi-threaded processor is configured with a phase-movable on-chip memory clock, and the operating clock frequency of the on-chip memory clock is lower than the processor core main clock frequency.

[0105] In an optional embodiment, the photovoltaic DC arc detection and defense module 408 is further configured to: When the arc identification result output by the second thread domain is an arc alarm, the second thread domain synchronously outputs the arc fault confidence level; the first thread domain classifies the fault level based on the arc fault confidence level; when the arc fault confidence level is less than or equal to the first confidence threshold, the fault level is a low-confidence suspected arc, the first thread domain stops operating the PWM emergency block register, reports the alarm log locally, and continuously collects bus current for re-judgment; when the arc fault confidence level is greater than the first confidence threshold and less than or equal to the second confidence threshold, the fault level is a high-confidence confirmed arc, the PWM emergency block register is continuously latched, and an arc fault message is synchronously output to the external fault communication interface; when the arc fault confidence level is greater than the second confidence threshold, the fault level is an ultra-high-confidence strong arc, the PWM is blocked and the hardware switch drive signal is triggered to disconnect the DC circuit breaker at the front end of the photovoltaic string.

[0106] In an optional embodiment, the photovoltaic DC arc protection device based on a multi-threaded processor further includes: The mapping module is configured to map the MPPT power calculation task belonging to the first thread domain and the arc identification task belonging to the second thread domain to two isolated pipeline execution stages within the multi-level pipelined parallel execution architecture, wherein the multi-threaded processor is configured with a multi-level pipelined parallel execution architecture.

[0107] In an optional embodiment, the mapping module is further configured to: The two sets of pipeline execution stages are equipped with independent computing paths and dedicated computing storage spaces. Each computing path can only perform read and write operations on its own dedicated computing storage space. The computing processes of the first thread domain and the second thread domain are completed in their respective pipeline execution stages.

[0108] The above is a schematic scheme of a photovoltaic DC arc protection device based on a multi-threaded processor according to this embodiment. It should be noted that the technical solution of this photovoltaic DC arc protection device based on a multi-threaded processor and the technical solution of the photovoltaic DC arc protection method based on a multi-threaded processor described above belong to the same concept. Details not described in detail in the technical solution of the photovoltaic DC arc protection device based on a multi-threaded processor can be found in the description of the technical solution of the photovoltaic DC arc protection method based on a multi-threaded processor described above. Furthermore, the components in the device embodiment should be understood as functional modules necessary to implement each step of the program flow or each step of the method; these functional modules are not actual functional divisions or separations. The device claims defined by such a set of functional modules should be understood as a functional module architecture that primarily implements the solution through the computer program described in the specification, and not as a physical device that primarily implements the solution through hardware.

[0109] Figure 5 A structural block diagram of a computing device 500 according to an embodiment of this application is shown. The components of the computing device 500 include, but are not limited to, a memory 510 and a processor 520. The processor 520 is connected to the memory 510 via a bus 530, and a database 550 is used to store data.

[0110] The computing device 500 also includes an access device 540, which enables the computing device 500 to communicate via one or more networks 560. Examples of these networks include a Public Switched Telephone Network (PSTN), a Local Area Network (LAN), a Wide Area Network (WAN), a Personal Area Network (PAN), or a combination of communication networks such as the Internet. The access device 540 may include one or more of any type of wired or wireless network interface (e.g., a Network Interface Card (NIC)), such as an IEEE 802.11 Wireless Local Area Network (WLAN) interface, a Wi-MAX interface, an Ethernet interface, a Universal Serial Bus (USB) interface, a cellular network interface, a Bluetooth interface, a Near Field Communication (NFC) interface, and so on.

[0111] In one embodiment of this application, the aforementioned components of the computing device 500 and Figure 5 Other components, not shown, can also be connected to each other, for example, via a bus. It should be understood that... Figure 5 The block diagram of the computing device shown is for illustrative purposes only and is not intended to limit the scope of this application. Those skilled in the art can add or replace other components as needed.

[0112] The computing device 500 can be any type of stationary or mobile computing device, including mobile computers or mobile computing devices (e.g., tablet computers, personal digital assistants, laptop computers, notebook computers, netbooks, etc.), mobile phones (e.g., smartphones), wearable computing devices (e.g., smartwatches, smart glasses, etc.) or other types of mobile devices, or stationary computing devices such as desktop computers or PCs. The computing device 500 can also be a mobile or stationary server.

[0113] The processor 520 is used to execute computer-executable instructions for each step of the photovoltaic DC arc defense method based on a multi-threaded processor.

[0114] The above is an illustrative scheme of a computing device according to this embodiment. It should be noted that the technical solution of this computing device belongs to the same concept as the technical solution of the photovoltaic DC arc defense method based on a multi-threaded processor described above. For details not described in detail in the technical solution of the computing device, please refer to the description of the technical solution of the photovoltaic DC arc defense method based on a multi-threaded processor described above.

[0115] An embodiment of this application also provides a computer-readable storage medium storing computer instructions that, when executed by a processor, are used to implement the steps of the photovoltaic DC arc defense method based on a multi-threaded processor.

[0116] The above is an illustrative scheme of a computer-readable storage medium according to this embodiment. It should be noted that the technical solution of this storage medium belongs to the same concept as the technical solution of the photovoltaic DC arc defense method based on a multi-threaded processor described above. Details not described in detail in the technical solution of the storage medium can be found in the description of the technical solution of the photovoltaic DC arc defense method based on a multi-threaded processor described above.

[0117] An embodiment of this application also provides a chip that stores a computer program, which, when executed by the chip, implements the steps of the photovoltaic DC arc defense method based on a multi-threaded processor.

[0118] The foregoing has described specific embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired results. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0119] The computer instructions include computer program code, which may be in the form of source code, object code, executable file, or certain intermediate forms. The computer-readable medium may include any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium may be appropriately added to or subtracted according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media may not include electrical carrier signals and telecommunication signals.

[0120] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0121] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0122] The preferred embodiments disclosed above are merely illustrative of this application. The optional embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this application. These embodiments are selected and specifically described in this application to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to better understand and utilize this application. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A photovoltaic DC arc defense method based on a multi-threaded processor, characterized in that, include: The ADC based on the multi-threaded processor performs oversampling on the photovoltaic DC bus current and synchronously calls the adaptive notch filter algorithm of the multi-threaded processor to filter out the frequency interference of the dynamic switching of the photovoltaic inverter in real time and obtain the initial sampling data. The hardware threads of the multi-threaded processor are divided into a first thread domain and a second thread domain that are isolated from each other. The first thread domain is used to control maximum power point tracking, and the second thread domain is used for arc detection. MPPT power calculation is performed based on the first thread domain, and the dynamic switch of the photovoltaic inverter is adjusted based on the calculation result. A trigger signal is generated after a single cycle of MPPT power calculation. In response to the trigger signal, the second thread domain determines the arc identification result based on the initial sampling data. If the arc identification result is an arc alarm, the first thread domain operates the built-in PWM emergency block register of the multi-threaded processor to cut off the photovoltaic DC circuit.

2. The method according to claim 1, characterized in that, In response to the trigger signal, the second thread domain determines the arc identification result based on the initial sampled data, including: In response to the trigger signal, the second thread domain extracts the feature vector of the initial sampled data to obtain an arc multidimensional feature vector containing abrupt entropy, temporal kurtosis, and broadband energy flatness; The arc multidimensional feature vector is input into the on-chip lightweight Tiny-CNN model through the second thread domain to perform arc recognition, and the arc recognition result is obtained, wherein the arc recognition result includes normal operation or arc alarm.

3. The method according to claim 2, characterized in that, The lightweight Tiny-CNN used for photovoltaic arc recognition has its binarized weights pre-stored in off-chip flash memory or on-chip shared memory in a packaged bitstream format. When the second thread domain performs the current network layer inference operation through the current arc multidimensional feature vector, the weight DMA engine configured in the second thread domain asynchronously and in parallel reads and unpacks the bitstream of the next layer's binarized weights.

4. The method according to claim 1, characterized in that, The step of dividing the hardware threads of the multi-threaded processor into mutually isolated first thread domains and second thread domains includes: The controllable dynamic multithreaded architecture based on the multithreaded processor adds a mark to each instruction, wherein the mark contains the thread domain identifier to which the corresponding instruction belongs and the execution priority; Based on the thread domain identifier carried by the mark, MPPT control instructions belonging to the first thread domain and arc detection instructions belonging to the second thread domain are distinguished. At the same time, the processor hardware computing resources are dynamically allocated in combination with the execution priority recorded by the mark.

5. The method according to claim 4, characterized in that, The MPPT control instructions include MPPT operation instructions, and the arc detection instructions include arc feature extraction instructions and Tiny-CNN inference instructions. The execution priority of the marks corresponding to the MPPT control instructions is uniformly configured as high priority, and the execution priority of the marks corresponding to the arc detection instructions is uniformly configured as low priority. During the instruction issuance phase, the processor hardware prioritizes scheduling the MPPT control instructions to occupy the computational units based on the difference in execution priority of the marks.

6. The method according to claim 5, characterized in that, When the first thread domain generates a high-priority MPPT emergency calculation request, the arc-related calculation process currently being executed by the second thread domain is paused, and the intermediate calculation data of the process is saved. During the pause, no computing resources are allocated to the second thread domain, and read and write operations of the second thread domain to the storage area are blocked. Only the first thread domain is allowed to read and write to the storage area to execute MPPT calculations. After the first thread domain completes all the MPPT emergency calculations, the resource and storage access restrictions on the second thread domain are lifted, and the second thread domain retrieves the pre-saved intermediate calculation data and continues to execute the paused arc-related calculation process.

7. The method according to claim 1, characterized in that, The multi-threaded processor is configured with a phase-shiftable on-chip memory clock, and the on-chip memory clock operates at a frequency lower than the processor core main clock frequency. During the process of the first thread domain performing MPPT power calculation and / or the second thread domain determining the arc identification result based on the initial sampling data, the on-chip memory clock synchronously and dynamically adjusts the output clock phase to adapt to the processor core read and write timing, and the multi-threaded processor performs gated clock stop operation on idle memory modules whose read and write channels are not occupied by the first thread domain and the second thread domain.

8. The method according to claim 1, characterized in that, When the arc identification result output by the second thread domain is an arc alarm, the second thread domain synchronously outputs the arc fault confidence level; The first thread domain classifies the fault level based on the arc fault confidence level; When the confidence level of the arc fault is less than or equal to the first confidence threshold, the fault level is a low-confidence suspected arc. The first thread domain stops operating the PWM emergency block register, reports an alarm log locally, and continuously collects bus current for re-judgment. When the confidence level of the arc fault is greater than the first confidence threshold and less than or equal to the second confidence threshold, the fault level is a high confidence confirmed arc, the PWM emergency lockout register is continuously latched, and an arc fault message is synchronously output to the peripheral fault communication interface. When the confidence level of the arc fault is greater than the second confidence threshold, the fault level is an ultra-high confidence strong arc, the PWM is blocked and the hardware switch drive signal is triggered to disconnect the DC circuit breaker at the front end of the photovoltaic string.

9. The method according to claim 1, characterized in that, The multi-threaded processor is configured with a multi-stage pipelined parallel execution architecture, and maps the MPPT power calculation task belonging to the first thread domain and the arc recognition task belonging to the second thread domain to two mutually isolated pipeline execution stages within the multi-stage pipelined parallel execution architecture.

10. The method according to claim 9, characterized in that, The two sets of pipeline execution stages are equipped with independent computing paths and dedicated computing storage spaces. Each computing path can only perform read and write operations on its own dedicated computing storage space. The computing processes of the first thread domain and the second thread domain are completed in their respective pipeline execution stages.

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