Control method and device for variable frequency equipment of pumped storage unit and computer device

Abstract

The application relates to a control method and device for a variable frequency device of a pumped storage unit and computer equipment. The method comprises the following steps: in response to a grid-connected triggering event of the pumped storage unit, in the process of driving the variable frequency device to connect the pumped storage unit to the power grid, determining the frequency variation rate and the harmonic distortion rate of the power grid and the phase difference between the power grid voltage and the output voltage of the variable frequency device in each commutation period of the variable frequency device; determining the initial value of the control parameter of the phase-locked loop of the variable frequency device in the current commutation period according to the current rotating speed of the pumped storage unit; adjusting the initial value according to the frequency variation rate, the harmonic distortion rate and the phase difference to obtain the target value of the control parameter of the phase-locked loop in the current commutation period; and adjusting the initial value of the control parameter of the phase-locked loop in the next commutation period according to the commutation margin deviation until the pumped storage unit is connected to the grid. The method can improve the control precision of the grid connection of the pumped storage unit.

Description

Technical Field

[0001] This application relates to the field of power technology, and in particular to a control method, device and computer equipment for frequency conversion equipment of pumped storage units. Background Technology

[0002] With the continuous growth of installed capacity of pumped storage power stations and the increasing demand of the power grid for rapid response and dispatch of units, the static frequency converter, as the core equipment for starting pumped storage units, directly affects the start-up success rate and grid connection efficiency of the units.

[0003] In traditional technology, speed control of static frequency converters typically employs proportional-integral (PI) regulators, with the proportional and integral coefficients manually tuned and fixed based on typical operating conditions (e.g., near the rated speed). During grid connection, the process is executed stage by stage according to a pre-set sequential control flow: first, the static frequency converter accelerates the unit from standstill to synchronous speed; then, a synchronization device detects the phase difference between the unit voltage and the grid voltage; once the deviation meets the grid connection requirements, the circuit breaker is closed. In this process, collision protection relies on independent protection modules, which communicate with each other via fieldbus (e.g., Modbus, PROFIBUS), and fault information is processed by their respective independent controllers.

[0004] The aforementioned traditional methods suffer from problems such as insufficient control precision, redundant and complex control systems, and poor system stability. Summary of the Invention

[0005] Therefore, it is necessary to provide a control method, device, computer equipment, computer-readable storage medium, and computer program product for frequency conversion equipment of pumped storage units that can improve control accuracy in response to the above-mentioned technical problems.

[0006] In a first aspect, this application provides a control method for variable frequency drive (VFD) equipment in a pumped storage unit, comprising:

[0007] In response to the grid connection triggering event of the pumped storage unit, during the process of the pumped storage unit being connected to the grid by the frequency converter, for each commutation cycle of the frequency converter, the frequency change rate and harmonic distortion rate of the grid in the current commutation cycle, as well as the phase difference between the grid voltage and the output voltage of the frequency converter are determined.

[0008] The initial values ​​of the control parameters of the phase-locked loop of the frequency converter are determined based on the current rotational speed of the pumped storage unit for the current commutation cycle; the control parameters include response sensitivity and error elimination speed.

[0009] The initial values ​​are adjusted based on the frequency change rate, harmonic distortion rate, and phase difference to obtain the target values ​​of the control parameters of the phase-locked loop in the current commutation cycle; wherein, the response sensitivity is negatively correlated with the harmonic distortion rate, and the error elimination speed is positively correlated with the frequency change rate;

[0010] The frequency converter is controlled for commutation in the current commutation cycle according to the target value, and the commutation margin deviation of the frequency converter in the current commutation cycle is determined according to the commutation performance of the frequency converter in the current commutation cycle and the commutation performance standard.

[0011] The initial values ​​of the control parameters of the phase-locked loop for the next commutation cycle are adjusted according to the commutation margin deviation until the pumped storage unit is connected to the grid.

[0012] Secondly, this application also provides a control device for a frequency converter of a pumped storage unit, the device comprising:

[0013] The response module is used to respond to the grid connection triggering event of the pumped storage unit. During the process of the pumped storage unit being connected to the grid by the frequency converter, for each commutation cycle of the frequency converter, the frequency change rate and harmonic distortion rate of the grid in the current commutation cycle, as well as the phase difference between the grid voltage and the output voltage of the frequency converter are determined.

[0014] The determination module is used to determine the initial values ​​of the control parameters of the phase-locked loop of the frequency converter equipment for the current commutation cycle based on the current rotational speed of the pumped storage unit; the control parameters include response sensitivity and error elimination speed;

[0015] The first adjustment module is used to adjust the initial value according to the frequency change rate, harmonic distortion rate, and phase difference to obtain the target value of the control parameters of the phase-locked loop in the current commutation cycle; wherein, the response sensitivity is negatively correlated with the harmonic distortion rate, and the error elimination speed is positively correlated with the frequency change rate;

[0016] The control module is used to perform commutation control on the frequency converter for the current commutation cycle according to the target value, and to determine the commutation margin deviation of the frequency converter for the current commutation cycle according to the commutation performance of the frequency converter and the commutation performance standard for the current commutation cycle.

[0017] The second adjustment module is used to adjust the initial values ​​of the control parameters of the phase-locked loop for the next commutation cycle according to the commutation margin deviation, until the pumped storage unit is connected to the grid.

[0018] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps included in any of the foregoing method embodiments.

[0019] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps included in any of the foregoing method embodiments.

[0020] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps included in any of the foregoing method embodiments.

[0021] The aforementioned control method, device, computer equipment, computer-readable storage medium, and computer program product for pumped storage unit frequency converters, on the one hand, adjust the phase-locked loop (PLL) parameters feedforward based on grid operating conditions (frequency change rate, harmonic distortion rate), and on the other hand, correct the PLL parameters feedback based on commutation effect (commutation margin deviation). This allows the PLL parameters to adapt to changes in the grid environment and optimize commutation execution quality. This embodiment determines the initial parameters for speed adaptation by collecting grid characteristics and phase errors, adaptively adjusts the PLL parameters based on grid characteristics, executes commutation, quantifies the commutation effect deviation, and feeds back the deviation to the initial parameter values ​​for the next cycle. Compared to related technologies that use fixed parameters or only open-loop adjustments, this embodiment effectively suppresses speed overshoot during the constant speed control phase by continuously correcting the PLL parameters through commutation margin deviation. During the natural commutation phase, an effective regulation mechanism is established through commutation effect evaluation and feedback adjustment, significantly improving speed control accuracy and greatly shortening grid connection time. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is an application environment diagram of a control method for a frequency converter in a pumped storage unit, as shown in one embodiment.

[0024] Figure 2 This is a flowchart illustrating a control method for a frequency converter in a pumped storage unit, as shown in one embodiment.

[0025] Figure 3This is a structural block diagram of a control device for a pumped storage unit frequency converter in one embodiment.

[0026] Figure 4 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0028] Before describing the solutions of the embodiments of the present invention, the related technologies and their existing problems will be further explained:

[0029] A static frequency converter converts the grid's power frequency AC power into adjustable frequency AC power, driving a synchronous motor to smoothly accelerate from a standstill to synchronous speed, thus avoiding the impact load caused by direct grid connection.

[0030] The relevant technologies suffer from at least the following problems: insufficient speed control precision leads to prolonged grid connection time. Since the startup to grid connection of a pumped storage unit is a highly nonlinear process, motor parameters (such as back EMF and impedance) change with speed, and the grid operating conditions also exhibit frequency fluctuations and harmonic distortion. Fixed-parameter PI regulators cannot adapt to these dynamic changes: during the constant speed control phase, setting a large proportional gain to pursue rapid response easily leads to speed overshoot (i.e., the speed exceeds the target value and then corrects back); during the natural commutation phase (typically corresponding to the 200rpm to 800rpm range), there is a lack of real-time evaluation and adjustment mechanisms for the commutation process, and insufficient commutation margin cannot be actively compensated for, resulting in commutation jitter or even commutation failure. Both speed overshoot and commutation jitter force the synchronizing device to repeatedly check the stability window, significantly extending the grid connection waiting time and reducing the unit's response speed to grid dispatch commands.

[0031] Secondly, the control system is redundant and complex, resulting in poor system stability and a low unit start-up success rate. Traditional static frequency converter control systems typically employ an architecture where multiple independent controllers work together, such as independent speed regulators, excitation regulators, logic controllers (PLCs), and dedicated protection modules. These modules communicate via fieldbus, and any malfunction in any controller or communication link can interrupt the start-up process. Furthermore, the sequential control process lacks an instruction verification mechanism. If control instructions are distorted due to electromagnetic interference when sent from the PLC to the execution module, the receiver cannot identify and directly execute the erroneous instructions. In addition, fault diagnosis relies primarily on single-point thresholds (e.g., shutdown when the temperature exceeds 85°C). When a sensor generates transient noise, the system may falsely trigger protection, leading to start-up failure. These combined issues result in a low unit start-up success rate, particularly pronounced in pumped-storage power stations with complex electromagnetic environments.

[0032] Therefore, a static inverter control scheme that can improve speed control accuracy and system stability is needed to shorten grid connection time and increase the unit start-up success rate.

[0033] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0034] The control method for frequency converter equipment of pumped storage units provided in this application embodiment can be applied to, for example... Figure 1 In the application environment shown, terminal 102 communicates with server 104 via a network. A data storage system can store the data that server 104 needs to process. The data storage system can be integrated onto server 104 or located on the cloud or other network servers. Terminal 102 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, drones, low-altitude aircraft, IoT devices, and portable wearable devices. IoT devices can include smart speakers, smart TVs, smart air conditioners, smart in-vehicle devices, projection devices, etc. Portable wearable devices can include smartwatches, smart bracelets, head-mounted devices, etc. Head-mounted devices can be virtual reality (VR) devices, augmented reality (AR) devices, smart glasses, etc. Server 104 can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud computing services.

[0035] In one exemplary embodiment, such as Figure 2 As shown, a control method for variable frequency drive (VFD) equipment in a pumped storage unit is provided, which is then applied to... Figure 1 The following steps are used as an example to illustrate the process of terminal 102, which is a static frequency inverter:

[0036] Step 202: In response to the grid connection trigger event of the pumped storage unit, during the process of the frequency converter driving the pumped storage unit to connect to the grid, for each commutation cycle of the frequency converter, determine the frequency change rate and harmonic distortion rate of the grid in the current commutation cycle, as well as the phase difference between the grid voltage and the output voltage of the frequency converter.

[0037] Among them, the grid connection trigger event refers to the event that the pumped storage unit, driven by the static frequency converter, reaches a speed close to the synchronous speed, thus meeting the grid connection conditions. Specifically, it can be determined based on the command signal issued by the control system to initiate the grid connection process. For example, for a unit with a rated speed of 1500 rpm, when the speed reaches the range of 1490 rpm to 1495 rpm, the control system determines that the grid connection trigger condition is met and triggers the grid connection event.

[0038] Variable frequency drive (VFD) equipment includes static frequency converters (SFDs), which are used to start pumped-storage hydroelectric generators (HPGs) during pump operation. They convert the grid's AC power into AC power with adjustable frequency, thus smoothly accelerating the stationary synchronous motor to synchronous speed. During grid connection, the SFD ensures that the generator's output voltage matches the grid voltage in amplitude, frequency, and phase.

[0039] The commutation cycle, also known as the natural commutation cycle, refers to a complete cycle in a static inverter where the thyristors turn off using the natural zero-crossing characteristic of alternating current, triggering the next thyristor to turn on. During the natural commutation phase (typically corresponding to a motor speed of approximately 200 rpm to 800 rpm), each commutation cycle constitutes a basic control unit. In this embodiment, each natural commutation cycle serves as the control cycle, and subsequent steps are repeated until the pumped storage unit is connected to the grid.

[0040] The rate of frequency change is a physical quantity that characterizes the severity of power grid frequency fluctuations, measured in Hz / s. For example, when the power grid frequency changes from 50.00Hz to 50.10Hz in 0.02 seconds, the rate of frequency change is 5Hz / s. A higher rate of frequency change indicates a more unstable power grid, and thus requires a higher level of tracking capability from the phase-locked loop (PLL).

[0041] Harmonic distortion rate, also known as total harmonic distortion (THD), is a physical quantity that characterizes the degree of distortion in the voltage waveform of a power grid. It is a dimensionless percentage. For example, when the power grid contains 5th and 7th harmonics, the THD may reach between 5% and 8%. The higher the harmonic distortion rate, the more the power grid voltage waveform deviates from a sine wave, and the greater the interference to the phase-locked loop (PLL).

[0042] Phase difference: refers to the difference between the instantaneous phase of the grid voltage and the instantaneous phase of the static inverter's output voltage, measured in radians or degrees. In essence, the phase difference reflects the synchronization deviation between the inverter's output voltage and the grid voltage. When the phase difference is zero, the two are perfectly synchronized.

[0043] The frequency change rate can be obtained by tracking the instantaneous frequency of the grid voltage using a phase-locked loop (PLL), recording the frequency values ​​at the start and end of the current commutation cycle, and calculating the difference between the two by dividing by the cycle duration. The harmonic distortion rate can be obtained by performing a Fast Fourier Transform (FFT) on the grid voltage signal, extracting the effective values ​​of the fundamental component and each harmonic component, and calculating the ratio of the total effective harmonic value to the effective value of the fundamental component. The phase difference can be obtained by simultaneously detecting the phase of the grid voltage and the phase of the static inverter's output voltage using a PLL, and calculating the difference between the two.

[0044] In related technologies, the parameters of phase-locked loops (PLLs) are usually fixed or preset in segments, making them unable to adapt to dynamic changes in power grid conditions. When the power grid experiences frequency fluctuations or harmonic distortion, PLLs with fixed parameters are prone to phase tracking errors, leading to speed overshoot during grid connection and prolonging grid connection time.

[0045] This embodiment provides multi-dimensional input data for the dynamic adjustment of phase-locked loop (PLL) parameters by real-time acquisition and calculation of frequency change rate, harmonic distortion rate, and phase difference during each commutation cycle. The frequency change rate reflects the stability of the power grid, the harmonic distortion rate reflects the quality of the power grid, and the phase difference directly reflects the current synchronization error, thus providing a comprehensive characterization of the power grid operating conditions during the current commutation cycle.

[0046] Step 204: Determine the initial values ​​of the control parameters of the phase-locked loop of the frequency converter in the current commutation cycle based on the current rotational speed of the pumped storage unit; the control parameters include response sensitivity and error elimination speed.

[0047] The current speed refers to the real-time rotational speed of the pumped-storage unit driven by the static frequency converter, measured in rpm. The current speed can be measured by a photoelectric encoder or rotary transformer mounted on the motor shaft, or estimated by the frequency of the motor's back electromotive force. The electrical and mechanical characteristics of the motor differ across different speed ranges, therefore the control parameters required by the phase-locked loop (PLL) also vary.

[0048] A phase-locked loop (PLL) is a functional module in a static frequency converter (SFD) used to detect the phase and frequency of the mains voltage and synchronize the phase of the converter's output voltage with the mains voltage. The PLL's output serves as the phase reference for the converter's trigger pulses.

[0049] Response sensitivity refers to the degree to which a phase-locked loop (PLL) responds to instantaneous phase errors. In this embodiment, response sensitivity is specifically reflected in the PLL's proportional gain (denoted as Kp). The proportional gain is used to proportionally map the current value of the phase difference to the adjustment amount of the PLL output. It can be understood that a larger proportional gain results in a faster response to phase errors, but is more prone to oscillations; a smaller proportional gain results in a smoother response, but slower tracking speed.

[0050] Error elimination speed refers to the rate at which the phase-locked loop (PLL) eliminates accumulated phase errors. In this embodiment, the error elimination speed is specifically reflected in the integral coefficient (Ki) of the PLL. The integral coefficient is used to map the accumulated integral value of the phase difference to the adjustment amount of the PLL output. It can be understood that the larger the integral coefficient, the faster the steady-state phase error is eliminated, but it is prone to overshoot; the smaller the integral coefficient, the slower the elimination, but the more stable the operation.

[0051] For example, a mapping between speed ranges and initial parameters can be pre-stored. The initial parameters of the phase-locked loop (PLL) differ across different speed ranges. For instance: when the unit speed is between 800 rpm and 1000 rpm, the initial value of the proportional coefficient can be set to 0.8, and the initial value of the integral coefficient can be set to 0.05; when the speed is between 1000 rpm and 1200 rpm, the initial value of the proportional coefficient can be set to 0.6, and the initial value of the integral coefficient can be set to 0.08; when the speed is between 1200 rpm and 1400 rpm, the initial value of the proportional coefficient can be set to 0.5, and the initial value of the integral coefficient can be set to 0.10; when the speed is between 1400 rpm and 1500 rpm, the initial value of the proportional coefficient can be set to 0.4, and the initial value of the integral coefficient can be set to 0.12. Based on the current speed, the mapping is queried to determine the initial values ​​of the proportional and integral coefficients for the current commutation cycle.

[0052] Considering that the pumped storage unit's speed spans a wide range from zero to rated speed during startup and grid connection, the following considerations apply. At low speeds, the motor's back EMF is low, and the electrical time constant is large, requiring high response sensitivity to maintain stable tracking. At high speeds (close to synchronous speed), the motor's back EMF is high, the system tends to stabilize, and lower response sensitivity can be used to avoid overshoot. However, in related technologies, phase-locked loop (PLL) parameters are often fixed, failing to adapt to the different control requirements caused by speed variations, leading to speed overshoot during constant-speed control. This embodiment determines initial parameters based on segmented current speeds, enabling the PLL to have compatible control characteristics across different speed ranges, providing a reasonable benchmark for subsequent fine-tuning.

[0053] Step 206: Adjust the initial value according to the frequency change rate, harmonic distortion rate and phase difference to obtain the target value of the control parameters of the phase-locked loop in the current commutation cycle; wherein, the response sensitivity is negatively correlated with the harmonic distortion rate, and the error elimination speed is positively correlated with the frequency change rate.

[0054] The adjustment of the proportional gain follows the principle of being negatively correlated with the harmonic distortion rate. Specifically, when the grid harmonic distortion rate is high, the grid voltage waveform is severely distorted. If the proportional gain is too large, the phase-locked loop (PLL) will over-respond to the phase jitter caused by harmonics, leading to unstable output. Therefore, the proportional gain needs to be reduced according to the harmonic distortion rate. For example, one or more harmonic distortion rate thresholds can be set. For instance, when the harmonic distortion rate does not exceed 3%, the proportional gain remains unchanged at its initial value; when the harmonic distortion rate is between 3% and 6%, the proportional gain is adjusted to 0.8 times the initial value; and when the harmonic distortion rate exceeds 6%, the proportional gain is adjusted to 0.5 times the initial value.

[0055] The adjustment of the integral coefficient follows the principle of positive correlation with the frequency change rate. Specifically, when the grid frequency change rate is large, it indicates that the grid frequency is fluctuating rapidly. In this case, it is necessary to increase the integral coefficient to accelerate the phase-locked loop's tracking speed of frequency changes and avoid the accumulation of phase errors. For example, one or more frequency change rate thresholds can be set. For instance, when the absolute value of the frequency change rate does not exceed 1 Hz / s, the integral coefficient remains unchanged at its initial value; when the absolute value of the frequency change rate is between 1 Hz / s and 3 Hz / s, the integral coefficient is adjusted to 1.2 times the initial value; when the absolute value of the frequency change rate exceeds 3 Hz / s, the integral coefficient is adjusted to 1.5 times the initial value.

[0056] In this embodiment, the phase difference can be used as the main input quantity for the closed-loop regulation of the phase-locked loop (PLL). Specifically, within each commutation cycle, the PLL calculates the output regulation quantity based on the current phase difference, combined with the adjusted proportional and integral coefficients, using a proportional-integral control law: the proportional regulation component equals the proportional coefficient multiplied by the current phase difference, the integral regulation component equals the integral coefficient multiplied by the cumulative integral value of the phase difference, and the total regulation quantity is the sum of the two. This total regulation quantity is used to adjust the voltage phase command output by the PLL, so that the inverter output voltage gradually approaches the phase of the grid voltage.

[0057] In related technologies, phase-locked loop (PLL) parameters are typically adjusted proportionally and integrally based solely on the phase difference, neglecting the impact of grid quality (e.g., harmonic distortion rate) and grid stability (e.g., frequency change rate) on control performance. When grid quality is poor, a fixed proportional coefficient, or one adjusted solely based on the phase difference, can lead to excessive harmonic response and phase jitter in the PLL. Conversely, when the grid frequency fluctuates drastically, a fixed integral coefficient can cause frequency tracking lag, resulting in steady-state phase error. Therefore, this embodiment introduces the frequency change rate and harmonic distortion rate as constraints into the PLL parameter adjustment process, enabling the PLL to adaptively respond to changes in grid operating conditions: actively reducing response sensitivity to avoid oscillations when harmonic distortion is severe, and actively increasing error elimination speed to accelerate tracking when the frequency fluctuates drastically. Simultaneously, the phase difference is used as the primary control variable for closed-loop tracking.

[0058] Step 208: Perform commutation control on the frequency converter for the current commutation cycle according to the target value, and determine the commutation margin deviation of the frequency converter for the current commutation cycle based on the commutation performance of the frequency converter and the commutation performance standard for the current commutation cycle.

[0059] Commutation control refers to the process of sending trigger pulses to the thyristors in the static inverter according to the phase command output by the phase-locked loop and the set trigger sequence and trigger angle, so that the current is transferred from one thyristor to the next, thereby enabling the static inverter to achieve frequency conversion output.

[0060] Commutation performance refers to physical quantities measured during actual commutation control, reflecting the actual commutation effect. For example, commutation performance can include the commutation overlap angle and the actual current fall time. The commutation overlap angle refers to the phase angle corresponding to the time between the previous thyristor being fully turned off and the next thyristor starting to conduct during commutation; the actual current fall time refers to the time difference between the issuance of the turn-off trigger signal and the thyristor current dropping to a certain percentage (e.g., 10%) of its rated value.

[0061] Commutation performance standards refer to standard values ​​obtained through theoretical calculations based on current operating parameters, serving as a benchmark for measuring commutation performance. For example, commutation performance standards may include theoretical commutation overlap angles, which can be calculated using commutation equations based on the current value, DC bus voltage value, motor synchronous reactance, and angular frequency of the current commutation cycle.

[0062] Commutation margin deviation refers to the difference between commutation performance and the standard commutation performance, reflecting the degree of leeway or stress in the commutation process. For example, commutation margin deviation can be expressed as the difference between the commutation overlap angle and the theoretical commutation overlap angle.

[0063] During commutation control execution, the thyristor current waveform is acquired via a current transformer. The time window of commutation overlap is identified from the current waveform, and the corresponding phase angle is calculated to obtain the commutation overlap angle. Simultaneously, based on the currently acquired current value, DC bus voltage value, and pre-stored motor synchronous reactance parameters, the theoretical commutation overlap angle is calculated using the commutation equation. Subtracting the theoretical commutation overlap angle from the theoretical commutation overlap angle yields the commutation margin deviation.

[0064] In this embodiment, a commutation margin deviation of zero indicates that the commutation process is consistent with theoretical expectations and the commutation margin is moderate. A positive commutation margin deviation indicates that the commutation overlap angle is greater than the theoretical value, the commutation process is too slow, and the commutation margin is too large. A negative commutation margin deviation indicates that the commutation overlap angle is less than the theoretical value, the commutation process is too tight, the commutation margin is too small, and there is a risk of commutation failure. For example, if the theoretical commutation overlap angle is 8° and the commutation overlap angle is 10°, then the commutation margin deviation is +2°, indicating that the commutation is too slow; if the commutation overlap angle is 6°, then the commutation margin deviation is -2°, indicating that the commutation is too tight.

[0065] In related technologies, commutation control typically operates according to a preset trigger angle, lacking a mechanism for evaluating the actual effect of the commutation process. Therefore, when operating conditions change (such as load fluctuations or temperature variations causing thyristor characteristic drift), the commutation overlap angle deviates from the theoretical value. However, the control system cannot detect this deviation, leading to a gradual deterioration of the commutation process until commutation failure. This embodiment quantifies the commutation margin deviation by acquiring the actual current waveform after each commutation, extracting the commutation overlap angle, and comparing it with the theoretically calculated value. This deviation provides quantitative feedback for parameter correction in subsequent steps, enabling the control system to perceive the quality of the commutation process and achieving a leap from open-loop execution to closed-loop perception.

[0066] Step 210: Adjust the initial values ​​of the control parameters of the phase-locked loop for the next commutation cycle according to the commutation margin deviation, until the pumped storage unit is connected to the grid.

[0067] The adjustment rules for the initial values ​​of the control parameters of the phase-locked loop (PLL) in the next commutation cycle can be as follows: When the commutation margin deviation is positive (i.e., commutation is too slow), it indicates that the current proportional coefficient is too large, causing the PLL response to be too fast, and the initial value of the proportional coefficient for the next commutation cycle needs to be reduced. For example, the current initial value of the proportional coefficient can be multiplied by a factor less than 1 (e.g., 0.9) as the initial value of the proportional coefficient for the next cycle. When the commutation margin deviation is negative (i.e., commutation is too tight), it indicates that the current proportional coefficient is too small, causing the PLL response to be insufficient, and the initial value of the proportional coefficient for the next commutation cycle needs to be increased. For example, the current initial value of the proportional coefficient can be multiplied by a factor greater than 1 (e.g., 1.1) as the initial value of the proportional coefficient for the next cycle. Correspondingly, when the commutation margin deviation is zero or close to zero, it indicates that the current parameters are appropriate, and the initial value of the proportional coefficient remains unchanged. The integral coefficient can also be adjusted similarly according to the commutation margin deviation, or the adjustment result determined by the frequency change rate can be kept unchanged.

[0068] At the start of the next commutation cycle, the control system repeats the above steps: using the adjusted initial values ​​of the phase-locked loop parameters, it re-acquires the grid characteristic parameters, adjusts the parameters again based on the new grid characteristics, executes commutation control, evaluates the new commutation margin deviation, and continues to provide feedback correction. This iterative process continues. Therefore, when the commutation margin deviation of multiple consecutive commutation cycles (e.g., 10 consecutive cycles) converges to the preset allowable range (e.g., between -1° and +1°), and the deviations of the unit's voltage, frequency, and phase from the grid meet the grid connection conditions (e.g., voltage deviation not exceeding 5%, frequency deviation not exceeding 0.1Hz, and phase deviation not exceeding 3°), the control system determines that the grid connection conditions are met, issues a circuit breaker closing command, and the pumped storage unit is officially connected to the grid.

[0069] In related technologies, commutation margin deviation is only used for protection judgment in case of commutation failure (i.e., triggering shutdown when the deviation is too large), and not for active adjustment of control parameters. This passive protection mode can only respond after a fault occurs and cannot prevent the deterioration of commutation quality. This embodiment uses the commutation margin deviation as a feedback signal, which is sent back to the parameter adjustment stage of the phase-locked loop to construct a complete closed-loop control system. When the commutation is too tight (the deviation is negative), the proportional coefficient is increased to speed up the response; when the commutation is too slow (the deviation is positive), the proportional coefficient is decreased to suppress overshoot. Through this continuous iteration, the commutation margin deviation is continuously converged to the ideal range, and the commutation process is always kept in the optimal state.

[0070] This embodiment adjusts the phase-locked loop (PLL) parameters feedforward based on grid operating conditions (frequency change rate, harmonic distortion rate) and corrects them feedback-based based on commutation performance (commutation margin deviation). This allows the PLL parameters to adapt to changes in the grid environment while optimizing commutation execution quality. By collecting grid characteristics and phase errors, this embodiment determines the initial parameters for speed adaptation, adaptively adjusts the PLL parameters based on grid characteristics, executes commutation, quantifies the commutation performance deviation, and feeds back the deviation to the initial parameter values ​​for the next cycle. Compared to related technologies that use fixed parameters or only open-loop adjustments, this embodiment effectively suppresses speed overshoot during the constant speed control phase by continuously correcting the PLL parameters through commutation margin deviation. During the natural commutation phase, an effective regulation mechanism is established through commutation performance evaluation and feedback adjustment, significantly improving speed control accuracy and greatly shortening grid connection time.

[0071] In some embodiments, the response sensitivity includes a proportional coefficient of the phase-locked loop, which is used to proportionally map the current value of the phase difference to an adjustment amount of the phase-locked loop output; the error elimination speed includes an integral coefficient of the phase-locked loop, which is used to map the cumulative integral value of the phase difference to an adjustment amount of the phase-locked loop output.

[0072] The step of adjusting the initial value based on the frequency change rate, harmonic distortion rate, and phase difference to obtain the target value of the phase-locked loop control parameters in the current commutation cycle includes:

[0073] Based on the comparison result between the harmonic distortion rate and the first preset threshold, the proportional coefficient is adjusted to obtain the adjusted proportional coefficient; wherein, the adjusted proportional coefficient is negatively correlated with the harmonic distortion rate;

[0074] Based on the comparison result between the frequency change rate and the second preset threshold, the integral coefficient is corrected to obtain the adjusted integral coefficient; wherein, the adjusted integral coefficient is positively correlated with the frequency change rate;

[0075] Calculate the proportional adjustment component based on the current value of the phase difference and the adjusted proportional coefficient;

[0076] The integral adjustment component is calculated based on the cumulative integral value of the phase difference and the adjusted integral coefficient.

[0077] The proportional adjustment component and the integral adjustment component are used to determine the target adjustment amount for the initial value.

[0078] Specifically, the response sensitivity can be considered as the proportional gain of the phase-locked loop (PLL). This proportional gain maps the current value of the phase difference proportionally to the adjustment amount of the PLL output. It can be understood that the proportional gain determines the magnitude of the PLL's response to instantaneous phase errors: a larger proportional gain results in a higher amplification factor for the current phase error and a faster response, but it is more prone to oscillations; a smaller proportional gain results in a smoother response, but a slower tracking speed.

[0079] The speed of error elimination is specifically reflected in the integral coefficient of the phase-locked loop (PLL). This integral coefficient maps the cumulative integral value of the phase difference to the adjustment amount of the PLL output. It can be understood that the integral coefficient determines the PLL's ability to eliminate long-term accumulated phase errors: a larger integral coefficient results in faster elimination of steady-state phase errors but is more prone to overshoot; a smaller integral coefficient results in slower elimination but greater stability, however, an excessively small integral coefficient may prevent the steady-state error from being completely eliminated.

[0080] The adjusted proportional coefficient is negatively correlated with the harmonic distortion rate. Considering that when the grid harmonic distortion rate is high, the grid voltage waveform distortion is severe, and if the proportional coefficient is too large, the phase-locked loop will over-respond to the phase jitter caused by harmonics, leading to unstable output. Therefore, the proportional coefficient needs to be reduced according to the harmonic distortion rate. For example, one or more harmonic distortion rate thresholds can be set. For instance, a first preset threshold of 3% can be set. When the harmonic distortion rate does not exceed 3%, the proportional coefficient remains unchanged at its initial value; when the harmonic distortion rate exceeds 3%, the proportional coefficient is reduced by a preset step size. Optionally, multiple thresholds can be set; for example, when the harmonic distortion rate is between 3% and 6%, the proportional coefficient is adjusted to 0.8 times the initial value; when the harmonic distortion rate exceeds 6%, the proportional coefficient is adjusted to 0.5 times the initial value.

[0081] Considering that a large rate of change in grid frequency indicates rapid fluctuations in the grid frequency, it is necessary to increase the integral coefficient to accelerate the phase-locked loop's (PLL) tracking speed and prevent the accumulation of phase errors. For example, one or more frequency change rate thresholds can be set. For instance, a second preset threshold can be set to 1 Hz / s. When the absolute value of the frequency change rate does not exceed 1 Hz / s, the integral coefficient remains unchanged at its initial value; when the absolute value of the frequency change rate exceeds 1 Hz / s, the integral coefficient is increased by a preset step size. Optionally, multiple thresholds can be set. For example, when the absolute value of the frequency change rate is between 1 Hz / s and 3 Hz / s, the integral coefficient is adjusted to 1.2 times the initial value; when the absolute value of the frequency change rate exceeds 3 Hz / s, the integral coefficient is adjusted to 1.5 times the initial value.

[0082] The proportional adjustment component equals the adjusted proportional coefficient multiplied by the current phase difference. This component reflects the phase-locked loop's immediate response to the current instantaneous error. The integral adjustment component is calculated based on the cumulative integral value of the phase difference and the adjusted integral coefficient. Specifically, the integral adjustment component equals the adjusted integral coefficient multiplied by the cumulative integral value of the phase difference over time. This component reflects the phase-locked loop's ability to eliminate long-term accumulated errors.

[0083] The proportional adjustment component and the integral adjustment component are added together to determine the target adjustment amount for the initial value. This target adjustment amount is the phase adjustment command output by the phase-locked loop, used to correct the phase of the static inverter's output voltage, gradually bringing it closer to the phase of the grid voltage. For example, suppose the phase difference of the current commutation cycle is 0.05 rad (approximately 2.86°), the harmonic distortion rate is 4%, the frequency change rate is 2 Hz / s, the initial value of the proportional coefficient is 0.5, and the initial value of the integral coefficient is 0.10. Based on the harmonic distortion rate of 4% exceeding 3% but not exceeding 6%, the proportional coefficient is adjusted to 0.5 × 0.8 = 0.4. Based on the frequency change rate of 2 Hz / s being between 1 Hz / s and 3 Hz / s, the integral coefficient is adjusted to 0.10 × 1.2 = 0.12. Assuming the cumulative integral of the phase difference is 0.2 rad·s, the proportional adjustment component is 0.4 × 0.05 = 0.02, the integral adjustment component is 0.12 × 0.2 = 0.024, and the target adjustment is 0.02 + 0.024 = 0.044 rad. This target adjustment is applied to the output phase command of the phase-locked loop, causing the phase of the static inverter output voltage to be adjusted forward by 0.044 rad.

[0084] In related technologies, the proportional and integral coefficients of a phase-locked loop (PLL) are either fixed values ​​or adjusted based on a single parameter (such as phase difference), making it difficult to distinguish the different roles of proportional and integral regulation and to cope with the combined effects of power grid quality changes and frequency fluctuations. This embodiment explicitly decouples the proportional and integral coefficients and establishes adjustment rules for them with harmonic distortion rate (negative correlation) and frequency change rate (positive correlation), respectively, achieving independent adaptive adjustment of the two coefficients: the proportional coefficient primarily addresses power grid quality changes, automatically reducing response sensitivity when harmonics are severe; the integral coefficient primarily addresses power grid stability changes, automatically increasing tracking speed when frequency fluctuations are severe. Both perform their respective functions and cooperate with each other. Simultaneously, by calculating the proportional and integral regulation components separately and adding them together to determine the target regulation amount, this embodiment maintains the complete structure of the proportional-integral control law, enabling the PLL to respond quickly to instantaneous errors and completely eliminate steady-state errors. This achieves fast, stable, and error-free phase tracking in the complex and variable power grid conditions of pumped-storage grid-connected systems.

[0085] In some embodiments, the commutation performance standard includes the theoretical commutation overlap angle of the frequency converter; the step of performing commutation control on the frequency converter for the current commutation cycle according to the target value, and determining the commutation margin deviation of the frequency converter for the current commutation cycle based on the commutation performance of the frequency converter and the commutation performance standard for the current commutation cycle, includes:

[0086] During the turn-off process of multiple switching structures within the frequency converter, the commutation overlap angle of the multiple switching structures is determined;

[0087] The theoretical commutation overlap angle is determined based on the voltage signal of the power grid during the current commutation cycle and the configuration parameters of the pumped storage unit.

[0088] The commutation overlap angle is compared with the theoretical commutation overlap angle to obtain the commutation margin deviation;

[0089] The step of adjusting the initial values ​​of the control parameters of the phase-locked loop for the next commutation cycle based on the commutation margin deviation includes:

[0090] When the commutation margin deviation is positive, decrease the initial value of the response sensitivity for the next commutation cycle;

[0091] When the commutation margin deviation is negative, the initial value of the response sensitivity for the next commutation cycle is increased.

[0092] The commutation performance standard includes the theoretical commutation overlap angle of the frequency converter. The commutation overlap angle refers to the phase angle corresponding to the time between the previous thyristor being fully turned off and the next thyristor starting to conduct during the commutation process. The theoretical commutation overlap angle can be a standard value calculated theoretically based on current operating parameters, used as a benchmark to measure actual commutation performance. The commutation margin deviation is the difference between the commutation overlap angle and the theoretical commutation overlap angle, reflecting the degree of leeway or tension in the commutation process. When the commutation overlap angle is greater than the theoretical commutation overlap angle, the commutation margin deviation is positive, indicating that the commutation process is too slow and the commutation margin is too large; when the commutation overlap angle is less than the theoretical commutation overlap angle, the commutation margin deviation is negative, indicating that the commutation process is too tight, the commutation margin is too small, and there is a risk of commutation failure; when the two are equal, the commutation margin deviation is zero, indicating that the commutation process is consistent with theoretical expectations.

[0093] In this embodiment, the switching structure refers to the thyristors in the static inverter. During commutation control, the thyristor current waveform is acquired via a current transformer. The commutation overlap time window is identified from the current waveform: specifically, the moment when the previous thyristor current begins to decrease and the moment when the next thyristor current fully establishes are recorded, and the time interval between these two moments is calculated. Multiplying this time interval by the current angular frequency yields the phase angle corresponding to that time interval, which is the commutation overlap angle.

[0094] For example, suppose the acquired current waveform shows that the time when the previous thyristor current begins to decrease is t1, and the time when the next thyristor current is fully established is t2. The time interval Δt = t2 - t1 = 0.5 ms, the current angular frequency ω = 100π rad / s (corresponding to 50 Hz), and the commutation overlap angle μ_actual = ω × Δt = 100π × 0.0005 = 0.157 rad, which is approximately 9°.

[0095] The theoretical commutation overlap angle can be calculated using the commutation equation based on the current value, DC bus voltage value, motor synchronous reactance, and angular frequency of the current commutation cycle. The commutation equation reflects the quantitative relationship between the angle required for current transfer during thyristor commutation and the electrical parameters. For example, the formula for calculating the theoretical commutation overlap angle μ_theoretical can be expressed as: μ_theoretical = arccos(1 - (2ωX_d·I) / (√2·U_dc)), where ω is the current angular frequency, X_d is the motor synchronous reactance, I is the current value of the current commutation cycle, and U_dc is the DC bus voltage value. Assuming the current angular frequency ω = 100π rad / s, the motor synchronous reactance X_d = 0.2Ω, the current value I = 500A, and the DC bus voltage value U_dc = 1000V, then substituting these values ​​into the formula yields μ_theoretical ≈ 8°.

[0096] The commutation margin deviation Δμ equals the commutation overlap angle minus the theoretical commutation overlap angle. Continuing the example above, if the commutation overlap angle μ_actual = 9° and the theoretical commutation overlap angle μ_theoretical = 8°, then the commutation margin deviation Δμ = 9° - 8° = +1°, indicating that the commutation process is slightly slower than expected by about 1°. If the commutation overlap angle is 7°, then the commutation margin deviation Δμ = 7° - 8° = -1°, indicating that the commutation process is slightly slower than expected by about 1°.

[0097] When the commutation margin deviation is positive, the initial value of the response sensitivity for the next commutation cycle is decreased; when the commutation margin deviation is negative, the initial value of the response sensitivity for the next commutation cycle is increased. Considering that the commutation margin deviation reflects the influence of the current phase-locked loop (PLL) parameters on the commutation process: when the commutation margin deviation is positive (i.e., commutation is too slow), it indicates that the current proportional gain is too large, causing the PLL response to be too fast, making the commutation process too loose. Therefore, the initial value of the proportional gain for the next commutation cycle needs to be decreased to tighten the commutation process. When the commutation margin deviation is negative (i.e., commutation is too tight), it indicates that the current proportional gain is too small, causing the PLL response to be insufficient. Therefore, the initial value of the proportional gain for the next commutation cycle needs to be increased to speed up the commutation process.

[0098] For example, when the commutation margin deviation Δμ = +1°, it indicates that the commutation is too slow. The current initial value of the proportional coefficient can be multiplied by a factor less than 1 (e.g., 0.9) as the initial value of the proportional coefficient for the next commutation cycle. When the commutation margin deviation Δμ = -1°, it indicates that the commutation is too tight. The current initial value of the proportional coefficient can be multiplied by a factor greater than 1 (e.g., 1.1) as the initial value of the proportional coefficient for the next commutation cycle. When the commutation margin deviation is zero or close to zero, it indicates that the current parameters are appropriate, and the initial value of the proportional coefficient remains unchanged. At the beginning of the next commutation cycle, the control system uses the adjusted initial value of the proportional coefficient and repeats the steps described in Example 1. Through this continuous iteration, the commutation margin deviation is continuously converged to the ideal range, and the commutation process is always kept in an optimal state.

[0099] In related technologies, commutation margin deviation is only used for protection judgment of commutation failure (i.e., triggering shutdown when the deviation is too large), and not for active adjustment of control parameters. This passive protection mode can only respond after a fault occurs and cannot prevent the deterioration of commutation quality. This embodiment uses the commutation margin deviation as a feedback signal, which is sent back to the proportional coefficient adjustment stage of the phase-locked loop to construct a complete closed-loop control system. When the commutation is too tight (the deviation is negative), the proportional coefficient is increased to speed up the response; when the commutation is too slow (the deviation is positive), the proportional coefficient is decreased to suppress overshoot. By quantitatively comparing the commutation overlap angle with the theoretically calculated value, this embodiment transforms the qualitative judgment of commutation quality into a quantitative parameter correction command, so that the optimization of the commutation process has a clear direction and magnitude basis. Through this continuous iteration, the commutation margin deviation is continuously converged to the ideal range, and the commutation process is always kept in the optimal state, thereby effectively avoiding commutation failure and improving the stability of the grid connection process.

[0100] In some embodiments, the step of performing commutation control on the frequency converter for the current commutation cycle based on the target value includes:

[0101] Based on the current change rate and voltage phase of the switching structure of the frequency converter, a feedforward compensation algorithm is used to calculate the trigger angle correction, and the trigger angle correction is superimposed on the reference trigger angle of the current commutation trigger to obtain the target trigger angle for the switching structure; wherein, the feedforward compensation algorithm is used to compensate for the response delay during the switching process of the switching structure;

[0102] During the turn-off process of the switch structure, the current drop time of the frequency converter is determined and compared with a standard drop time;

[0103] When the deviation between the current drop time and the standard drop time exceeds a third preset threshold, it is determined that the frequency converter is abnormal, and at least one of the following is executed: generating a warning message, reducing the switching frequency of subsequent commutation cycles, and prompting a shutdown.

[0104] The firing angle refers to the delay angle between the natural commutation point and the emission of the thyristor firing pulse. Its magnitude directly affects the timing and effectiveness of the commutation process. The firing angle correction is an adjustment value of the reference firing angle, used to compensate for various response delays during the thyristor switching process.

[0105] Considering the mechanical response delays during thyristor switching, such as turn-off delays caused by the internal carrier storage effect, and potential electrical response delays, such as drive circuit transmission delays and current rate-of-change limitations, these delays can cause the actual commutation time to deviate from the theoretically calculated time, thus affecting commutation accuracy. Without compensation, accumulated delay errors may cause the commutation margin to gradually deviate from the ideal range, increasing the risk of commutation failure.

[0106] The rate of change of current refers to the rate at which the thyristor current changes over time, measured in A / s. A larger rate of change indicates more drastic current transfer, resulting in a longer turn-off time and necessitating a corresponding increase in the firing angle correction to advance the triggering. Voltage phase refers to the instantaneous phase of the grid voltage or inverter output voltage at the current moment. It is used to determine the accurate location of the natural commutation point, ensuring that the firing angle correction is superimposed on the natural commutation point. For example, if the reference firing angle for the current commutation cycle is 15°, and the rate of change of current di / dt = 200 A / μs, the voltage phase indicates that there is still a 5° electrical angle remaining from the natural commutation point. The feedforward compensation algorithm calculates a firing angle correction of +2° based on pre-calibrated delay characteristics—such as the correspondence between the thyristor turn-off delay and the rate of change of current. Therefore, the target firing angle = 15° + 2° = 17°. The control system issues a firing pulse at a firing angle of 17°, ensuring that the thyristor completes commutation at the desired commutation time after accounting for response delay. It is understandable that the feedforward compensation algorithm is different from feedback compensation: feedback compensation needs to be adjusted after the deviation occurs, which has a lag; while feedforward compensation predicts the required correction amount in advance based on the current operating parameters (current change rate, voltage phase), and completes the compensation before the deviation occurs, thereby effectively offsetting the response delay in the thyristor switching process.

[0107] The current fall time refers to the time difference between the issuance of the turn-off trigger signal and the thyristor current dropping to a certain percentage (e.g., 10%) of its rated value. This time reflects the thyristor's turn-off characteristics and is an important indicator for assessing the thyristor's health. The standard fall time can be the nominal value specified by the thyristor at the manufacturer's specifications or a historical benchmark value established during normal system operation. For example, during the thyristor turn-off process, the thyristor current waveform is captured by a current transformer at a sampling rate of no less than 10kHz. The time t_off when the turn-off trigger signal is issued and the time t_10% when the current waveform drops to 10% of the rated value are recorded. Then, the current fall time t_fall = t_10% - t_off. Assuming the standard fall time is 50μs and the measured current fall time is 65μs, the deviation is 15μs.

[0108] In this embodiment, considering that the thyristor may age after long-term operation, its turn-off characteristics will change, manifested as a prolonged current fall time. When the current fall time deviates significantly from the standard value, continued operation at the normal switching frequency may lead to commutation failure or even device damage. Therefore, it is necessary to set an allowable deviation range (i.e., a third preset threshold). When the deviation exceeds this range, an anomaly is determined and corresponding measures are taken. For example, the third preset threshold can be set to 20% of the standard fall time. If the standard fall time is 50μs, then the allowable deviation range is ±10μs. The measured current fall time t_fall = 65μs, with a deviation of 15μs, exceeding the allowable range of 10μs, indicating that the thyristor is aging or has a driving anomaly.

[0109] Specifically, depending on the severity of the deviation, the control system can perform one or a combination of the following operations: generate an early warning message, such as displaying "Thyristor A turn-off time is abnormal, maintenance recommended" on the operation interface to remind maintenance personnel to pay attention. Optionally, the switching frequency of subsequent commutation cycles can be reduced, for example, reducing the switching frequency from the rated value to 80% of the rated value, to reduce the switching stress on the thyristor and prevent the fault from worsening. Optionally, a shutdown prompt can also be issued, suggesting that maintenance be arranged at an appropriate time. For example, when the deviation exceeds twice the third preset threshold (e.g., the measured current drop time exceeds 70μs), the control system can perform a "shutdown prompt" operation; when the deviation is between one and two times the third preset threshold, the "generate early warning message" and "reduce switching frequency" operations are performed.

[0110] This embodiment compensates for the response delay at the trigger moment using a feedforward compensation algorithm, making the actual commutation time closer to the theoretical expected time and improving the accuracy of commutation control. Compared with schemes that rely solely on feedback compensation, feedforward compensation can predict deviations in advance and actively correct them, resulting in faster response speed and less hysteresis. Simultaneously, this embodiment achieves online diagnosis of the thyristor's health status by monitoring the current fall time and comparing it with standard values. When an anomaly is detected, the system can respond in stages: for minor anomalies, it issues a warning and reduces the switching frequency to slow the fault development; for severe anomalies, it prompts a shutdown to prevent accidents. This staged response mechanism ensures both system availability (avoiding immediate shutdown) and equipment safety, such as timely intervention in severe cases, realizing an evolution from post-fault protection to pre-fault warning.

[0111] In some embodiments, the response to the grid connection triggering event of the pumped storage unit includes:

[0112] Receive control commands from the host computer to start or control the grid connection process;

[0113] Based on the current unit status and the content of the control command, an internal mathematical model is invoked to generate a virtual response signal, which represents the expected operating trajectory of the system after the control command is executed.

[0114] The virtual response signal is matched and verified with the expected behavior pattern, wherein the expected behavior pattern is a standard response curve pre-stored based on historical normal operation data and equipment parameters;

[0115] If the match is successful, the control command is confirmed to be valid and executed.

[0116] If the matching fails, it is determined that the control command has been distorted during transmission, and a request is made to the host computer to resend the command, and a communication error log is recorded.

[0117] In response to the grid connection triggering event of a pumped-storage unit, the system may not simply forward the host computer command directly to the actuator. Instead, it may first verify the validity of the command itself. This prevents the control command from being distorted during transmission due to electromagnetic interference, communication failures, or other reasons, which could lead to erroneous actions by the frequency converter. Considering that the static frequency converters in pumped-storage power stations are typically installed in strong electromagnetic environments (such as near high-power switching devices), control commands transmitted from the host computer to the controller via fieldbus (such as RS485, CAN, Ethernet, etc.) may be subject to electromagnetic interference, resulting in bit flips or data packet corruption. In related technologies, control systems typically lack a verification mechanism for the command itself, and distorted commands may be executed incorrectly, leading to serious consequences such as speed control failure or commutation failure.

[0118] The system receives control commands from the host computer to initiate or control the grid connection process. These commands can be grid connection start commands, target speed setting commands, acceleration setting commands, or other parameter configuration commands related to the grid connection process. For example, the host computer issues a control command stating "target speed 1500 rpm, acceleration 5 rpm / s²". The control system receives the data packet containing this command via the Ethernet interface.

[0119] The internal mathematical model is a pre-established state equation or simulation model based on the physical parameters of the pumped storage unit (such as moment of inertia, motor constants, load characteristics, etc.). This model can calculate and predict the system's expected behavior over a future period based on the current state (such as current speed, current current, current phase) and input commands (such as target speed, acceleration). For example, suppose the current unit speed is 1420 rpm, and the received control command is "target speed 1500 rpm, acceleration 5 rpm / s²". Based on the moment of inertia J = 1000 kg·m², rated torque, and other information, the internal mathematical model simulates and calculates that it takes approximately 16 seconds to accelerate from 1420 rpm to 1500 rpm, during which the speed smoothly increases according to the preset acceleration, reaching 1500 rpm at t = 16 seconds without overshoot. The system generates a virtual "speed-time" curve as a virtual response signal, which includes a series of time points and their corresponding expected speed values.

[0120] The expected behavior pattern is a separate benchmark independent of the internal mathematical model. It can be a standard response curve obtained from historical operating data of similar units, or an ideal response trajectory pre-calibrated based on theoretical analysis and field testing. The purpose of the expected behavior pattern is to serve as a third-party verification benchmark, preventing misjudgments caused by biases in the internal mathematical model or incorrect parameter settings. For example, the expected behavior pattern stores a standard response curve: under an acceleration of 5 rpm / s², the standard time to accelerate from 1420 rpm to 1500 rpm is between 15.8 and 16.2 seconds, with a smooth speed increase and no overshoot. The control system compares the virtual response curve generated in step S506 with this standard response curve to check whether key characteristic points (such as acceleration time, peak speed, and acceleration gradient) are within the allowable deviation range.

[0121] A successful match indicates that the consistency between the virtual response signal and the expected behavior pattern is within a preset deviation range, suggesting that the received control command is physically reasonable, complete, and undistorted. If the match fails, it is determined that the control command has been distorted during transmission, a request is made to the host computer to retransmit the command, and a communication anomaly log is recorded. Match failures may manifest as: a significant deviation of the acceleration time from the standard range (e.g., calculation requires 30 seconds, the standard is 16 seconds), or expected overshoot (no overshoot in the standard), or abnormal fluctuations during the speed increase. For example, if the received command is distorted due to electromagnetic interference, becoming "target speed 1500 rpm, acceleration 50 rpm / s²", the acceleration time calculated by the internal mathematical model will be much smaller than the standard value (e.g., only 1.6 seconds), and a severe overshoot is expected. The virtual response signal was clearly mismatched with the expected behavior pattern (smooth rise, no overshoot, acceleration time of about 16 seconds). The control system determined that the instruction was distorted and did not execute the instruction. Instead, it returned a message to the host computer that "instruction verification failed, request retransmission" and recorded this anomaly in the communication anomaly log for subsequent troubleshooting.

[0122] In related technologies, control commands are transmitted unidirectionally, making it impossible for the receiver to determine if the command has been distorted during transmission. Executing an incorrect command could lead to serious consequences. This embodiment establishes a bidirectional command verification mechanism. Before executing a command, an expected response is generated using an internal mathematical model and compared with an independently stored expected behavior pattern to determine the command's validity. In this embodiment, the virtual response signal and the expected behavior pattern constitute dual verification: the virtual response signal is dynamically calculated based on a physical model, adapting to current operating conditions; the expected behavior pattern is pre-stored based on historical data, providing an independent verification benchmark. Thus, this embodiment ensures both the flexibility (adapting to changes in operating conditions) and the reliability (with an independent reference benchmark) of verification. When verification fails, the system can proactively request a retransmission instead of blindly executing, effectively preventing malfunctions caused by command distortion and improving the safety and reliability of the grid connection process.

[0123] In some embodiments, adjusting the initial values ​​of the control parameters of the phase-locked loop for the next commutation cycle based on the commutation margin deviation includes:

[0124] In response to the completion of grid connection of the pumped storage unit, the current rotor position, current phase, and phase-locked loop parameters of the frequency converter are saved to non-volatile memory.

[0125] The residual energy on the DC bus of the frequency converter is calculated, and the output power is reduced in a linear decreasing manner while the residual energy is transferred to the standby load through the braking unit.

[0126] When the output current of the frequency converter drops to the rated value, the frequency converter is disconnected from the power grid.

[0127] The process of decommissioning the frequency converter (FD) equipment is initiated in response to the completion of grid connection of the pumped storage unit. The completion of grid connection can be indicated by a circuit breaker closing signal, a synchronization success signal from the grid connection detection device, or a grid connection completion command issued by the control system after the voltage, frequency, and phase deviations have converged to the allowable range. The goal of the FD equipment decommissioning process is to safely isolate the static frequency converter from the power grid and the unit without generating electrical shocks or affecting the normal operation of the unit, allowing the unit to continue operating directly driven by the power grid, while the FD equipment enters standby or shutdown mode.

[0128] Considering that in related technologies, the process of shutting down frequency converter equipment usually involves directly cutting off the output or quickly shutting down, this abrupt shutdown method will generate voltage spikes on the DC bus and current surges on the output side, which may damage power devices. Furthermore, after shutdown, re-initialization is required before restarting, affecting the unit's ability to quickly respond to pumped storage dispatch commands.

[0129] Rotor position refers to the current angular position of the pumped-storage unit's rotor, typically measured by a photoelectric encoder or rotary transformer. Current phase refers to the phase angle of the inverter's output current relative to the voltage. Phase-locked loop (PLL) parameters refer to the proportional gain, integral gain, and frequency tracking value currently used by the PLL after the adaptive adjustment process described above. In this embodiment, the purpose of the state snapshot is to save a "snapshot" of the inverter equipment at the moment of grid connection completion. This allows the parameters to be restored from the snapshot when the static inverter needs to intervene again (e.g., when the pumped-storage unit switches from generation mode to pumping mode), eliminating the need to re-tune and self-test from scratch, thus shortening the preparation time for the next startup. For example, at the moment of grid connection completion, the rotor position is 135°, the current phase is 8°, the PLL proportional gain Kp = 0.42, the integral gain Ki = 0.15, and the current tracking frequency is 50.02Hz. The control system packages these data and writes them to a designated storage area in non-volatile memory (e.g., NOR FLASH or eMMC), overwriting the previously saved snapshot data.

[0130] The residual energy on the DC bus of the frequency converter is calculated, and while the output power is reduced linearly, the residual energy is transferred to the standby load through the braking unit. The residual energy on the DC bus originates from the electrical energy still stored in the DC bus capacitor after the frequency converter's output power gradually decreases. If left untreated, this energy will generate voltage spikes when the frequency converter cuts off the output, potentially damaging power devices. The calculation of residual energy is based on the capacitance of the DC bus capacitor and the current bus voltage. Let the capacitance of the DC bus capacitor be C, and the current bus voltage be U, then the stored energy E = ½·C·U². The braking unit is a circuit module in the frequency converter used to consume or transfer excess energy, typically including a braking resistor and a switching transistor. The standby load can be a braking resistor or other energy-absorbing devices (such as energy storage devices, auxiliary power supplies, etc.). Reducing the output power linearly means that the output power gradually decreases from its current value to zero at a fixed slope, rather than a step jump. This smooth power reduction allows energy on the DC bus to be transferred in a timely manner, avoiding sudden voltage spikes.

[0131] For example, suppose the current inverter output power is 500kW, the DC bus voltage is 1000V, and the capacitor value is 10mF. Then the stored energy E = 0.5 × 0.01 × 1000² = 5000J. The control system is set to a power decrease slope of -50kW / ms, meaning it takes 10ms for the output power to drop from 500kW to 0. During these 10ms, the braking unit operates synchronously, dissipating the energy released from the DC bus capacitor as heat in the braking resistor, thus stabilizing the bus voltage.

[0132] Output current is the effective value of the output current of the frequency converter. As the output power decreases linearly, the output current also decreases. When the output current drops below 2% of the rated value, it can be considered that the frequency converter has essentially stopped outputting power to the grid and the generating unit; disconnecting at this point will not generate an electric arc or surge. The rated value refers to the effective value of the output current of the frequency converter under rated operating conditions. For example, assuming the rated output current of the frequency converter is 1000A, when the output current drops below 20A (i.e., 2% of the rated value), the control system issues a tripping command to the circuit breaker. The circuit breaker performs the tripping action, disconnecting the electrical connection between the frequency converter and the grid, and the frequency converter is decommissioned.

[0133] After the frequency converter is decommissioned, its internal parameters are stored in non-volatile memory. When the static frequency converter needs to be restarted, the control system does not need to start self-testing and parameter tuning from scratch. It only needs to load the saved state snapshot to quickly restore the operating state before decommissioning, thus achieving rapid restart. This embodiment achieves uninterrupted decommissioning of the frequency converter through the coordinated operation of three links: state snapshot saving, residual energy transfer, and output current monitoring. State snapshot saving allows the optimized parameters obtained by the frequency converter through multiple rounds of adaptive adjustment in the current control cycle to be persisted, eliminating the need for retuning during the next startup and significantly shortening the preparation time for restarting. Residual energy transfer smoothly releases the energy in the DC bus capacitor through the braking unit, avoiding voltage spikes generated when directly cutting off the output and protecting the power devices. Output current monitoring ensures that the circuit breaker trips after the output current has dropped to a safe range, avoiding arcing caused by breaking under load and extending the service life of the circuit breaker. The above steps work together and are executed sequentially, making the decommissioning process of the frequency converter smooth, lossless, and recoverable, improving the overall reliability and rapid response capability of the system.

[0134] In some embodiments, the frequency converter includes a data processing unit, a data acquisition unit, a drive unit, a power supply unit, and a reset unit; wherein, the data processing unit includes at least one floating-point digital signal processor core and at least one data coprocessing unit, all cores being interconnected via a built-in multi-channel data bus; the data coprocessing unit performs logic control, auxiliary control, and external communication tasks; the floating-point digital signal processor core is used to perform control parameter adjustment and commutation control of the phase-locked loop; the data acquisition unit, drive unit, power supply unit, and reset unit are all connected to the data processing unit via the built-in multi-channel data bus;

[0135] The data processing unit has an external flash memory for storing fault record data, an external dynamic random access memory for running the operating system and applications, and an embedded multimedia card for storing critical operating data.

[0136] The driving unit converts the first-level pulse signal generated by the floating-point digital signal processor core into a second-level signal and outputs it.

[0137] The reset unit provides a continuous reset signal during system power-on and monitors the power supply voltage in real time. When the voltage drops below a fifth preset threshold, it outputs a protective blocking signal.

[0138] The data processing unit is the core computing and control center of the frequency converter, responsible for performing calculations such as phase-locked loop parameter adjustment, commutation control, and logic judgment. The data acquisition unit collects analog and digital signals such as grid voltage, grid current, motor voltage, motor current, temperature, and speed, converting them into digital signals recognizable by the data processing unit. The drive unit converts the low-level control signals generated by the data processing unit into high-level drive signals capable of driving thyristors or other power switching devices. The power supply unit provides different voltage levels of operating power to the data processing unit, data acquisition unit, drive unit, and reset unit. The reset unit restores each unit to its initial state upon system power-on or in case of an anomaly.

[0139] Floating-point digital signal processor (DSP) cores excel at performing high-precision floating-point arithmetic and complex digital signal processing algorithms, such as proportional-integral (PI) calculations for phase-locked loops (PLLs), fast Fourier transforms for harmonic analysis, and commutation equation solving. Data coprocessing units (such as ARM cores or other microcontroller cores) excel at performing tasks such as logic control, state management, and communication protocol stack processing. Both exchange data directly through a built-in multi-channel data bus, without needing an external interface, resulting in low latency and high bandwidth. For example, the data coprocessing unit is responsible for receiving control commands from the host computer, managing the startup sequence control process, and communicating with the human-machine interface—logic-intensive tasks; the floating-point DSP core is responsible for performing algorithm-intensive tasks such as PLL parameter calculations and commutation margin deviation calculations mentioned above. Both share data and status information through high-performance buses such as AHB or AXI. For example, the data coprocessing unit writes the received target speed parameter into the shared memory, and the floating-point DSP core reads the parameter from the shared memory for phase-locked loop calculation. The commutation margin deviation calculated by the floating-point DSP core is then sent back to the data coprocessing unit through the shared memory for status judgment and log recording.

[0140] In this embodiment, logic control includes startup sequence management, state machine maintenance, fault diagnosis and protection logic, etc. Auxiliary control includes auxiliary power management, fan control, indicator light control, etc. External communication tasks include protocol parsing and data transmission / reception with the host computer, human-machine interface, and other controllers. The data coprocessing unit is responsible for these tasks, fully utilizing its rich peripheral interfaces and mature software ecosystem. The floating-point DSP core is specifically used for phase-locked loop control parameter adjustment and commutation control, because these two types of tasks involve a large number of real-time floating-point operations (such as trigonometric functions, integral operations, FFT, etc.), requiring high computational accuracy and real-time performance, making them suitable for execution by the floating-point DSP core.

[0141] The data acquisition unit transmits acquired data such as voltage, current, temperature, and rotational speed to the data processing unit via a data bus. The drive unit receives trigger pulse parameters generated by the data processing unit via the data bus. The power supply unit and reset unit report their own status (such as whether the voltage is stable and whether the reset is complete) to the data processing unit via the data bus and can receive configuration commands from the data processing unit. In this embodiment, all units are connected to the data processing unit via the same data bus, rather than each unit connecting independently. This connection method simplifies system wiring and reduces potential failure points introduced by connectors and cables.

[0142] Flash memory (such as NOR FLASH) features fast read / write speeds and direct code execution, making it suitable for storing fault log data. Dynamic random access memory (DRAM) offers large capacity and fast read / write speeds, making it suitable as memory for running operating systems and applications. Embedded multimedia cards (eMMC) offer large capacity and bad block management and wear leveling capabilities, making them suitable for long-term storage of critical operational data (such as historical operational statistics, parameter configurations, and status snapshots). In this embodiment, the three types of memory have clearly defined roles: NOR FLASH stores fault logs with high frequency and limited write cycles; DRAM serves as runtime memory; and eMMC stores large-capacity critical data that needs to be stored long-term. This division of labor ensures reliable storage of critical data while optimizing storage costs.

[0143] The control signals generated by the floating-point DSP core are typically 3.3V, while the standard level required for thyristor gate drive is usually 15V or higher. The drive unit is responsible for performing this level conversion. In addition, the drive unit can also implement protection functions such as hardware dead-time control (preventing shoot-through of upper and lower bridge arms) and minimum pulse width control (preventing narrow pulses from causing unreliable thyristor conduction). For example, if the PWM pulse generated by the floating-point DSP core is 3.3V with a pulse width of 10μs, the drive unit converts this signal to 15V with a pulse width of 10μs before outputting it to the thyristor gate drive circuit, ensuring reliable thyristor conduction.

[0144] Considering the time required for the establishment of different power rails during power-up, the reset unit in this embodiment maintains a reset signal (e.g., a low level for 500ms) during power-up, during which the data processing unit does not perform any operations. Once all power supplies are stable, the reset unit releases the reset signal, and the system begins normal operation. This ensures that the system only starts working after the power supply is fully stable, avoiding unpredictable behavior during power-up. Simultaneously, the reset unit monitors key power supply voltages such as 5V, 3.3V, and 1.2V in real time. When any power supply voltage drops below a fifth preset threshold (e.g., a drop exceeding 10% of the rated value), the reset unit immediately outputs a protective blocking signal, such as pulling the reset pin of the data processing unit low or sending a blocking pulse signal to the drive unit, causing the power module to stop outputting. This prevents damage to power devices due to undervoltage or overcurrent in case of abnormal power supply conditions.

[0145] This embodiment, by limiting the data processing unit to a dual-core architecture comprising a floating-point DSP core and a data co-processing unit, achieves the division of labor and collaboration between computationally intensive and logic-intensive tasks, improving the system's real-time performance and stability. By limiting all units to connect via the same built-in multi-channel data bus, it avoids the node redundancy and communication failure risks associated with interconnecting multiple independent controllers via external buses in traditional solutions. The reduction of faulty nodes directly improves system reliability. By limiting the use of NOR FLASH, DRAM, and eMMC memory, it balances the needs for rapid fault record writing, large-capacity memory requirements for running programs, and long-term storage of critical data, achieving optimized storage resource allocation. By limiting the continuous reset and voltage monitoring functions of the reset unit, it ensures system power-on stability and rapid protection in case of power failure.

[0146] In some embodiments, the method further includes:

[0147] During the power-on phase of the frequency converter, the reset unit and monitoring unit are powered on before the peripheral circuits of the data processing unit, and the peripheral circuits of the data processing unit are powered on before the core of the data processing unit.

[0148] During the hardware initialization of the frequency converter, a diagnostic pulse signal is injected into at least one of the power supply units to collect the power ripple characteristics output by the power supply unit.

[0149] When the peak-to-peak value of the power supply ripple exceeds the fourth preset threshold, it is determined that the corresponding capacitor is aging, and the upper limit of the pulse width modulation switching frequency in the subsequent grid connection process is automatically reduced.

[0150] Using the signal spectrum correlation analysis method, voltage phase deviation, temperature gradient and electromagnetic interference intensity are constructed into a dynamic weight evaluation model. The model dynamically assigns weight coefficients to each signal according to the current speed range and calculates the comprehensive health score.

[0151] When the overall health score falls below the fifth preset threshold, an early warning is triggered, and the control parameters are adjusted.

[0152] During the power-up phase of the frequency converter, the reset unit and monitoring unit are powered on before the peripheral circuits of the data processing unit, and the peripheral circuits of the data processing unit are powered on before the core of the data processing unit. This hierarchical power-up strategy ensures that the core functional units (reset unit and monitoring unit) in the unit control system receive stable power first, thus being available before the data processing unit starts, guaranteeing the normal startup of the entire system. The reset unit needs to be powered on before the data processing unit to correctly output the reset signal during power-up. The monitoring unit needs to be powered on before the data processing unit to monitor the establishment process of each power rail in real time.

[0153] The peripheral circuits of the data processing unit (such as bus controllers, peripheral interfaces, GPIO, etc.) need to be powered on before the kernel so that the peripheral circuits are ready when the kernel starts, avoiding unpredictable behavior caused by uninitialized peripheral circuits after kernel startup. For example, the power-on sequence control logic executes sequentially: at 0ms, 5V power is switched on to power the reset unit and monitoring unit; at 10ms, 3.3V power is switched on to power the peripheral circuits of the data processing unit; at 20ms, 1.2V power is switched on to power the kernel of the data processing unit. The reset unit continuously outputs a reset signal for the first 500ms after power-on, ensuring that the data processing unit remains in a reset state from 20ms to 500ms. After 500ms, the reset is released, and the system begins normal operation.

[0154] Hardware initialization refers to the period after the system powers on but before the application program is executed. During this time, the data processing unit has not yet begun complex calculations, but the basic clock and peripherals have been initialized, allowing for the execution of some simple diagnostic tests. The diagnostic pulse signal refers to a small perturbation signal with known characteristics, such as a voltage pulse with a fixed amplitude and width. This pulse is injected into the output of the power supply unit, and the power supply response waveform is then acquired using a high-precision ADC. Ripple characteristics can be extracted from the response waveform, mainly including the peak-to-peak value (difference between the maximum and minimum values) and the ripple spectrum distribution (amplitude of each frequency component). There is a known correlation between power supply ripple characteristics and hardware health: when the output capacitor ages, the equivalent series resistance (ESR) increases, and the peak-to-peak value of the ripple increases; when the switching transistor performance deteriorates, harmonic components of specific frequencies appear in the ripple.

[0155] The fourth preset threshold is a judgment value pre-set based on the typical peak-to-peak ripple of the power supply unit in a healthy state and a safety margin. For example, the peak-to-peak ripple of a 5V power supply in a healthy state is 30mV, and the fourth preset threshold is set to 50mV. When the collected peak-to-peak ripple reaches 75mV, it exceeds the 50mV threshold, and the output capacitor is judged to be aging. In this embodiment, after judging that the capacitor is aging, the control system automatically reduces the upper limit of the pulse width modulation (PWM) switching frequency in the subsequent grid connection process from the default value. For example, the normal switching frequency can be as high as 4kHz, and after the capacitor ages, its upper limit is reduced to 2.5kHz. Reducing the switching frequency can slow down the aging process of the capacitor, prevent power supply failure caused by capacitor failure, and at the same time, it does not affect the basic function.

[0156] The signal spectrum correlation analysis method is used to construct a dynamic weight evaluation model based on voltage phase deviation, temperature gradient and electromagnetic interference intensity. The model dynamically assigns weight coefficients to each signal according to the current speed range and calculates the comprehensive health score.

[0157] Voltage phase deviation reflects the tracking accuracy of the phase-locked loop (PLL), temperature gradient reflects the rate of change of thermal stress in power devices, and electromagnetic interference intensity reflects the degree of environmental interference with the control signal. These three parameters reflect the health status of the system from different dimensions. The dynamic weighted evaluation model differs from the single-point judgment method with a fixed threshold. In traditional methods, each parameter is independently compared with a fixed threshold, and an alarm is triggered if the threshold is exceeded. This method is prone to false alarms due to single-point noise and is also difficult to detect early faults where multiple parameters deteriorate simultaneously but none exceed the threshold.

[0158] In this embodiment, the comprehensive health score R can be calculated as follows:

[0159] R = w_A×S_A + w_B×S_B + w_C×S_C, where S_A, S_B, and S_C are the normalized risk scores (ranging from 0 to 1) for voltage phase deviation, temperature gradient, and electromagnetic interference intensity, respectively, and w_A, w_B, and w_C are the weighting coefficients of each signal, with the sum of the weighting coefficients being 1.

[0160] The weighting coefficients are dynamically allocated based on the current speed range. For example: during the natural commutation phase (approximately 200 rpm to 800 rpm), commutation is sensitive to voltage phase deviation, with w_A assigned 0.5, w_B assigned 0.3, and w_C assigned 0.2; during the constant speed phase (approximately 800 rpm to 1500 rpm), heat accumulation is more critical, with w_B assigned 0.5, w_A assigned 0.3, and w_C assigned 0.2; when electromagnetic interference suddenly increases, the confidence level in voltage phase deviation is temporarily reduced, and w_C is increased.

[0161] The fifth preset threshold is the lower limit characterizing the overall health status of the system. For example, the fifth preset threshold is set to 0.6. When the calculated comprehensive health score R is lower than 0.6, it indicates that the overall health status of the system is poor and there is a potential risk of failure. After triggering the warning, the warning information is displayed on the interactive interface (e.g., "The comprehensive health score of the system is low; it is recommended to arrange maintenance in the near future"), and the control parameters are adjusted according to the reason for the low score. For example, if the voltage phase deviation contributes the most, the phase-locked loop proportional coefficient can be further reduced; if the electromagnetic interference intensity contributes the most, additional software filtering can be enabled or the communication rate can be reduced; if the temperature gradient contributes the most, the upper limit of the switching frequency can be reduced to reduce heat generation.

[0162] This embodiment employs a tiered power-on strategy to ensure that critical units receive stable power before data processing units, preventing data processing units from malfunctioning due to power instability during power-on. Through diagnostic pulse injection and power ripple acquisition, online prediction of the power unit's health status is achieved, enabling early detection of problems in capacitor aging and proactively reducing the upper limit of the switching frequency to delay faults. Using a dynamic weighted evaluation model, this embodiment integrates multiple dimensions of health parameters into a single comprehensive health score, overcoming the shortcomings of traditional fixed-threshold single-point judgments, which are prone to false alarms and fail to detect early faults. The weighting coefficients are dynamically adjusted according to the speed range, allowing the evaluation model to adapt to changes in risk distribution under different operating conditions, improving the accuracy of fault prediction.

[0163] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0164] Based on the same inventive concept, this application also provides a control device for a pumped-storage unit frequency converter, which implements the control method for the pumped-storage unit frequency converter described above. The solution provided by this device is similar to the solution described in the above method. Therefore, the specific limitations of one or more control device embodiments for pumped-storage unit frequency converters provided below can be found in the limitations of the control method for pumped-storage unit frequency converters described above, and will not be repeated here.

[0165] In one exemplary embodiment, such as Figure 3 As shown, a control device 300 for frequency converter equipment of a pumped storage unit is provided, comprising:

[0166] The response module 302 is used to respond to the grid connection triggering event of the pumped storage unit. During the process of the frequency converter driving the pumped storage unit to connect to the grid, for each commutation cycle of the frequency converter, the frequency change rate and harmonic distortion rate of the grid in the current commutation cycle, as well as the phase difference between the grid voltage and the output voltage of the frequency converter are determined.

[0167] The determining module 304 is used to determine the initial values ​​of the control parameters of the phase-locked loop of the frequency converter equipment in the current commutation cycle based on the current rotational speed of the pumped storage unit; the control parameters include response sensitivity and error elimination speed;

[0168] The first adjustment module 306 is used to adjust the initial value according to the frequency change rate, harmonic distortion rate and phase difference to obtain the target value of the control parameters of the phase-locked loop in the current commutation cycle; wherein, the response sensitivity is negatively correlated with the harmonic distortion rate, and the error elimination speed is positively correlated with the frequency change rate;

[0169] The control module 308 is used to perform commutation control on the frequency converter in the current commutation cycle according to the target value, and to determine the commutation margin deviation of the frequency converter in the current commutation cycle according to the commutation performance of the frequency converter in the current commutation cycle and the commutation performance standard.

[0170] The second adjustment module 310 is used to adjust the initial value of the control parameters of the phase-locked loop in the next commutation cycle according to the commutation margin deviation, until the pumped storage unit is connected to the grid.

[0171] The modules in the control device for the frequency converter of the pumped storage unit described above can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0172] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 4 As shown, the computer device includes a processor, memory, input / output interface, communication interface, display unit, and input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interface. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The input / output interface is used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a control method for the frequency converter equipment of a pumped storage unit. The display unit is used to form a visually visible image and can be a display screen, projection device, or virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0173] Those skilled in the art will understand that Figure 4 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0174] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps included in any of the foregoing method embodiments.

[0175] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps included in any of the foregoing method embodiments.

[0176] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps included in any of the foregoing method embodiments.

[0177] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0178] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0179] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0180] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A control method for variable frequency drive (VFD) equipment in a pumped storage unit, characterized in that, The method includes: In response to the grid connection triggering event of the pumped storage unit, during the process of the pumped storage unit being connected to the grid by the frequency converter, for each commutation cycle of the frequency converter, the frequency change rate and harmonic distortion rate of the grid in the current commutation cycle, as well as the phase difference between the grid voltage and the output voltage of the frequency converter are determined. The initial values ​​of the control parameters of the phase-locked loop of the frequency converter are determined based on the current rotational speed of the pumped storage unit for the current commutation cycle; the control parameters include response sensitivity and error elimination speed. The initial values ​​are adjusted based on the frequency change rate, harmonic distortion rate, and phase difference to obtain the target values ​​of the control parameters of the phase-locked loop in the current commutation cycle; wherein, the response sensitivity is negatively correlated with the harmonic distortion rate, and the error elimination speed is positively correlated with the frequency change rate; The frequency converter is controlled for commutation in the current commutation cycle according to the target value, and the commutation margin deviation of the frequency converter in the current commutation cycle is determined according to the commutation performance of the frequency converter in the current commutation cycle and the commutation performance standard. The initial values ​​of the control parameters of the phase-locked loop for the next commutation cycle are adjusted according to the commutation margin deviation until the pumped storage unit is connected to the grid.

2. The method according to claim 1, characterized in that, The response sensitivity includes the proportional coefficient of the phase-locked loop, which is used to proportionally map the current value of the phase difference to the adjustment amount of the phase-locked loop output; the error elimination speed includes the integral coefficient of the phase-locked loop, which is used to map the cumulative integral value of the phase difference to the adjustment amount of the phase-locked loop output. The step of adjusting the initial value based on the frequency change rate, harmonic distortion rate, and phase difference to obtain the target value of the phase-locked loop control parameters in the current commutation cycle includes: Based on the comparison result between the harmonic distortion rate and the first preset threshold, the proportional coefficient is adjusted to obtain the adjusted proportional coefficient; wherein, the adjusted proportional coefficient is negatively correlated with the harmonic distortion rate; Based on the comparison result between the frequency change rate and the second preset threshold, the integral coefficient is corrected to obtain the adjusted integral coefficient; wherein, the adjusted integral coefficient is positively correlated with the frequency change rate; Calculate the proportional adjustment component based on the current value of the phase difference and the adjusted proportional coefficient; The integral adjustment component is calculated based on the cumulative integral value of the phase difference and the adjusted integral coefficient. The proportional adjustment component and the integral adjustment component are used to determine the target adjustment amount for the initial value.

3. The method according to claim 1, characterized in that, The commutation performance standard includes the theoretical commutation overlap angle of the frequency converter; the step of performing commutation control on the frequency converter for the current commutation cycle based on the target value, and determining the commutation margin deviation of the frequency converter for the current commutation cycle based on the commutation performance of the frequency converter and the commutation performance standard for the current commutation cycle, includes: During the turn-off process of multiple switching structures within the frequency converter, the commutation overlap angle of the multiple switching structures is determined; The theoretical commutation overlap angle is determined based on the voltage signal of the power grid during the current commutation cycle and the configuration parameters of the pumped storage unit. The commutation overlap angle is compared with the theoretical commutation overlap angle to obtain the commutation margin deviation; The step of adjusting the initial values ​​of the control parameters of the phase-locked loop for the next commutation cycle based on the commutation margin deviation includes: When the commutation margin deviation is positive, decrease the initial value of the response sensitivity for the next commutation cycle; When the commutation margin deviation is negative, the initial value of the response sensitivity for the next commutation cycle is increased.

4. The method according to claim 1, characterized in that, The step of performing commutation control on the frequency converter for the current commutation cycle based on the target value includes: Based on the current change rate and voltage phase of the switching structure of the frequency converter, a feedforward compensation algorithm is used to calculate the trigger angle correction, and the trigger angle correction is superimposed on the reference trigger angle of the current commutation trigger to obtain the target trigger angle for the switching structure; wherein, the feedforward compensation algorithm is used to compensate for the response delay during the switching process of the switching structure; During the turn-off process of the switch structure, the current drop time of the frequency converter is determined and compared with a standard drop time; When the deviation between the current drop time and the standard drop time exceeds a third preset threshold, it is determined that the frequency converter is abnormal, and at least one of the following is executed: generating a warning message, reducing the switching frequency of subsequent commutation cycles, and prompting a shutdown.

5. The method according to claim 1, characterized in that, The response to the grid connection triggering event of the pumped storage unit includes: Receive control commands from the host computer to start or control the grid connection process; Based on the current unit status and the content of the control command, an internal mathematical model is invoked to generate a virtual response signal, which represents the expected operating trajectory of the system after the control command is executed. The virtual response signal is matched and verified with the expected behavior pattern, wherein the expected behavior pattern is a standard response curve pre-stored based on historical normal operation data and equipment parameters; If the match is successful, the control command is confirmed to be valid and executed. If the matching fails, it is determined that the control command has been distorted during transmission, and a request is made to the host computer to resend the command, and a communication error log is recorded.

6. The method according to claim 1, characterized in that, The step of adjusting the initial values ​​of the control parameters of the phase-locked loop for the next commutation cycle based on the commutation margin deviation includes: In response to the completion of grid connection of the pumped storage unit, the current rotor position, current phase, and phase-locked loop parameters of the frequency converter are saved to non-volatile memory. The residual energy on the DC bus of the frequency converter is calculated, and the output power is reduced in a linear decreasing manner while the residual energy is transferred to the standby load through the braking unit. When the output current of the frequency converter drops to the rated value, the frequency converter is disconnected from the power grid.

7. The method according to claim 1, characterized in that, The frequency converter includes a data processing unit, a data acquisition unit, a drive unit, a power supply unit, and a reset unit. The data processing unit comprises at least one floating-point digital signal processor core and at least one data coprocessing unit, all cores being interconnected via a built-in multi-channel data bus. The data coprocessing unit performs logic control, auxiliary control, and external communication tasks. The floating-point digital signal processor core is used to perform control parameter adjustment and commutation control of the phase-locked loop. The data acquisition unit, drive unit, power supply unit, and reset unit are all connected to the data processing unit via the built-in multi-channel data bus. The data processing unit has an external flash memory for storing fault record data, an external dynamic random access memory for running the operating system and applications, and an embedded multimedia card for storing critical operating data. The driving unit converts the first-level pulse signal generated by the floating-point digital signal processor core into a second-level signal and outputs it. The reset unit provides a continuous reset signal during system power-on and monitors the power supply voltage in real time. When the voltage drops below a fifth preset threshold, it outputs a protective blocking signal.

8. The method according to claim 7, characterized in that, The method further includes: During the power-on phase of the frequency converter, the reset unit and monitoring unit are powered on before the peripheral circuits of the data processing unit, and the peripheral circuits of the data processing unit are powered on before the core of the data processing unit. During the hardware initialization of the frequency converter, a diagnostic pulse signal is injected into at least one of the power supply units to collect the power ripple characteristics output by the power supply unit. When the peak-to-peak value of the power supply ripple exceeds the fourth preset threshold, the corresponding capacitor is determined to be aging, and the upper limit of the pulse width modulation switching frequency in the subsequent grid connection process is automatically reduced. Using the signal spectrum correlation analysis method, voltage phase deviation, temperature gradient and electromagnetic interference intensity are constructed into a dynamic weight evaluation model. The model dynamically assigns weight coefficients to each signal according to the current speed range and calculates the comprehensive health score. When the overall health score falls below the fifth preset threshold, an early warning is triggered, and the control parameters are adjusted.

9. A control device for frequency converter equipment of pumped storage units, characterized in that, The device includes: The response module is used to respond to the grid connection triggering event of the pumped storage unit. During the process of the pumped storage unit being connected to the grid by the frequency converter, for each commutation cycle of the frequency converter, the frequency change rate and harmonic distortion rate of the grid in the current commutation cycle, as well as the phase difference between the grid voltage and the output voltage of the frequency converter are determined. The determination module is used to determine the initial values ​​of the control parameters of the phase-locked loop of the frequency converter equipment for the current commutation cycle based on the current rotational speed of the pumped storage unit; the control parameters include response sensitivity and error elimination speed; The first adjustment module is used to adjust the initial value according to the frequency change rate, harmonic distortion rate, and phase difference to obtain the target value of the control parameters of the phase-locked loop in the current commutation cycle; wherein, the response sensitivity is negatively correlated with the harmonic distortion rate, and the error elimination speed is positively correlated with the frequency change rate; The control module is used to perform commutation control on the frequency converter in the current commutation cycle according to the target value, and to determine the commutation margin deviation of the frequency converter in the current commutation cycle according to the commutation performance of the frequency converter in the current commutation cycle and the commutation performance standard. The second adjustment module is used to adjust the initial values ​​of the control parameters of the phase-locked loop for the next commutation cycle according to the commutation margin deviation, until the pumped storage unit is connected to the grid.

10. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 8.

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