A high-bandwidth photovoltaic inverter control apparatus and method

Abstract

The application provides a photovoltaic inverter control device and method with high control bandwidth, and belongs to the technical field of power electronics. The control device comprises a multi-core heterogeneous MPU chip, an FPGA chip, an external ADC sampling chip and an optical fiber communication module. The multi-core heterogeneous MPU chip comprises a first processor and a second processor. The first processor is used for executing outer loop control calculation such as a voltage loop and a power loop. The second processor is used for data interaction with an external monitoring device. The FPGA chip comprises a data preprocessing module, a phase-locked angle interpolation module and a current loop control module. The current loop control module is used for executing current loop control calculation and generating a PWM modulation instruction. The application strips the current loop control calculation to the FPGA for execution, and uses the phase-locked angle interpolation module to eliminate the phase step caused by the frequency difference between the inner loop and the outer loop, effectively improves the system control bandwidth, and realizes the rapid response and effective suppression to high-frequency power grid fluctuations.

Description

Technical Field

[0001] This application belongs to the field of power electronics technology, specifically relating to a photovoltaic inverter control device and method with high control bandwidth. Background Technology

[0002] As the proportion of new energy power generation in the power grid continues to increase, the photovoltaic inverter, as the core power conversion device connecting photovoltaic modules and the power grid, directly determines the power quality, grid connection stability, and operational performance indicators of the photovoltaic power plant. In complex power grid environments, the inverter control system needs to have extremely high dynamic response speed and precise control commands to effectively suppress grid disturbances and ensure the safe and reliable operation of the power generation system.

[0003] Existing photovoltaic inverter control devices are increasingly adopting an architecture combining an MPU and an FPGA. In this existing architecture, the multi-core heterogeneous MPU undertakes the calculation tasks of all control algorithms, including voltage loop, power loop control, and current loop control; while the FPGA serves only as an auxiliary interface chip, mainly responsible for responding to MPU commands, executing the reading of low-level external ADC sampling data, and passing the PWM control signal calculated by the MPU to the power module.

[0004] However, in the above architecture, the current loop and voltage loop are both concentrated in a single MPU and run serially in software. The computing speed is limited by the MPU's main frequency and the task scheduling cycle of the real-time operating system. When high-frequency disturbances occur in the power grid, the MPU needs to calculate the voltage loop and current loop sequentially, resulting in significant delays in control command output and a substantial reduction in system control bandwidth. Due to the limited control bandwidth, the inverter struggles to respond quickly and effectively to high-frequency power grid fluctuations, severely impacting grid connection stability. Summary of the Invention

[0005] This application addresses the problem in existing technologies where the current loop and voltage loop are all concentrated in a single MPU, resulting in low control bandwidth and difficulty in quickly responding to and effectively suppressing high-frequency grid fluctuations. It provides a photovoltaic inverter control device and method with high control bandwidth. By transferring the current loop calculation task to the FPGA for execution, the system control bandwidth is effectively improved, thereby achieving rapid response and effective suppression of high-frequency grid fluctuations.

[0006] In the first aspect, to solve the above problems, this application provides a photovoltaic inverter control device with high control bandwidth, including a multi-core heterogeneous MPU chip, an FPGA chip, an external ADC sampling chip, and an optical fiber communication module;

[0007] The multi-core heterogeneous MPU chip includes a first processor and a second processor. The first processor is used to perform voltage loop and power loop control calculations, and the second processor is used to interact with external monitoring equipment.

[0008] The FPGA chip includes a data preprocessing module, a phase-locked angle interpolation module, and a current loop control module. The phase-locked angle interpolation module is used to interpolate and compensate the phase-locked angle of the power grid, and the current loop control module is used to perform current loop control calculations and generate PWM modulation commands.

[0009] An external ADC sampling chip is connected to a data preprocessing module. The data preprocessing module is connected to a first processor and a current loop control module. The first processor is connected to a phase-locked angle interpolation module and a current loop control module. The phase-locked angle interpolation module is connected to the current loop control module. The current loop control module is connected to an optical fiber communication module. The optical fiber communication module is used to connect to the power module.

[0010] Compared to existing technologies, this solution significantly improves system control bandwidth through hardware architecture innovation. In existing technologies, the MPU must perform inner and outer loop control calculations serially in software, resulting in significant control latency. This solution, however, delegates outer loop calculations and monitoring interactions to the first and second processors of a multi-core heterogeneous MPU, respectively, and completely decouples current loop control calculations to be executed within the FPGA. The FPGA integrates a data preprocessing module, a phase-locked loop interpolation module, and a current loop control module. After preprocessing, the data collected by the external ADC sampling chip, the current loop setpoint parameters generated by the first processor, the feedforward voltage, and the real-time phase-locked angle compensated by the phase-locked loop interpolation module are all directly sent to the current loop control module within the FPGA. The module then directly generates PWM modulation commands and sends them to the power module via an optical fiber communication module. This architecture enables high-speed closed-loop current loop calculation and output within the FPGA, greatly improving upon the shortcomings of slow MPU calculations and large cross-chip transmission latency in existing technologies, thereby achieving rapid response and effective suppression of high-frequency power grid fluctuations.

[0011] Furthermore, the multi-core heterogeneous MPU chip incorporates a shared memory region, to which both the first and second processors are connected. The first processor runs an RTOS (Real-Time Operating System) or a bare-metal program, while the second processor runs a Linux operating system. This shared memory region enables high-speed data exchange between the first and second processors, avoiding congestion and latency associated with external bus communication. Simultaneously, the RTOS or bare-metal program ensures efficient execution of real-time control tasks, while the Linux system handles complex communication and monitoring tasks. This achieves physical isolation between real-time control and general-purpose computing, preventing interference and significantly improving system response speed and reliability.

[0012] Furthermore, the multi-core heterogeneous MPU chip also includes a third processor. This third processor is connected to the shared memory area and to an external circuit breaker. A bare-metal program runs on the third processor, which is used to control the external circuit breaker to disconnect when the first processor crashes or experiences an abnormal failure. The addition of a dedicated third processor with a bare-metal program serves as a low-level safety redundancy backup. When the first processor, responsible for real-time control, crashes or experiences an abnormality, the third processor can bypass the faulty core and independently output a control signal to drive the external circuit breaker to disconnect. This achieves hardware-level local safety protection, effectively preventing system device loss of control and fault escalation due to main control chip failure, and greatly improving the safety level of inverter operation.

[0013] Secondly, this application also provides a photovoltaic inverter control method with high control bandwidth, applied to a photovoltaic inverter control device with high control bandwidth, comprising:

[0014] The first processor performs voltage loop and power loop control calculations at a first frequency, generates current loop setpoint parameters, feedforward voltage and grid phase-locked angle, and sends the grid phase-locked angle to the phase-locked angle interpolation module, and sends the current loop setpoint parameters and feedforward voltage to the current loop control module.

[0015] The phase-locked angle interpolation module performs interpolation compensation based on the grid phase-locked angle to obtain the real-time phase-locked angle; the external ADC sampling chip collects the actual current of the inverter and sends the actual current of the inverter to the data preprocessing module. After preprocessing the actual current of the inverter, the data preprocessing module sends it to the current loop control module.

[0016] The current loop control module performs current loop control calculations at a second frequency based on the current loop given parameters, feedforward voltage, real-time phase-locked angle, and pre-processed actual inverter current, generates PWM modulation commands, and sends them to the power module through the fiber optic communication module. The ratio of the second frequency to the first frequency is a positive integer greater than 1.

[0017] Compared with existing technologies, this solution significantly improves the system control bandwidth through coordinated control of inner and outer loop frequencies. In existing technologies, the MPU needs to execute inner and outer loop calculations sequentially in software, resulting in large delays in sampling and control command output and limited bandwidth. In this method, the first processor executes voltage loop and power loop control calculations at a first frequency, while the current loop control module executes current loop control calculations at a second frequency, and the ratio of the second frequency to the first frequency is greater than 1. This makes the current loop calculation frequency much higher than the outer loop frequency, significantly shortening the current loop operation cycle. At the same time, the phase-locked angle interpolation module performs interpolation compensation based on the grid phase-locked angle to generate a real-time phase-locked angle, eliminating the phase step caused by the frequency difference between the inner and outer loops. Thus, this solution achieves high-frequency, fast closed-loop control of the current loop, effectively improving the system control bandwidth, thereby enabling rapid response and effective suppression of high-frequency grid fluctuations.

[0018] Furthermore, the ratio is a positive integer greater than 1 and not exceeding 20. Limiting the frequency difference between the inner and outer loops to a factor of 1 to 20 significantly improves the computational speed of the current loop while avoiding the hardware computational burden caused by excessively high frequency multiplication, thus balancing high performance and engineering feasibility.

[0019] Furthermore, the first frequency is no less than 3kHz, and the communication frequency between the first processor and the FPGA chip is no less than the first frequency; the sampling frequency of the external ADC sampling chip is no less than the second frequency. By limiting the lower limits of the outer loop frequency, communication frequency, and sampling frequency, it is ensured that the data transmission and sampling speeds are always faster than the calculation speed, avoiding data congestion or lag problems caused by using old data for calculation, and guaranteeing the high real-time performance and high bandwidth of the control loop.

[0020] Furthermore, the phase-locked angle interpolation module performs interpolation compensation based on the grid phase-locked angle, including:

[0021] The phase increment step size is calculated based on the fundamental frequency, the first frequency, and their ratio. When the grid phase-locked angle is increasing in a positive direction, the grid phase-locked angle is added to the phase increment step size. If the sum is greater than 2π, 2π is subtracted. When the grid phase-locked angle is decreasing in a negative direction, the grid phase-locked angle is subtracted from the phase increment step size. If the subtraction is less than 0, 2π is added. By calculating the phase increment step size and setting a 2π-cycle overflow protection mechanism, the phase steps caused by high and low frequency operations are accurately eliminated, phase abrupt changes across cycles are prevented, the output current waveform is ensured to be smooth and continuous, and high-frequency disturbances in the grid are effectively suppressed.

[0022] Furthermore, it also includes:

[0023] The second processor acquires data from the first processor via a shared memory area and uploads it to external monitoring equipment. It also converts instructions from the external monitoring equipment using a protocol and sends them back to the first processor via the shared memory area. Furthermore, the second processor runs a predictive model based on the data from the first processor to predict the inverter's operating status and equipment lifespan, generating alarm signals. By leveraging the powerful computing capabilities of the second processor to achieve monitoring communication and edge computing, proactive prediction and early warning of equipment status and lifespan are realized. This helps maintenance personnel identify potential problems in advance, significantly reducing the risk of unplanned downtime and improving the system's intelligent operation and maintenance level.

[0024] Furthermore, it also includes:

[0025] The third processor monitors the operating status of the first processor in real time through a shared memory area. In the event of a system crash or abnormal failure in the first processor, the third processor controls the external circuit breaker to disconnect. Utilizing the third processor as hardware-level safety redundancy, it can directly disconnect the external circuit breaker in extreme abnormal situations such as a main processor crash, ensuring safe equipment shutdown and effectively preventing accidents caused by system malfunction, thus greatly improving the overall system security.

[0026] Furthermore, it also includes:

[0027] After receiving the PWM modulation command, the power module executes the corresponding action, collects its own DC voltage, temperature, and fault status information, and feeds it back to the FPGA chip via the fiber optic communication module. This establishes a complete closed-loop feedback chain, allowing the power module to transmit its operating status back to the FPGA in real time. This provides the system with accurate online protection data and a reliable underlying data source for subsequent prediction models, ensuring the closed-loop stability of the system operation.

[0028] As can be seen from the above technical solutions, this application has the following advantages:

[0029] 1. Significantly improve system control bandwidth and response speed: By offloading the current loop calculation to be executed inside the FPGA and using the phase-locked loop interpolation module to eliminate the phase ladder caused by the frequency difference between the inner and outer loops, high-frequency fast closed-loop control of the current loop is realized, which greatly improves the bandwidth of the control system, thus making it possible to effectively suppress high-frequency power grid fluctuations or oscillations.

[0030] 2. Improve system reliability and security: Through the physical isolation of multi-core heterogeneous chips, real-time control and monitoring communication tasks are handled separately, avoiding mutual interference between tasks; at the same time, an independent third processor is added as hardware-level safety redundancy, which can directly control the external circuit breaker to disconnect when the main control core crashes, effectively preventing the expansion of faults caused by system loss of control.

[0031] 3. Reduce maintenance costs and downtime risks: By using a second processor to run a predictive model, the inverter's operating status and equipment lifespan can be predicted online and alarm signals can be generated, helping maintenance personnel to discover potential problems in advance and realizing a shift from passive maintenance to proactive early warning.

[0032] 4. Ensure the accuracy and stability of closed-loop control: By limiting the matching relationship between frequency, communication and sampling frequency, it is ensured that the latest sampled values ​​are always used for calculation; at the same time, the power module feeds back DC voltage, temperature and fault status information to the FPGA in real time and transmits it to the multi-core heterogeneous MPU chip, providing the system with accurate online protection basis and real data source, ensuring the long-term stability of the system.

[0033] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. The objectives and other advantages of this application are realized and obtained through the structures particularly pointed out in the description, claims and drawings.

[0034] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0036] Figure 1 This is a system connection diagram of the photovoltaic inverter control device provided in the embodiments of this application;

[0037] Figure 2 This is a hardware structure block diagram of the photovoltaic inverter control device provided in Embodiment 1 of this application;

[0038] Figure 3 This is a hardware structure block diagram of the photovoltaic inverter control device provided in Embodiment 2 of this application;

[0039] Figure 4 This is a hardware structure block diagram of the photovoltaic inverter control device provided in Embodiment 3 of this application. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0041] Example 1: This example provides a photovoltaic inverter control device with high control bandwidth, applied to photovoltaic inverters. For example... Figure 1 As shown, the DC side of the photovoltaic inverter is connected to multiple photovoltaic modules, and the AC side is connected to the power grid. This control device, as the core control unit of the photovoltaic inverter, is used to collect electrical information from the photovoltaic modules and the power grid, enabling grid connection and grid configuration control of the inverter.

[0042] like Figure 2 As shown, the control device includes a multi-core heterogeneous MPU chip, an FPGA chip, an external ADC sampling chip, and an optical fiber communication module. In this embodiment, the multi-core heterogeneous MPU chip includes a first processor and a second processor, and the FPGA chip includes a data preprocessing module, a phase-locked angle interpolation module, and a current loop control module.

[0043] The first processor integrates a control data processing module and voltage and power loop control modules. The second processor integrates a monitoring module and a protocol conversion module.

[0044] Regarding hardware connectivity and data flow: The external ADC sampling chip is connected to the FPGA chip's data preprocessing module to collect high-frequency key electrical signals such as grid voltage and inverter three-phase current, and sends the collected data to the data preprocessing module. The data preprocessing module performs preprocessing such as per-unit scaling and filtering on the data. The preprocessed data is divided into two paths: one path is sent to the control data processing module inside the first processor, and the other path is sent directly to the current loop control module inside the FPGA chip.

[0045] After receiving the data, the control data processing module adds its own collected DC bus voltage and other information, performs corresponding filtering and transformation processing, and sends the processed data to the voltage loop and power loop control modules. The voltage loop and power loop control modules combine the processed data with a preset control model to complete the calculation of the inverter's outer loop, including at least one of the following: grid voltage phase-locked loop, power outer loop, voltage outer loop, and grid construction function. They also generate the current loop setpoint parameters, feedforward voltage, and grid phase-locked angle.

[0046] The voltage loop and power loop control modules generate two outputs: the first output sends the current loop setpoint parameters and feedforward voltage to the current loop control module of the FPGA chip; the second output sends the grid phase-locked angle to the phase-locked angle interpolation module of the FPGA chip. The phase-locked angle interpolation module is used to interpolate and compensate the grid phase-locked angle, and then sends the real-time phase-locked angle to the current loop control module.

[0047] The current loop control module performs current loop control calculations based on the current loop given parameters, feedforward voltage, real-time phase-locked angle, and actual current output by the data preprocessing module. It then generates PWM modulation commands and sends them to the inverter's power module via the fiber optic communication module to control the inverter to output the expected current and power.

[0048] The multi-core heterogeneous MPU chip also includes a shared memory region. The first and second processors are connected to this shared memory region to enable data exchange between them. The first processor runs an RTOS (Real-Time Operating System) or a bare-metal program, while the second processor runs a Linux operating system. The first processor communicates with the FPGA chip via a bus and I / O pins.

[0049] The monitoring module acquires data from the first processor via a shared memory area, monitors the inverter's operating status, and performs fault recording and event logging functions. The protocol conversion module performs communication protocol conversion with external monitoring equipment, converting commands from the external monitoring equipment into an internal format and converting internal data into an externally recognizable format, interacting with the first processor via the shared memory area. Through the monitoring module and the protocol conversion module, the second processor achieves data interaction with the external monitoring equipment.

[0050] Furthermore, the control device also includes peripheral interface circuits, including a DI / DO interface module, a GPS interface module, an IIC interface module, an SPI interface module, a 485 interface module, a CAN interface module, and an Ethernet interface module.

[0051] The DI / DO interface module is connected to the FPGA chip. The protection action commands generated by the FPGA chip are sent to external devices through the DI / DO interface module, such as controlling the opening of external circuit breakers or contactors, or controlling cooling fans or water cooling systems.

[0052] The GPS interface module, IIC interface module, SPI interface module, 485 interface module, CAN interface module, and Ethernet interface module are all connected to the multi-core heterogeneous MPU chip to enable data transmission with external monitoring equipment, back-end systems, or other devices.

[0053] In addition, the multi-core heterogeneous MPU chip also features multiple ADC sampling interfaces. These ADC sampling interfaces are used to directly acquire DC bus voltage, component voltage, and internal or external slowly varying analog quantities, such as ambient temperature and humidity signals. Through analog switching, this ADC sampling interface can perform time-division multiplexing of multiple analog quantities for digital acquisition and conversion. Meanwhile, the external ADC sampling chip is specifically designed for acquiring high-frequency critical electrical signals such as grid voltage and inverter three-phase current.

[0054] Example 2: This example further expands the second processor of the multi-core heterogeneous MPU chip by adding edge computing functionality. The remaining hardware structure, connection relationships, and data flow are basically the same as in Example 1, and will not be described again here.

[0055] like Figure 3 As shown in this embodiment, the second processor also integrates an edge computing module. The edge computing module obtains data from the first processor through a shared memory area, including the inverter's current voltage, current, power module temperature, and historical operating status parameters. Based on this data, the edge computing module runs a prediction model to predict the inverter's operating status and lifespan. For example, this prediction model can predict the lifespan of the DC bus support capacitor online or predict the health status of the power module. When the prediction result exceeds the normal range, the edge computing module generates an alarm signal and sends it to external monitoring equipment via a protocol conversion module or Ethernet interface module, reminding maintenance personnel to handle it promptly. Through the edge computing module, the inverter completes data analysis and mining locally, eliminating the need to upload all data to the cloud or remote server, effectively reducing communication bandwidth requirements and improving the real-time performance of fault warnings.

[0056] In this embodiment, the multi-core heterogeneous MPU chip can be a Zynq architecture chip, which integrates an ARM processor core and FPGA logic. The ARM processor and the internal FPGA communicate via an AXI bus. The two ARM processors can serve as the first and second processors, respectively. The first processor runs an RTOS operating system or a bare-metal program, while the second processor runs a Linux operating system. Because the Zynq architecture chip possesses heterogeneous computing capabilities with the ARM processor and FPGA logic unit working collaboratively, the edge computing module in this embodiment can utilize the second processor running Linux to execute the prediction model, while simultaneously using the FPGA logic unit to perform hardware acceleration on the convolution operations in the model, thereby achieving fast, low-latency prediction of the inverter's operating status and equipment lifespan.

[0057] Based on Example 1, this embodiment utilizes the powerful computing capabilities of the Linux operating system in the second processor to run the prediction model, thereby achieving localized intelligent analysis of the inverter equipment status, lifespan prediction, and proactive alarms, significantly improving the system's intelligent operation and maintenance level and reliability.

[0058] Example 3: The multi-core heterogeneous MPU chip in this example also includes a third processor. The remaining hardware structure, connection relationships, and data flow are basically the same as in Example 2, and will not be described again here.

[0059] like Figure 4 As shown, the third processor is connected to the shared memory region and also to an external circuit breaker. A bare-metal program runs on the third processor.

[0060] The third processor integrates an environmental parameter sampling module and a critical I / O redundancy control module. The environmental parameter sampling module collects ambient temperature, humidity, and other slowly varying analog parameters inside the inverter chassis and provides the collected data to the first and second processors via a shared memory area as a reference for system operating status. The critical I / O redundancy control module monitors the operating status of the first processor in real time. When the first processor crashes or experiences an abnormal fault, the critical I / O redundancy control module directly controls the external circuit breaker to disconnect, achieving local protection and preventing system loss of control due to main control chip failure.

[0061] In this embodiment, the multi-core heterogeneous MPU chip can be a Fuxi H2 series chip, which includes a dual-core CK860 processor, two CK810F processors, and a dual-core CK803S microcontroller. The CK860 serves as the second processor running a Linux operating system, the CK810F serves as the first processor running an RTOS or bare-metal program, and the CK803S serves as the third processor running a bare-metal program. The first processor interacts with the FPGA chip via the GPMC bus, and the third processor interacts with the first and second processors via shared memory.

[0062] This embodiment adds an independent third processor with bare-metal program as a low-level security redundancy backup. When the first processor responsible for real-time control crashes or other abnormal situations, the third processor can directly bypass the faulty core and independently output control signals to drive the external circuit breaker to disconnect, realizing hardware-level local safety protection. This effectively prevents system loss of control due to main control chip failure and greatly improves the safety level of inverter operation.

[0063] Example 4: Based on Example 3, this example adds a status monitoring function for the multi-core heterogeneous MPU chip to the FPGA chip. When the FPGA chip detects a crash or abnormal operation of the multi-core heterogeneous MPU chip, the FPGA chip directly controls the critical I / O redundancy control module, which in turn controls the external circuit breaker to disconnect, achieving local protection and preventing the system failure from escalating due to the main control chip crashing or malfunctioning, thereby improving system operational safety.

[0064] Specifically, this embodiment provides two implementation methods for FPGA chips to perform status monitoring on multi-core heterogeneous MPU chips.

[0065] The first method involves at least one I / O pin connecting the multi-core heterogeneous MPU chip and the FPGA chip. The multi-core heterogeneous MPU chip outputs a toggle signal at a preset frequency through this I / O pin. The FPGA chip monitors the input signal connected to this I / O pin in real time. If it does not detect a toggle of the pin's level within a preset time period, or if the frequency of the input pin signal deviates from a preset value by more than a threshold, the FPGA chip determines that the multi-core heterogeneous MPU chip is malfunctioning and requires redundant protection measures.

[0066] The second approach involves adding a heartbeat signal to the communication protocol between the multi-core heterogeneous MPU chip and the FPGA chip. The FPGA chip periodically checks whether this heartbeat signal is updated normally according to a preset cycle. If the heartbeat signal does not change within a preset time, the FPGA chip determines that the multi-core heterogeneous MPU chip is malfunctioning and redundancy protection measures are required.

[0067] When the FPGA chip determines that the multi-core heterogeneous MPU chip is malfunctioning through any of the above methods, the FPGA chip directly outputs a protection control signal to the critical IO redundancy control module, which then drives the external circuit breaker to disconnect, achieving hardware-level local protection without relying on the software response of the multi-core heterogeneous MPU chip.

[0068] This embodiment enhances the system's safety redundancy by adding a status monitoring function for multi-core heterogeneous MPU chips to the FPGA chip and utilizing the reliable operation characteristics of the FPGA chip's hardware logic to promptly disconnect the external circuit breaker when the main control chip fails.

[0069] Example 5: This example provides a high-control-bandwidth photovoltaic inverter control method based on Example 4, including the following steps:

[0070] An external ADC sampling chip acquires the actual current of the inverter and sends it to the data preprocessing module. After performing preprocessing such as per-unit scaling and filtering, the data preprocessing module divides the preprocessed data into two outputs: one is sent to the current loop control module, and the other is sent to the control data processing module inside the first processor.

[0071] After receiving the data, the control data processing module inside the first processor performs corresponding filtering and transformation processing, and sends the processed data to the internal voltage loop and power loop control modules. The voltage loop and power loop control modules perform voltage loop and power loop control calculations at a first frequency, generate current loop setpoint parameters, feedforward voltage, and grid phase-locked angle, and send the grid phase-locked angle to the phase-locked angle interpolation module, and send the current loop setpoint parameters and feedforward voltage to the current loop control module.

[0072] The phase-locked angle interpolation module performs interpolation compensation based on the grid phase-locked angle to obtain the real-time phase-locked angle.

[0073] The current loop control module performs current loop control calculations at a second frequency based on the given current loop parameters, feedforward voltage, real-time phase-locked angle, and pre-processed actual inverter current. This generates PWM modulation commands, which are then sent to the power module via the fiber optic communication module. The ratio of the second frequency to the first frequency is a positive integer greater than 1; in this embodiment, this ratio is limited to a positive integer greater than 1 and not exceeding 20.

[0074] Specifically, the first frequency is not lower than 3kHz, the communication frequency between the first processor and the FPGA chip is not lower than the first frequency, and the sampling frequency of the external ADC sampling chip is not lower than the second frequency. This embodiment ensures that data transmission and sampling are always faster than computation speed by setting the above frequency constraints, guaranteeing high real-time performance of the control loop.

[0075] The specific process of the phase-locked angle interpolation module for interpolation compensation based on the grid phase-locked angle includes: calculating the phase increment step size according to the grid fundamental frequency, the first frequency, and the ratio; when the grid phase-locked angle is increasing in a positive direction, the grid phase-locked angle is added to the phase increment step size, and if the sum is greater than 2π, then 2π is subtracted; when the grid phase-locked angle is decreasing in a negative direction, the grid phase-locked angle is subtracted from the phase increment step size, and if the sum is less than 0, then 2π is added.

[0076] To more clearly illustrate the interpolation compensation process in this embodiment, the ratio is set to 2 and explained. Assuming the first frequency, i.e. the current loop reference input frequency, is 3000Hz, the mains voltage frequency is 50Hz, and the ratio is 2, then the second frequency is 6000Hz.

[0077] The phase-locked angle interpolation module calculates the interpolation angle step size based on the above parameters. The specific calculation formula is as follows:

[0078]

[0079] Substitute the values, that is This translates to approximately 3 degrees in electrical angles.

[0080] The first calculation of the current loop uses the grid phase-locked angle given by the MPU. The second calculation in the same control cycle uses an angle calculated by adding an interpolated angle step size to the grid phase-locked angle given by the MPU. When the grid phase-locked angle is increasing in a positive direction, the grid phase-locked angle is added to the phase increment step size; if the sum is greater than 2π, 2π is subtracted. When the grid phase-locked angle is decreasing in a negative direction, the grid phase-locked angle is subtracted from the phase increment step size; if the subtraction is less than 0, 2π is added. The phase-locked angle can be calibrated to a value suitable for processor processing. The calculation results of each current loop are sent to the power module for execution.

[0081] The above interpolation compensation method can accurately eliminate the phase steps caused by high and low frequency operations, prevent phase abrupt changes during cycle transitions, and ensure a smooth and continuous output current waveform, thereby achieving rapid response and effective suppression of high-frequency power grid fluctuations.

[0082] After receiving the PWM modulation command, the power module executes the corresponding action, collects its own DC voltage, temperature, and fault status information, and feeds it back to the FPGA chip via the fiber optic communication module. Through this feedback link, the system can obtain the operating status of the power module in real time, providing a reliable data foundation for subsequent online protection and lifespan prediction.

[0083] The second processor retrieves data from the first processor via a shared memory area and uploads it to an external monitoring device. It also converts commands from the external monitoring device using a protocol and sends them back to the first processor via the shared memory area. Based on the data from the first processor, the second processor runs a predictive model to predict the inverter's operating status and equipment lifespan, generating alarm signals to alert maintenance personnel for timely intervention. Through this process, the system can perform data analysis and mining locally, eliminating the need to upload all data to a remote server, effectively reducing communication bandwidth requirements and improving the real-time nature of fault warnings.

[0084] The third processor monitors the operating status of the first processor in real time through a shared memory area. If the first processor crashes or malfunctions, the third processor controls an external circuit breaker to trip, providing local protection and preventing system failure due to main control chip malfunction. This step ensures safe shutdown even in extreme abnormal conditions, significantly improving the inverter's operational safety.

[0085] This embodiment constructs a complete closed-loop link from sampling, calculation, output to feedback through the above control method, realizing high-frequency fast closed-loop control of the current loop, effectively improving the system control bandwidth, thereby achieving rapid response and effective suppression of high-frequency power grid fluctuations.

[0086] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0087] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The scope of protection of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of protection of the claims.

Claims

1. A photovoltaic inverter control device with high control bandwidth, characterized in that, Includes multi-core heterogeneous MPU chips, FPGA chips, external ADC sampling chips, and fiber optic communication modules; The multi-core heterogeneous MPU chip includes a first processor and a second processor. The first processor is used to perform voltage loop and power loop control calculations, and the second processor is used to interact with external monitoring equipment. The FPGA chip includes a data preprocessing module, a phase-locked angle interpolation module, and a current loop control module. The phase-locked angle interpolation module is used to interpolate and compensate the phase-locked angle of the power grid, and the current loop control module is used to perform current loop control calculations and generate PWM modulation commands. The external ADC sampling chip is connected to the data preprocessing module. The data preprocessing module is connected to the first processor and the current loop control module. The first processor is connected to the phase-locked angle interpolation module and the current loop control module. The phase-locked angle interpolation module is connected to the current loop control module. The current loop control module is connected to the optical fiber communication module. The optical fiber communication module is used to connect to the power module.

2. The photovoltaic inverter control device with high control bandwidth according to claim 1, characterized in that, The multi-core heterogeneous MPU chip has a shared memory region, and both the first processor and the second processor are connected to the shared memory region; the first processor runs an RTOS real-time operating system or a bare-metal program, and the second processor runs a Linux operating system.

3. The photovoltaic inverter control device with high control bandwidth according to claim 2, characterized in that, The multi-core heterogeneous MPU chip also includes a third processor, which is connected to the shared memory region and to an external circuit breaker. The third processor runs a bare-metal program and is used to control the external circuit breaker to disconnect when the first processor crashes or malfunctions.

4. A photovoltaic inverter control method with high control bandwidth, applied to the photovoltaic inverter control device with high control bandwidth as described in claim 3, characterized in that, include: The first processor performs voltage loop and power loop control calculations at a first frequency, generates current loop given parameters, feedforward voltage and grid phase-locked angle, and sends the grid phase-locked angle to the phase-locked angle interpolation module, and sends the current loop given parameters and the feedforward voltage to the current loop control module; The phase-locked angle interpolation module performs interpolation compensation based on the grid phase-locked angle to obtain the real-time phase-locked angle; the external ADC sampling chip collects the actual current of the inverter and sends the actual current of the inverter to the data preprocessing module; the data preprocessing module preprocesses the actual current of the inverter and sends it to the current loop control module. The current loop control module performs current loop control calculations at a second frequency based on the given parameters of the current loop, the feedforward voltage, the real-time phase-locked angle, and the pre-processed actual inverter current, generates PWM modulation commands, and sends them to the power module through the optical fiber communication module. The ratio of the second frequency to the first frequency is a positive integer greater than 1.

5. The photovoltaic inverter control method with high control bandwidth according to claim 4, characterized in that, The ratio is a positive integer greater than 1 and not exceeding 20.

6. The photovoltaic inverter control method with high control bandwidth according to claim 4, characterized in that, The first frequency is not lower than 3kHz, the communication frequency between the first processor and the FPGA chip is not lower than the first frequency, and the sampling frequency of the external ADC sampling chip is not lower than the second frequency.

7. The photovoltaic inverter control method with high control bandwidth according to claim 4, characterized in that, The phase-locked angle interpolation module performs interpolation compensation based on the power grid phase-locked angle, including: The phase increment step size is calculated based on the fundamental frequency of the power grid, the first frequency, and the ratio. When the phase-locked angle of the power grid is increasing in a positive direction, the phase-locked angle of the power grid is added to the phase increment step size. If the sum is greater than 2π, then 2π is subtracted. When the phase-locked angle of the power grid is decreasing in a negative direction, the phase-locked angle of the power grid is subtracted from the phase increment step size. If the sum is less than 0, then 2π is added.

8. The photovoltaic inverter control method with high control bandwidth according to claim 4, characterized in that, Also includes: The second processor obtains data from the first processor through the shared memory area and uploads it to the external monitoring device. It also sends instructions issued by the external monitoring device to the first processor through the shared memory area after protocol conversion. The second processor also runs a prediction model based on the data from the first processor to predict the inverter's operating status and equipment lifespan, and generates alarm signals.

9. The photovoltaic inverter control method with high control bandwidth according to claim 4, characterized in that, Also includes: The third processor monitors the operating status of the first processor in real time through the shared memory area. When the first processor crashes or experiences an abnormal fault, the third processor controls the external circuit breaker to disconnect.

10. The photovoltaic inverter control method with high control bandwidth according to claim 4, characterized in that, Also includes: After receiving the PWM modulation command, the power module performs corresponding actions, collects its own DC voltage, temperature and fault status information, and feeds it back to the FPGA chip through the optical fiber communication module.

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