A PWM edge perturbation-based energy storage battery embedded node downlink communication method and system

Abstract

The application discloses a kind of energy storage battery embedded node downlink communication method and system based on PWM edge perturbation.The nominal duty cycle of the output of energy storage converter power control loop is obtained, and the nominal time position of the PWM switch edge is determined;According to the value of downlink bit, the switch edge is advanced or delayed by a preset perturbation relative to the nominal time position, and the downlink information is carried in the edge offset direction.The PWM signal drives the power switch device to generate a switching ripple, which is propagated to each cell terminal through the battery power channel.The receiving node extracts the switching ripple and converts it into a digital square wave, and recovers the downlink bits and analyzes the downlink instruction according to the deviation of the square wave pulse width relative to the nominal pulse width reference value.The application can reuse the existing PWM switching process of energy storage converter and implement downlink communication through battery power channel, and can accurately complete downlink information recovery using a simpler receiving structure.

Description

Technical Field

[0001] This invention belongs to the field of battery communication technology, specifically relating to a downlink communication method and system for embedded nodes in energy storage batteries based on PWM edge perturbation. Background Technology

[0002] As energy storage battery systems develop towards larger capacity, higher integration, and more refined state management, relying solely on external parameters such as cell terminal voltage, circuit current, and surface temperature is no longer sufficient to fully reflect the local state changes within the cell. To improve the ability to sense the operating state of the cell, sensors for temperature, strain, and pressure can be installed inside or near the cell, and various state information can be acquired through corresponding receiving nodes.

[0003] As the number of distributed sensing nodes in a battery system increases, establishing reliable communication between each receiving node and the battery management system becomes a problem that needs to be solved. Deploying independent communication lines for each receiving node not only increases the number of wiring harnesses and connectors within the battery system, but also increases the complexity of system layout and connection and maintenance costs, which is particularly evident in energy storage systems containing a large number of series and parallel cells.

[0004] To reduce additional communication cabling, existing solutions utilize the existing conductive paths of the battery system for power line communication. These solutions typically require corresponding carrier generation, modulation, and demodulation circuits to transmit communication signals over the power lines. For miniature receiving nodes located inside or near the battery cells, configuring both uplink and downlink communication with similar power line communication structures increases the number of communication devices, power consumption, and implementation complexity required on both the node and management sides. Especially when a separate communication transmitting unit is still used in the downlink direction, the existing periodic switching processes and electrical connections between the energy storage converter and the battery pack are not fully utilized.

[0005] Therefore, how to form downlink communication to multiple cell receiving nodes by utilizing the existing switching process and battery power channel of the energy storage system without affecting the normal PWM power control process of the energy storage converter is a problem that needs to be solved in the existing technology. Summary of the Invention

[0006] One of the objectives of this invention is to at least solve one or more of the aforementioned problems existing in the prior art. In other words, one of the objectives of this invention is to provide a downlink communication method and system for embedded nodes in energy storage batteries based on PWM edge perturbation that meets one or more of the aforementioned requirements.

[0007] To achieve the above-mentioned objectives, the present invention adopts the following technical solution: This invention provides a downlink communication method for embedded nodes in energy storage batteries based on PWM edge perturbation, comprising: Obtain the nominal duty cycle output by the power control loop of the energy storage converter during battery charging and discharging, and determine the nominal time position of the switching edge based on the nominal duty cycle and PWM period; Based on the value of the downlink bit information to be transmitted, the switch edge is advanced or delayed by a preset perturbation relative to the nominal time position, so as to represent the value of the downlink bit information by the offset direction of the switch edge, and thus obtain the PWM signal carrying the downlink bit information. The power switching devices of the energy storage converter are driven by PWM signals, so that the generated switching ripple signals are propagated to the terminals of each cell in the series battery pack through the battery power channel. The switching ripple signal is extracted from the terminal through the receiving node electrically connected to the terminal and converted into a digital square wave; The pulse width of the digital square wave is measured, the downlink bit information is recovered based on the deviation of the pulse width from the nominal pulse width reference value, the downlink command is parsed based on the recovered downlink bit information, and the operation corresponding to the downlink command is executed.

[0008] As a preferred embodiment, the switching edge is advanced or delayed by a preset perturbation relative to the nominal time position, including: Keeping the rising edge time position of each PWM cycle unchanged, the falling edge is advanced or delayed by the same preset perturbation amount relative to the nominal time position according to the value of the downlink bit information. Bit 0 corresponds to the preset perturbation amount advanced, and bit 1 corresponds to the preset perturbation amount delayed.

[0009] As a preferred implementation, the preset perturbation amount is determined according to the following method: The lower limit of the preset perturbation amount is determined based on the combined time jitter standard deviation of the receiver timer and the channel, and the coefficient determined by the target bit error rate. The upper limit of the preset perturbation is determined by multiplying the maximum allowable equivalent duty cycle offset by the PWM period. Select a preset perturbation amount between the lower limit and the upper limit.

[0010] As a preferred embodiment, extracting the switching ripple signal from the terminal and converting it into a digital square wave includes: High-frequency ripple components in the switching ripple signal are extracted using a coupling capacitor. The high-frequency ripple component is biased and high-pass filtered to keep it within the common-mode input range of the comparator and suppress low-frequency interference. The processed high-frequency ripple component is converted into a digital square wave using a comparator.

[0011] As a preferred embodiment, the method further includes: Apply the same and equal time offset to the switching edge in multiple consecutive PWM cycles to repeatedly send the same downlink bit information in multiple consecutive PWM cycles; Measure the pulse width of the digital square wave corresponding to multiple consecutive PWM cycles, and average the obtained pulse width measurements. The value of the downlink bit information is determined based on the deviation of the average pulse width from the nominal pulse width reference value.

[0012] As a preferred embodiment, the method further includes: The energy storage converter advances or delays the switching edges in multiple consecutive PWM cycles relative to the nominal time position according to a predefined synchronization codeword, forming a periodically transmitted synchronization header. The total advance time of each switching edge in the synchronization header is equal to the total delay time. The receiving node determines the received sequence based on the cycle-by-cycle pulse width deviation, performs a sliding correlation between the received sequence and a predefined synchronization codeword, and determines the position of the synchronization header when the correlation result exceeds a preset threshold. The arrival time of the predetermined pulse in the synchronization header is captured, and the local clock of the receiving node is corrected based on the deviation between the arrival time of the edge and the expected arrival time of the local clock.

[0013] As a further preferred embodiment, correcting the local clock of the receiving node includes: The phase deviation is determined based on the difference between the edge arrival time and the expected arrival time of the local clock, and the frequency deviation of the local clock is determined based on the difference between the phase deviations of two consecutive time synchronizations and the transmission period of the synchronization header. Compensate for phase and frequency deviations.

[0014] As a further preferred embodiment, the downlink instruction includes a synchronous sampling command, which includes a sampling delay parameter, the sampling delay parameter representing the number of PWM cycles between the end of the downlink frame carrying the synchronous sampling command and the execution of sampling; At multiple receiving nodes, timing begins from the end of the downlink frame according to the corrected local clock, and sensor sampling is triggered after the number of PWM cycles specified by the sampling delay parameter.

[0015] On the other hand, the present invention also provides a downlink communication system for embedded nodes of energy storage batteries based on PWM edge perturbation, including an energy storage converter, a series battery pack, and a receiving node electrically connected to the terminals of the cells in the series battery pack. Energy storage converters include power control loops, communication modulators, and power switching devices; The power control loop is used to output the nominal duty cycle during battery charging and discharging; The communication modulator is used to determine the nominal time position of the switch edge according to the nominal duty cycle and PWM period, and to advance or delay the switch edge relative to the nominal time position by a preset perturbation amount according to the value of the downlink bit information to be transmitted, so as to represent the value of the downlink bit information by the offset direction of the switch edge, and obtain the PWM signal carrying the downlink bit information. The power switching device is driven by a PWM signal, which causes the generated switching ripple signal to propagate through the battery power channel to the terminals of each cell in the series battery pack. The receiving node is used to extract the switching ripple signal from the terminal, convert it into a digital square wave, measure the pulse width of the digital square wave, recover the downlink bit information based on the deviation of the pulse width from the nominal pulse width reference value, parse the downlink command based on the recovered downlink bit information, and execute the operation corresponding to the downlink command.

[0016] In one preferred embodiment, the receiving node includes a coupling capacitor, a comparator, and a microcontroller; The coupling capacitor is connected to the terminal to extract the high-frequency ripple component in the switching ripple signal; A comparator is used to convert high-frequency ripple components into digital square waves; The microcontroller is used to record the rising edge count value and falling edge count value of the digital square wave respectively, and determines the pulse width count value based on the difference between the two to recover the downlink bit information.

[0017] Compared with the prior art, the downlink communication method and system for embedded nodes in energy storage batteries based on PWM edge perturbation provided by the present invention has the following advantages: This invention uses the PWM signal generated by the normal power control of the energy storage converter as the communication basis. Communication information is represented by the time offset of the switch edge relative to the nominal position determined by power control. The corresponding perturbations are converted into switching ripples that can propagate along the existing battery power path by the power switch action. Therefore, the existing PWM generation, power switching devices, and battery power connection path of the energy storage converter can be reused to complete downlink information transmission, reducing the need for dedicated downlink communication transmission hardware and additional communication lines.

[0018] Furthermore, this invention utilizes the advance or delay of the switch edge to create information differences in the time dimension. On the receiving side, it is only necessary to extract the corresponding switch ripple from the cell terminal and compare and shape it. The pulse width of the digital square wave can be measured using a timer, and the downlink information can be recovered based on the deviation of the pulse width from the nominal pulse width reference value. This is beneficial for accurately completing the downlink information recovery using a simpler receiving structure. Attached Figure Description

[0019] Figure 1 This is a flowchart of a downlink communication method for embedded nodes in an energy storage battery based on PWM edge perturbation, according to an embodiment of the present invention. Figure 2 This is a schematic diagram of the equivalent power channel model according to an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the process of PWM signal modulation carrying downlink bit information according to an embodiment of the present invention; Figure 4 This is a structural block diagram of a downlink communication system for an embedded node in an energy storage battery based on PWM edge perturbation, according to an embodiment of the present invention. Detailed Implementation

[0020] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0021] The following description provides examples and does not limit the scope, applicability, or examples set forth in the claims. Changes may be made to the function and arrangement of the described elements without departing from the scope of the invention. Various processes or components may be appropriately omitted, substituted, or added to the various examples. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Furthermore, features described with respect to some examples may be combined into other examples.

[0022] To facilitate understanding of the technical solutions of the embodiments of the present invention, before describing the specific method steps, the basic transmission process of the PWM signal in the energy storage battery system to which the present invention applies, and the basic principle of PWM switching edge modulation will be explained first.

[0023] In commonly used energy storage battery systems, the energy storage converter is connected to a battery pack consisting of multiple cells connected in series, and regulates the battery-side power through power switching devices during battery charging or discharging. The control side of the energy storage converter typically includes a power control loop, a PWM generation unit, a gate driver, and power switching devices. The power control loop determines the corresponding nominal duty cycle based on the current charge / discharge control requirements, and the PWM generation unit generates a periodic PWM drive signal based on the nominal duty cycle, controlling the power switching devices to turn on and off through the gate driver.

[0024] A PWM signal consists of consecutive PWM cycles. Within each PWM cycle, the PWM signal typically has a rising edge that transitions from a low level to a high level, and a falling edge that transitions from a high level to a low level. The timing of the rising and falling edges within a PWM cycle determines the duration of the high level within that cycle, i.e., the PWM pulse width; the ratio of the PWM pulse width to the PWM cycle corresponds to the duty cycle of that cycle.

[0025] After the PWM signal is applied to the power switching device of the energy storage converter via the gate driver, the power switching device performs turn-on and turn-off according to the corresponding PWM timing. Due to the periodic switching action of the power switching device, a switching ripple corresponding to the switching process will also be generated in the voltage and current of the energy storage converter. This ripple can be transmitted to the battery side through electrical connection paths such as output filter, busbar, connectors, and battery pack.

[0026] An embodiment of the present invention provides a downlink communication method for embedded nodes in an energy storage battery based on PWM edge perturbation, the flowchart of which is shown below. Figure 1 As shown, it includes steps S100-S500.

[0027] S100: Obtain the nominal duty cycle output by the power control loop of the energy storage converter during battery charging and discharging, and determine the nominal time position of the switching edge based on the nominal duty cycle and PWM period.

[0028] Specifically, during the charging or discharging power regulation of the battery, the energy storage converter outputs a corresponding nominal duty cycle based on the current power control requirements through the power control loop. The nominal duty cycle represents the PWM duty cycle determined to achieve the current charging and discharging power control without the superimposed edge perturbations corresponding to downlink communication.

[0029] Accordingly, based on the nominal duty cycle and the PWM period, the original timing of the switching edge within the corresponding PWM period can be determined, and this timing is taken as the nominal timing position of the switching edge. In other words, the nominal timing position corresponds to the switching sequence when the energy storage converter generates the PWM signal according to the original power control requirements. It serves as the reference for subsequent adjustment of the switching edge timing without changing the process by which the power control loop determines the nominal duty cycle.

[0030] In one specific implementation, the start time of each PWM cycle is used as the nominal time position of the rising edge of that cycle, and the time position of the falling edge relative to the start time of that cycle is determined according to the nominal duty cycle. For the first... The nominal time position of the rising edge of a PWM cycle can be expressed as: .

[0031] The corresponding nominal falling edge time position can be represented as: .

[0032] in, For PWM period, This is the nominal duty cycle of the power control loop output. Indicates the first The nominal falling edge time position of each PWM cycle without applied edge perturbation.

[0033] Understandably, when the nominal duty cycle of the power control loop output changes with the charging and discharging power control requirements, the nominal falling edge time position of the corresponding PWM cycle also changes. Therefore, the edge time reference used in subsequent communication modulation is always based on the nominal PWM timing given by the current power control loop, so that the edge adjustment during communication can correspond to the original power control result of the energy storage converter.

[0034] Furthermore, when a timer is used to generate a PWM signal, the PWM period and the nominal time position of the switching edge in the time domain can also be converted into the timer's count value for implementation.

[0035] As a feasible example, a microcontroller with a high-resolution timer (HRTIM) is used to generate PWM signals. Let the effective time resolution of the high-resolution timer be... The period register count value corresponding to one PWM cycle It can be represented as: .

[0036] For nominal duty cycle The corresponding nominal compare register value for: .

[0037] The nominal compare register value corresponds to the nominal time position of the falling edge under the current nominal duty cycle.

[0038] S200: Based on the value of the downlink bit information to be transmitted, the switch edge is advanced or delayed by a preset perturbation relative to the nominal time position, so as to represent the value of the downlink bit information through the offset direction of the switch edge, and thus obtain the PWM signal carrying the downlink bit information.

[0039] Specifically, such as Figure 3 As shown, after determining the nominal time position of the switching edge corresponding to the current PWM cycle in step S100, time offsets with different directions are applied to the switching edge according to the downlink bit information that the PWM cycle needs to carry. Different downlink bit values ​​correspond to different edge offset directions, thereby mapping the binary information to the advance or delay of the PWM switching edge relative to the nominal time position. Thus, a time perturbation is superimposed on the nominal PWM timing already determined by the power control loop, instead of regenerating a communication carrier independent of the power control PWM signal.

[0040] In one specific implementation, the rising edge time position of each PWM cycle remains unchanged, while the falling edge time position is changed according to the value of the downlink bit information. Specifically, when the downlink bit is 0, the falling edge is advanced by a preset perturbation amount relative to its nominal time position; when the downlink bit is 1, the falling edge is delayed by the same preset perturbation amount relative to its nominal time position.

[0041] As a feasible example, suppose the first The downlink bits carried by each PWM cycle are The preset perturbation amount is Then the edge time offset corresponding to this PWM cycle can be expressed as: .

[0042] Right now: .

[0043] For the nominal time position of the falling edge in step S100 After applying the above edge perturbation, the first The falling edge time position of each PWM cycle is: .

[0044] in, For PWM period, This represents the nominal duty cycle for the corresponding PWM period.

[0045] Since the rising edge position and the PWM period itself remain unchanged in each PWM cycle, when the falling edge is earlier, the corresponding PWM pulse width is shorter than the nominal pulse width; when the falling edge is later, the corresponding PWM pulse width is longer than the nominal pulse width. Therefore, the downlink bit information is ultimately represented by a positive or negative deviation of the PWM pulse width from the nominal state, allowing the receiver to recover the corresponding downlink bits through subsequent edge capture and pulse width measurement, without needing to make information decisions based on the increase or decrease of the ripple amplitude itself.

[0046] Furthermore, preset perturbation amount The size of the perturbation needs to simultaneously satisfy the requirements for downlink information identifiability and the limitation on its impact on the original power control. If the perturbation is too small, the resulting edge time offset is easily masked by timing errors at the receiver and timing jitter generated during channel transmission; if the perturbation is too large, it will cause the actual pulse width of the corresponding PWM cycle to deviate significantly from the nominal pulse width, increasing the disturbance of communication modulation on the power control process. Therefore, a lower limit and an upper limit for the perturbation can be determined separately, and a preset perturbation value can be selected between the two.

[0047] Specifically, the preset perturbation amount is determined according to the following method: Let the combined time jitter standard deviation of the receiver timer and the channel be... Determine the corresponding coefficients based on the target bit error rate. Then the lower limit of the preset perturbation can be expressed as: .

[0048] in, This is used to limit the required time decision margin based on the target bit error rate. As the overall time jitter increases, or the requirements for the reliability of downlink bit decisions become more stringent, the lower limit of the required perturbation increases accordingly.

[0049] On the other hand, the single-cycle equivalent duty cycle offset caused by edge perturbation corresponds to the ratio between the edge time offset and the PWM period. For the first... For each PWM cycle, we have: .

[0050] Therefore, let the maximum allowable equivalent duty cycle offset be... Then the upper limit of the preset perturbation quantity satisfies: .

[0051] Therefore, the lower limit of the perturbation required for communication reliability and the upper limit of the perturbation determined by the power perturbation limit together form a selectable range of preset perturbations, and the perturbation used for edge modulation is selected within this range. .

[0052] As a specific example, when the PWM switching frequency is 20kHz, the corresponding PWM period is... Preset perturbation measurement At this point, the time offset of the falling edge relative to the nominal position accounts for only a small proportion of one PWM cycle, and the corresponding equivalent duty cycle offset is: .

[0053] At this time, each PWM cycle carrying the downlink bit only forms a positive or negative duty cycle offset of 0.2% based on the nominal duty cycle.

[0054] Furthermore, in order to evaluate the impact of the edge perturbation used in this invention on the PWM control itself, the increase in inductor current ripple caused by the edge perturbation can be calculated as follows: .

[0055] An estimate is made, in which, For the corresponding bus voltage, This is the output filter inductor.

[0056] As a feasible example, adopt , , Estimation revealed that the inductor current ripple increment is approximately 0.115A, which is less than the magnitude of the inductor current ripple during normal operation. Therefore, by limiting the upper limit of the perturbation, it is possible to control the additional disturbance generated by the perturbation in the original PWM power regulation process while simultaneously generating a detectable edge time offset.

[0057] For the case where downlink bit 0 and bit 1 occur with approximately equal probability, since they correspond to edge perturbations of the same amplitude but opposite direction, we have: .

[0058] Therefore, under statistical conditions, the average value of positive and negative edge perturbations is zero, which can reduce the long-term average duty cycle offset caused by communication modulation.

[0059] Furthermore, the preset perturbation amount can be adjusted based on the actual communication link quality corresponding to the receiving node. Specifically, the receiving node determines the link quality indication based on the received downlink signal and transmits the corresponding link quality indication back to the BMS master controller via uplink communication. The BMS master controller adjusts the preset perturbation amount used in subsequent downlink communication based on the link quality indication.

[0060] When the link quality is below a preset lower threshold, the preset perturbation amount is increased within the aforementioned selectable range to increase the time difference between the corresponding edge positions of different downlink bits. When the link quality is above a preset upper threshold, the preset perturbation amount can be decreased to reduce the duty cycle disturbance caused by communication modulation. The adjusted preset perturbation amount is still limited between the lower limit determined based on the receiver detection capability and the upper limit determined based on the allowable equivalent duty cycle offset.

[0061] S300 uses a PWM signal carrying downlink bit information to drive the power switching device of the energy storage converter, so that the generated switching ripple signal is propagated through the battery power channel to the terminals of each cell in the series battery pack.

[0062] Specifically, after obtaining the PWM signal carrying the downlink bit information in step S200, the PWM signal is output to the gate driver of the energy storage converter, and the gate driver drives the corresponding power switching device to perform turn-on and turn-off according to the switching timing determined by the PWM signal.

[0063] The connection between the energy storage converter and the series battery pack is not ideal (DC). When the power switching devices periodically turn on and off according to the PWM signal, they generate high-frequency ripple components corresponding to the switching action at the switching nodes. This ripple, after passing through the output filter inductor and capacitor of the energy storage converter, as well as the busbars, busbars, and connectors in the battery system, can propagate along the battery power path to the terminals of each cell in the series battery pack. Thus, the switching ripple signal does not need to be transmitted through a separate communication line; instead, it propagates to the terminals of each cell via the existing electrical connection path between the energy storage converter and the series battery pack.

[0064] More specifically, in the energy storage battery system to which the method of this embodiment is applied, the battery power channel includes the output filter inductor of the energy storage converter, the output filter capacitor, the busbar or busbar of the battery system, connectors, and multiple cells arranged in series.

[0065] Since multiple cells are located in the aforementioned power channel, the switching ripple generated by the same energy storage converter can propagate to the terminals of multiple cells in the series-connected battery pack. This allows receiving nodes, located near or embedded within each cell terminal, to obtain the corresponding downlink signal from their respective cell terminals. Consequently, each receiving node can share the downlink signal generated on the converter side, and this also provides a signal propagation basis for subsequently sending broadcast commands to multiple receiving nodes via the same downlink signal and for providing a unified time reference.

[0066] Furthermore, in order to determine the signal amplitude of the switching ripple at the cell terminal after passing through the aforementioned power channel, an equivalent power channel model can be established for the power channel from the energy storage converter switching node to the cell terminal.

[0067] Specifically, as a feasible example, for Figure 2 The power channel shown is used to establish an equivalent power channel model. For the output filter inductor, its impedance can be expressed as: .

[0068] in, The inductance of the output filter inductor. Its equivalent series resistance.

[0069] For the output filter capacitor, its impedance is expressed as: .

[0070] in, This refers to the capacitance of the output filter capacitor. and These are the equivalent series resistance and equivalent series inductance of the output filter capacitor, respectively. In this embodiment: When using parameters: , , , , hour, The resonant frequency of the output LC filter is: .

[0071] Using PWM switching frequency At that time, the attenuation of the switching frequency component by the output filter is approximately as follows: .

[0072] That is approximately .

[0073] The above calculations also show that the output filter attenuates the switching frequency components generated by the power switch, but does not completely filter out the corresponding high-frequency ripple.

[0074] Furthermore, the equivalent impedance of the busbar and connectors is expressed as: .

[0075] in, The equivalent resistance of the busbar. The busbar equivalent inductance, This refers to the contact impedance of the connector. In this example, the parameter used is: .

[0076] For series-connected cells, the simplified Randles model is used to describe the cell impedance: .

[0077] in, The internal resistance of the battery cell is ohms. For charge transfer resistor, It is a double-layer capacitor.

[0078] When the angular frequency corresponding to the PWM switching frequency satisfies At that frequency, the high-frequency impedance of the battery cell is approximated by its ohmic internal resistance. ,and .

[0079] Therefore, we can further analyze the voltage division at the individual cell terminals after the switching ripple reaches the series battery pack.

[0080] For by A battery pack formed by connecting individual cells in series, the first The ripple voltage divider coefficient for each battery cell can be determined based on the cell impedance and the total impedance formed by the busbar, connectors, and other cells connected in series. Under the above high-frequency approximation conditions, it can be expressed as: .

[0081] Pick Based on its equivalent impedance calculation results, the following is obtained: .

[0082] Considering the attenuation from the output filter and the voltage division relationship on the series battery side, the overall channel gain from the energy storage converter switching node to the corresponding cell terminal is: .

[0083] Substituting the parameters into this example, we get: .

[0084] Furthermore, the fundamental amplitude is estimated based on the PWM waveform of the switching node. For the bus voltage... and nominal duty cycle The fundamental amplitude of the switching node is expressed as: .

[0085] when At that time, .

[0086] Based on the aforementioned channel gain estimation, the ripple amplitude at the cell terminal is: .

[0087] The typical detection threshold of a comparator is approximately Therefore, based on the given converter parameters, battery pack parameters and switching frequency, in this feasible example, the ripple amplitude at the cell terminal is still higher than the corresponding receiving detection threshold, and can be further extracted and processed by subsequent receiving nodes.

[0088] The above equivalent power channel analysis is mainly used to illustrate that, under the system parameters and switching frequency conditions included in the example, the PWM switching ripple, after passing through the output filter and the battery power channel, can still retain a signal amplitude that can be detected by the receiving node at the cell terminal.

[0089] The S400 extracts the switching ripple signal from the terminal through a receiving node electrically connected to the cell terminal and converts it into a digital square wave.

[0090] Specifically, the switching ripple signal propagated to the cell terminal via step S300 is superimposed on the DC voltage of the cell terminal. The receiving node first extracts the high-frequency ripple component through a coupling capacitor while simultaneously isolating the DC voltage of the cell terminal; then, the extracted high-frequency ripple is biased and high-pass filtered to bring it within the common-mode input range of the comparator and reduce the influence of low-frequency electrochemical noise and power frequency interference; the processed ripple signal is input to the comparator, and the level flipping of the comparator forms a digital square wave suitable for capture by the microcontroller timer.

[0091] A coupling capacitor is connected in series between the cell terminal and the subsequent receiving node to block the DC component of the cell terminal and allow the high-frequency ripple corresponding to the PWM switching process to pass through.

[0092] To verify the effect of coupling capacitors on signal transmission loss caused by high-frequency ripple, in a feasible example, the coupling capacitor is a C0G / NP0 dielectric ceramic capacitor with a rated voltage of 50V and a capacitance of 100nF.

[0093] For PWM switching frequency The capacitive reactance of the coupling capacitor is: .

[0094] when Sometimes, .

[0095] This impedance is much lower than the comparator's input impedance of more than 10MΩ.

[0096] Furthermore, the AC ripple of the coupling capacitor output needs to be converted to a voltage range suitable for the comparator input.

[0097] In one specific implementation, the bias circuit employs two equal-value bias circuits. The resistors are used to divide the voltage, establishing the DC bias at the comparator input. Nearby, the high-frequency ripple obtained through coupling is superimposed on the common-mode bias level.

[0098] A high-pass RC filter circuit is also provided between the bias and the comparator.

[0099] When using At that time, the cutoff frequency of the corresponding high-pass filter is: .

[0100] exist At the PWM switching frequency, the attenuation of this high-pass filter is approximately 0.25dB.

[0101] Furthermore, the ripple signal, after coupling, biasing, and high-pass filtering, is input to the positive input terminal of the comparator, and the reference voltage is... The negative input terminal of the input comparator.

[0102] When the cell-end ripple superimposed on the common-mode bias crosses the comparator threshold, the comparator's output state flips, thereby converting the original analog ripple into a digital square wave.

[0103] Through the aforementioned receiving nodes, the switching ripple superimposed on the DC voltage at the battery cell terminals undergoes DC isolation and high-frequency coupling, common-mode bias, high-pass filtering, and comparison shaping in sequence, ultimately forming a digital square wave that can be directly captured by the microcontroller's timer.

[0104] Further considering the propagation delay of the comparator itself, due to the propagation delay of the comparator... For a relatively fixed delay, its typical value is approximately For consecutive periodic measurements formed by the same comparator, when the edges being compared are all subject to the same fixed propagation delay, this common delay can be canceled out in the edge time difference processing. For example, for measurements applied relative to the nominal position... and The difference between the two time positions of the perturbation is as follows: .

[0105] Therefore, when the propagation delay can be considered as a common fixed delay, the time difference between the two opposite edge perturbations will not change.

[0106] The S500 measures the pulse width of a digital square wave, recovers the downlink bit information based on the deviation of the pulse width from the nominal pulse width reference value, parses the downlink command based on the recovered downlink bit information, and executes the operation corresponding to the downlink command.

[0107] Specifically, after converting the switching ripple signal at the battery cell terminal into a digital square wave in step S400, the timer of the microcontroller in the receiving node is configured to a dual-edge input capture mode. When the rising edge or falling edge of the comparator output digital square wave arrives, the timer capture is triggered respectively to record the timer count value corresponding to the corresponding edge.

[0108] For any PWM cycle, let the capture count value corresponding to the rising edge of its digital square wave be... The capture count value corresponding to the falling edge is Then the pulse width count value corresponding to that PWM cycle for: .

[0109] In one specific implementation, for the modulation scheme of step S200, an earlier falling edge will shorten the pulse width of the received digital square wave relative to the nominal pulse width, while a later falling edge will lengthen it relative to the nominal pulse width. Therefore, the corresponding downlink bits can be recovered based on the direction of deviation of the measured pulse width from the nominal pulse width reference value.

[0110] Let the average pulse width count used for decision be . The nominal pulse width reference value is The bit decision relationship used is as follows: .

[0111] in, Indicates the recovered first One downlink bit.

[0112] During actual charging and discharging, the nominal duty cycle of the energy storage converter may change with power control requirements. Therefore, the receiving node can also update the nominal pulse width reference value according to the continuously received PWM pulse widths so that the adopted decision benchmark corresponds to the current PWM operating state.

[0113] In one implementation, a slow-varying baseline estimation method is used to determine the nominal pulse width reference value. Specifically, pulse width measurement results for multiple consecutive PWM cycles are saved, and the pulse width measurement results are averaged using a sliding window to obtain the reference pulse width corresponding to the current time period. For the... One PWM cycle can be represented as: .

[0114] in, The length of the sliding window. This represents the pulse width measurement for each PWM cycle within the window. As a possible example, You can choose 16 or 32.

[0115] As another implementation, the nominal pulse width reference value can be determined using a known synchronization sequence already transmitted during the synchronization phase. Since the edge perturbation sequence corresponding to the synchronization header is known in advance, the receiving node, after identifying the synchronization header, can estimate the pulse width reference under the current receiving state based on the pulse width measurement results corresponding to multiple known synchronization cycles, and use the obtained reference for bit decision-making in subsequent data areas. For synchronization sequences employing a balance of positive and negative perturbations, the corresponding reference pulse width can be determined using multi-cycle measurement results within the synchronization window, without needing to determine the reference based solely on a single PWM cycle.

[0116] In other implementations, a different receiving decision method than comparing with a reference pulse width can be used. For example, the corresponding bit can be determined based on the pulse width difference between adjacent PWM cycles to reduce the impact of slow changes in the nominal duty cycle on the absolute pulse width reference; or an information bit can be represented by a pair of consecutive PWM cycles, and the decision can be made based on the pulse width relationship between the two PWM cycles corresponding to the same bit.

[0117] Furthermore, when the single-cycle counting resolution of the receiving node's timer is insufficient to stably distinguish preset edge perturbations, the following method can be used to improve the stability of bit decisions through repeated coding and multi-cycle averaging: Apply the same and equal time offset to the switching edge in multiple consecutive PWM cycles to repeatedly send the same downlink bit information in multiple consecutive PWM cycles; Measure the pulse width of the digital square wave corresponding to multiple consecutive PWM cycles, and average the obtained pulse width measurements. The value of the downlink bit information is determined based on the deviation of the average pulse width from the nominal pulse width reference value.

[0118] Specifically, making the same downlink bit in consecutive Repeatedly sent in each PWM cycle, that is, in In each PWM cycle, the same edge perturbation is applied in the direction corresponding to that bit. The receiving node obtains this... The pulse width count value for each PWM cycle, and according to: .

[0119] Calculate the average pulse width count value corresponding to this downlink bit, and then... Compared with the nominal pulse width reference value The corresponding bit value is determined by comparison, thereby improving the detection margin of a single information bit by having the same bit occupy multiple consecutive PWM cycles and averaging multiple measurements.

[0120] After continuously recovering downlink bits, the receiving node combines and parses the recovered bit stream according to the predetermined downlink frame structure.

[0121] In a feasible frame structure, the data area of ​​a downlink frame sequentially includes the frame delimiter SFD, frame type TYPE, destination address ADDR, payload length LEN, payload PAYLOAD, and CRC check field. A synchronization field can be set before the data area, and a protection interval can be set at the end of the frame.

[0122] Among them, the SFD field is used to identify the end of the synchronization area and the beginning of the data area; the TYPE field is used to determine the downlink command type; the ADDR field is used to indicate the target receiving node of the downlink frame; the LEN field is used to indicate the payload length; the PAYLOAD field is used to carry the data or parameters corresponding to the corresponding command; and the CRC field is used to verify the content of the corresponding frame.

[0123] In this frame structure, the number of PWM cycles and time occupied by each field in a downlink frame are shown in Table 1.

[0124]

[0125] Table 1 After receiving a complete downlink frame, the receiving node first determines whether the downlink frame is intended for this node based on the ADDR field. For downlink frames that need to be processed by this node, the node further verifies the recovered frame content based on the CRC field. After the frame verification passes, the receiving node determines the corresponding downlink instruction based on the TYPE field, reads the relevant parameters or data from the PAYLOAD field, and executes the operation corresponding to the downlink instruction.

[0126] Furthermore, in some embodiments of the present invention, the PWM sequence output by the energy storage converter is also used to provide a common time synchronization reference to multiple receiving nodes.

[0127] Specifically, the energy storage converter applies an advance or delay time offset to the corresponding switching edges in multiple consecutive PWM cycles according to a predefined synchronization codeword, thereby forming a periodically transmitted synchronization header. The synchronization header is still formed using the aforementioned edge perturbation method, that is, the synchronization codeword is represented by the offset direction of the switching edge relative to the nominal time position in each PWM cycle, without the need to set up an independent time synchronization line or generate an independent synchronization carrier.

[0128] Assume the synchronization header contains For each PWM cycle, the predefined synchronization codeword is represented as: .

[0129] Each codeword value corresponds to one of two perturbation directions on the switch edge. For example, a codeword value can correspond to a positive perturbation. Another codeword value corresponds to a negative perturbation. Accordingly, the communication modulator sequentially sets the edge perturbation direction corresponding to each PWM cycle according to the predefined synchronization codeword, thereby forming a synchronization header with a predetermined time structure in the PWM sequence. The synchronization header adopts a positive and negative perturbation balance form, so that the total advance time and the total delay time of each switch edge within the same synchronization header are equal, that is, the algebraic sum of edge time perturbations within the synchronization window is zero.

[0130] Therefore, the synchronization head has a predetermined edge perturbation sequence that can be identified by the receiving node, and it will not accumulate an average duty cycle offset due to the continuous use of edge offset in a single direction throughout the synchronization window.

[0131] The synchronization header, along with the PWM switching ripple generated by the energy storage converter, propagates along the aforementioned battery power path to each cell terminal. Since multiple receiving nodes receive the synchronization header generated by the same energy storage converter, each receiving node can establish a correspondence between its local clock and the synchronization reference for the same synchronization event.

[0132] After processing consecutive PWM cycles sequentially, the receiving node forms a received sequence corresponding to a predefined synchronization codeword. Subsequently, the received sequence is shifted cycle by cycle and subjected to sliding correlation with the predefined synchronization codeword. For any candidate position, the correlation result is determined based on the degree of matching between the received results of multiple consecutive PWM cycles starting from that position and the synchronization codeword; when the correlation result exceeds a preset threshold, the corresponding position is determined as the synchronization header position.

[0133] Through the above processing, the time interval where the synchronization head is located can be determined first in the continuously received PWM sequence, that is, the coarse positioning of the synchronization head is completed.

[0134] After determining the position of the synchronization head, a more accurate time correspondence is established by further utilizing the predetermined pulses in the synchronization head.

[0135] Specifically, a specific edge in the synchronization header can be pre-selected as a timestamp marker. For example, in one example, the rising edge of a predetermined pulse at the end of the synchronization header is used as the timestamp marker. After determining the synchronization header position, the receiving node records the actual arrival time of this predetermined edge using the input capture function of the microcontroller's timer. .in, Indicates the receiving node. Indicates the first Secondary time synchronization.

[0136] At the same time, based on the local clock's operating status after the previous calibration, determine the local time that the synchronization header timestamp should be expected to arrive at. .

[0137] By comparing the actual arrival time of the captured edge with the expected arrival time of the local clock, the arrival time of the receiving node at the [time value missing] is obtained. Phase deviation during subsynchronization This phase deviation reflects the degree to which the current local time reference is ahead or behind the synchronization reference provided by the energy storage converter.

[0138] Correcting a time deviation based solely on a single phase offset can correct for a time skew already established at the current moment; however, due to frequency discrepancies between the local oscillators of different receiving nodes, time deviations may re-accumulate between two synchronizations. Therefore, the frequency deviation of the local clock can also be estimated using the phase deviation obtained from two consecutive synchronizations.

[0139] Phase deviation is used to reflect the local time deviation that has formed at the current moment, while the change in continuous phase deviation is used to reflect the trend of the time deviation continuing to accumulate over time.

[0140] For example, for the consecutive th Second and third The corresponding phase deviations for the next synchronization are as follows: and Let the transmission period between the two synchronization headers be . The corresponding frequency deviation can then be expressed as: .

[0141] Furthermore, the local clock of the receiving node is corrected based on the phase and frequency deviations. For implementations using a local timer as the time reference, the measured phase deviation can first be converted into the corresponding timer count deviation: .

[0142] in, For the first The local timer counting frequency of each receiving node. This represents the timer count deviation corresponding to the current phase deviation.

[0143] The reload value of the local timer can then be adjusted based on this counting deviation. For example: .

[0144] in, This is the current local timer reload value. This is the corrected reload value. To correct the gain.

[0145] By adjusting the local timer parameters, the local clock of the receiving node is corrected, so that the local time base subsequently formed by the receiving node is gradually corrected to the common time base provided by the PWM synchronization head.

[0146] For frequency deviation, the frequency deviation results obtained from continuous synchronization can be combined during subsequent clock correction to compensate for the operating rate of the local clock, thereby reducing the time error that continues to accumulate between two adjacent synchronization heads due to the frequency deviation of the local oscillator. In other words, phase compensation mainly targets the time deviation that has already occurred, while frequency deviation compensation is mainly used to reduce the time drift that the local clock will continue to generate in the next synchronization cycle.

[0147] Furthermore, the transmission period of the synchronization head can be determined based on the residual frequency offset that may still exist in the local oscillator after frequency offset compensation and the maximum allowable synchronization time error.

[0148] Let the residual frequency offset after frequency offset compensation be... The allowed synchronization error to accumulate between adjacent synchronization headers is Then the synchronization header sending period It can satisfy .

[0149] That is, the larger the residual frequency offset, or the smaller the allowable synchronization error, the shorter the synchronization period required.

[0150] In one example, the residual frequency offset after frequency offset compensation is no greater than [value missing]. The allowable synchronization error is The corresponding synchronization period satisfies The synchronization header sending period can be further set to This enables the energy storage converter to periodically provide a time synchronization reference to each receiving node.

[0151] In some implementations, the sources of error in a single time synchronization process can also be estimated. Synchronization errors may include timing jitter at the transmitting side's PWM edge, quantization errors captured by the receiving side's timer, and time uncertainties arising from the propagation of the synchronization signal through the power channel. For the case where each error source is approximately independent, it can be expressed as: .

[0152] For example, under a set of implementation parameters, the timing jitter at the transmitter edge is approximately The receiver's timer counting period is... When the quantization error is estimated according to uniform quantization, it is: Simultaneously, the uncertainty of propagation time is taken into account. Approximately For two nodes that establish a time base using the same PWM synchronization signal, their relative synchronization error under this error estimation condition is approximately: .

[0153] Through the above time synchronization process, each receiving node first uses the same PWM synchronization head to determine a common synchronization event, then determines the phase deviation of the local clock relative to the synchronization reference according to the predetermined mark edge, and further estimates and compensates for the frequency deviation through continuous synchronization, thereby maintaining a relatively consistent local time reference between the periodic synchronization heads.

[0154] Furthermore, in some embodiments of the present invention, synchronous sampling of multiple receiving nodes can also be performed.

[0155] Specifically, in these embodiments, the downlink instruction includes a synchronization sampling command. The synchronization sampling command includes a sampling delay parameter, which represents the number of PWM cycles between the end of the downlink frame carrying the synchronization sampling command and the execution of sensor sampling.

[0156] Specifically, each receiving node receives the synchronization sampling command and recovers the downlink bits and parses the corresponding frame fields as described above. When a complete downlink frame ends, each receiving node uses the time corresponding to the end of that downlink frame as a unified timing start point and counts subsequent PWM cycles based on its calibrated local clock. After the number of PWM cycles specified by the sampling delay parameter has elapsed, the corresponding sensor is triggered to perform sampling.

[0157] Using the end time of the downlink frame as the timing start point allows different receiving nodes to determine the subsequent sampling time based on the same communication event.

[0158] In one specific implementation, the payload of the synchronization sampling command may include a sampling delay parameter Delay and a channel selection parameter Mask. Delay specifies the number of PWM cycles delayed since the end of the current synchronization sampling command frame, and Mask specifies the sensing channels to be enabled for this synchronization sampling, such as cell temperature, voltage, strain, etc. After parsing the Mask, each receiving node triggers sampling only on the corresponding specified channel.

[0159] For example, when the sampling delay parameter is At that time, each receiving node starts counting from the common reference time corresponding to the end of the synchronization sampling command frame, and in the subsequent... Sensor sampling is triggered at a predetermined time corresponding to each PWM cycle. Since the local clock of each node has been phase and frequency corrected by a periodic synchronization header, the same sampling delay parameter corresponds to the same target sampling time at each node.

[0160] For a single synchronous sampling process, each receiving node can complete the data acquisition of the designated channel at the trigger time and temporarily store the corresponding sampling results locally on the node. After the sampling action is completed, the sampling results are then transmitted back to the BMS master control via the uplink communication link.

[0161] When multiple receiving nodes need to transmit sampling results back, the aforementioned TDMA (Time Division Multiple Access) method can be used for uplink transmission. Each receiving node transmits its own sampling data within its pre-allocated uplink time slot, thus avoiding multiple nodes simultaneously sending uplink signals to the power channel after completing synchronous sampling. Synchronous sampling and time-division uplink ensure that the sensor sampling of multiple nodes occurs at a unified target time, and the data transmission after sampling is completed is performed sequentially according to the uplink time slot corresponding to each node.

[0162] Furthermore, in some embodiments of the present invention, on-demand wake-up can also be achieved through downlink communication.

[0163] Specifically, the energy storage converter forms a predetermined wake-up pulse cluster in the PWM sequence. The wake-up pulse cluster includes a pulse burst segment, a gap segment, and a pulse burst segment that appear in sequence.

[0164] The receiving node in low-power state detects the envelope change corresponding to the ripple signal at the battery cell terminal. When it detects the drop and recovery timing corresponding to the wake-up pulse cluster, it wakes up the microcontroller. After being woken up, the microcontroller enters the synchronization header search state and continues to execute the aforementioned time synchronization and downlink frame reception process.

[0165] Therefore, when there is no downlink communication task, the receiving node does not need to continuously execute the complete downlink decoding process, but enters the normal communication state after detecting the predetermined wake-up sequence.

[0166] Furthermore, in some embodiments of the present invention, when the series-connected battery pack contains a large number of cells, the voltage division ratio corresponding to the propagation of PWM switching ripple to a single cell terminal may decrease, resulting in a corresponding reduction in the downlink signal margin obtained by the receiving node. In this case, the edge perturbation parameters or repetition coding parameters can be adjusted based on the aforementioned downlink communication method.

[0167] Specifically, as a feasible example, the preset perturbation amount can be appropriately increased within the selectable range of the perturbation amount determined in step S200, so that there is a greater time difference between the edge time positions corresponding to bit 0 and bit 1, thereby improving the time domain signal margin for the receiving node to identify the edge perturbation direction.

[0168] As another feasible example, the number of repeated PWM cycles corresponding to the same information bit can be increased. That is, the same downlink bit is repeatedly transmitted in the same direction and with the same perturbation in more consecutive PWM cycles, and the receiving node completes the bit decision by averaging the pulse width measurement results of the corresponding multiple cycles. By increasing the number of repeated cycles, the measurement information used for receiving decisions can be increased without changing the perturbation in a single cycle; correspondingly, the number of PWM cycles occupied by each information bit increases, and the downlink information rate decreases.

[0169] Another embodiment of the present invention provides a downlink communication system for embedded nodes in an energy storage battery based on PWM edge perturbation. The system includes an energy storage converter, a series battery pack, and a receiving node electrically connected to the terminals of each cell in the series battery pack.

[0170] Specifically, refer to Figure 4 The system is functionally divided into a transmitter module 10, a power channel 20, receiver nodes 30, and a management layer 40. The transmitter module 10 is located on the energy storage converter side and is used to generate a PWM signal carrying downlink information based on the power control results. The power channel 20 is used to realize power transmission between the energy storage converter and the series battery pack, and simultaneously provides a propagation path for PWM switching ripple. The receiver nodes 30 include multiple receiver nodes respectively located near the terminals of each battery cell or embedded within the corresponding battery cell. The management layer 40 includes a BMS / EMS controller 41, used to receive and manage the data transmitted back from each receiver node.

[0171] The transmitter module 10 may include a BMS master controller 11, a downlink frame generator 12, a communication modulator 13, a power control loop 14, a high-resolution timer 15, a gate driver 16, and a power stage switch 17 as a power switching device, and also includes an uplink PLC receiver 18.

[0172] The power control loop 14 is used to output the nominal duty cycle according to the current power control requirements during the battery charging and discharging power regulation process of the energy storage converter. The downlink frame generator 12 is used to receive downlink communication content provided by the BMS master controller 11 and form a downlink bit stream to be transmitted according to the corresponding frame type, target address and payload data.

[0173] The communication modulator 13 works in conjunction with the power control loop 14 and the downlink frame generator 12. On one hand, the communication modulator 13 determines the nominal time position of the switching edge of each PWM cycle based on the nominal duty cycle output by the power control loop 14 and the PWM cycle. On the other hand, based on the downlink bit information provided by the downlink frame generator 12, it applies an advanced or delayed edge time offset based on the corresponding nominal time position, thereby forming PWM control parameters that combine power control timing and downlink information.

[0174] The high-resolution timer 15 generates a corresponding PWM drive signal based on the PWM control parameters formed by the communication modulator 13. In one specific embodiment, the falling edge position of the PWM can be controlled by the comparator register of the high-resolution timer 15, and the positive or negative edge perturbation calculated by the communication modulator 13 can be converted into a corresponding comparator register count offset. The gate driver 16 receives the PWM signal output by the high-resolution timer 15 and drives the power stage switch 17 to perform turn-on and turn-off according to the corresponding timing.

[0175] Furthermore, the communication modulator 13 can pre-form a sequence of comparison register values ​​corresponding to each PWM cycle within a downlink frame and store the comparison register value sequence in a memory buffer. The cycle reset event of the high-resolution timer 15 can trigger the DMA to sequentially write the comparison register values ​​in the buffer into the timer comparison register, so that the falling edge position of each PWM cycle is continuously updated according to the pre-formed edge perturbation sequence, without the processor having to perform register writing cycle by cycle.

[0176] The power channel 20 is located between the energy storage converter and the series battery pack, and may include an output filter inductor 21, an output filter capacitor 22, a bus or busbar 23, a connector 24, and multiple battery cells 25-1 to 25-N arranged in series. After the power stage switch 17 performs a switching action according to the PWM signal, it generates a corresponding switching ripple at the converter switching node. The switching ripple propagates sequentially through the output filter structure, the bus or busbar, and the connector to the series battery pack, so that each battery cell terminal can obtain a high-frequency ripple signal corresponding to the PWM switching process of the energy storage converter.

[0177] The receiving node 30 includes receiving nodes 30-1 to 30-N, each corresponding to a plurality of battery cells. Taking any receiving node 30-i as an example, it may include a coupling capacitor 31, a bias and high-pass filter circuit 32, a main comparator 33, and a microcontroller 35; it may further include a wake-up detection circuit 34, a sensor interface 36, a power supply circuit 37, and an uplink PLC transmitter 38.

[0178] The coupling capacitor 31 is connected to the terminals of the corresponding cells 25-1 to 25-N to isolate the DC voltage at the cell terminals and extract the high-frequency switching ripple. The bias and high-pass filter circuit 32 establishes a common-mode bias suitable for the input of the main comparator 33 on the extracted high-frequency ripple and suppresses low-frequency electrochemical noise and power frequency interference. The main comparator 33 converts the processed analog ripple into a digital square wave and outputs the digital square wave to the microcontroller 35.

[0179] The microcontroller 35 uses the input capture function of its internal timer to record the count values ​​of the rising and falling edges of the digital square wave, determines the pulse width of the corresponding PWM cycle based on the difference between the two, and recovers the downlink bit information according to the aforementioned pulse width decision method. For downlink bits using repetitive encoding, the microcontroller 35 can also average the pulse width measurement results of multiple consecutive PWM cycles and determine the corresponding downlink bit based on the deviation of the average pulse width from the nominal pulse width reference value.

[0180] The microcontroller 35 further performs frame parsing on the continuously recovered downlink bits, determines whether the corresponding downlink frame is directed to the current receiving node based on the target address in the frame, and performs corresponding operations according to the frame type and payload content after the verification is successful. The sensor interface 36 can be connected to sensors such as temperature, voltage, and strain sensors. When sensor sampling, synchronous sampling, or other measurement commands are parsed, the microcontroller 35 controls the corresponding sensor to perform corresponding operations through the sensor interface 36.

[0181] When time synchronization is required, the BMS master controller 11 forms a predefined synchronization header using the downlink frame generator 12 and the communication modulator 13, and transmits it using the same high-resolution timer 15, gate driver 16, and power stage switch 17. The synchronization header is simultaneously propagated to multiple receiving nodes 30-1 to 30-N via the power channel 20. The microcontroller 35 of each receiving node identifies the synchronization header based on the pulse width deviation of consecutive PWM cycles and captures the predetermined marker edges in the synchronization header to correct its own local clock.

[0182] During synchronous sampling, the BMS master controller 11 sends a synchronous sampling command containing sampling delay parameters. After parsing the synchronous sampling command, each receiving node uses the time corresponding to the end of the same downlink frame as the timing reference. After a specified number of PWM cycles under its own corrected local clock, the microcontroller 35 triggers the corresponding sensor to sample through the sensor interface 36.

[0183] Furthermore, the wake-up detection circuit 34 can remain operational even when the microcontroller 35 is in a low-power state. When the transmitter module 10 sends a predetermined wake-up pulse cluster, the wake-up detection circuit 34 detects changes in the switching ripple envelope at the battery cell terminals and triggers the microcontroller 35 to exit the low-power state after recognizing the corresponding wake-up mode. After waking up, the microcontroller 35 enters the synchronization header search state and further performs downlink frame reception.

[0184] The power supply circuit 37 can be connected to the terminals of the corresponding battery cell 25-i to convert the battery cell terminal voltage into the operating voltage required by the receiving node. The power supply circuit 37 can also be configured with an energy storage capacitor to provide transient current to the uplink PLC transmitter 38 and other node circuits during uplink communication transmission.

[0185] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this invention can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0186] The above description is merely an exemplary embodiment of this application and should not be construed as limiting the scope of this application. Any equivalent changes and modifications made in accordance with the teachings of this application shall still fall within the scope of this application. Other embodiments of this application will readily conceive of those skilled in the art upon consideration of the specification and practice of the disclosure herein. This invention is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application. The specification and embodiments are to be considered exemplary only, and the scope and spirit of this application are defined by the claims.

Claims

1. A downlink communication method for embedded nodes in an energy storage battery based on PWM edge perturbation, characterized in that, include: Obtain the nominal duty cycle output by the power control loop of the energy storage converter during battery charging and discharging, and determine the nominal time position of the switching edge based on the nominal duty cycle and the PWM period; Based on the value of the downlink bit information to be transmitted, the switch edge is advanced or delayed by a preset perturbation relative to the nominal time position, so that the value of the downlink bit information is represented by the offset direction of the switch edge, and a PWM signal carrying the downlink bit information is obtained. The power switching device of the energy storage converter is driven by the PWM signal, so that the generated switching ripple signal is propagated to the terminal of each cell in the series battery pack through the battery power channel; The switching ripple signal is extracted from the terminal through a receiving node electrically connected to the terminal and converted into a digital square wave; The pulse width of the digital square wave is measured, the downlink bit information is recovered based on the deviation of the pulse width from the nominal pulse width reference value, the downlink instruction is parsed based on the recovered downlink bit information, and the operation corresponding to the downlink instruction is executed.

2. The downlink communication method for embedded nodes in an energy storage battery based on PWM edge perturbation according to claim 1, characterized in that, Advancing or delaying the switch edge relative to the nominal time position by a preset perturbation amount includes: Keeping the rising edge time position of each PWM cycle unchanged, the falling edge is advanced or delayed by the same preset perturbation amount relative to the nominal time position according to the value of the downlink bit information, wherein bit 0 corresponds to advancing the preset perturbation amount and bit 1 corresponds to delaying the preset perturbation amount.

3. The downlink communication method for embedded nodes in an energy storage battery based on PWM edge perturbation according to claim 1, characterized in that, The preset perturbation amount is determined according to the following method: The lower limit of the preset perturbation amount is determined based on the combined time jitter standard deviation of the receiver timer and the channel, and the coefficient determined by the target bit error rate. The upper limit of the preset perturbation is determined by multiplying the maximum allowable equivalent duty cycle offset by the PWM period. The preset perturbation amount is selected between the lower limit and the upper limit.

4. The downlink communication method for embedded nodes in an energy storage battery based on PWM edge perturbation according to claim 1, characterized in that, Extracting the switching ripple signal from the terminal and converting it into a digital square wave includes: High-frequency ripple components in the switching ripple signal are extracted using a coupling capacitor. The high-frequency ripple component is biased and high-pass filtered to keep it within the common-mode input range of the comparator and suppress low-frequency interference; The comparator converts the processed high-frequency ripple component into the digital square wave.

5. The downlink communication method for embedded nodes in an energy storage battery based on PWM edge perturbation according to claim 1, characterized in that, The method also includes: Apply the same and equal time offset to the switching edge in multiple consecutive PWM cycles to repeatedly send the same downlink bit information in multiple consecutive PWM cycles; The pulse width of the digital square wave corresponding to the consecutive multiple PWM cycles is measured respectively, and the obtained pulse width measurements are averaged. The value of the downlink bit information is determined based on the deviation of the average pulse width from the nominal pulse width reference value.

6. The downlink communication method for embedded nodes in an energy storage battery based on PWM edge perturbation according to claim 1, characterized in that, The method also includes: The energy storage converter advances or delays the switching edges in multiple consecutive PWM cycles relative to the nominal time position according to a predefined synchronization codeword, forming a periodically transmitted synchronization header, wherein the total advance time of each switching edge in the synchronization header is equal to the total delay time. The receiving node determines the receiving sequence based on the cycle-by-cycle pulse width deviation, performs a sliding correlation between the receiving sequence and the predefined synchronization codeword, and determines the position of the synchronization header when the correlation result exceeds a preset threshold. The arrival time of the predetermined pulse in the synchronization header is captured, and the local clock of the receiving node is corrected based on the deviation between the arrival time of the edge and the expected arrival time of the local clock.

7. The downlink communication method for embedded nodes in an energy storage battery based on PWM edge perturbation according to claim 6, characterized in that, Correcting the local clock of the receiving node includes: The phase deviation is determined based on the deviation between the edge arrival time and the expected arrival time of the local clock, and the frequency deviation of the local clock is determined based on the difference between the phase deviations of two consecutive time synchronizations and the transmission period of the synchronization header. Compensate for the phase and frequency deviations.

8. The downlink communication method for embedded nodes in an energy storage battery based on PWM edge perturbation according to claim 6, characterized in that, The downlink instruction includes a synchronous sampling command, which contains a sampling delay parameter. The sampling delay parameter represents the number of PWM cycles between the end of the downlink frame carrying the synchronous sampling command and the execution of sampling. At each of the multiple receiving nodes, timing begins from the end of the downlink frame according to the corrected local clock, and sensor sampling is triggered after the number of PWM cycles specified by the sampling delay parameter.

9. A downlink communication system for an embedded node in an energy storage battery based on PWM edge perturbation, characterized in that, It includes an energy storage converter, a series battery pack, and a receiving node electrically connected to the terminals of the cells in the series battery pack; The energy storage converter includes a power control loop, a communication modulator, and power switching devices; The power control loop is used to output the nominal duty cycle during battery charging and discharging. The communication modulator is used to determine the nominal time position of the switch edge according to the nominal duty cycle and PWM period, and to advance or delay the switch edge relative to the nominal time position by a preset perturbation amount according to the value of the downlink bit information to be transmitted, so as to represent the value of the downlink bit information by the offset direction of the switch edge, and to obtain the PWM signal carrying the downlink bit information. The power switching device is driven by the PWM signal, so that the generated switching ripple signal is propagated through the battery power channel to the terminals of each cell in the series battery pack; The receiving node is used to extract the switching ripple signal from the terminal, convert it into a digital square wave, measure the pulse width of the digital square wave, recover the downlink bit information based on the deviation of the pulse width from the nominal pulse width reference value, parse the downlink instruction based on the recovered downlink bit information, and execute the operation corresponding to the downlink instruction.

10. The downlink communication system for embedded nodes in an energy storage battery based on PWM edge perturbation according to claim 9, characterized in that, The receiving node includes a coupling capacitor, a comparator, and a microcontroller; The coupling capacitor is connected to the terminal and is used to extract the high-frequency ripple component in the switching ripple signal; The comparator is used to convert the high-frequency ripple component into the digital square wave; The microcontroller is used to record the rising edge count value and falling edge count value of the digital square wave respectively, and determine the pulse width count value based on the difference between the two to recover the downlink bit information.

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