Dual-path heterogeneous power supply quick switching circuit and control method for power communication gateway machine

Abstract

The application discloses a dual-path heterogeneous power supply quick switching circuit and a control method for a power communication gateway machine, and relates to the field of power system automation. The circuit adopts a digital analysis and hardware comparator dual-path heterogeneous detection architecture: a PLD analysis unit intelligently judges the main power supply voltage through ADC sampling, a hardware comparator monitors the bottom threshold value of the main power supply and the threshold value is set to be lower than the PLD abnormality determination value, thereby forming a bottom protection. The switching execution adopts a MOS tube to realize seamless switching by being quickly turned on first, and a relay is turned on to bear the main power supply, and the IO3 port of the PLD cooperates with the R7 / R8 voltage division network to independently turn off the MOS tube after the relay is turned on, thereby solving the heating problem of the MOS tube caused by long-time conduction in a high-power-consumption scene. The application has the advantages of quick response and large current bearing capacity, and is suitable for a strong electromagnetic environment such as a substation.

Description

Technical Field

[0001] This invention relates to the fields of power system automation and communication technology, and in particular to a dual heterogeneous power supply fast switching circuit and control method for power communication gateways. Background Technology

[0002] The power communication gateway is a key device in a substation automation system, enabling data communication between substation equipment and the dispatch master station. It plays a crucial role in collecting, processing, and forwarding various telemetry and telesignaling information, as well as receiving and executing dispatch control commands. Its power supply reliability directly affects the normal operation of power grid dispatch monitoring and control functions. When the main power supply experiences voltage drops, fluctuations, or interruptions, it is necessary to quickly switch to the backup power supply to ensure the continuous operation of the power communication gateway and avoid serious consequences such as communication interruptions, data packet loss, or even loss of connection with the dispatch master station.

[0003] Currently, the power switching technology of power communication gateways has the following main shortcomings: First, the reliability of a single detection method is insufficient. Existing gateway products mostly use a single detection method to determine the main power supply status, such as relying solely on ADC (Analog-to-Digital Converter) data acquisition for digital analysis, or relying solely on comparators for hardware threshold judgment. Power communication gateways are typically deployed in strong electromagnetic environments such as substations and distribution stations, where electromagnetic interference may affect the normal operation of the detection circuit. A single detection method carries the risk of a single point of failure in the detection process; if the detection circuit malfunctions, it will lead to switching failure, potentially causing a serious accident such as a communication interruption between the gateway and the dispatch master station.

[0004] Secondly, digital detection methods have limited response speed. While using ADC acquisition combined with programmable logic devices (PLDs, preferably FPGAs in this embodiment) for analysis offers strong analytical capabilities and allows for complex decision-making logic, inherent delays in ADC sampling, data conversion, and digital computation mean that it may not be able to respond quickly enough to sudden events such as a sharp drop in mains power voltage. Furthermore, the gateway, as the data communication hub, has extremely high requirements for seamless power switching—any minor power interruption can cause the communication link to break, requiring a re-establishment of connection with the dispatch master station and impacting real-time power grid monitoring.

[0005] Third, it is difficult to balance the response speed and reliability of switching actuators. Relays offer high reliability, low on-resistance, and high current handling capacity, but their mechanical action time is relatively long (typically several milliseconds to tens of milliseconds). MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) offer fast switching speeds (microseconds), but their current handling capacity is relatively low, leading to significant heat generation and instability during prolonged high-current conduction. Currently, these two technologies are mostly used independently, making it difficult to simultaneously meet the requirements of rapid response and high current handling. In particular, power communication gateways typically feature multi-core processors and multiple communication interfaces, resulting in higher power consumption than traditional secondary equipment, making the heat generation problem caused by prolonged MOSFET conduction even more pronounced.

[0006] Fourth, in existing solutions that use MOSFETs and relays for coordinated switching, the MOSFETs and relays are usually driven by the same control signal, preventing the MOSFET from being independently turned off after the relay is turned on. This causes the MOSFET to remain on after the relay has completed the switching process, bearing the gateway's load current for an extended period, resulting in significant heat dissipation. In high-power gateway operation scenarios, this can lead to excessive temperature rise in the power module, affecting system reliability and device lifespan, and even causing equipment failure.

[0007] Fifth, power switching lacks anticipation of the backup power supply status. Current technologies often only focus on whether the main power supply is abnormal during switching, without fully verifying whether the backup power supply is normal and available. As a "data hub," the power communication gateway's power supply system must be absolutely reliable. Switching to a faulty backup power supply will result in a complete power outage for the gateway, causing serious consequences such as communication interruption.

[0008] Sixth, existing gateway power switching solutions are insufficiently adaptable to strong electromagnetic environments. IEC 61850-3:2013, "Requirements for communication networks and systems in substations," Clause 4.1.3, clearly stipulates the power performance requirements for substation communication equipment, specifying that power switching should not cause equipment restarts or communication interruptions. Power communication gateways must meet the national power industry's Level 4 electromagnetic compatibility standard. Existing switching solutions using single detection or purely software-based judgment are at risk of misjudgment or failure under strong interference. Summary of the Invention

[0009] To overcome the shortcomings of the prior art, the present invention provides a dual heterogeneous power supply fast switching circuit and control method for power communication gateways, which solves the problems of insufficient detection reliability, limited response speed, difficulty in balancing the performance of switching actuators, lack of backup power supply status prediction, and insufficient adaptability to strong electromagnetic environments in the prior art.

[0010] To achieve the aforementioned objectives of the invention, the technical solution adopted to solve its technical problems is as follows: This invention discloses a dual-channel heterogeneous power supply fast-switching circuit for a power communication gateway, comprising: Main power supply (U9) and backup power supply (U10); The ADC sampling unit (U4) is used to collect the voltage signals of the main power supply (U9) and the backup power supply (U10) and convert them into digital signals and transmit them to the PLD analysis unit (U1) via the data bus. The PLD analysis unit (U1) is connected to the ADC sampling unit (U4) and is used to monitor and analyze the voltage data of the main power supply (U9) and the backup power supply (U10) in real time, and output the backup power supply status signal (IO1), the main power supply status signal (IO2) and the MOSFET turn-off control signal (IO3). The hardware comparator detection unit (U6) has one input connected to the sampled voltage after voltage division of the main power supply, and the other input connected to the reference voltage source (V-ref), which is used to output an abnormal signal when the main power supply voltage is lower than the preset bottom line threshold. The preset bottom line threshold voltage of the hardware comparator detection unit (U6) is lower than the voltage threshold at which the PLD analysis unit (U1) determines that the main power supply is abnormal, thus making the hardware comparator detection unit (U6) a fallback protection mechanism in case the PLD analysis unit (U1) fails or cannot respond in time; the preset bottom line threshold voltage of the hardware comparator detection unit (U6) is 5% to 20% lower than the voltage threshold at which the PLD analysis unit (U1) determines that the main power supply is abnormal. The logic decision unit (U2) has its first input terminal connected to the backup power status signal (IO1), its second input terminal connected to the main power status signal (IO2), and its third input terminal connected to the output terminal of the hardware comparator detection unit (U6). Its output terminal is connected to the input terminal of the NMOS driver chip (U5) via the eighth resistor (R8), and is used to output a switching control signal when the backup power supply (U10) is normal and the main power supply (U9) is abnormal. The MOS transistor fast switching unit (U7) has its source connected to the output terminal of the backup power supply (U10), its drain connected to the output terminal of the gateway load (U11), and its gate connected to the output terminal of the NMOS driver chip (U5), and is controlled by the NMOS driver chip (U5). The NMOS driver chip (U5) has its input terminals connected to the output terminal of the logic decision unit (U2) via the eighth resistor (R8) and to the IO3 output terminal of the PLD analysis unit (U1) via the seventh resistor (R7), which is used to drive the MOS transistor fast switching unit (U7). The seventh resistor (R7) and the eighth resistor (R8) form a resistor divider network at the input of the NMOS driver chip (U5). The resistance of the seventh resistor (R7) is less than that of the eighth resistor (R8), such that when the MOS transistor turn-off control signal (IO3) port is in a high-impedance state, the input voltage of the NMOS driver chip (U5) is determined by the output level of the logic decision unit (U2); when the MOS transistor turn-off control signal (IO3) port is in a push-pull output low level, the input voltage of the NMOS driver chip (U5) is lower than its input low-level threshold. The relay switching unit (U8) has its common terminal connected to the gateway load output terminal (U11), its first stationary contact connected to the output terminal of the main power supply (U9), and its second stationary contact connected to the output terminal of the backup power supply (U10), and is controlled by the output signal of the logic decision unit (U2). When the logic decision unit (U2) outputs a switching control signal, the MOS transistor fast switching unit (U7) turns on before the relay switching unit (U8), and the backup power supply (U10) supplies power to the gateway load through the MOS transistor. After the relay switching unit (U8) turns on, the PLD analysis unit (U1) switches the IO3 port from a high impedance state to a push-pull output low level, and pulls the input voltage of the NMOS driver chip (U5) down to below its low level threshold through the seventh resistor (R7), so that the MOS transistor fast switching unit (U7) turns off. At the same time, the output of the logic decision unit (U2) remains at a high level, and the relay switching unit (U8) remains on, with the relay solely responsible for powering the gateway.

[0011] Furthermore, the IO3 port of the PLD analysis unit (U1) is configured as a high-impedance state under normal power supply, and is configured as a push-pull output low level after the relay switching unit (U8) is turned on.

[0012] Furthermore, it also includes a relay driving circuit, which includes an NPN transistor (U3), a first resistor (R1), a second resistor (R2), and a diode (D1). The output terminal of the logic decision unit (U2) is connected to the base of the NPN transistor (U3) via the second resistor (R2). The collector of the NPN transistor (U3) is connected to the power supply (VCC) via the relay coil and the first resistor (R1). The diode (D1) is connected in parallel across the relay coil.

[0013] Furthermore, the output of the main power supply (U9) is divided by the third resistor (R3) and the fourth resistor (R4) in series to form the first sampling voltage; the first sampling voltage is transmitted to the analog input of the ADC sampling unit (U4) and the non-inverting input of the hardware comparator detection unit (U6), respectively. The output terminal of the standby power supply (U10) forms a second sampling voltage after series voltage division by the fifth resistor (R5) and the sixth resistor (R6); this second sampling voltage is transmitted to another analog input terminal of the ADC sampling unit (U4).

[0014] Further, the logic judgment unit (U2) is a logic chip for implementing the logic function Y=(A+B)·C or an AND gate, and its logical relationship is: when the standby power supply status signal (IO1) is at a high level, and the main power supply status signal (IO2) is at a high level or the output of the hardware comparator detection unit (U6) is at a high level, a high-level switching control signal is output.

[0015] Further, the turn-on speed of the MOS tube fast switching unit (U7) is faster than the action speed of the relay switching unit (U8); during switching, the MOS tube is turned on first, then the relay is turned on, and after the relay is turned on, the MOS tube is controlled to turn off through the MOS tube turn-off control signal (IO3).

[0016] Further, the response time of the hardware comparator detection unit (U6) is less than 10 microseconds, which is faster than the response time of the PLD analysis unit (U1).

[0017] Further, the resistance ratio of the seventh resistor (R7) to the eighth resistor (R8) satisfies: R7 / (R7+R8)<V_IL / V_H, where V_H is the high-level voltage output by the logic judgment unit (U2), and V_IL is the input low-level threshold voltage of the NMOS drive chip (U5).

[0018] Further, the response time of the hardware comparator detection unit (U6) is less than the sum of the sampling period of the ADC sampling unit (U4) and the digital operation delay of the PLD analysis unit (U1).

[0019] The present invention also discloses a dual-channel heterogeneous power supply fast switching control method for a power communication gateway, which uses the above-mentioned dual-channel heterogeneous power supply fast switching circuit for control, and includes the following steps: Step S1: Collect the voltage signals of the main power supply (U9) and the standby power supply (U10) through the ADC sampling unit (U4), and at the same time monitor through the hardware comparator detection unit (U6) whether the main power supply voltage is lower than the preset bottom threshold. Step S2: The ADC sampling unit (U4) converts the analog voltage signals of the main power supply (U9) and the standby power supply (U10) into digital signals, and transmits them to the PLD analysis unit (U1). The PLD analysis unit (U1) monitors and analyzes the ADC sampling data in real time, and judges whether the main power supply (U9) is abnormal and whether the standby power supply (U10) is normal. Step S3: When the backup power supply (U10) is normal and the PLD analysis unit (U1) determines that the main power supply (U9) is abnormal or the hardware comparator detection unit (U6) determines that the main power supply voltage is lower than the bottom line threshold, a switching control signal is output; wherein, the bottom line threshold voltage monitored by the hardware comparator detection unit (U6) is lower than the voltage threshold at which the PLD analysis unit (U1) determines that the main power supply is abnormal, so that the hardware comparator detection unit (U6) serves as a fallback protection mechanism when the PLD analysis unit (U1) fails or cannot respond in time; Step S4: The logic decision unit (U2) receives the backup power status signal (IO1), the main power status signal (IO2) output by the PLD analysis unit (U1), and the abnormal signal output by the hardware comparator detection unit (U6), and performs a logic decision: When the backup power status signal (IO1) is high and the main power status signal (IO2) is high or the hardware comparator detection unit (U6) outputs a high level, the logic decision unit (U2) outputs a high-level switching control signal. Step S5: The high-level switching control signal output by the logic decision unit (U2) is simultaneously transmitted to the input terminal of the NMOS driver chip (U5) and the relay driver circuit; since the conduction response time of the MOS transistor fast switching unit (U7) is much shorter than the inherent pull-in time of the relay switching unit (U8), therefore: The NMOS driver chip (U5) drives the MOS transistor fast switching unit (U7) to complete the conduction before the relay. The backup power supply (U10) supplies power to the gateway load through the MOS transistor to ensure that the gateway's communication is not interrupted during the power switching process. Subsequently, the relay drive circuit drives the relay switching unit (U8) to operate. After the inherent operating time, the backup power supply (U10) supplies power to the gateway load through the relay contacts. Step S6: After the relay switching unit (U8) is turned on, the PLD analysis unit (U1) switches the IO3 port from high impedance to push-pull output low level. The input voltage of the NMOS driver chip (U5) is pulled down to below the turn-off threshold through the seventh resistor (R7), so that the MOS transistor fast switching unit (U7) is turned off. At the same time, the output of the logic decision unit (U2) remains high level, and the relay switching unit (U8) remains on. The relay alone provides power to the gateway, avoiding overheating caused by the MOS transistor being on for a long time.

[0020] Furthermore, in step S1, when the main power supply (U9) supplies power, the main power supply voltage is sampled by voltage division through the third resistor (R3) and the fourth resistor (R4), and the divided signals are sent to the ADC sampling unit (U4) and the hardware comparator detection unit (U6) respectively; at the same time, the backup power supply (U10) is sampled by voltage division through the fifth resistor (R5) and the sixth resistor (R6) and then sent to the ADC sampling unit (U4).

[0021] Furthermore, in step S3, the conditions under which the PLD analysis unit (U1) determines that the main power supply is abnormal include: The main power supply voltage is below the lower limit of the normal range and the duration exceeds the preset time threshold; or, The rate of change of adjacent sampling points of the main power supply exceeds the preset rate of change threshold N times consecutively, where N≥3.

[0022] By employing the above technical solutions, this invention has the following advantages and positive effects compared with the prior art: 1. Dual-path redundant detection ensures high reliability and adaptability to strong electromagnetic environments. This invention employs two independent detection mechanisms: PLD digital analysis detection and hardware comparator detection. PLD digital analysis detection can perform complex waveform analysis and trend prediction on voltage signals, possessing intelligent judgment capabilities; hardware comparator detection has a fast response speed (microsecond level) and is unaffected by digital system latency. The two detection mechanisms serve as backups and are mutually redundant. Switching can be triggered if either path detects a main power supply abnormality, effectively avoiding the detection blind spots and single-point failure risks inherent in single detection methods. Specifically, for power communication gateways deployed in strong electromagnetic environments such as substations and distribution stations, the dual-path heterogeneous redundancy design ensures reliable operation of the power switching circuit under strong electromagnetic interference, meeting the requirements of IEC 61850 standards and the power industry's Level 4 electromagnetic compatibility standard.

[0023] 2. Hardware detection provides a safety net, ensuring timely response and uninterrupted communication. This invention incorporates a hardware comparator detection unit that monitors the main power supply voltage threshold. When the main power supply voltage drops sharply, or the PLD cannot respond in time due to ADC sampling delay or digital processing delay, the hardware comparator can immediately trigger a switchover. The hardware comparator's response time is in the microsecond range, far faster than the PLD's digital analysis path, ensuring timely power switching even under the worst operating conditions. For the power communication gateway, this feature guarantees uninterrupted communication and no data loss during power switching, avoiding the serious consequences of losing contact with the dispatch master station.

[0024] 3. Coordinated switching of MOSFETs and relays balances speed and capacity. This invention employs a dual-path switching scheme using MOSFETs and relays working in tandem. MOSFETs offer fast response times (microseconds), enabling seamless and rapid power switching and preventing gateway restarts during switching. Relays, with low on-resistance, high current capacity, and high reliability, take over the main power supply path after switching, resolving the issues of severe overheating and insufficient stability associated with prolonged high-current conduction of MOSFETs. The complementary advantages of both achieve a balance between rapid response and high current carrying capacity, making it particularly suitable for high-power operation scenarios with multi-core processors and multiple communication interfaces in power communication gateways.

[0025] 4. Independent MOSFET shutdown reduces heat dissipation and improves the long-term reliability of the gateway. This invention adds a configurable high-impedance IO3 output terminal to the PLD analysis unit U1. Through a voltage divider network formed by the seventh resistor R7 and the eighth resistor R8, the MOSFET is independently shut down after the relay is turned on. This function relies on the resistance relationship between the seventh resistor R7 and the eighth resistor R8: the resistance of R7 is much smaller than that of R8 (specifically, R7 / (R7+R8) < V_IL / V_H), allowing IO3 to reliably pull the input of U5 below its low-level threshold via R7 when in push-pull mode, while the high-level output of U2 will not interfere with this pull-down process via R8. When IO3 is in a high-impedance state, the R7 branch is essentially open, and the output level of U2 can directly control the input of U5. When IO3 does not need to be turned off, it is in a high-impedance state and does not interfere with the level of the input terminal of U5. When it needs to be turned off, simply pull IO3 low, and pull the input terminal of U5 low through R7. R8 (R8 >> R7) ensures that the high level of U2 will not interfere with this pull-down process. This solution has a simple circuit structure and clear control logic, without the need for additional logic gates or complex control circuits. It effectively reduces the heat dissipation and conduction loss of the MOSFET, solves the problem of excessive temperature rise of the power module in the high-power operation scenario of the power communication gateway, and improves the long-term reliability of the system.

[0026] 5. Backup power status prediction to avoid secondary failures. This invention detects and judges the status of the backup power supply before switching, using ADC sampling and PLD analysis. Switching is only allowed when the backup power supply is normal. This avoids situations where the gateway's power supply still fails after switching due to a fault in the backup power supply itself, improving the effectiveness of power switching and the overall reliability of the system, ensuring the gateway's power supply as a "data hub" is absolutely reliable.

[0027] 6. Meets the industry standard requirements for power communication gateways. The technical solution of this invention complies with the relevant requirements for power supply conditions and hardware reliability in Clauses 5.3.2 and 6.4 of GB / T 40435-2021 "Technical Specification for Substation Data Communication Gateways", providing a highly reliable and fast-response power switching solution for power communication gateways. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This is a circuit diagram of a dual heterogeneous power supply fast switching circuit for a power communication gateway according to the present invention. Figure 2 This is a flowchart illustrating a fast switching control method for dual heterogeneous power supplies used in a power communication gateway according to the present invention.

[0029] [Explanation of Key Symbols] U1 - PLD analysis unit; U2 - Logic decision unit; U3 - NPN transistor; U4 - ADC sampling unit; U5 - NMOS driver chip; U6 - Hardware comparator detection unit; U7 - MOS transistor fast switching unit; U8 - Relay switching unit; U9 - Main power supply; U10 - Backup power supply; U11 - Gateway load output terminal; R1 - First resistor; R2 - Second resistor; R3 - Third resistor; R4 - Fourth resistor; R5 - Fifth resistor; R6 - Sixth resistor; R7 - Seventh resistor; R8 - Eighth resistor; D1 - Diode; VCC - Power supply; V-ref - Reference voltage source; IO1 - Backup power supply status signal; IO2 - Main power supply status signal; IO3 - MOS transistor turn-off control signal. Detailed Implementation

[0030] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] Example 1: Dual-channel heterogeneous power supply fast switching circuit like Figure 1As shown, this invention discloses a dual-channel heterogeneous power supply fast-switching circuit for a power communication gateway, mainly including a main power supply U9, a backup power supply U10, a PLD analysis unit U1, an ADC sampling unit U4, a hardware comparator detection unit U6, a logic decision unit U2, a MOSFET fast-switching unit U7, a relay switching unit U8, and a gateway load output terminal U11, wherein: The output of the main power supply U9 is divided by the third resistor R3 and the fourth resistor R4 in series to form the first sampling voltage. The first sampling voltage is transmitted to the analog input of the ADC sampling unit U4 and the non-inverting input of the hardware comparator detection unit U6.

[0032] The output of the backup power supply U10 is divided by the fifth resistor R5 and the sixth resistor R6 in series to form the second sampling voltage; this second sampling voltage is transmitted to another analog input terminal of the ADC sampling unit U4.

[0033] The ADC sampling unit U4 is used to collect the voltage signals of the main power supply U9 and the backup power supply U10, convert them into digital signals, and transmit them to the PLD analysis unit U1 through a data bus (such as SPI bus, i.e., Serial Peripheral Interface, corresponding to MISO / SDO and other signal lines).

[0034] The PLD analysis unit U1 (Programmable Logic Device, preferably an FPGA in this embodiment, i.e., Field-Programmable Gate Array) receives digital voltage data output by the ADC sampling unit U4 and integrates a voltage analysis algorithm module. The PLD analysis unit U1 monitors and analyzes the main power supply voltage data in real time to determine if there are any abnormalities such as voltage drops, fluctuations, or interruptions in the main power supply U9; simultaneously, it monitors the backup power supply voltage data to determine if the backup power supply U10 is functioning properly. In other embodiments, the PLD analysis unit U1 can also be implemented using a CPLD (Complex Programmable Logic Device) or other logic devices with programmable logic and configurable I / O ports; all such modifications are within the scope of this invention.

[0035] In this embodiment, the PLD analysis unit U1 outputs three control signals: the first is the backup power status signal IO1, which outputs a high level when the backup power supply U10 is normal; the second is the main power status signal IO2, which outputs a low level when the main power supply U9 is normal and a high level when the main power supply U9 is abnormal; the third is the MOSFET turn-off control signal IO3, used to independently turn off the MOSFET after the relay completes the switching. The IO3 port can be configured to a high-impedance state or a push-pull output mode: under normal power supply conditions, it is configured to a high-impedance state, which does not affect the input level of the NMOS driver chip U5; when it is necessary to turn off the MOSFET, IO3 is switched to a push-pull output and outputs a low level, pulling the input of the NMOS driver chip U5 below the turn-off threshold.

[0036] The hardware comparator detection unit U6 has one input terminal connected to the sampled voltage after voltage division of the main power supply, and the other input terminal connected to the reference voltage source V-ref. The voltage value corresponding to the reference voltage source V-ref is the bottom threshold voltage for normal power supply of the main power supply U9.

[0037] In this embodiment, when the sampled voltage after voltage division by the main power supply U9 is lower than the reference voltage, the hardware comparator detection unit U6 outputs a high-level abnormal signal; when the sampled voltage is not lower than the reference voltage, it outputs a low-level normal signal.

[0038] Preferably, the response time of the hardware comparator detection unit U6 is in the microsecond range, less than 10 microseconds, which is faster than the response time of the PLD analysis unit U1. It can serve as a fallback protection mechanism when the main power supply U9 voltage drops suddenly, ensuring that the gateway can still trigger switching in time when the PLD cannot respond in time due to ADC sampling delay or digital calculation delay.

[0039] The preset bottom line threshold voltage of the hardware comparator detection unit U6 is lower than the voltage threshold for the PLD analysis unit U1 to determine the main power supply abnormality, and the former is 5% to 20% lower than the latter, so that the hardware comparator detection unit U6 serves as a fallback protection mechanism when the PLD analysis unit U1 fails or cannot respond in time.

[0040] The logic decision unit U2 has its first input connected to the backup power status signal IO1 of the PLD analysis unit U1, its second input connected to the main power status signal IO2 of the PLD analysis unit U1, and its third input connected to the output of the hardware comparator detection unit U6. Its output is connected to the input of the NMOS driver chip U5 via the eighth resistor R8, and is used to output a switching control signal when the backup power supply U10 is normal and the main power supply U9 is abnormal.

[0041] In this embodiment, the logic decision unit U2 is an OR AND gate logic chip that implements the logic function Y=(A+B)·C. Its logic relationship is as follows: when the backup power status signal IO1 is high (backup power is normal) and (the main power status signal IO2 is high (PLD detects main power abnormality) or the hardware comparator detection unit U6 outputs high (hardware detects main power abnormality)), the logic decision unit U2 outputs a high-level switching control signal.

[0042] The switching signal is output when the following logical conditions are met: Condition 1: The backup power supply is normal (IO1 = high level); and Condition 2: Main power supply malfunction (IO2 = high level or U6 output = high level).

[0043] The MOS transistor fast switching unit U7 is an N-channel MOS transistor (i.e., an N-channel enhancement-mode MOSFET). Its source is connected to the output terminal of the backup power supply U10, its drain is connected to the output terminal of the gateway load U11, and its gate is connected to the output terminal of the NMOS driver chip U5, and it is controlled by the NMOS driver chip U5.

[0044] The NMOS driver chip U5 has its input terminals connected to the output terminal of the logic decision unit U2 via the eighth resistor R8, and to the IO3 output terminal of the PLD analysis unit U1 via the seventh resistor R7, for driving the MOS transistor fast switching unit U7.

[0045] The seventh resistor R7 and the eighth resistor R8 form a resistor divider network at the input of the NMOS driver chip U5. The resistance of the seventh resistor R7 is less than the resistance of the eighth resistor R8, such that when the MOS transistor turn-off control signal IO3 port is in a high-impedance state, the input voltage of the NMOS driver chip U5 is determined by the output level of the logic decision unit U2; when the MOS transistor turn-off control signal IO3 port is in a push-pull output low level, the input voltage of the NMOS driver chip U5 is lower than its input low-level threshold.

[0046] Under normal power supply, the MOS transistor turn-off control signal IO3 port of PLD analysis unit U1 is configured in a high-impedance state. The MOS transistor turn-off control signal IO3 branch is essentially open and does not participate in the voltage division at the input of NMOS driver chip U5. At this time, the voltage at the input of NMOS driver chip U5 is determined by the output of logic decision unit U2 through the eighth resistor R8.

[0047] When the logic decision unit U2 outputs a high-level switching control signal, the input voltage of the NMOS driver chip U5 is higher than its high-level threshold, driving the MOS transistor fast switching unit U7 to conduct, and the backup power supply U10 supplies power to the gateway load U11 through the MOS transistor fast switching unit U7.

[0048] The relay switching unit U8 is a single-pole double-throw relay. Its common terminal is connected to the gateway load output terminal U11, its first stationary contact is connected to the output terminal of the main power supply U9, and its second stationary contact is connected to the output terminal of the backup power supply U10. It is controlled by the output signal of the logic decision unit U2.

[0049] The relay switching unit U8 is driven by a relay driving circuit, which includes an NPN transistor U3, a first resistor R1, a second resistor R2, and a diode D1. The output terminal of the logic decision unit U2 is connected to the base of the NPN transistor U3 via the second resistor R2. The collector of the NPN transistor U3 is connected to the power supply VCC via the relay coil and the first resistor R1. The diode D1 is connected in parallel across the relay coil to provide freewheeling protection.

[0050] When the logic decision unit U2 outputs a switching control signal, the MOS transistor fast switching unit U7 turns on before the relay switching unit U8, and the backup power supply U10 supplies power to the gateway load through the MOS transistor. After the relay switching unit U8 turns on, the PLD analysis unit U1 switches the IO3 port from a high impedance state to a push-pull output low level, and pulls the input voltage of the NMOS driver chip U5 down to below its low level threshold through the seventh resistor R7, so that the MOS transistor fast switching unit U7 turns off. At the same time, the output of the logic decision unit U2 remains at a high level, and the relay switching unit U8 remains on, with the relay solely responsible for powering the gateway.

[0051] In a preferred embodiment, the turn-on speed of the MOS transistor fast switching unit U7 is faster than the operating speed of the relay switching unit U8; when the logic decision unit U2 outputs a switching control signal: Phase 1: The MOSFET fast switching unit U7 turns on within microseconds, and the backup power supply U10 supplies power to the gateway load through the MOSFET, realizing seamless and fast power switching and ensuring that the gateway communication is uninterrupted and data is not lost. Second stage: After the relay switching unit U8 completes the contact switching after its inherent operating time (milliseconds), the backup power supply U10 supplies power to the gateway load through the relay contacts; Phase 3: After relay switching unit U8 completes its conduction, PLD analysis unit U1 outputs a low-level control signal through IO3. This signal, after being divided by resistors R7 and R8, pulls the input voltage of NMOS driver chip U5 below the turn-off threshold, causing MOS transistor fast switching unit U7 to turn off, and relay switching unit U8 becomes the sole power supply unit. During this process, the output signal of logic decision unit U2 remains high, and the relay remains on.

[0052] Example 2: Circuit Connection Method Continue to refer to Figure 1 This embodiment of a dual heterogeneous power supply fast-switching circuit for a power communication gateway includes the following connection relationships: The positive output terminal of the main power supply U9 is grounded to GND via a voltage divider formed by the third resistor R3 and the fourth resistor R4 in series. The common node of the third resistor R3 and the fourth resistor R4 is connected to an analog input terminal of the ADC sampling unit U4 and the non-inverting input terminal of the hardware comparator detection unit U6, respectively. The inverting input terminal of the hardware comparator detection unit U6 is connected to the reference voltage source V-ref.

[0053] The positive output terminal of the backup power supply U10 is grounded to GND after being divided by the fifth resistor R5 and the sixth resistor R6 in series. The common node of the fifth resistor R5 and the sixth resistor R6 is connected to another analog input terminal of the ADC sampling unit U4.

[0054] The digital signal output terminal (such as MISO, SDO, etc.) of the ADC sampling unit U4 is connected to the corresponding data input terminal of the PLD analysis unit U1.

[0055] The backup power status signal IO1 output of the PLD analysis unit U1 is connected to the first input of the logic decision unit U2, and the main power status signal IO2 output is connected to the second input of the logic decision unit U2. The output of the hardware comparator detection unit U6 is connected to the third input of the logic decision unit U2.

[0056] The output of logic decision unit U2 is connected to the input of NMOS driver chip U5 via resistor R8. The output of MOS transistor turn-off control signal IO3 of PLD analysis unit U1 is connected to the input of NMOS driver chip U5 via resistor R7. The connection path between MOS transistor turn-off control signal IO3 and resistor R7 is independent of the path U2→R8→U5. They converge at the input of NMOS driver chip U5 to form a resistor voltage divider network. The output of NMOS driver chip U5 is connected to the gate of MOS transistor fast switching unit U7. The source of MOS transistor fast switching unit U7 is connected to the output of backup power supply U10, and the drain is connected to the gateway load output U11.

[0057] The output of logic decision unit U2 is also connected to the base of NPN transistor U3 (current limited by the second resistor R2). The emitter of NPN transistor U3 is grounded to GND, and the collector is connected to power supply VCC via the relay coil and the first resistor R1. Diode D1 is connected in reverse parallel across the relay coil.

[0058] The common terminal of the relay switching unit U8 (single-pole double-throw relay) is connected to the gateway load output terminal U11. The first stationary contact is connected to the output terminal of the main power supply U9, and the second stationary contact is connected to the output terminal of the backup power supply U10. One end of the relay coil is connected to the power supply VCC, and the other end is connected to the collector of the NPN transistor U3.

[0059] Example 3: Fast Switching Control Method for Dual-Path Heterogeneous Power Supplies like Figure 2 As shown, this invention also discloses a dual-heterogeneous power supply fast switching control method for a power communication gateway, which uses the aforementioned dual-heterogeneous power supply fast switching circuit for control, and includes the following steps: Step S1: Collect the voltage signals of the main power supply U9 and the backup power supply U10 through the ADC sampling unit U4, and at the same time monitor whether the main power supply voltage is lower than the preset bottom line threshold through the hardware comparator detection unit U6. Step S2: The ADC sampling unit U4 converts the analog voltage signals of the main power supply U9 and the backup power supply U10 into digital signals and transmits them to the PLD analysis unit U1. The PLD analysis unit U1 monitors and analyzes the main power supply voltage in real time to determine whether the main power supply U9 is abnormal; at the same time, it monitors the backup power supply voltage to determine whether the backup power supply U10 is normal and usable. Step S3: When the backup power supply U10 is normal and the PLD analysis unit U1 determines that the main power supply U9 is abnormal or the hardware comparator detection unit U6 determines that the main power supply voltage is lower than the bottom line threshold, a switching control signal is output; wherein, the bottom line threshold voltage monitored by the hardware comparator detection unit U6 is lower than the voltage threshold at which the PLD analysis unit U1 determines that the main power supply is abnormal, and the former is 5% to 20% lower than the latter, so that the hardware comparator detection unit U6 serves as a fallback protection mechanism when the PLD analysis unit U1 fails or cannot respond in time; Step S4: The logic decision unit U2 receives the backup power status signal IO1 and the main power status signal IO2 output by the PLD analysis unit U1, as well as the abnormal signal output by the hardware comparator detection unit U6, and performs a logic decision: When the backup power status signal IO1 is high (backup power is normal) and the main power status signal IO2 is high (PLD detects main power abnormality) or the hardware comparator detection unit U6 outputs high (hardware detects main power abnormality)), the logic decision unit U2 outputs a high-level switching control signal. Step S5: The high-level switching control signal output by the logic decision unit U2 is simultaneously transmitted to the input terminal of the NMOS driver chip U5 and the relay driver circuit; since the conduction response time of the MOS transistor fast switching unit U7 is much shorter than the inherent closing action time of the relay switching unit U8, therefore: The NMOS driver chip U5 drives the MOS transistor fast switching unit U7 to complete the conduction before the relay. The backup power supply U10 supplies power to the gateway load through the MOS transistor to ensure that the gateway's communication is not interrupted during the power switching process. Subsequently, the relay drive circuit drives the relay switching unit U8 to operate. After the inherent operating time, the backup power supply U10 supplies power to the gateway load through the relay contacts. Step S6: After the relay switching unit U8 is turned on, the PLD analysis unit U1 switches the IO3 port from high impedance to push-pull output low level. The input voltage of the NMOS driver chip U5 is pulled down to below the turn-off threshold through the seventh resistor R7, so that the MOS transistor fast switching unit U7 is turned off. At the same time, the output of the logic decision unit U2 remains high level, and the relay switching unit U8 remains on. The relay alone provides power to the gateway, avoiding overheating caused by the MOS transistor being on for a long time.

[0060] Furthermore, in step S1, when the main power supply U9 supplies power, the main power supply voltage is sampled by voltage division through the third resistor R3 and the fourth resistor R4, and the divided signals are sent to the ADC sampling unit U4 and the hardware comparator detection unit U6 respectively; at the same time, the backup power supply U10 is sampled by voltage division through the fifth resistor R5 and the sixth resistor R6 and then sent to the ADC sampling unit U4.

[0061] Furthermore, in step S3, the conditions under which the PLD analysis unit U1 determines that the main power supply is abnormal include: The main power supply voltage is below the lower limit of the normal range and the duration exceeds the preset time threshold; or, The rate of change of adjacent sampling points of the main power supply voltage exceeds the preset rate of change threshold N times consecutively, where N≥3.

[0062] Example 4: Judgment Logic of PLD Analysis Unit The PLD analysis unit U1 integrates a voltage analysis algorithm, and its workflow is as follows: (1) The PLD analysis unit U1 obtains the digital voltage of the main power supply U9 in real time through the ADC sampling unit U4 and compares it with the normal voltage range of the main power supply stored internally. When the main power supply voltage is continuously lower than the lower limit of the normal range for more than a preset time threshold, the main power supply is determined to be abnormal and the main power supply status signal IO2 is set to high level; otherwise, the main power supply status signal IO2 remains low level.

[0063] (2) The PLD analysis unit U1 simultaneously obtains the digital voltage of the backup power supply U10 through the ADC sampling unit U4 and compares it with the normal voltage range of the backup power supply stored internally. When the backup power supply voltage is within the normal range, the backup power supply status signal IO1 is set to high level (backup power supply U10 is normal); otherwise, the backup power supply status signal IO1 is set to low level (backup power supply U10 is abnormal).

[0064] (3) The PLD analysis unit U1 can also include a voltage change rate analysis function: when the change rate of adjacent sampling points of the main power supply voltage exceeds the preset change rate threshold (N≥3) for N consecutive times, it can predict the possible risk of power failure and output the main power supply abnormal signal in advance.

[0065] (4) The IO3 port of PLD analysis unit U1 is configured as high impedance under normal power supply. After the relay switching unit U8 completes conduction, PLD analysis unit U1 confirms that the relay has been stably turned on by internal timing or by detecting the feedback signal of the relay, and then switches the IO3 port from high impedance to push-pull output low level to turn off the MOS transistor.

[0066] Example 5: Threshold setting of hardware comparator detection unit The reference voltage source V-ref of the hardware comparator detection unit U6 is set according to the baseline voltage value of the main power supply under normal operation. Specifically, if the normal operating voltage of the main power supply U9 is V_norm and the minimum allowable operating voltage is V_min, then the corresponding reference voltage after voltage division is V_ref = V_min × R4 / (R3 + R4).

[0067] When the main power supply voltage is normal, the sampled voltage after voltage division is higher than V_ref, and the hardware comparator detection unit U6 outputs a low level. When the main power supply voltage drops below V_min, the sampled voltage after voltage division is lower than V_ref, and the hardware comparator detection unit U6 immediately flips to output a high level, triggering the switching.

[0068] The baseline threshold voltage is lower than the voltage threshold used by the PLD analysis unit U1 to determine the main power supply abnormality, and the former is 5% to 20% lower than the latter. This allows the hardware comparator detection unit U6 to still act as a fallback protection mechanism to trigger switching when the PLD analysis unit U1 is unable to respond due to ADC sampling delay or digital operation delay, ensuring the continuity of power supply to the gateway.

[0069] Example 6: Timing control of coordinated switching between MOSFET and relay In this embodiment, the timing control for the coordinated switching of the MOSFET and the relay is as follows: Let time t0 be the time when the logic decision unit U2 outputs a high-level switching control signal.

[0070] Starting at time t0, the NMOS driver chip U5 immediately responds, driving the MOSFET fast switching unit U7 to conduct. The conduction time of the MOSFET fast switching unit U7 is t_on_MOS (typically in the microsecond range, such as 1-10μs). At time t0+t_on_MOS, the backup power supply U10 supplies power to the gateway's load output terminal U11 through the MOSFET fast switching unit U7, achieving seamless power switching and ensuring that the gateway does not lose power, restart, or experience communication interruption during the switching process.

[0071] Meanwhile, the relay drive circuit drives the relay switching unit U8 to operate. The relay's engagement time is t_on_relay (typically in milliseconds, such as 5-20ms). At time t0+t_on_relay, the relay switching unit U8 completes the contact switching, and the backup power supply U10 supplies power to the gateway's load output terminal U11 through the relay contacts.

[0072] After the relay switching unit U8 completes its conduction (i.e., after t0 + t_on_relay), the PLD analysis unit U1 switches the IO3 port from a high-impedance state to a push-pull output low level. The low level of IO3 pulls the input voltage of the NMOS driver chip U5 below its logic low-level threshold through the seventh resistor R7. The NMOS driver chip U5 then stops driving, and the MOS transistor fast switching unit U7 turns off. At this time, the output of the logic decision unit U2 remains at a high level and is connected to the input of the NMOS driver chip U5 through the eighth resistor R8. However, because the resistance of the eighth resistor R8 is relatively large compared to the seventh resistor R7 (i.e., R8 >> R7), the low level of IO3 is dominated by the pull-down effect of the seventh resistor R7, causing the input of the NMOS driver chip U5 to eventually present a low level. At the same time, the high-level output signal of the logic decision unit U2 drives the relay drive circuit through another branch (through the second resistor R2), and the relay switching unit U8 remains in the conducting state.

[0073] Subsequently, the relay switching unit U8 independently took over the main power supply path of the gateway, and the MOSFET was turned off independently, effectively avoiding the overheating problem caused by the MOSFET being turned on for a long time under the high power consumption operation state of the gateway.

[0074] Example 7: Working Process Combination Figure 2 The process shown is based on the example of the main power supply U9 supplying power to the power communication gateway during normal operation: (1) Normal power supply state: The main power supply U9 supplies power to the gateway load output terminal U11 through the normally closed contact of the relay switching unit U8 (the first stationary contact is connected to the common terminal). The ADC sampling unit U4 continuously collects the voltage of the main power supply U9 and the backup power supply U10, the PLD analysis unit U1 continuously performs analysis, and the hardware comparator detection unit U6 continuously monitors the main power supply voltage baseline. At this time, the IO3 port is configured in a high impedance state.

[0075] (2) PLD detects main power supply abnormality: When the main power supply U9 experiences voltage fluctuations, the PLD analysis unit U1 determines the main power supply is abnormal through ADC data analysis. Simultaneously, after confirming that the backup power supply U10 is normal, it sets the backup power supply status signal IO1 high and the main power supply status signal IO2 high. The logic decision unit U2 outputs a high-level switching signal, triggering the rapid conduction of the MOSFET and the relay switching. The MOSFET conducts within microseconds, ensuring uninterrupted communication with the gateway; the relay completes the switching within milliseconds.

[0076] (3) Hardware detects main power supply abnormality: When the main power supply voltage drops rapidly and the PLD analysis unit U1 cannot respond in time, the hardware comparator detection unit U6 detects that the sampled voltage is lower than the reference voltage V-ref and immediately outputs a high level. The logic decision unit U2 receives this signal and, after confirming that the backup power supply status signal IO1 is high (backup power supply U10 is normal), outputs a high-level switching signal to trigger the rapid conduction of the MOSFET and the switching of the relay. The hardware comparator serves as a fallback protection mechanism to ensure that power switching can still be completed in a timely manner under the worst operating conditions.

[0077] (4) Switching execution: Whether triggered by PLD detection or hardware comparator detection, the switching execution process is the same -- the MOS transistor first turns on in microseconds to achieve seamless switching, ensuring that the communication between the gateway machine and the dispatch master station is uninterrupted and the data is not lost; the relay then completes the switching and takes over the power supply in milliseconds.

[0078] (5) MOS transistor turn-off: After the relay completes conduction, the PLD analysis unit U1 switches the MOS transistor turn-off control signal IO3 port from a high-impedance state to a push-pull output low level. Through the seventh resistor R7, the input voltage of the NMOS driver chip U5 is pulled down to below the turn-off threshold, and the MOS transistor is turned off. The relay remains on and is powered by the relay alone, which solves the problem of heat generation caused by the MOS transistor being on for a long time in the high-power operation scenario of the gateway.

[0079] (6) Power supply restoration: When the main power supply is restored to normal, the power supply can be switched back to the main power supply manually or automatically.

[0080] Example 8: MOSFET turn-off control principle and parameter design of the seventh resistor R7 and the eighth resistor R8 This embodiment describes in detail the control principle for realizing independent turn-off of the MOS transistor through the seventh resistor R7 and the eighth resistor R8.

[0081] As shown Figure 1 , the output end of the logic judgment unit U2 is connected to the input end of the NMOS driver chip U5 via the eighth resistor R8; the MOS transistor turn-off control signal IO3 port of the PLD analysis unit U1 is connected to the input end of the NMOS driver chip U5 via the seventh resistor R7. The MOS transistor turn-off control signal IO3 port can be configured as a high-impedance state or push-pull output low level. The two resistors form a resistor voltage divider network at the input end of the NMOS driver chip U5.

[0082] (1) Normal power supply state (IO3 is in high-impedance state): When the MOS transistor turn-off control signal IO3 port is configured to a high-impedance state, the branch of the MOS transistor turn-off control signal IO3 is approximately open-circuited, no current flows through the seventh resistor R7, and the voltage at the input end of the NMOS driver chip U5 is determined by the output end of the logic judgment unit U2 via the eighth resistor R8: V_U5_IN=V_H where V_H is the high-level voltage output by the logic judgment unit U2. At this time, the voltage at the input end of the NMOS driver chip U5 is V_H, which is higher than its high-level threshold V_IH, so the NMOS driver chip U5 works normally and drives the MOS transistor fast switching unit U7 to conduct (when the switching signal is valid).

[0083] (2) MOS transistor turn-off state (IO3 outputs low level in push-pull mode): When the MOS transistor turn-off control signal IO3 port switches to push-pull output low level (0V), the seventh resistor R7 pulls the input end of the NMOS driver chip U5 low, and the eighth resistor R8 is connected to the output end of the logic judgment unit U2 (which is still at high level V_H). Neglecting the input current at the input end of the NMOS driver chip U5, according to Kirchhoff's current law, the voltage at the input end of U5 is: V_U5_IN=V_H×R7 / (R7+R8) To ensure reliable turn-off of the MOS transistor, the following condition shall be satisfied: V_U5_IN<V_IL, where V_IL is the input low-level threshold of the NMOS driver chip U5.

[0084] (3) Resistance value selection conditions: Considering the two states above, the resistance values of the seventh resistor R7 and the eighth resistor R8 need to satisfy the following two conditions: Conduction state (IO3 is in high-impedance state): V_H>V_IH (since the IO3 branch is open-circuited, the voltage at the input end of the NMOS driver chip U5 is exactly V_H, and it is only required that V_H itself is higher than V_IH, which is independent of the seventh resistor R7 and the eighth resistor R8) Off state (IO3 push-pull low level): V_H×R7 / (R7+R8)<V_IL It can be derived from the turn-off condition that R7 / (R7+R8)<V_IL / V_H, that is, the ratio of the seventh resistor R7 to the eighth resistor R8 needs to be sufficiently small. In other words, the eighth resistor R8 should be much larger than the seventh resistor R7, so that the high level of the logic judgment unit U2 is divided by the eighth resistor R8 and appears as a low level at the input end of the NMOS driver chip U5.

[0085] In a specific application of this embodiment, by way of example, taking V_H=3.3V and V_IL=0.8V, it is required to satisfy R7 / (R7+R8)<0.8 / 3.3≈0.242. Taking R7=1kΩ and R8=10kΩ, then R7 / (R7+R8)=1 / 11≈0.091 < 0.242, which satisfies the turn-off condition. At turn-off, V_U5_IN=3.3V ×1kΩ / (1kΩ+10kΩ)=0.3V<0.8V, and the MOS transistor is reliably turned off.

[0086] When turned on, IO3 is in a high-impedance state, the voltage at the input end of the NMOS driver chip U5 is V_H=3.3V, which is higher than its high-level threshold V_IH (usually 2.0V), and the MOS transistor can be turned on normally.

[0087] The advantages of this solution are: the MOS transistor turn-off control signal IO3 is in a high-impedance state when turn-off is not required, and does not interfere with the level at the input end of the NMOS driver chip U5 at all; when turn-off is required, the MOS transistor turn-off control signal IO3 only needs to be pulled low to pull the input end of the NMOS driver chip U5 to a low level through the seventh resistor R7, and the eighth resistor R8 ensures that the high level of the logic judgment unit U2 will not interfere with this pulling-low process. The circuit structure is simple, and the control logic is clear.

[0088] (4) Implementation of independent conduction maintenance of the relay: During the above turn-off process of the MOS transistor, the output terminal voltage V_H of the logic judgment unit U2 remains constant all the time, and its high-level signal drives the base of the NPN triode U3 through the second resistor R2, so that the triode remains conductive, the relay coil is continuously energized, and the relay switching unit U8 maintains the pull-in state. Therefore, the turn-off action of the MOS transistor does not affect the conduction state of the relay, realizing the cooperative working effect of "the MOS transistor is independently turned off, and the relay independently maintains conduction".

[0089] Embodiment 9: Core chip selection In this embodiment, the logic decision unit U2 is preferably implemented using a Texas Instruments SN74LVC1G3208 single-channel three-input positive OR AND gate logic chip. The positive logic Boolean function implemented by this chip is Y=(A+B)·C. Here, the C input corresponds to the backup power status signal IO1 output by the PLD analysis unit U1, the B input corresponds to the abnormal signal output by the hardware comparator detection unit U6, and the A input corresponds to the main power status signal IO2 output by the PLD analysis unit U1. The output Y outputs a switching control signal to the NMOS driver chip U5 and the relay driver circuit. When the C input is high (backup power supply U10 is normal) and at least one of A or B is high (backup power supply U10 is normal and any detection mechanism is triggered), a high-level switching control signal is output, which meets the logic decision conditions required by this invention.

[0090] The NMOS driver chip U5 preferably uses the LTC7001 fast high-side N-channel MOSFET gate driver manufactured by Analog Devices. This chip has a built-in internal charge pump, which can comprehensively enhance the external N-channel MOSFET switch and keep it on indefinitely; its powerful 1Ω gate driver has an extremely short switching time and a 35ns propagation delay, enabling it to drive the fast switching unit U7 of the MOSFET within microseconds, meeting the timing requirements for fast switching in this invention. This chip receives a low-voltage digital input signal based on ground (i.e., a combination of the switching control signal output by the logic decision unit U2 and the MOSFET turn-off control signal IO3), quickly driving the high-side N-channel power MOSFET.

[0091] Example 10: Typical Application Scenarios in Power Communication Gateway This embodiment specifically illustrates the application of the power switching circuit of the present invention in a power communication gateway.

[0092] Power communication gateways are typically deployed in the relay protection room or communication equipment room of substations, power plants, or distribution stations, serving as a data communication hub between the station's equipment and the dispatch master station. Internally, the gateway is equipped with a multi-core processor, multiple Ethernet communication interfaces, serial communication interfaces, and a human-machine interface module. Its power consumption is typically tens to hundreds of watts, higher than traditional relay protection devices, placing higher demands on the heat dissipation of the power module and its long-term operational reliability.

[0093] When the power switching circuit of this invention is applied to a gateway, the main power supply U9 and the backup power supply U10 provide dual DC power inputs (typically DC 220V or DC 110V) to the gateway's power module. During normal operation, the gateway is powered by the main power supply via the normally closed contact of the relay switching unit U8. The ADC sampling unit U4 continuously monitors the voltages of both power supplies, the PLD analysis unit U1 analyzes the power quality in real time, and the hardware comparator detection unit U6 monitors the main power supply baseline threshold in real time.

[0094] When the main power supply U9 experiences an anomaly (such as voltage drop, fluctuation, or interruption), the circuit of this invention completes the MOSFET turn-on within microseconds, and the backup power supply U10 supplies power to the gateway device through the MOSFET. Due to the extremely short switching time, the gateway device's processor, communication module, and operating system are unaffected, the communication link with the dispatch master station remains uninterrupted, telemetry and teleindication data are not lost, and remote control commands can be executed normally.

[0095] After the relay completes the switching within milliseconds, the PLD analysis unit U1 independently turns off the MOSFET via the IO3 port, allowing the relay to solely power the gateway. During this process, the MOSFET's on-time is only a few milliseconds, far less than its thermal time constant under high-power gateway operation, making the MOSFET's temperature rise negligible. Subsequent power supply is handled by the relay contacts with extremely low on-resistance (typically milliohms), resulting in very low conduction losses and minimal heat generation, effectively ensuring the thermal stability and reliability of the gateway's power module during long-term operation.

[0096] Once the main power supply U9 is restored, the power supply can be switched back to the main power supply U9 manually or automatically, and the system will return to normal operation. The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A dual-channel heterogeneous power supply fast-switching circuit for a power communication gateway, characterized in that, include: Main power supply (U9) and backup power supply (U10); The ADC sampling unit (U4) is used to collect the voltage signals of the main power supply (U9) and the backup power supply (U10) and convert them into digital signals and transmit them to the PLD analysis unit (U1) via the data bus. The PLD analysis unit (U1) is connected to the ADC sampling unit (U4) and is used to monitor and analyze the voltage data of the main power supply (U9) and the backup power supply (U10) in real time, and output the backup power supply status signal (IO1), the main power supply status signal (IO2) and the MOSFET turn-off control signal (IO3). The hardware comparator detection unit (U6) has one input connected to the sampled voltage after voltage division of the main power supply, and the other input connected to the reference voltage source (V-ref), which is used to output an abnormal signal when the main power supply voltage is lower than the preset bottom line threshold. The preset bottom line threshold voltage of the hardware comparator detection unit (U6) is lower than the voltage threshold at which the PLD analysis unit (U1) determines that the main power supply is abnormal, thus making the hardware comparator detection unit (U6) a fallback protection mechanism in case the PLD analysis unit (U1) fails or cannot respond in time; the preset bottom line threshold voltage of the hardware comparator detection unit (U6) is 5% to 20% lower than the voltage threshold at which the PLD analysis unit (U1) determines that the main power supply is abnormal. The logic decision unit (U2) has its first input terminal connected to the backup power status signal (IO1), its second input terminal connected to the main power status signal (IO2), and its third input terminal connected to the output terminal of the hardware comparator detection unit (U6). Its output terminal is connected to the input terminal of the NMOS driver chip (U5) via the eighth resistor (R8), and is used to output a switching control signal when the backup power supply (U10) is normal and the main power supply (U9) is abnormal. The MOS transistor fast switching unit (U7) has its source connected to the output terminal of the backup power supply (U10), its drain connected to the output terminal of the gateway load (U11), and its gate connected to the output terminal of the NMOS driver chip (U5), and is controlled by the NMOS driver chip (U5). The NMOS driver chip (U5) has its input terminals connected to the output terminal of the logic decision unit (U2) via the eighth resistor (R8) and to the IO3 output terminal of the PLD analysis unit (U1) via the seventh resistor (R7), which is used to drive the MOS transistor fast switching unit (U7). The seventh resistor (R7) and the eighth resistor (R8) form a resistor divider network at the input of the NMOS driver chip (U5). The resistance of the seventh resistor (R7) is less than that of the eighth resistor (R8), such that when the MOS transistor turn-off control signal (IO3) port is in a high-impedance state, the input voltage of the NMOS driver chip (U5) is determined by the output level of the logic decision unit (U2); when the MOS transistor turn-off control signal (IO3) port is in a push-pull output low level, the input voltage of the NMOS driver chip (U5) is lower than its input low-level threshold. The relay switching unit (U8) has its common terminal connected to the gateway load output terminal (U11), its first stationary contact connected to the output terminal of the main power supply (U9), and its second stationary contact connected to the output terminal of the backup power supply (U10), and is controlled by the output signal of the logic decision unit (U2). When the logic decision unit (U2) outputs a switching control signal, the MOS transistor fast switching unit (U7) turns on before the relay switching unit (U8), and the backup power supply (U10) supplies power to the gateway load through the MOS transistor. After the relay switching unit (U8) turns on, the PLD analysis unit (U1) switches the IO3 port from a high impedance state to a push-pull output low level, and pulls the input voltage of the NMOS driver chip (U5) down to below its low level threshold through the seventh resistor (R7), so that the MOS transistor fast switching unit (U7) turns off. At the same time, the output of the logic decision unit (U2) remains at a high level, and the relay switching unit (U8) remains on, with the relay solely responsible for powering the gateway.

2. The dual-channel heterogeneous power supply fast-switching circuit for a power communication gateway according to claim 1, characterized in that, The IO3 port of the PLD analysis unit (U1) is configured as a high-impedance state under normal power supply, and is configured as a push-pull output low level after the relay switching unit (U8) is turned on.

3. A dual-channel heterogeneous power supply fast-switching circuit for a power communication gateway according to claim 1, characterized in that, It also includes a relay driving circuit, which includes an NPN transistor (U3), a first resistor (R1), a second resistor (R2), and a diode (D1). The output terminal of the logic decision unit (U2) is connected to the base of the NPN transistor (U3) via the second resistor (R2). The collector of the NPN transistor (U3) is connected to the power supply (VCC) via the relay coil and the first resistor (R1). The diode (D1) is connected in parallel across the relay coil.

4. A dual-channel heterogeneous power supply fast-switching circuit for a power communication gateway according to claim 1, characterized in that, The output of the main power supply (U9) is divided by the third resistor (R3) and the fourth resistor (R4) in series to form the first sampling voltage; the first sampling voltage is transmitted to the analog input terminal of the ADC sampling unit (U4) and the non-inverting input terminal of the hardware comparator detection unit (U6) respectively. The output of the backup power supply (U10) is divided by the fifth resistor (R5) and the sixth resistor (R6) in series to form the second sampling voltage; the second sampling voltage is transmitted to the other analog input terminal of the ADC sampling unit (U4).

5. A dual-channel heterogeneous power supply fast-switching circuit for a power communication gateway according to claim 1, characterized in that, The logic decision unit (U2) is an OR AND gate logic chip that implements the logic function Y=(A+B)·C. Its logic relationship is as follows: when the backup power status signal (IO1) is high and the main power status signal (IO2) is high or the hardware comparator detection unit (U6) outputs a high level, a high level switching control signal is output.

6. A dual-channel heterogeneous power supply fast-switching circuit for a power communication gateway according to claim 1, characterized in that, The MOS transistor fast switching unit (U7) turns on faster than the relay switching unit (U8); during switching, the MOS transistor turns on first, and the relay turns on later. After the relay turns on, the MOS transistor is turned off by the MOS transistor turn-off control signal (IO3).

7. A dual-channel heterogeneous power supply fast-switching circuit for a power communication gateway according to claim 1, characterized in that, The response time of the hardware comparator detection unit (U6) is less than 10 microseconds, which is faster than the response time of the PLD analysis unit (U1).

8. A dual-channel heterogeneous power supply fast-switching circuit for a power communication gateway according to claim 1, characterized in that, The resistance ratio of the seventh resistor (R7) to the eighth resistor (R8) satisfies: R7 / (R7+R8)<V_IL / V_H, where V_H is the high-level voltage output by the logic judgment unit (U2), and V_IL is the input low-level threshold voltage of the NMOS driving chip (U5).

9. A dual-channel heterogeneous power supply fast-switching circuit for a power communication gateway according to claim 1, characterized in that, The response time of the hardware comparator detection unit (U6) is less than the sum of the sampling period of the ADC sampling unit (U4) and the digital operation delay of the PLD analysis unit (U1).

10. A fast switching control method for dual heterogeneous power supplies in a power communication gateway, characterized in that, Control is performed using the dual-channel heterogeneous power supply fast switching circuit as described in any one of the preceding claims 1 to 9, comprising the following steps: Step S1: Collect voltage signals of the main power supply (U9) and the standby power supply (U10) through the ADC sampling unit (U4), and simultaneously monitor whether the main power supply voltage is lower than a preset bottom threshold through the hardware comparator detection unit (U6); Step S2: The ADC sampling unit (U4) converts the analog voltage signals of the main power supply (U9) and the standby power supply (U10) into digital signals, and transmits the digital signals to the PLD analysis unit (U1). The PLD analysis unit (U1) monitors and analyzes the ADC sampling data in real time, and judges whether the main power supply (U9) is abnormal and whether the standby power supply (U10) is normal; Step S3: When the standby power supply (U10) is normal and the PLD analysis unit (U1) determines that the main power supply (U9) is abnormal, or the hardware comparator detection unit (U6) determines that the main power supply voltage is lower than the bottom threshold, a switching control signal is output; wherein the bottom threshold voltage monitored by the hardware comparator detection unit (U6) is lower than the voltage threshold for the PLD analysis unit (U1) to determine that the main power supply is abnormal, so that the hardware comparator detection unit (U6) serves as a fallback protection mechanism when the PLD analysis unit (U1) fails or cannot respond in time; Step S4: The logic judgment unit (U2) receives the standby power supply status signal (IO1) and the main power supply status signal (IO2) output by the PLD analysis unit (U1), and the abnormal signal output by the hardware comparator detection unit (U6), and performs logic judgment: When the standby power supply status signal (IO1) is at a high level and the main power supply status signal (IO2) is at a high level, or the hardware comparator detection unit (U6) outputs a high level, the logic judgment unit (U2) outputs a high-level switching control signal; Step S5: The high-level switching control signal output by the logic judgment unit (U2) is simultaneously transmitted to the input terminal of the NMOS driving chip (U5) and the relay driving circuit. Since the turn-on response time of the MOS tube fast switching unit (U7) is much shorter than the inherent pull-in operation time of the relay switching unit (U8), therefore: The NMOS driving chip (U5) drives the MOS tube fast switching unit (U7) to complete turn-on before the relay, and the standby power supply (U10) supplies power to the gateway load through the MOS tube, ensuring that the communication of the gateway is not interrupted during the power supply switching process; Subsequently, the relay driving circuit drives the relay switching unit (U8) to operate. After the inherent operation time, the standby power supply (U10) supplies power to the gateway load through the relay contact; Step S6: After the relay switching unit (U8) is turned on, the PLD analysis unit (U1) switches the IO3 port from high impedance to push-pull output low level. The input voltage of the NMOS driver chip (U5) is pulled down to below the turn-off threshold through the seventh resistor (R7), so that the MOS transistor fast switching unit (U7) is turned off. At the same time, the output of the logic decision unit (U2) remains high level, and the relay switching unit (U8) remains on. The relay alone provides power to the gateway, avoiding overheating caused by the MOS transistor being on for a long time.

11. A fast switching control method for dual heterogeneous power supplies in a power communication gateway according to claim 10, characterized in that, In step S1, when the main power supply (U9) supplies power, the main power supply voltage is sampled by voltage division through the third resistor (R3) and the fourth resistor (R4), and the divided signals are sent to the ADC sampling unit (U4) and the hardware comparator detection unit (U6) respectively; at the same time, the backup power supply (U10) is sampled by voltage division through the fifth resistor (R5) and the sixth resistor (R6) and then sent to the ADC sampling unit (U4).

12. A fast switching control method for dual heterogeneous power supplies in a power communication gateway according to claim 10, characterized in that, In step S3, the conditions under which the PLD analysis unit (U1) determines that the main power supply is abnormal include: (1) The main power supply voltage is lower than the lower limit of the normal range and the duration exceeds the preset time threshold; or, (2) The rate of change of adjacent sampling points of the main power supply voltage exceeds the preset rate of change threshold N times in a row, where N≥3.

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