Single-input multiple-output power conversion circuit and control method thereof

Abstract

A single-input multiple-output power conversion circuit and a control method thereof. The power conversion circuit converts an input voltage into a main channel output voltage and a first channel output voltage. The power conversion circuit includes a power stage circuit and a conversion control circuit. The power stage circuit includes an inductor, at least one main switch, a main channel output switch and a first channel output switch. The conversion control circuit includes a channel control circuit and a main control circuit. The channel control circuit generates a first channel amplification signal and an output control signal according to the first channel output voltage and a first channel reference voltage to control the on-off state of each channel output switch and to generate different output voltages in a time-division manner. The main control circuit generates a main switch control signal according to the main channel output voltage, a main reference voltage and the first channel amplification signal to control the switching of the at least one main switch.

Description

Technical Field

[0001] This invention relates to a power conversion circuit, and more particularly to a power conversion circuit capable of supporting single-input multiple-output applications. The invention also relates to a control method for controlling the power conversion circuit for the aforementioned single-input multiple-output applications. Background Technology

[0002] In existing technologies, power conversion circuits with a Single-Input Multi-Output (SIMO) architecture typically have multiple channel switches following a switched power stage. These channel switches are controlled by a time-division control circuit. This time-division control circuit includes multiple sets of error amplifier circuits and modulation circuits corresponding to each output channel. By using time-division multiplexing, the switches of each output channel are turned on sequentially, and the conduction ratio of the switched power stage is adjusted according to the feedback signal of each individual output to achieve multi-channel voltage regulation control.

[0003] To simplify control logic and avoid inter-channel interference, this type of time-division multiplexing architecture often employs discontinuous conduction mode operation. In this mode, the inductor current of each output channel returns to zero in each cycle. While this reduces control complexity, it introduces the following disadvantages:

[0004] Output current capability is limited: In discontinuous conduction mode, the inductor current of each channel must return to zero within one switching cycle, which limits the actual average output current that can be provided by both the conduction time and the rise and fall rate of the inductor current.

[0005] Large output current ripple: The non-continuous conduction mode operation increases the ripple amplitude of the output voltage and current. Summary of the Invention

[0006] From one perspective, the present invention provides a power conversion circuit for converting an input voltage into multiple output voltages, including a first channel output voltage and a main channel output voltage. The power conversion circuit includes: a power stage circuit comprising: an inductor coupled between a first switching node and a second switching node; at least one main switch coupled to the inductor; a main channel output switch coupled between the second switching node and the main channel output voltage; and a first channel output switch coupled between the second switching node and the first channel output voltage. The at least one main switch, the main channel output switch, and the first channel output switch are used to periodically switch the electrical connection state of the first switching node and / or switch the second switching node. The circuit comprises: an electrical connection state of a point to control the magnetization and demagnetization of the inductor to generate an inductor current; and a switching control circuit, including: a channel control circuit for generating a first channel amplified signal based on the first channel output voltage and a first channel reference voltage, and generating a first output control signal and a main output control signal based on the first channel amplified signal, for controlling the switching of the first channel output switch and the main channel output switch respectively, and generating the first channel output voltage and the main channel output voltage sequentially based on the inductor current in a time-division manner according to a preset time sequence; and a main control circuit for generating a main switch control signal based on the main channel output voltage, a main reference voltage and the first channel amplified signal, to control the switching of the at least one main switch.

[0007] In one embodiment, the channel control circuit includes: a first channel amplifier for amplifying the difference between a first channel reference voltage and a first channel feedback voltage to generate the first channel amplified signal, wherein the first channel feedback voltage is related to the first channel output voltage; a first channel comparator for comparing the first channel amplified signal with a first channel ramp signal to generate a first channel trigger signal; and a channel modulation circuit for generating the first output control signal and the main output control signal based on the first channel trigger signal; wherein the main control circuit includes: a main channel amplifier for amplifying the difference between the main channel reference voltage and a main channel feedback voltage to generate a main channel amplified signal, wherein the main channel feedback voltage is related to the main channel output voltage; and a main modulation circuit for generating the main switching control signal based on the main channel amplified signal and the first channel amplified signal.

[0008] In one embodiment, the main modulation circuit further generates the main switch control signal based on an inductor current related signal, and controls the switching of the at least one main switch to perform loop control in a valley current mode, a peak current mode, or a fixed on-time mode; wherein the inductor current related signal is related to the inductor current.

[0009] In one embodiment, the main modulation circuit includes: a main channel comparator for comparing the sum of two of a composite amplified signal, a main channel ramp signal, and the inductor current-related signal with the third of the three signals to generate a main channel trigger signal; and a state circuit for generating the main switch control signal based on the main channel trigger signal; wherein the composite amplified signal is a linear combination of the first channel amplified signal and the main channel amplified signal.

[0010] In one embodiment, the first channel output switch includes a first channel rectifier switch and a first channel path switch, which are connected in series between the second switching node and the first channel output voltage, wherein the reverse end of the body diode of the first channel rectifier switch and the reverse end of the body diode of the first channel path switch are coupled to each other; wherein the main channel output switch includes a main channel rectifier switch and a main channel path switch, which are connected in series between the second switching node and the main channel output voltage, wherein the reverse end of the body diode of the main channel rectifier switch and the reverse end of the body diode of the main channel path switch are coupled to each other.

[0011] In one embodiment, during all transition periods when the inductor current shifts between the first channel output voltage and the main channel output voltage, both the first channel rectifier switch and the main channel rectifier switch are in the off state, and both the first channel path switch and the main channel path switch are in the on state. Thus, the body diode of the first channel rectifier switch and the body diode of the main channel rectifier switch work together to rectify the first channel output voltage and the main channel output voltage to determine the voltage at the second switching node.

[0012] In one embodiment, the power stage circuit further includes a second channel output switch coupled between the second switching node and a second channel output voltage; wherein the channel control circuit further generates a second channel amplified signal based on the second channel output voltage and a second channel reference voltage, and also generates a first output control signal, a main output control signal, and a second output control signal based on the second channel amplified signal, to control the switching of the first channel output switch, the main channel output switch, and the second channel output switch respectively, thereby generating the main channel output voltage, the first channel output voltage, and the second channel output voltage sequentially based on the inductor current in a time-division manner according to a preset time sequence; wherein the main control circuit further generates the main switch control signal based on the second channel amplified signal.

[0013] In one embodiment, the channel control circuit further includes: a second channel amplifier for amplifying the difference between the second channel reference voltage and a second channel feedback voltage to generate the second channel amplified signal, wherein the second channel feedback voltage is related to the second channel output voltage; and a second channel comparator for comparing the second channel amplified signal with a second channel ramp signal to generate a second channel trigger signal; wherein the channel modulation circuit further generates the first output control signal, the second output control signal, and the main output control signal based on the second channel trigger signal; wherein the main modulation circuit further generates the main switch control signal based on a linear combination of the main channel amplified signal, the first channel amplified signal, and the second channel amplified signal.

[0014] In one embodiment, the power stage circuit further includes a flying capacitor, wherein the at least one main switch includes a plurality of main switches for switching the electrical connection between the flying capacitor and the inductor to perform multi-stage pulse width modulation power conversion to generate the inductor current.

[0015] In one embodiment, the power stage circuit further includes an auxiliary transistor coupled between the input voltage and the first channel output voltage; wherein in a bypass mode, the auxiliary transistor is used to turn on the input voltage to the first channel output voltage; or in a linear adjustment mode, the auxiliary transistor is used to perform linear loop control to linearly adjust the first channel output voltage to a first target voltage; wherein in the bypass mode or the linear adjustment mode, the first output control signal is disabled and the main output control signal is enabled.

[0016] In one embodiment, the channel control circuit is further configured to generate an auxiliary control signal to control the auxiliary transistor; wherein when the difference between the first target voltage of the first channel output voltage and the input voltage is less than a preset range, or the difference between the first channel reference voltage and the input voltage is less than a preset range, the channel control circuit controls the power conversion circuit to enter the bypass mode or the linear adjustment mode.

[0017] In one embodiment, the at least one main switch includes a first main switch and a second main switch, the first main switch and the second main switch being connected in series between the input voltage and a ground, and the first main switch and the second main switch being coupled to each other at the first switching node.

[0018] In one embodiment, the at least one main switch further includes a third main switch coupled between the second switching node and the ground; wherein the power stage circuit can selectively operate in buck power conversion mode, boost power conversion mode or buck-boost power conversion mode.

[0019] In one embodiment, the at least one main switch includes a fourth main switch coupled between the second switching node and the ground.

[0020] From another perspective, the present invention provides a control method for controlling a power conversion circuit. The power conversion circuit converts an input voltage into multiple output voltages, including a first channel output voltage and a main channel output voltage. The power conversion circuit includes: an inductor coupled between a first switching node and a second switching node; at least one main switch coupled to the inductor; a main channel output switch coupled between the second switching node and the main channel output voltage; and a first channel output switch coupled between the second switching node and the first channel output voltage. The control method includes: controlling the at least one main switch, the main channel output switch, and the first channel output switch to periodically switch the electrical connection state of the first switching node and / or switch the electrical connection state of the second switching node to control the magnetization and demagnetization of the inductor to generate an inductor current; wherein the step of generating the inductor current includes: generating a first channel amplified signal based on the first channel output voltage and a first channel reference voltage; generating a first output control signal and a main output control signal based on the first channel amplified signal; controlling the switching of the first channel output switch and the main channel output switch with the first output control signal and the main output control signal respectively; generating the first channel output voltage and the main channel output voltage sequentially based on the inductor current in a time-division manner according to a preset time sequence; and generating a main switch control signal based on the main channel output voltage, a main reference voltage, and the first channel amplified signal to control the switching of the at least one main switch.

[0021] This invention provides a power conversion circuit for single-input multiple-output applications, which effectively overcomes inter-channel interference, supports continuous conduction mode, improves output current capability, and reduces inductor current surge and output current ripple.

[0022] The following detailed description through specific embodiments will make it easier to understand the purpose, technical content, features and effects achieved by the present invention. Attached Figure Description

[0023] Figure 1 This shows a circuit diagram of a power conversion circuit according to an embodiment of the present invention.

[0024] Figure 2 This illustrates a specific embodiment of the present invention, corresponding to... Figure 1 A circuit diagram of the power conversion circuit.

[0025] Figure 3 This illustrates an embodiment of the present invention corresponding to... Figure 2 The waveform diagram of the operation.

[0026] Figure 4A This shows a circuit block diagram of the main control circuit in a specific embodiment of the present invention.

[0027] Figure 4B This shows a circuit block diagram of the main control circuit in another specific embodiment of the present invention.

[0028] Figure 4C This shows a circuit block diagram of the main control circuit in another specific embodiment of the present invention.

[0029] Figure 5A This diagram shows a power conversion circuit schematic of a specific embodiment of the present invention.

[0030] Figure 5B This diagram shows a power conversion circuit schematic of a specific embodiment of the present invention.

[0031] Figure 6 This illustrates an embodiment of the present invention corresponding to... Figure 5A The waveform diagram of the operation.

[0032] Figure 7 This shows a circuit block diagram of a channel control circuit in a specific embodiment of the present invention.

[0033] Figure 8 This diagram shows a power conversion circuit schematic of another embodiment of the present invention.

[0034] Figure 9A This shows a circuit diagram of a power conversion circuit in another embodiment of the present invention.

[0035] Figure 9B This illustrates a specific embodiment of the present invention, corresponding to... Figure 9A The circuit block diagram of the conversion control circuit.

[0036] Figure 10 This shows a circuit diagram of a power conversion circuit according to an embodiment of the present invention.

[0037] Figure 11 This illustrates an embodiment of the present invention corresponding to... Figure 10 The waveform diagram of the operation.

[0038] Figure 12 This shows a circuit diagram of a power conversion circuit according to an embodiment of the present invention.

[0039] Figure 13 This diagram shows a circuit diagram of the control circuit in one embodiment of the present invention.

[0040] Explanation of symbols in the diagram

[0041] 10, 10', 10”: Channel control circuit

[0042] 11, 111: First channel amplifier

[0043] 12, 121: First channel comparator

[0044] 13d1, 13d2: Delay circuits

[0045] 14: OR Gate

[0046] 15: OR Gate

[0047] 16: with the door

[0048] 17: Inverter

[0049] 20, 20', 20", 20A, 20B, 20C, 20'A, 20'B: Main control circuit

[0050] 21: Main Channel Amplifier

[0051] 22A, 22B, 22C, 22”: Main channel comparators

[0052] 23: State Circuit

[0053] 24, 25: Drivers

[0054] 50: Power stage circuit

[0055] 51, 81: Switching converter

[0056] 60, 70, 80, 90: Power stage circuits

[0057] 61: Switching to a capacitor converter

[0058] 112: Second Channel Amplifier

[0059] 120: Control Circuit

[0060] 122: Second channel comparator

[0061] 130, 130”: Channel modulation circuit

[0062] 100, 300, 500A, 500B, 700, 800, 900A, 900B, 1000, 1200: Power conversion circuits

[0063] 110: Conversion control circuit

[0064] 1210: Amplifier

[0065] 1220: Voltage divider circuit

[0066] 132: With the door

[0067] 133: NOR gate

[0068] 210: Main modulation circuit

[0069] 230, 231: Fixed conduction time control circuit

[0070] 232: First Single Pulse Generator

[0071] 233: Second Single Pulse Generator

[0072] CF: Flying Capacitor

[0073] CLK: Clock signal

[0074] Fsw: Switching frequency

[0075] G1, G2, Gc1, Gc2, Gcm: Amplification Gain

[0076] iL: Inductor current

[0077] Ioc1, Ioc2, Iocm: Channel output current

[0078] Izc: Zero current threshold

[0079] L: Inductor

[0080] LX1, LX2: Switching nodes

[0081] M1, M2, M3, Mm: Main switches

[0082] Qbp: Auxiliary transistor

[0083] Qc1, Qc2, Qcm: Channel output switches

[0084] Qm1, Qm2, Qm3, Qm4: Main switches

[0085] QRc1, QRcm: Channel rectifier switch

[0086] Qoc1, Qocm: Channel path switch

[0087] Sbp: Auxiliary control signal

[0088] Sc1, Sc2, Scm: Output control signals

[0089] Scom, Scom', Scom”: Combined amplified signal

[0090] Scot: On-time control signal

[0091] SeaX: Amplify Signal

[0092] Seac1, Seac2, Seacm: Channel amplification signals

[0093] SiL: Inductor current sensing signal

[0094] SiLb: Inductor current related signal

[0095] Sm1, Sm2, Sm3, Smm: Main switch control signals

[0096] Soc1, Socm: Channel path switch control signals

[0097] SRc1, SRcm: Channel rectifier switch control signals

[0098] Strc1, Strc2, Stcm: Channel trigger signals

[0099] Sd1, Sd2: Delayed trigger signals

[0100] Strc1b: Inverting trigger signal

[0101] t0, t1, t2, t3, t4, t5, t6: Time points

[0102] Tp1, Tp2: Time period

[0103] Tsw: Switching cycle

[0104] Vin: Input voltage

[0105] Vb: DC bias voltage

[0106] VfbX: Feedback voltage

[0107] Vrefc1, Vrefc2, Vrefcm, VrefX: Reference voltages

[0108] Voc1, Voc2, Vocm, VoX: Channel output voltage

[0109] Vrampc1, Vrampc2, Vrampcm: Channel ramp signals Detailed Implementation

[0110] The accompanying drawings in this invention are schematic and are primarily intended to illustrate the coupling relationships between circuits and the relationships between signal waveforms. The circuits, signal waveforms, and frequencies are not drawn to scale. For clarity, many practical details will be described in the following description, but this is not intended to limit the scope of the patent application.

[0111] Figure 1This diagram shows a power conversion circuit according to an embodiment of the present invention. The power conversion circuit 100 includes a power stage circuit 50 and a conversion control circuit 110.

[0112] The power stage circuit 50 is a switching converter with two outputs, including at least one main switch Mm, an inductor L, a main channel output switch Qcm, and a first channel output switch Qc1. The inductor L is coupled between the first switching node LX1 and the second switching node LX2.

[0113] The first channel output switch Qc1 is coupled between the inductor L and the first channel output voltage Voc1 through the second switching node LX2; the main channel output switch Qcm is coupled between the inductor L and the main channel output voltage Vocm through the second switching node LX2. At least one main switch Mm, the main channel output switch Qcm, and the first channel output switch Qc1 are used to periodically switch the electrical connection state of the first switching node LX1 and / or switch the electrical connection state of the second switching node LX2 to control the magnetization and demagnetization of the inductor L to generate an inductor current iL.

[0114] The conversion control circuit 110 includes a channel control circuit 10 and a main control circuit 20. The channel control circuit 10 generates a first output control signal Sc1 and a main output control signal Scm based on the first channel output voltage Voc1 and the first channel reference voltage Vrefc1. When the first output control signal Sc1 is enabled, it controls the first channel output switch Qc1 to turn on; when Sc1 is disabled, it enables the main output control signal Scm to turn on the main channel output switch Qcm. In one embodiment, Sc1 and Scm are enabled in a time-division manner according to a preset time sequence, thereby sequentially generating the first channel output voltage Voc1 and the main channel output voltage Vocm based on the inductor current iL. In one embodiment, this time sequence is Sc1 and Scm.

[0115] In one specific embodiment, the channel control circuit 10 is used to generate a first channel amplified signal Seac1 based on the first channel output voltage Voc1 and the first channel reference voltage Vrefc1, thereby generating the aforementioned first output control signal Sc1 and main output control signal Scm. In one embodiment, the channel control circuit 10 is used to amplify the difference between the first channel output voltage Voc1 and the first channel reference voltage Vrefc1 to generate the first channel amplified signal Seac1, the details of which will be described later.

[0116] The main control circuit 20 generates a main switch control signal Smm based on the main channel output voltage Vocm, the main reference voltage Vrefcm, and the first channel amplified signal Seac1, in order to control the switching of the at least one main switch and improve the cross-regulation capability between load transient response and multiple outputs.

[0117] In one embodiment, the main control circuit 20 further performs pulse width modulation loop control in a valley-current mode or a peak-current mode based on the inductor current sensing signal SiL. The inductor current sensing signal SiL is related to the inductor current iL, for example, obtained by sensing the inductor current iL.

[0118] Figure 2 This illustrates a specific embodiment of the present invention, corresponding to... Figure 1 A circuit diagram of the power conversion circuit is provided. In this embodiment, at least one main switch includes a first main switch M1 and a second main switch M2. The first main switch M1 and the second main switch M2 are connected in series and coupled between the input voltage Vin and ground. An inductor L is coupled to a first switching node LX1 where the first main switch M1 and the second main switch M2 are coupled to each other. In this embodiment, the first main switch M1, the second main switch M2, and the inductor L form a switching converter 51. Specifically, in this embodiment, the switching converter 51 corresponds to a buck switching converter, and the first main switch M1 and the second main switch M2 are used to switch the voltage VLX1 of the first switching node LX1 to generate an inductor current iL. In other embodiments, the switching converter 51 may also correspond to a boost or buck-boost switching converter.

[0119] Continue reading Figure 2 In one embodiment, the channel control circuit 10 includes a first channel amplifier 11, a first channel comparator 12, and a channel modulation circuit 130. The first channel amplifier 11 amplifies the difference between the first channel reference voltage Vrefc1 and the first channel output voltage Voc1 to generate a first channel amplified signal Seac1. The first channel comparator 12 compares the first channel amplified signal Seac1 with the first channel ramp signal Vrampc1 to generate a first channel trigger signal Strc1. The channel modulation circuit 130 generates a first output control signal Sc1 and a main output control signal Scm based on the first channel trigger signal Strc1 (i.e., the comparison between the first channel amplified signal Seac1 and the first channel ramp signal Vrampc1).

[0120] Continue reading Figure 2In one embodiment, the main control circuit 20 includes a main channel amplifier 21 and a main modulation circuit 210. The main channel amplifier 21 amplifies the difference between the main channel reference voltage Vrefcm and the main channel output voltage Vocm to generate a main channel amplified signal Seacm. The main modulation circuit 210 generates main switch control signals Sm1 and Sm2 based on the main channel amplified signal Seacm and the first channel amplified signal Seac1. In one embodiment, the main modulation circuit 210 also generates main switch control signals Sm1 and Sm2 based on the inductor current sensing signal SiL. The channel control circuit 10 and the main control circuit 20 adjust the first channel output voltage Voc1 to a first target voltage and adjust the main channel output voltage Vocm to a main target voltage through the first output control signal Sc1, the main output control signal Scm, and the main switch control signals Sm1 and Sm2.

[0121] Figure 3 This illustrates an embodiment of the present invention corresponding to... Figure 2 The operating waveform diagram is shown. In one embodiment, the switching control circuit 110 controls the switching operation of the switch in the power stage circuit 50 based on a switching cycle Tsw.

[0122] like Figure 3 As shown, during the time interval t0 to t1, the main switch control signal Sm1 is enabled (e.g., at a high level) to control the first main switch M1 to conduct, and the main switch control signal Sm2 is disabled (e.g., at a low level) to control the second main switch M2 to turn off, thereby magnetizing the inductor L. During the time interval t1 to t3, the first main switch M1 is turned off (i.e., not conducting), while the second main switch M2 is conducted, thereby demagnetizing the inductor L. In one embodiment, the main switch control signals Sm1 and Sm2 are out of phase.

[0123] The first channel ramp signal Vrampc1 begins to rise slowly at time t0. During the time interval t0 to t2, the first output control signal Sc1 is enabled to control the first channel output switch Qc1 to be in the on state, and the main output control signal Scm is disabled to control the main channel output switch Qcm to be in the off state, allowing the inductor current iL to flow to the first channel output voltage Voc1. When the first channel ramp signal Vrampc1 exceeds (for example, rises to be greater than) the first channel amplification signal Seac1 at time t2, the first output control signal Sc1 is disabled, and the main output control signal Scm is enabled. During the time interval t2 to t3, the main channel output switch Qcm is turned on, the first channel output switch Qc1 is turned off, and the inductor current iL flows to the main channel output voltage Vocm instead.

[0124] The conduction time (t0~t2) of the first output control signal Sc1 and the conduction time (t2~t3) of the main output control signal Scm are determined based on the comparison result of the first channel ramp signal Vrampc1 and the first channel amplification signal Seac1. Figure 3 The time point t2 shown is later than t1. In other embodiments, time point t2 may also be earlier than t1 or overlap with t1. Specifically, time point t2 is determined based on the relationship between the average value of the first channel output current Ioc1 and the average value of the main channel output current Iocm. In one embodiment, when the first channel output current Ioc1 and the main channel output current Iocm are large (i.e., under heavy load), the aforementioned switching converter 51 can operate in continuous conduction mode. In other embodiments, when the first channel output current Ioc1 and the main channel output current Iocm are low (i.e., under light load), the aforementioned switching converter 51 can operate in boundary conduction mode or discontinuous conduction mode.

[0125] From one perspective, the power conversion circuit 100 includes a dual-loop system: a main loop and a channel loop. The channel loop includes control of the first channel output switch Qc1 and the main channel output switch Qcm, fed back from the first channel output voltage Voc1 to the channel control circuit 10. The main loop includes control of the main switches M1 and M2, fed back from the main channel output voltage Vocm and the first channel output voltage Voc1 (via the channel control circuit 10) to the main control circuit 20. Specifically, the main control circuit 20 performs pulse width modulation (PWM) control of the main loop based on the main channel output voltage Vocm, the main reference voltage Vrefcm, and the first channel amplified signal Seac1 from the channel control circuit 10, determining the duty cycle of the main switches M1 and M2. The channel control circuit 10 performs PWM control of the channel loop based on the first channel output voltage Voc1 and the first channel reference voltage Vrefc1, determining the duty cycle of the first channel output switch Qc1 and the main channel output switch Qcm. In one embodiment, the first output control signal Sc1 and the main output control signal Scm are inversely related.

[0126] Figure 4AThis diagram shows a circuit block diagram of the main control circuit 20A in a specific embodiment of the present invention. In one embodiment, the main control circuit 20A includes a main channel amplifier 21, a main channel comparator 22A, and a state circuit 23. The main channel amplifier 21 amplifies the difference between the main channel output voltage Vocm and the main channel reference voltage Vrefcm to generate a main channel amplified signal Seacm. In one embodiment, the main channel comparator 22A generates a main channel trigger signal Strcm based on the comparison of the following signals: a first channel amplified signal Seac1, the main channel amplified signal Seacm, and a main channel ramp signal Vrampcm. Under pulse width modulation in current mode or fixed on-time mode, the main channel comparator 22A also generates the main channel trigger signal Strcm based on the inductor current related signal SiLb. In one embodiment, the inductor current related signal SiLb is the sum of the inductor current sensing signal SiL and the DC bias voltage Vb. In one embodiment, the potential of the DC bias voltage Vb is higher than the amplitude of the main channel ramp signal Vrampcm.

[0127] The state circuit 23 (e.g., a latching circuit) generates a first main switch control signal Sm1 and a second main switch control signal Sm2 through drivers 24 and 25 based on the main channel trigger signal Strcm and the clock signal CLK with a switching frequency Fsw. The switching frequency Fsw is the reciprocal of the aforementioned switching period Tsw.

[0128] In one embodiment, the main control circuit 20A can control the power conversion circuit to perform loop control in valley current mode to improve transient response characteristics. The valley current mode control architecture, due to its lower switching noise, can generate a first main switch control signal Sm1 and a second main switch control signal Sm2 with relatively short conduction times during pulse width modulation. In other embodiments, the main control circuit 20A can also control the power conversion circuit to perform loop control in peak current mode.

[0129] Figure 4B This shows a circuit block diagram of the main control circuit 20B in another specific embodiment of the present invention. The main control circuit 20B in this embodiment is similar to... Figure 4AThe main control circuit 20A performs loop control in either valley current mode or peak current mode. In one embodiment, the integrated amplified signal Scom is obtained by adding the first channel amplified signal Seac1 (the product of the two) amplified by the first amplification gain G1 and the main channel amplified signal Seacm (the product of the two) amplified by the second amplification gain G2. In other words, the integrated amplified signal Scom is a linear combination of the first channel amplified signal Seac1 and the main channel amplified signal Seacm, i.e., Scom = Gc1 × Seac1 + Gcm × Seacm, where the amplification gains Gc1 and Gcm are real numbers. From one perspective, assuming that both the first channel amplified signal Seac1 and the main channel amplified signal Seacm are continuous analog signals, the integrated amplified signal Scom is also a continuous, non-time-division analog signal.

[0130] The main control circuit 20B can set the ratio of the first amplification gain G1 and the second amplification gain G2 according to the output requirements of each channel, so as to improve the load transient response and the cross-adjustment capability between multiple outputs.

[0131] In one embodiment, the main channel comparator 22B generates a main channel trigger signal Strcm based on the comparison of the following inputs: a composite amplified signal Scom, a main channel ramp signal Vrampcm, and an inductor current-related signal SiLb.

[0132] Specifically, the main channel comparator 22B, for example, compares the sum of two of the synthesized amplified signal Scom, the main channel ramp signal Vrampcm, and the inductor current-related signal SiLb with the third of these signals to generate the main channel trigger signal Strcm. Further details can be found in [the documentation / reference]. Figure 4A Description of the main control circuit 20A.

[0133] Figure 4C This shows a circuit block diagram of the main control circuit 20C in another specific embodiment of the present invention. In this embodiment, the main control circuit 20C employs a loop control with a fixed on-time mode.

[0134] The main channel comparator 22C is used to compare the synthesized amplified signal Scom with the inductor current sensing signal SiL to generate the main channel trigger signal Strcm.

[0135] In this embodiment, the main control circuit 20C further includes a fixed conduction time control circuit 231, a first single pulse generator 232, a second single pulse generator 233, and a state circuit 23. The state circuit 23 controls the conduction of the first main switch M1 by enabling the first main switch control signal Sm1 in a latching manner, for example, by triggering the pulse generated by the main channel trigger signal Strcm via the first single pulse generator 232.

[0136] The fixed on-time control circuit 231 is triggered by the main channel trigger signal Strcm, generating an on-time control signal Scot. The state circuit 23 further receives the on-time control signal Scot via the second single-pulse generator 233, and after a fixed on-time period calculated from the triggering of the main channel trigger signal Strcm, disables the first main switch control signal Sm1 to control the first main switch M1 to turn off. In one embodiment, the on-time of the on-time control signal Scot is adaptively adjusted according to the input voltage Vin and the output voltage (e.g., Vocm).

[0137] Figure 5A This diagram shows a power conversion circuit 500A according to a specific embodiment of the present invention. In this embodiment, the first channel output switch Qc1 includes a first channel rectifier switch QRc1 and a first channel path switch Qoc1. These two switches are connected in series between the second switching node LX2 and the first channel output voltage Voc1, forming a back-to-back switch structure. The main channel output switch Qcm includes a main channel rectifier switch QRcm and a main channel path switch Qocm. These two switches are also connected in series between the second switching node LX2 and the main channel output voltage Vocm, forming a back-to-back switch structure. The back-to-back switch structure refers to the reverse coupling of the body diodes corresponding to two transistors (such as QRcm and Qocm), wherein the reverse ends of the two body diodes are coupled to each other. The back-to-back switch structure of QRc1 and Qoc1 is the same. In a specific embodiment, the forward ends of the body diodes of the main channel rectifier switch QRcm and the first channel rectifier switch QRc1 are both coupled to the inductor L side.

[0138] The channel control circuit 10 generates corresponding switching control signals (SRc1, Soc1, SRcm, Socm) to control the conduction and cutoff of the first channel rectifier switch QRc1, the main channel rectifier switch QRcm, the first channel path switch Qoc1, and the main channel path switch Qocm. Through the rectification mechanism described in detail later, it realizes a smooth transition of the inductor current iL when it transfers between the main channel output voltage Vocm and the first channel output voltage Voc1, so as to reduce voltage surges during the switching transition.

[0139] Figure 5B This diagram shows a circuit schematic of a power conversion circuit 500B according to a specific embodiment of the present invention. The power conversion circuit 500B and... Figure 5ASimilar to the power conversion circuit 500A, the difference is that the power stage circuit 60 corresponds to a hybrid switching converter, which includes multiple main switches (e.g., Qm1, Qm2, Qm3 and Qm4), at least one flying capacitor (e.g. CF) and an inductor L. The multiple main switches are used to switch the electrical connection between the flying capacitor and the inductor to perform, for example, third-order or higher multi-order pulse width modulation power conversion to generate the inductor current iL.

[0140] Multiple main switches and at least one flying capacitor are used to form a switching capacitor converter, which performs power conversion by switching capacitors, for example, by pumping or dividing voltage across the flying capacitor. Specifically, in this embodiment, the switching capacitor converter 61 includes Qm1, Qm2, Qm3, Qm4 and CF, which perform voltage division by switching capacitors. The voltage conversion ratio of the switching capacitor converter can be designed as 2:1, 3:1, 4:1, etc., as required. The switching capacitor converter can adopt a series-parallel topology, Dickson topology, or pipelined topology. An inductor L is coupled between the output terminal of the switching capacitor converter and the switching node LX2. The output terminal of the switching capacitor converter corresponds, for example, to the switching node LX1, which is jointly coupled to Qm2 and Qm3.

[0141] Specifically, in this embodiment, the power stage circuit 60 corresponds to a series-parallel topology with a voltage conversion ratio of 2:1. The main switches Qm1, Qm2, Qm3, and Qm4 switch according to the switching control signal generated by the main control circuit 20', causing the switching node voltage VLX1 at the switching node LX1 to switch between multiple voltage levels for multi-order pulse-width modulation (PWM) power conversion. These multiple voltage levels include Vin, ground, and a voltage divider of at least one Vin, which lies between Vin and the ground potential. In this embodiment, this voltage divider is, for example, 1 / 2 × Vin. The power stage circuit 60 thus performs third-order PWM power conversion.

[0142] Figure 6 This illustrates an embodiment of the present invention corresponding to... Figure 4B and Figure 5A The operating waveform diagram. Regarding the main control circuit, such as... Figure 6 As shown, during the time interval t0 to t1, for example, triggered by the main channel trigger signal Strcm, the first main switch M1 is turned on (Sm1 enabled, Sm2 disabled) to magnetize the inductor L. During the time interval t1 to t5, triggered by the predetermined clock signal CLK, the first main switch M1 is turned off and the second main switch M2 is turned on (Sm1 disabled, Sm2 enabled) to demagnetize the inductor L. Specifically, the main switches M1 and M2 are based on... Figure 4BThe loop control method shown operates in the valley current mode. Specifically, when the inductor current-related signal SiLb drops below the sum of the integrated amplifier signal Scom and the main ramp signal Vrampcm (e.g., triggered by Strcm at time t4), the first main switch control signal Sm1 will be enabled (e.g., at time t5). Then, the first main switch control signal Sm1 will be disabled under the trigger of the predetermined clock signal CLK (e.g., at time t6).

[0143] In terms of the channel control circuit, the first channel ramp signal Vrampc1 begins to rise slowly at time t0, for example, triggered by the main channel trigger signal Strcm. During the time interval t0 to t2, the first channel output switch (Qc1), i.e., the first channel rectifier switch QRc1 and the first channel path switch Qoc1, is turned on, while the main channel output switch (Qcm), i.e., the main channel rectifier switch QRcm and the main channel path switch Qocm, is turned off, thereby controlling the inductor current iL to flow to the first channel output voltage Voc1. In other words, at this time, the first channel output current Ioc1 is equal to the inductor current iL. When Vrampc1 is higher than the first channel amplification signal Strc1 at time t2, it triggers the switching between the first channel output switch (Qc1) and the main channel output switch (Qcm). The first channel output switch (Qc1) will turn off, and the main channel output switch (Qcm) will turn on. This controls the inductor current iL to flow to the main channel output voltage Vocm. In other words, the main channel output current Iocm is the inductor current iL at this time.

[0144] Then at time t4, the main channel trigger signal Strcm will trigger the switching of the first channel output switch (Qc1) and the main channel output switch (Qcm) in the next cycle.

[0145] In this embodiment, during all switching transition periods when the inductor current iL transfers between the main channel output voltage Vocm and the first channel output voltage Voc1, such as time intervals t2~t3 and t4~t5, the first channel rectifier switch QRc1, the first channel path switch Qoc1, the main channel rectifier switch QRcm, and the main channel path switch Qocm enter rectification mode. During the switching transition, QRc1 and QRcm are off, while Qoc1 and Qocm are on. In other words, within a complete switching cycle Tsw, the on-time of QRc1 and QRcm is non-overlapping, while Qoc1 and Qocm are in an overlapping on-time state during the switching transition. It should be noted that the aforementioned current transfer refers to iL transferring from flowing to Vocm to flowing to Voc1, or vice versa.

[0146] Specifically, such as Figure 6As shown, during the time interval t0 to t2, the inductor current iL provides the first channel output current Ioc1 to the first channel output voltage Voc1. Then, during the time interval t2 to t3 (the switching transition period), both the first channel rectifier switch QRc1 and the main channel rectifier switch QRcm are in the off state (i.e., non-overlapping conduction), while the first channel path switch Qoc1 and the main channel path switch Qocm are in the on state (i.e., overlapping conduction). This allows the diodes of the first channel rectifier switch QRc1 and the main channel rectifier switch QRcm to cooperate in rectification mode operation. Specifically, in this embodiment, during the rectification mode of the time interval t2 to t3, the diodes of QRc1 and QRcm cooperate in rectification operation to determine the switching node voltage VLX2 on the switching node LX2, thereby ensuring a smooth transition between the main channel output current Iocm and the first channel output current Ioc1 during the switching transition period. Specifically, the body diode of QRc1 and the body diode of QRcm are adaptively selected to have the lower voltage between the main channel output voltage Vocm and the first channel output voltage Voc1, which is used as the switching node voltage VLX2 on the switching node LX2. For example... Figure 6 As shown, in this embodiment, starting from time point t2, the inductor current iL immediately provides the main channel output current Iocm to the main channel output voltage Vocm. Therefore, the inductor current iL can be continuous and uninterrupted, which can effectively reduce the voltage surge that may be caused by the discontinuity of the inductor current iL during the switching transition.

[0147] Then, during the time interval t3 to t4, QRcm and Qocm are turned on (while QRc1 and Qoc1 are turned off) to continue controlling the inductor current iL to provide the main channel output current Iocm to flow to the main channel output voltage Vocm.

[0148] During the time interval t4 to t5, when the switching transition period begins again, the first channel rectifier switch QRc1 and the main channel rectifier switch QRcm are both off, while the first channel path switch Qoc1 and the main channel path switch Qocm are on again, so that QRc1 and QRcm also operate in rectification mode, ensuring a smooth transition between the main channel output current Iocm and the first channel output current Ioc1.

[0149] Figure 7 This diagram shows a circuit block diagram of a channel control circuit in a specific embodiment of the present invention. The channel control circuit 10 includes a first channel comparator 12 and a plurality of logic circuits for generating switch control signals (SRc1, SRcm, Soc1, Socm). The first channel comparator 12 compares the first channel ramp signal Vrampc1 with the first channel amplified signal Seac1 to generate a first channel trigger signal Strc1.

[0150] OR gate 14 generates a first channel path switch control signal Soc1 via a driver based on the first channel trigger signal Strc1 and the first delayed trigger signal Sd1. Delay circuit 13d1 delays the first channel trigger signal Strc1 to generate the first delayed trigger signal Sd1. OR gate 15 generates a main channel path switch control signal Socm via a driver based on the inverted trigger signal Strc1b of the first channel trigger signal Strc1 and the second delayed trigger signal Sd2. Delay circuit 13d2 delays the inverted trigger signal Strc1b to generate the second delayed trigger signal Sd2. Inverter 17 generates a first channel rectifier switch control signal SRc1 based on the output of OR gate 15. AND gate 16 generates the main channel rectifier switch control signal SRcm based on the inverted trigger signal Strc1b and the second delayed trigger signal Sd2.

[0151] Figure 8 This diagram shows a circuit schematic of a power conversion circuit 800 according to another embodiment of the present invention. The power conversion circuit 800 is similar to... Figure 1 The power conversion circuit 100, such as Figure 8 As shown, the power conversion circuit 800 further includes an auxiliary transistor Qbp, coupled between the input voltage Vin and the first channel output voltage Voc1. The channel control circuit 10' is also used to generate an auxiliary control signal Sbp to control the auxiliary transistor Qbp.

[0152] In one embodiment, when the difference between the target voltage of the first channel output voltage Voc1 and the input voltage Vin is less than a preset range, or when the difference between the first channel reference voltage Vrefc1 and the input voltage Vin is less than a preset range, the power conversion circuit 100 enters a bypass mode or a linear regulation mode. In bypass mode, the auxiliary control signal Sbp controls the auxiliary transistor Qbp to turn on, thereby bypassing the input voltage Vin to the first channel output voltage Voc1.

[0153] In linear adjustment mode, the auxiliary control signal Sbp continuously simulates linear loop control of the auxiliary transistor Qbp based on the first channel reference voltage Vrefc1 and the first channel output voltage Voc1, so as to control its conduction level and adjust the first channel output voltage Voc1 to the first target voltage in an analog and linear manner.

[0154] In bypass mode or linear control mode, the first output control signal Sc1 will be disabled, while the main output control signal Scm will remain enabled.

[0155] Figure 9A This shows a circuit diagram of a power conversion circuit in another embodiment of the present invention. The power conversion circuit 900A is similar to... Figure 2The power conversion circuit 200, in this embodiment, is compared to... Figure 1 The power stage circuit 50 and the power stage circuit 90 also include a second channel output switch Qc2, wherein the second channel output switch Qc2 is coupled between the inductor L (switching node LX2) and the second channel output voltage Voc2.

[0156] The channel control circuit 10” generates a first output control signal Sc1, a second output control signal Sc2, and a main output control signal Scm, which respectively control the first channel output switch Qc1, the second channel output switch Qc2, and the main channel output switch Qcm to generate the first channel output voltage Voc1, the second channel output voltage Voc2, and the main channel output voltage Vocm. In one embodiment, Sc1, Sc2, and Scm are enabled in a time-division manner according to a preset time sequence, thereby generating the first channel output voltage Voc1, the second channel output voltage Voc2, and the main channel output voltage Vocm sequentially according to the inductor current iL. In one embodiment, the time sequence may be Sc1, Sc2, and Scm; in other embodiments, the time sequences of Sc1 and Sc2 may be interchanged with Sc2 and Sc1.

[0157] In this embodiment, the channel control circuit 10” is used to generate a first channel amplified signal Seac1 based on the first channel output voltage Voc1 and the first channel reference voltage Vrefc1, and to generate a second channel amplified signal Seac2 based on the second channel output voltage Voc2 and the second channel reference voltage Vrefc2, thereby generating the aforementioned first output control signal Sc1, second output control signal Sc2 and main output control signal Scm, the details of which will be described later.

[0158] The main control circuit 20” generates main switch control signals Sm1 and Sm2 based on the main channel output voltage Vocm, the main reference voltage Vrefcm, the first channel amplified signal Seac1 and the second channel amplified signal Seac2, so as to control the switching of main switches M1 and M2.

[0159] In one embodiment, the main control circuit 20” also performs pulse width modulation loop control in a valley-current mode or a peak-current mode based on the inductor current sensing signal SiL, so as to improve the cross-regulation capability between load transient response and multiple outputs.

[0160] In addition, the first channel output switch Qc1, the second channel output switch Qc2 and the main channel output switch Qcm may, as in the aforementioned embodiment, include rectifier switches to reduce voltage surges during the switching transition.

[0161] Figure 9BThis illustrates a specific embodiment of the present invention, corresponding to... Figure 9A The circuit block diagram of the conversion control circuit. Channel control circuit 10” is similar to... Figure 2 The channel control circuit 10, in this embodiment, includes a first channel amplifier 111, a first channel comparator 121, a second channel amplifier 112, a second channel comparator 122, and a channel modulation circuit 130.

[0162] The first channel amplifier 111 amplifies the difference between the first channel reference voltage Vrefc1 and the first channel output voltage Voc1 to generate the first channel amplified signal Seac1. The second channel amplifier 112 amplifies the difference between the second channel reference voltage Vrefc2 and the second channel output voltage Voc2 to generate the second channel amplified signal Seac2.

[0163] The first channel comparator 121 compares the first channel amplified signal Seac1 with the first channel ramp signal Vrampc1 to generate the first channel trigger signal Src1. The second channel comparator 122 compares the second channel amplified signal Seac2 with the second channel ramp signal Vrampc2 to generate the second channel trigger signal Src2. The channel modulation circuit 130 generates a first output control signal Sc1, a second output control signal Sc2, and a main output control signal Scm based on the comparison between the first channel amplified signal Seac1 and the first channel ramp signal Vrampc1 (i.e., the first channel trigger signal Src1), and the comparison between the second channel amplified signal Seac2 and the second channel ramp signal Vrampc2 (i.e., the second channel trigger signal Src2).

[0164] In one embodiment, the first channel trigger signal Strc1 corresponds to the first output control signal Sc1. AND gate 132 generates a second output control signal Sc2 based on the inverted signal of the second channel trigger signal Strc2 and the first output control signal Sc1. The main output control signal Scm is generated by inputting the first output control signal Sc1 and the second output control signal Sc2 to NOR gate 133.

[0165] Continue reading Figure 9BIn this embodiment, the main control circuit 20” includes a main channel amplifier 21, a main channel comparator 22”, and a fixed on-time control circuit 230. The main channel amplifier 21 is used to amplify the difference between the main reference voltage Vrefcm and the main channel output voltage Vocm to generate a main channel amplified signal Seacm. The main channel comparator 22” is used to compare the amplified signal Seacm with the inductor current sensing signal SiL (or the aforementioned inductor current related signal SiLb) to generate a main channel trigger signal Strcm. The fixed on-time control circuit 230 is used to time a fixed on-time according to the triggering of the main channel trigger signal Strcm to generate a first main switch control signal Sm1 and a second main switch control signal Sm2. In one embodiment, the amplified signal Scom” is a linear combination of the first channel amplified signal Seac1, the second channel amplified signal Seac2, and the main channel amplified signal Seacm, that is, Scom” = Gc1 × Seac1 + Gc2 × Seac2 + Gcm × Seacm, where the amplification gains Gc1, Gc2 and Gcm are real numbers.

[0166] The channel control circuit 10” and the main control circuit 20” use the first output control signal Sc1, the second output control signal Sc2, the main output control signal Scm, and the main switch control signals Sm1 and Sm2 to adjust the first channel output voltage Voc1, the second channel output voltage Voc2 and the main channel output voltage Vocm to the first target voltage, the second target voltage and the main target voltage, respectively.

[0167] Figure 10 This diagram shows a circuit schematic of a power conversion circuit according to an embodiment of the present invention. The power stage circuit 70 of the power conversion circuit 1000 is similar to... Figure 2 The power stage circuit 70 differs from the previous one in that, in this embodiment, the power stage circuit 70 further includes a third main switch M3, coupled between the second switching node LX2 and ground. The third main switch M3 is controlled by a third main switch control signal Sm3 generated by the main control circuit 20'A. The power stage circuit 70 including the third main switch M3 can selectively operate in buck power conversion mode (M3 is always on, M1 and M2 switch periodically), boost power conversion mode (M1 is always on, M2 is always off, M3 switches periodically), or buck-boost power conversion mode (M1, M2, and M3 all switch periodically).

[0168] Figure 11 This illustrates a specific embodiment of the present invention, corresponding to Figure 10 The waveform diagram of the power conversion circuit 1000 operating in boost power conversion mode.

[0169] In one embodiment, the third main switch M3 uses peak current mode for pulse width modulation loop control. The third main switch control signal Sm3 is enabled when triggered by the preset clock signal CLK. When the inductor current sensing signal SiL exceeds the integrated amplification signal Scom, Sm3 is disabled.

[0170] like Figure 11 As shown, during the time interval t0 to t1, the third main switch M3 is turned on to excite the inductor L. Furthermore, during t0 to t1, the first channel path switch control signal Soc1 is enabled, while the first channel rectifier switch control signal SRc1, the main channel rectifier switch control signal SRcm, and the main channel path switch control signal Socm are all disabled.

[0171] During the period t1 to t2, SRcm and Socm remain disabled, while SRc1 and Soc1 are enabled, causing the inductor current iL to flow to the first channel output current Ioc1 to generate the first channel output voltage Voc1.

[0172] During the period from t2 to t3, SRc1 and SRcm are both disabled, while Soc1 and Socm are both enabled, so that the inductor current iL can be smoothly transferred from the first channel output current Ioc1 to the main channel output current Iocm.

[0173] During the period from t3 to t4, SRc1 and Soc1 are disabled, while SRcm and Socm are enabled, causing the inductor current iL to flow to the main channel output current Iocm to generate the main channel output voltage Vocm. When the main channel output current Iocm is lower than the zero current threshold Izc (t4), SRcm is disabled.

[0174] After a delay, Socm is disabled at t5, while Soc1 is enabled. The time interval t5 to t6 is the resttime of a switching cycle Tsw. During this resttime, M1, M2, and M3 are all off, and the inductor current iL is 0. In other words, this embodiment shows the waveform of the power conversion circuit operating in discontinuous conduction mode. In another embodiment, when the time interval t5 to t6 is 0 (i.e., t5 and t6 coincide), the power conversion circuit operates in continuous conduction mode.

[0175] The conduction time (t1~t2) of SRc1 is determined by comparing the first channel ramp signal Vrampc1 with the first channel amplified signal Seac1. The conduction times of SRc1 and SRcm do not overlap.

[0176] Figure 12 This diagram shows a circuit schematic of a power conversion circuit according to an embodiment of the present invention. The power stage circuit 80 of the power conversion circuit 1200 is similar to... Figure 10The power stage circuit 70 differs from the previous one in that, in this embodiment, the main switches M1 and M2 are omitted. Instead, one end of the inductor L is directly coupled to the input voltage Vin (that is, in this embodiment, the first switching node LX1 is directly coupled to the input voltage Vin), and the other end is coupled to the second switching node LX2 together with the third main switch M3. The inductor L and the third main switch M3 form a switching converter 81. The power stage circuit 80 can be regarded as a multi-channel boost switching converter, which includes a boost switching converter 81, a main channel output switch Qcm, and a first channel output switch Qc1, which switch together to realize boost-type multi-output power conversion.

[0177] Specifically, in this embodiment, the third main switch M3 is controlled by the third main switch control signal Sm3 generated by the main control circuit 20'B, thereby periodically switching the electrical connection state of the second switching node LX2. During the conduction period of Sm3, the inductor L is energized and accumulates inductor energy; during the turn-off period of Sm3, it is demagnetized and releases energy to the corresponding output terminal connected to Qcm or Qc1, thereby generating the main channel output voltage Vocm or the first channel output voltage Voc1.

[0178] In one embodiment, the amplifiers in the aforementioned embodiments can attenuate the corresponding channel output voltage through a voltage divider circuit before feeding it back to generate the corresponding amplified signal. An example is given below.

[0179] Figure 13 This diagram shows a circuit schematic of the control circuit 120 according to one embodiment of the present invention. The control circuit 120 may correspond to a channel control circuit or a part of a main control circuit. The control circuit 120 includes an amplifier 1210 and a voltage divider circuit 1220. The voltage divider circuit 1220 is used to divide the channel output voltage VoX to generate a feedback voltage VfbX. The amplifier 1210 is used to amplify the difference between the reference voltage VrefX and the feedback voltage VfbX to generate a corresponding amplified signal SeaX.

[0180] Specifically, in one embodiment, the control circuit 120 may correspond to the channel control circuit in the aforementioned embodiments, or it may correspond to the main control circuit. The amplifier 1210 may correspond to the first channel amplifier or the second channel amplifier in the channel control circuit, or it may correspond to the main channel amplifier in the main control circuit. The reference voltage VrefX may correspond to the main channel reference voltage Vrefcm received by the main control circuit, or it may correspond to the first channel reference voltage Vrefc1 or the second channel reference voltage Vrefc2 received by the channel control circuit. The channel output voltage VoX may correspond to the main channel output voltage Vocm received by the main control circuit, or it may correspond to the first channel output voltage Voc1 or the second channel output voltage Voc2 received by the channel control circuit; and the amplified signal SeaX may correspond to the main channel amplified signal Seacm generated by the main control circuit, or it may correspond to the first channel amplified signal Seac1 or the second channel amplified signal Seac2 generated by the channel control circuit. Voltage divider circuit 1220 is used to divide the channel output voltage VoX to generate a corresponding feedback voltage VfbX. The feedback voltage VfbX can correspond to the main channel feedback voltage received by the main control circuit, or to the first channel feedback voltage or the second channel feedback voltage received by the channel control circuit.

[0181] This invention generates multiple regulated outputs simultaneously using a single inductor, reducing the complexity and cost of traditional multi-inductor systems. Furthermore, this invention integrates rectifier switches on the output channel side, enabling rectification operations during the non-overlapping conduction periods of multiple rectifier switches (such as the first channel rectifier switch QRc1 and the main channel rectifier switch QRcm). This allows for smooth switching of currents between different channels during transitions, ensuring continuous and uninterrupted inductor current and effectively reducing voltage surges that may be caused by current discontinuities during transitions.

[0182] Furthermore, by using integrated amplified signals for main switch modulation control, mutual interference between multiple channel output voltages can be effectively reduced, improving overall voltage regulation performance. The power stage can be a buck, boost, or buck-boost switching converter to meet a wider range of input and output voltage requirements. This invention can operate in discontinuous or continuous conduction modes, increasing the application range of load current.

[0183] The present invention has been described above with reference to embodiments. However, the above description is only intended to facilitate understanding of the invention by those skilled in the art and is not intended to limit the broadest scope of the invention. The described embodiments are not limited to individual application and can also be used in combination. For example, two or more embodiments can be used in combination, and some components of one embodiment can be used to replace corresponding components in another embodiment. Furthermore, within the same spirit of the invention, those skilled in the art can conceive of various equivalent changes and combinations. For example, the phrase "processing or calculating based on a signal or generating an output result" in the present invention is not limited to the signal itself, but also includes, when necessary, performing voltage-to-current conversion, current-to-voltage conversion, and / or proportional conversion on the signal, and then processing or calculating based on the converted signal to generate an output result. Therefore, within the same spirit of the invention, those skilled in the art can conceive of various equivalent changes and combinations, and there are many ways to combine them, which will not be listed here. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

Claims

1. A power conversion circuit for converting an input voltage into multiple output voltages, characterized in that, The multiple output voltages include a first channel output voltage and a main channel output voltage. The power conversion circuit includes: A power stage circuit, including: An inductor is coupled between a first switching node and a second switching node; At least one main switch is coupled to the inductor; A main channel output switch is coupled between the second switching node and the main channel output voltage; and A first channel output switch is coupled between the second switching node and the first channel output voltage, wherein the at least one main switch, the main channel output switch, and the first channel output switch are used to periodically switch the electrical connection state of the first switching node and / or switch the electrical connection state of the second switching node to control the magnetization and demagnetization of the inductor to generate an inductor current; and A conversion control circuit, including: A channel control circuit is configured to generate a first-channel amplified signal based on the first-channel output voltage and a first-channel reference voltage, and to generate a first output control signal and a main output control signal based on the first-channel amplified signal, for controlling the switching of the first-channel output switch and the main-channel output switch respectively, and to generate the first-channel output voltage and the main-channel output voltage sequentially based on the inductor current in a time-division multiplexing manner according to a preset time sequence; and A main control circuit is used to generate a main switch control signal based on the main channel output voltage, a main reference voltage and the first channel amplified signal, so as to control the switching of the at least one main switch.

2. The power conversion circuit as described in claim 1, in, The channel control circuit includes: A first-channel amplifier is used to amplify the difference between the first-channel reference voltage and the first-channel feedback voltage to generate the first-channel amplified signal, wherein the first-channel feedback voltage is related to the first-channel output voltage; A first-channel comparator is used to compare the first-channel amplified signal with a first-channel ramp signal to generate a first-channel trigger signal; and A modulation circuit is provided to generate the first output control signal and the main output control signal based on the first channel trigger signal. The main control circuit includes: A main channel amplifier is used to amplify the difference between a main channel reference voltage and a main channel feedback voltage to generate a main channel amplified signal, wherein the main channel feedback voltage is related to the main channel output voltage; and A main modulation circuit is used to generate the main switch control signal based on the main channel amplified signal and the first channel amplified signal.

3. The power conversion circuit as described in claim 2, wherein, The main modulation circuit also generates the main switch control signal based on an inductor current related signal, and controls the switching of the at least one main switch to perform loop control in a valley current mode, a peak current mode, or a fixed on-time mode; wherein the inductor current related signal is related to the inductor current.

4. The power conversion circuit as claimed in claim 3, wherein, The main modulation circuit includes: A main channel comparator is used to compare the sum of two of a synthesized amplified signal, a main channel ramp signal, and an inductor current-related signal with the third of these signals to generate a main channel trigger signal; and A state circuit is used to generate the main switch control signal based on the main channel trigger signal; The amplified signal is a linear combination of the first channel amplified signal and the main channel amplified signal.

5. The power conversion circuit as claimed in claim 3, wherein, The first channel output switch includes a first channel rectifier switch and a first channel path switch, which are connected in series between the second switching node and the first channel output voltage, wherein the reverse end of the body diode of the first channel rectifier switch and the reverse end of the body diode of the first channel path switch are coupled to each other. The main channel output switch includes a main channel rectifier switch and a main channel path switch, which are connected in series between the second switching node and the main channel output voltage. The reverse end of the body diode of the main channel rectifier switch and the reverse end of the body diode of the main channel path switch are coupled to each other.

6. The power conversion circuit as claimed in claim 5, wherein, During all transition periods when the inductor current shifts between the first channel output voltage and the main channel output voltage, both the first channel rectifier switch and the main channel rectifier switch are in the off state, and both the first channel path switch and the main channel path switch are in the on state. Thus, the body diode of the first channel rectifier switch and the body diode of the main channel rectifier switch work together to rectify the first channel output voltage and the main channel output voltage to determine the voltage at the second switching node.

7. The power conversion circuit as claimed in claim 2, wherein, The power stage circuit also includes a second channel output switch coupled between the second switching node and a second channel output voltage; The channel control circuit also generates a second channel amplified signal based on the second channel output voltage and a second channel reference voltage, and generates a first output control signal, a main output control signal and a second output control signal based on the second channel amplified signal, so as to control the switching of the first channel output switch, the main channel output switch and the second channel output switch respectively, and then generates the main channel output voltage, the first channel output voltage and the second channel output voltage in a time-division manner based on a preset time sequence according to the inductor current. The main control circuit also generates the main switch control signal based on the amplified signal from the second channel.

8. The power conversion circuit as described in claim 7, in, The channel control circuit also includes: A second-channel amplifier for amplifying the difference between a second-channel reference voltage and a second-channel feedback voltage to generate the second-channel amplified signal, wherein the second-channel feedback voltage is related to the second-channel output voltage; and A second-channel comparator is used to compare the second-channel amplified signal with a second-channel ramp signal to generate a second-channel trigger signal; The channel modulation circuit also generates the first output control signal, the second output control signal, and the main output control signal based on the second channel trigger signal. The main modulation circuit also generates the main switch control signal based on a linear combination of the main channel amplified signal, the first channel amplified signal, and the second channel amplified signal.

9. The power conversion circuit as claimed in claim 1, wherein, The power stage circuit also includes a flying capacitor, wherein the at least one main switch includes multiple main switches for switching the electrical connection between the flying capacitor and the inductor to perform multi-stage pulse width modulation power conversion to generate the inductor current.

10. The power conversion circuit as claimed in claim 1, in, The power stage circuit also includes an auxiliary transistor coupled between the input voltage and the first channel output voltage; In a bypass mode, the auxiliary transistor is used to turn on the input voltage to the first channel output voltage; or In a linear regulation mode, the auxiliary transistor is used to perform linear loop control to linearly regulate the first channel output voltage to a first target voltage; In the bypass mode or the linear adjustment mode, the first output control signal is disabled, and the main output control signal is enabled.

11. The power conversion circuit as claimed in claim 10, in, The channel control circuit is also used to generate an auxiliary control signal to control the auxiliary transistor; Specifically, when the difference between the first target voltage of the first channel output voltage and the input voltage is less than a preset range, or the difference between the first channel reference voltage and the input voltage is less than a preset range, the channel control circuit controls the power conversion circuit to enter the bypass mode or the linear adjustment mode.

12. The power conversion circuit as claimed in claim 1, wherein, The at least one main switch includes a first main switch and a second main switch, the first main switch and the second main switch being connected in series between the input voltage and a ground, and the first main switch and the second main switch being coupled to each other at the first switching node.

13. The power conversion circuit as described in claim 12, in, The at least one main switch also includes a third main switch, coupled between the second switching node and the ground; The power stage circuit can be selectively operated in buck power conversion mode, boost power conversion mode, or buck-boost power conversion mode.

14. The power conversion circuit as claimed in claim 1, wherein, The at least one main switch includes a fourth main switch coupled between the second switching node and a ground.

15. A control method for controlling a power conversion circuit, the power conversion circuit being configured to convert an input voltage into a plurality of output voltages, the plurality of output voltages including a first channel output voltage and a main channel output voltage, the power conversion circuit comprising: An inductor is coupled between a first switching node and a second switching node; At least one main switch is coupled to the inductor; A main channel output switch is coupled between the second switching node and the main channel output voltage; and a first channel output switch is coupled between the second switching node and the first channel output voltage; characterized in that the control method includes: Controlling the at least one main switch, the main channel output switch, and the first channel output switch to periodically switch the electrical connection state of the first switching node, and / or switch the electrical connection state of the second switching node, to control the magnetization and demagnetization of the inductor to generate an inductor current; wherein the step of generating the inductor current includes: A first-channel amplified signal is generated based on the first-channel output voltage and a first-channel reference voltage; A first output control signal and a main output control signal are generated based on the amplified signal of the first channel. The switching of the first channel output switch and the main channel output switch is controlled by the first output control signal and the main output control signal, respectively, in a time-division manner, based on a preset time sequence, and the first channel output voltage and the main channel output voltage are generated sequentially according to the inductor current; and A main switch control signal is generated based on the main channel output voltage, a main reference voltage, and the first channel amplified signal to control the switching of the at least one main switch.

16. The control method as described in claim 15, wherein, The steps for generating the inductor current also include: The difference between the first channel reference voltage and the first channel feedback voltage is amplified to generate the first channel amplified signal, wherein the first channel feedback voltage is related to the first channel output voltage; The amplified signal of the first channel is compared with a ramp signal of the first channel to generate a trigger signal of the first channel; Based on the first channel trigger signal, the first output control signal and the main output control signal are generated; The difference between the main channel reference voltage and a main channel feedback voltage is amplified to generate a main channel amplified signal, wherein the main channel feedback voltage is related to the main channel output voltage; and The main switch control signal is generated based on the main channel amplified signal and the first channel amplified signal.

17. The control method as described in claim 16, wherein, The steps for generating the inductor current also include: Based on an inductor current related signal, the switching of at least one main switch is controlled to perform loop control in a valley current mode, a peak current mode, or a fixed on-time mode; wherein the inductor current related signal is related to the inductor current.

18. The control method as described in claim 17, wherein, The steps for generating the inductor current also include: The first channel amplified signal is linearly combined with the main channel amplified signal to generate a composite amplified signal; The sum of two of the amplified signal, the main channel ramp signal, and the inductor current-related signal is compared with the third of the three signals to generate a main channel trigger signal; and The main switch control signal is generated based on the main channel trigger signal.

19. The control method as described in claim 15, wherein, The first channel output switch includes a first channel rectifier switch and a first channel path switch, which are connected in series between the second switching node and the first channel output voltage, wherein the reverse end of the body diode of the first channel rectifier switch and the reverse end of the body diode of the first channel path switch are coupled to each other. The main channel output switch includes a main channel rectifier switch and a main channel path switch, which are connected in series between the second switching node and the main channel output voltage. The reverse end of the body diode of the main channel rectifier switch and the reverse end of the body diode of the main channel path switch are coupled to each other. The steps for generating the inductor current also include: During all transition periods when the inductor current shifts between the first channel output voltage and the main channel output voltage, both the first channel rectifier switch and the main channel rectifier switch are controlled to be in the off state, and both the first channel path switch and the main channel path switch are controlled to be in the on state. Thus, the body diode of the first channel rectifier switch and the body diode of the main channel rectifier switch work together to rectify the first channel output voltage and the main channel output voltage to determine the voltage at the second switching node.

20. The control method as described in claim 15, wherein, The power conversion circuit also includes an auxiliary transistor coupled between the input voltage and the first channel output voltage; The steps for generating the inductor current also include: When the difference between the first target voltage of the first channel output voltage and the input voltage is less than a preset range, or the difference between the first channel reference voltage and the input voltage is less than a preset range, the power conversion circuit is controlled to enter a bypass mode or a linear adjustment mode. Disable the first output control signal; and Enable this main output control signal; In the bypass mode, the auxiliary transistor is controlled to turn on the input voltage to the first channel output voltage; In the linear adjustment mode, the auxiliary transistor is controlled to perform linear loop control to adjust the output voltage of the first channel to the first target voltage in a linear manner.

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