A downlink selection method based on cross-redundant valve control architecture

Abstract

The application relates to a downlink selection method based on a cross-redundancy valve control framework, which generates a variable-position enable signal of a selection signal through master-slave states of first and second FPGAs, generates the selection signal based on the variable-position enable signal of the selection signal and the master-slave states of the first and second FPGAs, so that an interface board can independently complete link judgment and selection through self logic without relying on a main system instruction, the link utilization rate is effectively improved, unnecessary redundancy loss caused by main system switching is avoided, the redundancy potential of the cross-connection framework is fully released, the system redundancy and reliability are improved, the defects that a whole redundant link is invalid due to a single point fault in a traditional parallel valve control framework are solved, the risk that a converter is shut down due to a link fault is reduced, the overall reliability and operation and maintenance flexibility of a converter control protection system are improved, and the operation requirements of high reliability and high stability of a valve control system for long-distance power transmission technology development are met.

Description

Technical Field

[0001] This invention relates to the fields of DC power transmission and power electronics technology, specifically to a downlink selection method based on a cross-redundant valve-controlled architecture. Background Technology

[0002] With the continuous development of long-distance power transmission technology, the requirements for redundancy and reliability of converter control and protection systems are also constantly increasing. In the converter control system, the valve control system plays a key role. Its core function is to convert the modulation wave generated by the upper-level control system into actual switching trigger commands, while also playing an important role in the protection of sub-modules. Figure 1 This is a schematic diagram of the basic structure of a converter control system provided by the present invention, as shown below. Figure 1 As shown, the system mainly consists of three parts: a main controller, a valve controller, and sub-modules. The downlink from the valve controller to the sub-modules is primarily used to send the trigger pulses of the power switching devices calculated by the valve controller main unit to each sub-module. The uplink from the sub-modules to the valve controller is primarily used to feed back key operating information such as the capacitor voltage and bypass status of the sub-modules to the valve controller main unit, providing a basis for the valve control system's control decisions and protection actions.

[0003] Currently, mainstream converter control systems generally adopt a dual redundancy configuration, that is, setting up system A and system B, with the two systems serving as backups for each other, in order to avoid converter shutdown due to a single point of failure in the control system. Figure 2 This invention provides a schematic diagram of a dual-redundant control system for a converter with a parallel valve control architecture. Its core is a parallel connection architecture between the valve control host unit and the valve control interface unit. In this architecture, valve control host units A and B are respectively connected to a core board in the valve control interface unit, forming a deep binding relationship between the host unit and the valve control interface unit core boards A / B (i.e., core board 1 and core board 2). Each valve control interface unit consists of two core boards and several interface boards. Under this parallel connection architecture, the interface boards themselves have no autonomy in link selection; their link selection is entirely dependent on the primary system, and they can only passively select the link from the valve control interface unit core board corresponding to the primary system. This parallel valve control architecture has a fatal flaw: when any link in a single system from the host unit (host unit A and host unit B) to the sub-module fails, it will directly lead to the loss of the link from the valve control interface unit to the sub-module, preventing the full realization of the reliability advantages of the dual redundancy design and increasing the risk of converter downtime due to link failure.

[0004] To address the shortcomings of the aforementioned parallel valve control architecture, related technologies have proposed a cross-connection architecture between the valve control host unit and the valve control interface unit core board, such as... Figure 3As shown, both valve control host units A and B establish independent communication connections with the core board in each valve control interface unit. This cross-connect architecture breaks the deep binding limitation of the parallel connection architecture, providing two available downlinks for the interface boards and creating the foundation for independent link selection. Based on this cross-connect architecture, how to enable the interface boards to make independent judgments and autonomous link selections, while ensuring the final reception of data from the master system, and autonomously decide on the downlink selection to improve link utilization, redundancy, and system reliability, has become a key requirement that urgently needs to be addressed. Currently, there is no effective solution to this requirement, resulting in the redundancy potential of the cross-connect architecture not being fully utilized, making it difficult to meet the high reliability and high stability requirements of the converter valve control system. Summary of the Invention

[0005] To address the issue of how to achieve independent judgment and autonomous link selection of the interface board in the existing cross-redundant valve control architecture, this invention proposes a downlink selection method, system, electronic device, and medium.

[0006] A first aspect of the present invention provides a downlink selection method based on a cross-redundant valve-controlled architecture, the cross-redundant valve-controlled architecture comprising: a valve-controlled interface unit, the valve-controlled interface unit being connected to a submodule of an external converter, the downlink selection method comprising: Based on the fault levels of the first FPGA and the second FPGA in the valve control interface unit, the master-slave status of the first FPGA and the second FPGA is determined, and the first FPGA and the second FPGA are interconnected. Based on the master-slave state of the first FPGA and the second FPGA, a shift enable signal for the selection signal is generated; The selection signal is generated based on the shift enable signal of the selection signal and the master-slave status of the first FPGA and the second FPGA; Based on the selection signal, the FPGA link signal corresponding to the main state is selected, and the FPGA link signal corresponding to the main state is sent down to the sub-module.

[0007] Optionally, determining the master-slave status of the first FPGA and the second FPGA based on their fault levels in the valve control interface unit includes: When the fault level of the first FPGA in the valve control interface unit is lower than that of the second FPGA, the first FPGA is determined to be in master state and the second FPGA is in slave state. When the fault level of the first FPGA is higher than that of the second FPGA, the first FPGA is determined to be in slave state and the second FPGA to be in master state. When the fault level of the first FPGA is the same as that of the second FPGA, the current master-slave state of the first FPGA and the second FPGA remains unchanged.

[0008] Optionally, the step of generating the shift enable signal for the selection signal based on the master-slave state of the first FPGA and the second FPGA includes: Based on the master-slave state, the status signals of the first FPGA and the second FPGA are generated respectively. Based on the status signals of the first FPGA and the second FPGA, the master-slave status signals of the first FPGA and the master-slave status signals of the second FPGA are generated by combining them. When the master-slave status signals of the first FPGA and the second FPGA both change to the target signal, the shift enable signal of the selection signal is set to the target value to realize the shift of the selection signal.

[0009] Optionally, the step of combining the status signals of the first FPGA and the second FPGA to generate the master-slave status signals of the first FPGA and the second FPGA includes: The master-slave status signal of the first FPGA is generated by combining the status signals of the first FPGA and the second FPGA in the order of their respective status signals. The master-slave status signals of the second FPGA are generated by combining the status signals of the second FPGA and the status signals of the first FPGA in the order of their respective status signals.

[0010] Optionally, generating the selection signal based on the shift enable signal of the selection signal and the master-slave state of the first FPGA and the second FPGA includes: When the shift enable signal of the selection signal is the target value, a first standby signal of the first FPGA and a second standby signal of the second FPGA are generated based on the master-slave state of the first FPGA and the second FPGA. When the first standby signal and the second standby signal are opposite, a selection signal is generated from the first FPGA output to the 2-to-1 logic chip; or when the first standby signal and the second standby signal are the same, a selection signal is generated from the first FPGA output to the 2-to-1 logic chip.

[0011] Optionally, generating a first standby signal for the first FPGA and a second standby signal for the second FPGA based on the master-slave status of the first FPGA and the second FPGA includes: When the first FPGA is in the master state and the second FPGA is in the slave state, opposite first standby signals and second standby signals are generated. If the first FPGA is in slave state and the second FPGA is in master state, the same first standby signal and second standby signal are generated.

[0012] Optionally, before determining the master-slave status of the first FPGA and the second FPGA based on the fault levels of the first FPGA and the second FPGA in the valve-controlled interface unit, the downlink selection method further includes: Based on the fault information of the first FPGA and the second FPGA, the core board of the valve control unit obtains the fault level of the first FPGA and the second FPGA using a preset FPGA fault level judgment logic. The preset FPGA fault level judgment logic includes: When the first FPGA or the second FPGA has no communication physical interface, the fault level is set to the lowest; when the core board itself has a fault, the fault level is set to the highest. When a communication physical interface of the first FPGA or the second FPGA is abnormal, the fault level is set between the lowest and highest levels, and the fault level is increased sequentially according to the number of abnormal communication physical interfaces.

[0013] Optionally, the valve control interface unit includes: a first core board, a second core board, and at least one interface board; Each of the interface boards includes: a first FPGA, a second FPGA, and a plurality of 2-to-1 logic chips, wherein the first FPGA and the second FPGA are respectively connected to the plurality of 2-to-1 logic chips; The first FPGA is connected to the first core board through a 4-way communication physical interface, the second FPGA is connected to the second core board through a 4-way communication physical interface, and each of the 2-to-1 logic chips is connected to a sub-module of an external converter.

[0014] Optionally, the cross-redundant valve control architecture further includes: a first valve control host unit and a second valve control host unit; The first valve control host unit is connected to the first core board and the second core board respectively, and the second valve control host unit is connected to the first core board and the second core board respectively; The first valve control host unit and the second valve control host unit are respectively connected to an external main control unit.

[0015] Optionally, the cross-redundant valve control architecture further includes a backup valve control interface unit, which is connected to the first valve control host unit and the second valve control host unit respectively.

[0016] A second aspect of the present invention also provides a downlink selection system based on a cross-redundant valve-controlled architecture, the cross-redundant valve-controlled architecture comprising: a valve-controlled interface unit, the valve-controlled interface unit being connected to a sub-module of an external converter, and the downlink selection system comprising: The master-slave status determination unit is used to determine the master-slave status of the first FPGA and the second FPGA based on the fault levels of the first FPGA and the second FPGA in the valve control interface unit, wherein the first FPGA and the second FPGA are interconnected. The shift enable signal generation unit is used to generate a shift enable signal for the selection signal based on the master-slave state of the first FPGA and the second FPGA. The selection signal generation unit is used to generate the selection signal based on the shift enable signal of the selection signal and the master-slave state of the first FPGA and the second FPGA. The link signal selection unit is used to select the FPGA link signal corresponding to the main state based on the selection signal, and send the FPGA link signal corresponding to the main state to the sub-module.

[0017] Optionally, the master-slave state determination unit is specifically used for: When the fault level of the first FPGA in the valve control interface unit is lower than that of the second FPGA, the first FPGA is determined to be in master state and the second FPGA is in slave state. When the fault level of the first FPGA is higher than that of the second FPGA, the first FPGA is determined to be in slave state and the second FPGA to be in master state. When the fault level of the first FPGA is the same as that of the second FPGA, the current master-slave state of the first FPGA and the second FPGA remains unchanged.

[0018] Optionally, the displacement enable signal generation unit includes: A status signal generation module is used to generate status signals for the first FPGA and the second FPGA respectively based on the master-slave status. The master-slave status signal generation module is used to combine the status signals of the first FPGA and the second FPGA to generate master-slave status signals of the first FPGA and the second FPGA based on the status signals of the first FPGA and the second FPGA. The shift enable signal generation module is used to set the shift enable signal of the selection signal to the target value when the master-slave status signals of the first FPGA and the second FPGA both change to the target signal, thereby realizing the shift of the selection signal.

[0019] Optionally, the master-slave status signal generation module is specifically used for: The master-slave status signal of the first FPGA is generated by combining the status signals of the first FPGA and the second FPGA in the order of their respective status signals. The master-slave status signals of the second FPGA are generated by combining the status signals of the second FPGA and the status signals of the first FPGA in the order of their respective status signals.

[0020] Optionally, the selection signal generation unit includes: The standby signal generation module is used to generate a first standby signal for the first FPGA and a second standby signal for the second FPGA based on the master-slave state of the first FPGA and the second FPGA when the shift enable signal of the selected signal is a target value. The selection signal generation module is used to generate a selection signal from the first FPGA to the 2-to-1 logic chip when the first standby signal and the second standby signal are opposite, or to generate a selection signal from the first FPGA to the 2-to-1 logic chip when the first standby signal and the second standby signal are the same.

[0021] Optionally, the standby signal generation module is specifically used for: When the first FPGA is in the master state and the second FPGA is in the slave state, opposite first standby signals and second standby signals are generated. If the first FPGA is in slave state and the second FPGA is in master state, the same first standby signal and second standby signal are generated.

[0022] Optionally, the downlink selection system further includes: The fault level acquisition unit is used to obtain the fault level of the first FPGA and the second FPGA based on the fault information of the first FPGA and the second FPGA by the core board of the valve control unit and by using the preset FPGA fault level judgment logic. The preset FPGA fault level judgment logic includes: When the first FPGA or the second FPGA has no communication physical interface, the fault level is set to the lowest; when the core board itself has a fault, the fault level is set to the highest. When a communication physical interface of the first FPGA or the second FPGA is abnormal, the fault level is set between the lowest and highest levels, and the fault level is increased sequentially according to the number of abnormal communication physical interfaces.

[0023] Optionally, the valve control interface unit includes: a first core board, a second core board, and at least one interface board; Each of the interface boards includes: a first FPGA, a second FPGA, and a plurality of 2-to-1 logic chips, wherein the first FPGA and the second FPGA are respectively connected to the plurality of 2-to-1 logic chips; The first FPGA is connected to the first core board through a 4-way communication physical interface, the second FPGA is connected to the second core board through a 4-way communication physical interface, and each of the 2-to-1 logic chips is connected to a sub-module of an external converter.

[0024] Optionally, the cross-redundant valve control architecture further includes: a first valve control host unit and a second valve control host unit; The first valve control host unit is connected to the first core board and the second core board respectively, and the second valve control host unit is connected to the first core board and the second core board respectively; The first valve control host unit and the second valve control host unit are respectively connected to an external main control unit.

[0025] Optionally, the cross-redundant valve control architecture further includes a backup valve control interface unit, which is connected to the first valve control host unit and the second valve control host unit respectively.

[0026] A third aspect of the present invention also provides an electronic device, comprising: one or more processors; A processor is used to execute one or more programs; When the one or more programs are executed by the one or more processors, a downlink selection method as described above is implemented.

[0027] In a fourth aspect, the present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed, it implements a downlink selection method as described above.

[0028] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention provides a downlink selection method based on a cross-redundant valve-controlled architecture. This method generates a selection signal change enable signal based on the master-slave states of the first and second FPGAs. Based on the selection signal change enable signal and the master-slave states of the first and second FPGAs, a selection signal is generated. This allows the interface board to independently complete link judgment and selection through its own logic, without relying on master system instructions. This effectively improves link utilization, avoids unnecessary redundancy loss due to master system switching, fully releases the redundancy potential of the cross-connect architecture, and improves system redundancy and reliability. It helps solve the defect in traditional parallel valve-controlled architecture where a single point of failure causes the entire redundant link to fail, reduces the risk of converter downtime due to link failure, improves the overall reliability and operational flexibility of the converter control and protection system, and meets the high reliability and high stability requirements of valve-controlled systems in the development of long-distance power transmission technology. Attached Figure Description

[0029] Figure 1 This invention provides a schematic diagram of the basic structure of a converter control system. Figure 2 A schematic diagram of a dual-redundant control system for a converter with a parallel valve control architecture provided by the present invention; Figure 3 A schematic diagram of a dual-redundant control system for a converter with a cross-architecture valve control provided by the present invention; Figure 4 A flowchart illustrating a downlink selection method based on a cross-redundancy valve-controlled architecture provided by the present invention; Figure 5 A schematic diagram illustrating the detailed structure of a valve control interface unit interface board provided by the present invention; Figure 6 A flowchart for determining the master-slave status of an FPGA on an interface board is provided for this invention; Figure 7 A flowchart of the selection signal shift enable signal set logic provided by the present invention; Figure 8 A flowchart for determining the FPGA selection signal on an interface board is provided by the present invention; Figure 9 A flowchart for obtaining the fault level of an interface board FPGA is provided for this invention; Figure 10 A block diagram of a dual-layer compact cross-redundant valve control architecture provided by the present invention; Figure 11 This is a schematic diagram of a Y-type cascaded SVG topology provided by the present invention; Figure 12A flowchart of a downlink link selection method for a valve control interface unit interface board based on a cross-redundant valve control architecture, provided for this invention; Figure 13 A block diagram of a downlink selection system provided by the present invention; Figure 14 A block diagram of an electronic device provided by the present invention. Detailed Implementation

[0030] Example 1: Figure 4 This invention provides a flowchart of a downlink selection method based on a cross-redundant valve-controlled architecture. The cross-redundant valve-controlled architecture includes a valve-controlled interface unit, which connects to a sub-module of an external converter, such as... Figure 4 As shown, the downlink selection method may include the following steps 401 to 404: In step 401, based on the fault levels of the first FPGA and the second FPGA in the valve control interface unit, the master-slave status of the first FPGA (Field-Programmable Gate Array) and the second FPGA is determined, and the first FPGA and the second FPGA are interconnected.

[0031] In step 402, a shift enable signal for the selection signal is generated based on the master-slave status of the first FPGA and the second FPGA.

[0032] In step 403, the selection signal is generated based on the shift enable signal of the selection signal and the master-slave status of the first FPGA and the second FPGA.

[0033] In step 404, based on the selection signal, the FPGA link signal corresponding to the main state is selected, and the FPGA link signal corresponding to the main state is sent down to the sub-module.

[0034] The valve control interface unit may include: a first core board, a second core board, and at least one interface board; each interface board includes: a first FPGA, a second FPGA, and a plurality of 2-to-1 logic chips, wherein the first FPGA and the second FPGA are respectively connected to the plurality of 2-to-1 logic chips; the first FPGA is connected to the first core board through a 4-way communication physical interface, the second FPGA is connected to the second core board through a 4-way communication physical interface, and each 2-to-1 logic chip is connected to a sub-module of an external converter.

[0035] In some embodiments, the cross-redundant valve control architecture may further include: a first valve control host unit and a second valve control host unit; the first valve control host unit is connected to the first core board and the second core board respectively, and the second valve control host unit is connected to the first core board and the second core board respectively; the first valve control host unit and the second valve control host unit are respectively connected to an external master control unit.

[0036] In some embodiments, the cross-redundant valve control architecture may further include: a backup valve control interface unit, which is connected to the first valve control host unit and the second valve control host unit respectively.

[0037] In some implementations, the cross-redundant valve control architecture has multiple valve control interface units, each of which is connected to a first valve control host unit and a second valve control host unit.

[0038] It should be noted that the two FPGAs on the interface board need to be initialized to master and slave states beforehand, with FPGA1 initialized to master state and FPGA2 initialized to slave state. It is important to clarify that the master and slave states mentioned here are unrelated to the primary and backup systems of the valve control host unit and its upper-level control system; they are merely used as criteria for downlink selection in this invention to determine the priority order of the two downlinks.

[0039] For example, Figure 5 This is a schematic diagram illustrating the detailed structure of an interface board for a valve-controlled interface unit provided by the present invention. The diagram only shows the connections related to the downlink and does not show other unrelated structures of the interface board. The interface board mainly integrates two FPGAs (FPGA1 and FPGA2) and several 2-to-1 logic chips. Since this invention only discusses the downlink selection problem of one submodule, only one 2-to-1 logic chip is shown in the diagram for illustrative purposes. Figure 5 As shown, the two FPGAs are respectively connected to the two core boards (i.e., core board 1 and core board 2) of the valve control interface unit. Each FPGA is configured with 4 communication physical interfaces to receive data from the corresponding core board.

[0040] The above Figure 4 Possible implementations of step 401 shown may include the following steps 4011 to 4013: In step 4011, when the fault level of the first FPGA in the valve control interface unit is lower than the fault level of the second FPGA, the first FPGA is determined to be in master state and the second FPGA is in slave state.

[0041] In step 4012, when the fault level of the first FPGA is higher than the fault level of the second FPGA, the first FPGA is determined to be in the slave state, and the second FPGA is determined to be in the master state.

[0042] In step 4013, when the fault level of the first FPGA is the same as the fault level of the second FPGA, the current master-slave states of the first FPGA and the second FPGA remain unchanged.

[0043] For example, the specific judgment process of the master-slave state of a certain FPGA itself is as Figure 6 shown in the figure.

[0044] The two FPGAs judge their own master-slave states in real time according to the following principles. The core is to determine their respective master-slave states through the fault levels n1 and n2 of the two FPGAs, and the specific judgment principles are as follows: (1) If the fault level of the local FPGA is lower than the fault level of the other FPGA (i.e., n1<n2), the local FPGA is determined to be in the master state; (2) If the fault level of the local FPGA is higher than the fault level of the other FPGA (i.e., n1>n2), the local FPGA is determined to be in the slave state; (3) If the fault levels of the two FPGAs are the same (i.e., n1=n2), the local FPGA keeps the current master-slave state unchanged and does not perform state switching, so as to ensure the stability of link selection.

[0045] Wherein, the value range of the fault levels n1 and n2 of the FPGA is 0~5, where n1=0 represents no communication interface abnormality, n1=1-4 corresponds to the abnormality of 1-4 communication physical interfaces, and n1=5 represents that the downlink data is unavailable due to the fault of the core board itself.

[0046] That is to say, of the two FPGAs, the one with the lower fault level is determined to be in the master state, and the other is in the slave state.

[0047] The possible implementation of step 402 shown in the above Figure 4 may include the following steps 4021 to 4023: In step 4021, the status signal of the first FPGA and the status signal of the second FPGA are respectively generated based on the master-slave states.

[0048] In step 4022, based on the status signal of the first FPGA and the status signal of the second FPGA, the master-slave status signal of the first FPGA and the master-slave status signal of the second FPGA are generated in combination.

[0049] In step 4023, when the master-slave status signals of the first FPGA and the second FPGA both change to the target signal, the shift enable signal of the selection signal is set to the target value to realize the shift of the selection signal.

[0050] For example, after determining their respective master-slave states, the two FPGAs need to send their master-slave states to each other. Figure 5 Number ①), combining the master-slave signals from the two FPGAs to generate a master-slave status signal (denoted as ms_state). Then, a select signal change enable signal (denoted as sel_change_en) is introduced. The logical state of this signal is determined by conditions such as ms_state, as detailed in the following logic. Figure 7 As shown.

[0051] The logic state determination rule for the sel_change_en signal is as follows: when each FPGA detects that ms_state has become 10 (i.e., it is in master state and the other party is in slave state), it sets sel_change_en to 1; when sel_change_en is 1, it is immediately reset to 0.

[0052] In other words, the master-slave status signal ms_state is a 2-bit binary number. The high-order bit represents the master-slave status of the FPGA itself, and the low-order bit represents the master-slave status of the other FPGA being received. The sel_change_en signal is set to 1 only when ms_state becomes 10. The selection signals of the two FPGAs are initialized to CS1=1 and CS2=0. The selection signals are adjusted only when sel_change_en is 1; otherwise, the selection signals remain unchanged.

[0053] The specific implementation of step 4022 above may include the following steps S21 to S22: In step 21, the master-slave status signal of the first FPGA is generated by combining the status signals of the first FPGA and the second FPGA in the order of their respective status signals.

[0054] In step 22, the master-slave status signal of the second FPGA is generated by combining the status signals of the second FPGA and the status signals of the first FPGA in the order of the status signals of the second FPGA.

[0055] The above Figure 4 Possible implementations of step 403 shown may include the following steps 4031 to 4032: In step 4031, when the shift enable signal of the selection signal is the target value, a first standby signal of the first FPGA and a second standby signal of the second FPGA are generated based on the master-slave state of the first FPGA and the second FPGA.

[0056] In step 4032, when the first standby signal and the second standby signal are opposite, a selection signal is generated for the first FPGA output to the 2-to-1 logic chip, or when the first standby signal and the second standby signal are the same, a selection signal is generated for the first FPGA output to the 2-to-1 logic chip.

[0057] For example, the selection signal of the valve control interface unit's FPGA is mainly generated based on its master-slave status. The generation process of the selection signal is as follows: Figure 8 As shown, the selection signal of FPGA1 is initialized to 1, and the selection signal of FPGA2 is initialized to 0.

[0058] When sel_change_en is 1, the two FPGAs must first send their respective selection signals to each other, and then combine their own IDs and master-slave status to determine the final selection signal output to the 2-to-1 logic chip: if FPGA1 is in the master state, its selection signal output to the logic chip is opposite to the output signal of FPGA2; if FPGA2 is in the master state, its selection signal output to the logic chip is consistent with the output signal of FPGA2.

[0059] In other cases, the select signals for both FPGAs remain unchanged.

[0060]

[0061] Table 1 Table 1 is a truth table showing the logical relationship between the output of the 2-to-1 logic chip and the selection signals (CS1, CS2) of the two FPGAs. According to this truth table, when the selection signals output by the two FPGAs are opposite, the logic chip selects the output of FPGA1 to send to the central control board; when the selection signals output by the two FPGAs are the same, the logic chip selects the output of FPGA2 to send to the central control board.

[0062] Based on the selection signal generation logic described above, it is easy to see that when FPGA1 is in master state and FPGA2 is in slave state, the selection signals output by the two FPGAs are opposite, and the logic chip will select the output of FPGA1 accordingly; when FPGA2 is in master state and FPGA1 is in slave state, the selection signals output by the two FPGAs are the same, and the logic chip will select the output of FPGA2. This achieves the design goal of enabling the logic chip to accurately output the link signal corresponding to the master state FPGA.

[0063] The described link selection method requires no new complex hardware. It is implemented based on the existing FPGA and 2-to-1 logic chip on the interface board, and can be directly adapted to cross-redundant valve control architectures without large-scale modifications to existing systems. The truth table clearly defines the correspondence between the output of the 2-to-1 logic chip and the selection signals (CS1, CS2) of the two FPGAs, providing a clear logical basis for link selection and ensuring the reliability of the selection process. Furthermore, the link selection process requires no manual intervention; the FPGA automatically performs fault level comparison, master-slave status determination, and selection signal adjustment, achieving automatic and seamless link switching.

[0064] The specific implementation of step 4031 above may include the following steps S31 to S32: In step 31, when the first FPGA is in the master state and the second FPGA is in the slave state, opposite first standby signals and second standby signals are generated.

[0065] In step 32, if the first FPGA is in slave state and the second FPGA is in master state, the same first standby signal and second standby signal are generated.

[0066] For example, to facilitate understanding of the above selection signal generation logic and truth table application rules, a specific example is provided below: FPGA1's selection signal CS1 (i.e., the first standby signal) is initialized to 1, and FPGA2's selection signal CS2 (i.e., the second standby signal) is initialized to 0. When FPGA1 is in the master state and FPGA2 is in the slave state, FPGA2's selection signal remains CS2=0, and FPGA1's selection signal takes the inverse value of FPGA2's selection signal, i.e., CS1=~CS2=1. At this time, CS1=1 and CS2=0. Combining the truth table rules in Table 1, the logic chip ultimately selects the output signal of FPGA1, consistent with the previous logic determination result.

[0067] In the above Figure 4 Before step 401 shown, the downlink selection method may further include the following steps: Based on the fault information of the first FPGA and the second FPGA, the core board of the valve control unit obtains the fault level of the first FPGA and the second FPGA using a preset FPGA fault level judgment logic.

[0068] The preset FPGA fault level judgment logic includes: When the first FPGA or the second FPGA has no communication physical interface, the fault level is set to the lowest; when the core board itself has a fault, the fault level is set to the highest. When a communication physical interface of the first FPGA or the second FPGA is abnormal, the fault level is set between the lowest and highest levels, and the fault level is increased sequentially according to the number of abnormal communication physical interfaces.

[0069] For example, the following rules apply to the FPGA fault level of the interface board (i.e., the preset FPGA fault level judgment logic). The larger the number, the higher the severity of the fault. The specific rules are as follows: When the internal fault flag "Core board downlink data unavailable" on the core board is 0, the fault level n1 is equal to the number of communication anomalies of the interface board FPGA receiving the core board. That is, the value of n1 may be one of the five integers: 0, 1, 2, 3, and 4. Among them, n1=0 represents no communication physical interface anomaly (i.e., communication is normal), and n1 is 1 to 3, which correspond to 1 to 4 communication physical interface anomalies respectively. When the core board detects other faults that cause downlink data to fail and become unusable, the core board will set its internal fault flag "Core board downlink data unavailable" to 1. At this time, the FPGA fault level n1 of the interface board corresponding to the core board is uniformly set to 5 to distinguish between two scenarios: communication interface abnormality and core board fault.

[0070] The above-mentioned definition of fault level n1 also applies to fault level n2 for the other FPGA. The specific process for obtaining the FPGA fault level is as follows: Figure 9 As shown.

[0071] To address the fatal flaws of existing parallel valve control architectures, this invention, based on a cross-redundant valve control architecture, designs a link selection method that allows each interface board to independently determine and select links. This enables each interface board to independently complete link determination and selection through its own logic, without relying on instructions from the primary system. This effectively improves link utilization, avoids unnecessary redundancy loss due to primary system switching, fully releases the redundancy potential of the cross-connect architecture, enhances system reliability, and solves the aforementioned key requirements.

[0072] This invention provides a downlink selection method for interface boards of valve-controlled interface units based on a cross-redundant valve-controlled architecture. The core objective is to enable independent judgment and autonomous link selection by the interface boards, without relying on commands from the primary system. Specifically, this invention aims to allow each interface board to independently complete link judgment and selection through its own logic, effectively improving link utilization, avoiding unnecessary redundancy losses due to primary system switching, fully releasing the redundancy potential of the cross-connection architecture, and improving system redundancy and reliability. It completely solves the defect in traditional parallel valve-controlled architectures where a single point of failure causes the entire redundant link to fail, reducing the risk of converter downtime due to link failures, improving the overall reliability and operational flexibility of the converter control and protection system, and meeting the high reliability and high stability requirements of valve-controlled systems in my country's long-distance power transmission technology development.

[0073] This invention relies on a cross-connect architecture and employs a link selection strategy based on independent judgment by the interface board. Specifically, it determines the master-slave status based on the FPGA fault level and generates a selection signal, effectively releasing the redundancy potential of the cross-connect architecture and overcoming the fatal flaws of the traditional parallel valve-controlled architecture. The significant technical effects are as follows: (1) Improve link redundancy reliability and solve the fatal defects of traditional architecture: Based on the cross-connection architecture, the interface board can complete the link selection autonomously through the FPGA master-slave determination and selection signal generation logic designed in this invention, without relying on the master system instructions. This breaks the deep binding limitation between the master control system and the core board in the traditional parallel connection architecture, avoids the failure of the entire link due to a single point of failure of a single system, gives full play to the advantages of dual redundancy design, reduces the risk of the converter stopping due to link failure, and ensures the stable operation of the system.

[0074] (2) Improve link utilization and fully release the redundancy potential of cross-connect architecture: Through the FPGA fault level classification, master-slave determination and truth table matching strategy set by the present invention, the interface board can autonomously and quickly lock the downlink corresponding to the master state FPGA, realize the reasonable allocation and efficient utilization of two available downlinks, avoid unnecessary redundancy loss caused by master system switching, fully release the redundancy potential of cross-connect architecture, and further improve system redundancy and reliability.

[0075] (3) Highly practical and adaptable, reducing maintenance costs and easy to implement in engineering: This invention is based on the existing FPGA and 2-to-1 logic chip of the interface board. No new complex hardware is required, the cost is controllable, and it can be directly adapted to the cross-redundant valve control architecture without large-scale modification of the existing system. The FPGA automatically completes the fault level comparison, master-slave status determination and selection signal adjustment to realize the autonomous link selection of the interface board, reduce the difficulty and cost of maintenance, and can flexibly adjust parameters to adapt to different engineering needs.

[0076] Example 2: To further illustrate the feasibility and practicality of the technical solution of this invention, the following uses a two-layer compact cross-redundant valve control architecture as a specific application scenario. The two-layer compact cross-redundant valve control architecture is as follows: Figure 10 The embodiments of the present invention are described in detail below. These embodiments are based on the link selection strategy disclosed in the foregoing invention, clarifying specific implementation methods and application processes. The scope of protection of the present invention is not limited to the following embodiments.

[0077] This embodiment uses a static var generator (SVG) with a rated capacity of 300 Mvar as the application platform, such as... Figure 11 As shown, the SVG adopts a modular multilevel chain three-phase star topology, which includes three bridge arms, each of which is configured with several sub-modules. Each sub-module integrates four insulated gate bipolar transistors (IGBTs) and one capacitor. The valve control system is responsible for controlling the turn-on and turn-off of the sub-modules. It establishes communication with each MMC sub-module through optical fiber and sends data frames to precisely control the working state of the IGBTs. The control cycle of the SVG converter is set to 50μs.

[0078] The SVG valve control system adopts a dual-layer compact cross-redundant valve control architecture. Compactness refers to the fact that the sub-modules of the three bridge arms are not connected to different valve control interface units. The valve control host unit employs a dual-redundant design, configuring two valve control interface units. Valve control interface unit 1 is connected to the odd-numbered sub-modules, and valve control interface unit 2 is connected to the even-numbered sub-modules. The core boards of the valve control host unit and the two valve control interface units both use the cross-connection method described in this invention, meaning that valve control host units A and B each establish independent communication connections with each valve control interface unit core board. Simultaneously, adjacent odd-numbered and even-numbered sub-modules establish additional cross-redundant connections through a pair of optical fibers, further improving link reliability.

[0079] In the initial state, the valve control system is fault-free. The valve control host unit A, corresponding to the main control unit, is the primary system, and system B is the backup system. Each interface board of the valve control interface unit initially has FPGA1 in the primary state and FPGA2 in the secondary state. When FPGA1 of a certain interface board of valve control interface unit 1 receives data from core board 1, if a communication failure occurs on one channel, according to the interface board downlink selection logic of this invention, the fault level of FPGA1 on that interface board increases, thus switching to the secondary state, and FPGA2 switches to the primary state. Finally, the interface board selects the output signal of FPGA2 to send to the corresponding submodule. The three submodules corresponding to that channel do not need to receive data from adjacent submodules, and the entire system does not need to switch between primary and backup systems, making the impact of the fault controllable. Even if an anomaly occurs in the corresponding symmetrical channel of valve control interface unit 2 based on the above fault, the three pairs of adjacent submodules do not need to bypass or switch between primary and backup systems. Compared to the traditional parallel valve-controlled architecture, when the first fault occurs, the submodule needs to receive the trigger command through the adjacent submodule; when the second fault occurs, if the primary / backup system is not switched, the 3 pairs (6 submodules) will bypass because they cannot receive the valve control command. Therefore, it can be seen that the cross-connect architecture, combined with the link selection logic of this invention, can significantly improve hardware utilization and link reliability.

[0080] In summary, this embodiment verifies the feasibility and practicality of the technical solution of the present invention by applying the link selection strategy of the present invention to the SVG device with a two-layer compact cross-redundant valve control architecture. Compared with the traditional parallel valve control architecture, the present invention can effectively improve the reliability of link redundancy, reduce the scope of fault impact, and improve hardware utilization, fully releasing the technical advantages of the cross-connection architecture and fully meeting the high reliability and high stability operation requirements of the converter valve control system.

[0081] In some scenarios, the downlink selection method is also known as the downlink link selection method of the valve-controlled interface unit interface board based on the cross-redundant valve-controlled architecture.

[0082] For example, Figure 12 This invention provides a flowchart of a downlink link selection method for a valve control interface unit interface board based on a cross-redundant valve control architecture. The link selection method is implemented based on a cross-connection architecture between the valve control host unit and the valve control interface unit core board. Figure 12 As shown, the link selection process includes: Step S1: Clarify the fault level determination rules for the two FPGAs on the interface board. Based on the availability of downlink data on the core board and the number of abnormal communication physical interfaces, set the FPGA fault levels n1 and n2. When the downlink data on the core board is unavailable, the fault level is uniformly set to 5. When the communication interface is abnormal, the fault level is consistent with the number of abnormal interfaces. Step S2: Initialize the master-slave state of the two FPGAs. FPGA1 is initially in the master state and FPGA2 is initially in the slave state. This master-slave state is only used as a link selection condition and is not related to the main or backup system of the valve control host unit. Step S3: The two FPGAs compare their respective fault levels n1 and n2 in real time, and determine their master-slave status according to the principle that "the one with the lower fault level is the master and the one with the higher fault level is the slave. If the levels are the same, the current state is maintained." Step S4: The two FPGAs interact with each other to maintain their master-slave status and generate a master-slave status signal ms_state. Based on ms_state, the logic state of the select signal change enable signal sel_change_en is determined. After sel_change_en is set to 1, it is immediately reset to 0. Step S5: Based on its own master-slave state, the sel_change_en signal, and the selection signal after the interaction, the FPGA determines the final selection signal to be output to the 2-to-1 logic chip. When FPGA1 is in master state, the selection signal is opposite to that of FPGA2, and when FPGA2 is in master state, the selection signal is the same as that of FPGA2. Step S6: The 2-to-1 logic chip selects the link signal corresponding to the master FPGA and sends it to the sub-module based on the selection signals of the two FPGAs and the truth table rules, thereby achieving reliable selection of the downlink.

[0083] The cross-connection architecture specifically establishes independent communication connections between valve control host unit A and system B and each valve control interface unit core board, breaking the deep binding limitation of the traditional parallel connection architecture.

[0084] The selection rule for the 2-to-1 logic chip is as follows: when the selection signals of the two FPGAs are opposite, the output of FPGA1 is selected; when the selection signals are the same, the output of FPGA2 is selected, thereby achieving precise selection of the FPGA link in the main state.

[0085] Example 3: Figure 13 This invention provides a block diagram of a downlink selection system based on a cross-redundant valve control architecture. The cross-redundant valve control architecture includes a valve control interface unit, which connects to a submodule of an external converter, such as... Figure 13 As shown, the downlink selection system includes: The master-slave status determination unit is used to determine the master-slave status of the first FPGA and the second FPGA based on the fault levels of the first FPGA and the second FPGA in the valve control interface unit, wherein the first FPGA and the second FPGA are interconnected. The shift enable signal generation unit is used to generate a shift enable signal for the selection signal based on the master-slave state of the first FPGA and the second FPGA. The selection signal generation unit is used to generate the selection signal based on the shift enable signal of the selection signal and the master-slave state of the first FPGA and the second FPGA. The link signal selection unit is used to select the FPGA link signal corresponding to the main state based on the selection signal, and send the FPGA link signal corresponding to the main state to the sub-module.

[0086] Optionally, the master-slave state determination unit is specifically used for: When the fault level of the first FPGA in the valve control interface unit is lower than that of the second FPGA, the first FPGA is determined to be in master state and the second FPGA is in slave state. When the fault level of the first FPGA is higher than that of the second FPGA, the first FPGA is determined to be in slave state and the second FPGA to be in master state. When the fault level of the first FPGA is the same as that of the second FPGA, the current master-slave state of the first FPGA and the second FPGA remains unchanged.

[0087] Optionally, the displacement enable signal generation unit includes: A status signal generation module is used to generate status signals for the first FPGA and the second FPGA respectively based on the master-slave status. The master-slave status signal generation module is used to combine the status signals of the first FPGA and the second FPGA to generate master-slave status signals of the first FPGA and the second FPGA based on the status signals of the first FPGA and the second FPGA. The shift enable signal generation module is used to set the shift enable signal of the selection signal to the target value when the master-slave status signals of the first FPGA and the second FPGA both change to the target signal, thereby realizing the shift of the selection signal.

[0088] Optionally, the master-slave status signal generation module is specifically used for: The master-slave status signal of the first FPGA is generated by combining the status signals of the first FPGA and the second FPGA in the order of their respective status signals. The master-slave status signals of the second FPGA are generated by combining the status signals of the second FPGA and the status signals of the first FPGA in the order of their respective status signals.

[0089] Optionally, the selection signal generation unit includes: The standby signal generation module is used to generate a first standby signal for the first FPGA and a second standby signal for the second FPGA based on the master-slave state of the first FPGA and the second FPGA when the shift enable signal of the selected signal is a target value. The selection signal generation module is used to generate a selection signal from the first FPGA to the 2-to-1 logic chip when the first standby signal and the second standby signal are opposite, or to generate a selection signal from the first FPGA to the 2-to-1 logic chip when the first standby signal and the second standby signal are the same.

[0090] Optionally, the standby signal generation module is specifically used for: When the first FPGA is in the master state and the second FPGA is in the slave state, opposite first standby signals and second standby signals are generated. If the first FPGA is in slave state and the second FPGA is in master state, the same first standby signal and second standby signal are generated.

[0091] Optionally, the downlink selection system further includes: The fault level acquisition unit is used to obtain the fault level of the first FPGA and the second FPGA based on the fault information of the first FPGA and the second FPGA by the core board of the valve control unit and by using the preset FPGA fault level judgment logic. The preset FPGA fault level judgment logic includes: When the first FPGA or the second FPGA has no communication physical interface, the fault level is set to the lowest; when the core board itself has a fault, the fault level is set to the highest. When a communication physical interface of the first FPGA or the second FPGA is abnormal, the fault level is set between the lowest and highest levels, and the fault level is increased sequentially according to the number of abnormal communication physical interfaces.

[0092] Optionally, the valve control interface unit includes: a first core board, a second core board, and at least one interface board; Each of the interface boards includes: a first FPGA, a second FPGA, and a plurality of 2-to-1 logic chips, wherein the first FPGA and the second FPGA are respectively connected to the plurality of 2-to-1 logic chips; The first FPGA is connected to the first core board through a 4-way communication physical interface, the second FPGA is connected to the second core board through a 4-way communication physical interface, and each of the 2-to-1 logic chips is connected to a sub-module of an external converter.

[0093] Optionally, the cross-redundant valve control architecture further includes: a first valve control host unit and a second valve control host unit; The first valve control host unit is connected to the first core board and the second core board respectively, and the second valve control host unit is connected to the first core board and the second core board respectively; The first valve control host unit and the second valve control host unit are respectively connected to an external main control unit.

[0094] Optionally, the cross-redundant valve control architecture further includes a backup valve control interface unit, which is connected to the first valve control host unit and the second valve control host unit respectively.

[0095] Example 4: Based on the same inventive concept, the present invention also provides an electronic device, such as... Figure 14 As shown, the electronic device includes a processor and a memory. The memory stores a computer program, which includes program instructions. The processor executes the program instructions stored in the computer storage medium. The processor may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing and control core of the terminal, and is suitable for implementing one or more instructions. Specifically, it is suitable for loading and executing one or more instructions in the computer storage medium to implement the corresponding method flow or corresponding function, so as to implement the steps of the downlink selection method in the above embodiment.

[0096] Example 5: Based on the same inventive concept, this invention also provides a storage medium, specifically a computer-readable storage medium (Memory), which is a memory device in an electronic device used to store programs and data. It is understood that the computer-readable storage medium here can include both the built-in storage medium in the electronic device and extended storage media supported by the electronic device. The computer-readable storage medium provides storage space that stores the terminal's operating system. Furthermore, this storage space also stores one or more instructions suitable for loading and execution by a processor. These instructions can be one or more computer programs (including program code). It should be noted that the computer-readable storage medium here can be high-speed RAM or non-volatile memory, such as at least one disk storage device. The processor can load and execute one or more instructions stored in the computer-readable storage medium to implement the steps of the downlink selection method in the above embodiments.

[0097] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0098] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0099] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1The function specified in one or more boxes.

[0100] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0101] The above are merely embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of the claims of the present invention pending approval.

Claims

1. A downlink selection method based on a cross-redundant valve-controlled architecture, characterized in that, The cross-redundant valve control architecture includes: a valve control interface unit, which connects to a sub-module of an external converter; the downlink selection method includes: Based on the fault levels of the first FPGA and the second FPGA in the valve control interface unit, the master-slave status of the first FPGA and the second FPGA is determined, and the first FPGA and the second FPGA are interconnected. Based on the master-slave state of the first FPGA and the second FPGA, a shift enable signal for the selection signal is generated; The selection signal is generated based on the shift enable signal of the selection signal and the master-slave status of the first FPGA and the second FPGA; Based on the selection signal, the FPGA link signal corresponding to the main state is selected, and the FPGA link signal corresponding to the main state is sent down to the sub-module.

2. The method according to claim 1, characterized in that, The process of determining the master-slave status of the first FPGA and the second FPGA based on their fault levels in the valve-controlled interface unit includes: When the fault level of the first FPGA in the valve control interface unit is lower than that of the second FPGA, the first FPGA is determined to be in master state and the second FPGA is in slave state. When the fault level of the first FPGA is higher than that of the second FPGA, the first FPGA is determined to be in slave state and the second FPGA to be in master state. When the fault level of the first FPGA is the same as that of the second FPGA, the current master-slave state of the first FPGA and the second FPGA remains unchanged.

3. The method according to claim 1, characterized in that, The step-by-step enable signal for generating the selection signal based on the master-slave state of the first FPGA and the second FPGA includes: Based on the master-slave state, the status signals of the first FPGA and the second FPGA are generated respectively. Based on the status signals of the first FPGA and the second FPGA, the master-slave status signals of the first FPGA and the master-slave status signals of the second FPGA are generated by combining them. When the master-slave status signals of the first FPGA and the second FPGA both change to the target signal, the shift enable signal of the selection signal is set to the target value to realize the shift of the selection signal.

4. The method according to claim 3, characterized in that, The process of combining the status signals of the first FPGA and the second FPGA to generate the master-slave status signals of the first FPGA and the second FPGA includes: The master-slave status signal of the first FPGA is generated by combining the status signals of the first FPGA and the second FPGA in the order of their respective status signals. The master-slave status signals of the second FPGA are generated by combining the status signals of the second FPGA and the status signals of the first FPGA in the order of their respective status signals.

5. The method according to claim 1, characterized in that, The generation of the selection signal based on the shift enable signal of the selection signal and the master-slave state of the first FPGA and the second FPGA includes: When the shift enable signal of the selection signal is the target value, a first standby signal of the first FPGA and a second standby signal of the second FPGA are generated based on the master-slave state of the first FPGA and the second FPGA. When the first standby signal and the second standby signal are opposite, a selection signal is generated from the first FPGA output to the 2-to-1 logic chip; or when the first standby signal and the second standby signal are the same, a selection signal is generated from the first FPGA output to the 2-to-1 logic chip.

6. The method according to claim 5, characterized in that, The step of generating a first standby signal for the first FPGA and a second standby signal for the second FPGA based on the master-slave status of the first FPGA and the second FPGA includes: When the first FPGA is in the master state and the second FPGA is in the slave state, opposite first standby signals and second standby signals are generated. If the first FPGA is in slave state and the second FPGA is in master state, the same first standby signal and second standby signal are generated.

7. The method according to claim 1, characterized in that, Before determining the master-slave status of the first FPGA and the second FPGA based on their fault levels in the valve-controlled interface unit, the downlink selection method further includes: Based on the fault information of the first FPGA and the second FPGA, the core board of the valve control unit obtains the fault level of the first FPGA and the second FPGA using a preset FPGA fault level judgment logic. The preset FPGA fault level judgment logic includes: When the first FPGA or the second FPGA has no communication physical interface, the fault level is set to the lowest; when the core board itself has a fault, the fault level is set to the highest. When a communication physical interface of the first FPGA or the second FPGA is abnormal, the fault level is set between the lowest and highest levels, and the fault level is increased sequentially according to the number of abnormal communication physical interfaces.

8. The method according to claim 1, characterized in that, The valve control interface unit includes: a first core board, a second core board, and at least one interface board; Each of the interface boards includes: a first FPGA, a second FPGA, and a plurality of 2-to-1 logic chips, wherein the first FPGA and the second FPGA are respectively connected to the plurality of 2-to-1 logic chips; The first FPGA is connected to the first core board through a 4-way communication physical interface, the second FPGA is connected to the second core board through a 4-way communication physical interface, and each of the 2-to-1 logic chips is connected to a sub-module of an external converter.

9. The method according to claim 8, characterized in that, The cross-redundant valve control architecture further includes: a first valve control host unit and a second valve control host unit; The first valve control host unit is connected to the first core board and the second core board respectively, and the second valve control host unit is connected to the first core board and the second core board respectively; The first valve control host unit and the second valve control host unit are respectively connected to an external main control unit.

10. The method according to claim 9, characterized in that, The cross-redundant valve control architecture further includes a backup valve control interface unit, which is connected to the first valve control host unit and the second valve control host unit respectively.

11. A downlink selection system based on a cross-redundant valve-controlled architecture, characterized in that, The cross-redundant valve control architecture includes: a valve control interface unit, which connects to a submodule of an external converter; the downlink selection system includes: The master-slave status determination unit is used to determine the master-slave status of the first FPGA and the second FPGA based on the fault levels of the first FPGA and the second FPGA in the valve control interface unit, wherein the first FPGA and the second FPGA are interconnected. The shift enable signal generation unit is used to generate a shift enable signal for the selection signal based on the master-slave state of the first FPGA and the second FPGA. The selection signal generation unit is used to generate the selection signal based on the shift enable signal of the selection signal and the master-slave state of the first FPGA and the second FPGA. The link signal selection unit is used to select the FPGA link signal corresponding to the main state based on the selection signal, and send the FPGA link signal corresponding to the main state to the sub-module.

12. An electronic device, characterized in that, include: One or more processors; The processor is used to store one or more programs; When the one or more programs are executed by the one or more processors, a downlink selection method as described in any one of claims 1 to 10 is implemented.

13. A computer-readable storage medium, characterized in that, It contains a computer program, which, when executed, implements a downlink selection method as described in any one of claims 1 to 10.

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