Power converter and its turn-off time control circuit and control method

Abstract

Disclosed are a power converter and a turn-off time control circuit and method thereof. The turn-off time control circuit comprises a comparator having a first input terminal and a second input terminal, and an output terminal; a capacitor having one end coupled to the first input terminal of the comparator and the other end coupled to a first reference voltage; a first charging path between a switching node of the power converter and the first end of the capacitor; and a second charging path between an input terminal of the power converter and the first end of the capacitor, wherein the comparator compares a charging voltage of the capacitor with a second reference voltage to generate a turn-off time end signal of the power converter for controlling a turn-off time of a power tube in the power converter. The charging paths related to the input voltage are arranged in the turn-off time control circuit to compensate for the reference voltage fluctuation caused by the input voltage variation, so as to improve the stability of the switching frequency of the power converter.

Description

Technical Field

[0001] This disclosure relates to the field of power electronics technology, and more specifically, to power converters and their turn-off time control circuits and methods. Background Technology

[0002] Power converters are indispensable power management units in electronic devices and are widely used in consumer electronics, industrial control, communication equipment and automotive electronics. They are used to convert one form of electrical energy (such as a lower input voltage) into another form (such as a higher output voltage) to meet the power supply requirements of different loads.

[0003] Constant off-time control is a common method for controlling the operation of power transistors in power converters. Compared to traditional peak current control, constant off-time control eliminates the need for complex slope compensation circuits and offers a faster dynamic response, making it particularly suitable for applications with stringent requirements for power supply transient response. In power converters employing constant off-time control, the control circuit generates a fixed-duration off-time signal to determine when the power transistor switches from the off state back to the on state, thereby regulating energy transfer and maintaining a stable output voltage.

[0004] However, in existing constant off-time control circuits, the off-time is typically generated by detecting and comparing the converter's switching node voltage and the input voltage. Specifically, when the power transistor is turned off, the switching node voltage reflects the output voltage information, and this voltage charges the capacitor through a charging network consisting of resistors and capacitors. Simultaneously, the input voltage is divided by resistors and used as a reference. When the charging voltage on the capacitor exceeds this reference, the comparator state flips, indicating the end of the off-time and the power transistor is turned back on. Theoretically, this circuit structure allows the converter's switching frequency to be independent of the input and output voltages, thus achieving constant-frequency control.

[0005] However, this existing technical solution has a significant drawback: its theoretical constant-frequency characteristic is based on mathematical approximation. In practical applications, when the conversion ratio of the power converter varies over a wide range, especially when the conversion ratio is close to 1, this approximation introduces substantial errors. This error directly causes the actual turn-off time to shift significantly with changes in the conversion ratio, making it impossible for the converter's switching frequency to remain constant. This frequency drift leads to a series of problems, including increased electromagnetic interference, more complex design, increased output ripple, and reduced utilization of magnetic components, severely impacting the overall performance and reliability of the power converter. Therefore, there is an urgent need for a constant turn-off time control circuit that can maintain a high degree of consistency in the switching frequency across a wide range of conversion ratio variations. Summary of the Invention

[0006] In view of the above problems, the purpose of this disclosure is to provide a power converter and its off-time control circuit and control method, wherein a charging path related to the input voltage is set in the off-time control circuit to compensate for reference voltage fluctuations caused by input voltage changes, thereby improving the stability of the switching frequency of the power converter.

[0007] According to one aspect of this disclosure, a turn-off time control circuit for a power converter is provided, comprising: a comparator having a first input terminal and a second input terminal, and an output terminal; a capacitor having one end coupled to the first input terminal of the comparator and the other end coupled to a first reference voltage; a first charging path located between a switching node of the power converter and a first terminal of the capacitor; and a second charging path located between the input terminal of the power converter and the first terminal of the capacitor, wherein the comparator compares the charging voltage of the capacitor with the second reference voltage to generate a turn-off time end signal for controlling the turn-off time of a power transistor in the power converter.

[0008] Optionally, the first reference voltage is a predetermined potential or ground potential.

[0009] Optionally, the first charging path includes a first resistor coupled between the switching node of the power converter and a first terminal of the capacitor.

[0010] Optionally, the second charging path includes a second resistor coupled between the input terminal of the power converter and the first terminal of the capacitor.

[0011] Optionally, the second charging path includes a voltage-controlled current source coupled between the input terminal of the power converter and the first terminal of the capacitor, and its control terminal receives the input voltage of the power converter.

[0012] Optionally, the second reference voltage is generated by the input voltage of the power converter via a voltage divider network.

[0013] Optionally, the voltage divider network includes a third resistor and a fourth resistor connected in series between the input of the power converter and ground, and the node between the third resistor and the fourth resistor provides the second reference voltage to the second input of the comparator.

[0014] Optionally, during the conduction phase of the power transistor in the power converter, the capacitor is discharged via the first charging path.

[0015] According to another aspect of this disclosure, a power converter is provided, comprising: a power stage circuit for converting an input voltage into an output voltage; and a control circuit for controlling the on and off states of a power transistor in the power stage circuit, wherein the control circuit includes the aforementioned off-time control circuit.

[0016] Optionally, the control circuit further includes: an error amplifier for comparing the feedback signal of the output voltage with a reference signal to generate an error signal; a current sampling circuit for detecting the current flowing through the power transistor to generate a current sampling signal; a current comparator for comparing the current sampling signal with a control threshold corresponding to the error signal to generate a reset signal; and an RS flip-flop, whose reset terminal receives the reset signal, whose set terminal receives the off-time end signal, and whose output terminal generates a control signal to drive the power transistor.

[0017] Optionally, the power stage circuit includes: an inductor coupled between the input terminal and the switching node of the power converter; a power transistor coupled between the switching node and ground; and a freewheeling element coupled between the switching node and the output terminal.

[0018] Optionally, the freewheeling element is selected from either a diode or a transistor.

[0019] Optionally, the power converter is selected from any one of the following topologies: BUCK type, BOOST type, BUCK-BOOST type, and flyback topology.

[0020] According to another aspect of this disclosure, a method for controlling the turn-off time of a power converter is provided, comprising: charging a capacitor from a switching node of the power converter via a first charging path and charging the capacitor from an input terminal of the power converter via a second charging path during a power transistor turn-off period; comparing the charging voltage of the capacitor with a second reference voltage; and generating a turn-off time end signal to turn on the power transistor when the charging voltage reaches the second reference voltage.

[0021] According to the turn-off time control circuit of this disclosure, by setting a first charging path and a second charging path to charge the capacitor from the switching node and input terminal of the power converter respectively, the comparator compares the charging voltage of the capacitor with a second reference voltage to generate a turn-off time end signal. When the input voltage and output voltage of the power converter are close, this turn-off time control circuit can effectively compensate for the error introduced by the linear approximation of the switching frequency, thereby significantly improving the stability of the switching frequency of the power converter over a wide conversion ratio range and avoiding problems such as increased electromagnetic interference design complexity, increased output ripple, and reduced utilization of magnetic components caused by frequency drift.

[0022] In a further embodiment, by setting the first reference voltage to ground potential or a predetermined potential, and by setting the first charging path and the second charging path to include a first resistor and a second resistor respectively, or by setting the second charging path to include a voltage-controlled current source, precise control of the capacitor charging current can be achieved. In particular, when the second charging path uses a voltage-controlled current source, the charging rate can be dynamically adjusted according to the input voltage, further optimizing the adaptability of the turn-off time to changes in the conversion ratio, thereby achieving high-precision fixed-frequency control over a wider conversion ratio range. Furthermore, by setting the second reference voltage to be generated by the input voltage through a voltage divider network, and limiting the capacitor to discharge via the first charging path during the power transistor's conduction phase, the coordination between the turn-off time control circuit and the power converter's operating state is ensured, improving the overall control reliability. Attached Figure Description

[0023] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments of this disclosure with reference to the accompanying drawings.

[0024] Figure 1 A schematic block diagram of a power converter is shown.

[0025] Figure 2 A schematic circuit diagram of a turn-off time control circuit according to the prior art is shown.

[0026] Figure 3 Showing the use of Figure 2 The waveform diagram of the power converter when the off-time control circuit is shown is shown.

[0027] Figure 4 A schematic circuit diagram of a turn-off time control circuit according to a first embodiment of the present disclosure is shown.

[0028] Figure 5 Showing the use of Figure 4 The waveform diagram of the power converter when the off-time control circuit is shown is shown.

[0029] Figure 6 A schematic circuit diagram of a turn-off time control circuit according to a second embodiment of the present disclosure is shown. Detailed Implementation

[0030] Various embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various portions in the drawings are not drawn to scale.

[0031] The following explanation mainly uses a BOOST type power converter as an example; however, this disclosure is not limited thereto.

[0032] Figure 1A schematic block diagram of a power converter 100 is shown. The power converter 100 includes a power stage circuit and a control circuit 110. The power stage circuit is used to convert input electrical energy into output electrical energy, and the control circuit 110 is used to perform closed-loop control of the power stage circuit, thereby achieving a stable output voltage VOUT.

[0033] The power stage circuit includes an inductor L and a power transistor M1 connected in series between the input terminal and ground, a freewheeling diode D connected between the switching node SW between the inductor L and the power transistor M1 and the output terminal, and an output capacitor Co connected between the output terminal and ground.

[0034] The input voltage Vin is input to the switching node SW via the inductor L. The switching node SW is connected to the first terminal (e.g., drain or collector) of the power transistor M1. The second terminal (e.g., source or emitter) of the power transistor M1 is connected to ground. Under the action of the control signal VG, the power transistor M1 is periodically turned on and off, thereby periodically charging and discharging the switching node SW.

[0035] A freewheeling diode D is placed between the switching node SW and the output terminal. When the power transistor M1 is turned off, the energy stored in the inductor L is released to the output terminal through the freewheeling diode D, thereby maintaining the continuity of the output voltage.

[0036] An output capacitor Co is connected in parallel at the output terminal to filter and smooth the output voltage, thereby reducing output ripple. A load is also connected at the output terminal to actually dissipate the output energy.

[0037] Furthermore, the output terminal is sampled and fed back through a voltage divider network. The voltage divider network includes resistors R11 and R12, which are connected in series between the output terminal and ground. Its voltage divider nodes are used to generate a feedback signal FB to reflect the magnitude of the output voltage.

[0038] The control circuit 110 includes functional units such as an error amplifier 111, a current sampling circuit 112, a current comparator 113, a turn-off time control module 114, an RS flip-flop 115, and a driver 116.

[0039] Error amplifier 111 compares the feedback signal FB with the reference signal REF and outputs an error signal EA. The error signal EA characterizes the deviation between the output voltage VOUT and the target voltage.

[0040] The current sampling circuit 112 is used to detect the current information flowing through the power transistor M1 and output a current sampling signal ISEN corresponding to the current magnitude.

[0041] The first input of the current comparator 113 receives the current sampling signal ISEN, and the second input receives the control threshold corresponding to the error signal EA (e.g., the compensation signal generated at the output of the error amplifier 111). The output generates a comparison signal COMP. When the current sampling signal ISEN reaches the control threshold, the comparison signal COMP flips and is sent as a reset signal to the reset input (R) of the RS flip-flop 115 to turn off the power transistor M1.

[0042] The shutdown time control module 114 is used to start timing after the power transistor M1 is turned off. When the set shutdown time ends, it generates a shutdown time end signal TOFF, which is sent as a set signal to the set input (S) of the RS flip-flop 115 to restart the power transistor M1.

[0043] The RS flip-flop 115 generates a control signal VG based on the signals from the set input (S) and reset input (R): when the set signal TOFF is valid, the control signal VG flips to a high level, turning on the power transistor M1; when the reset signal COMP is valid, the control signal VG flips to a low level, turning off the power transistor M1. Thus, the system achieves constant off-time control within each switching cycle, meaning it turns off when the current reaches a threshold and turns on after a fixed off-time.

[0044] Furthermore, in one embodiment, the system 100 may also include a driving unit 116 for driving the gate of the power transistor M1. The driving unit 116 receives the control signal VG output by the RS flip-flop 115 and drives the power transistor M1 to achieve efficient switching operation.

[0045] The power converter 100 achieves high-precision and stable control of the output voltage VOUT through a current-mode control loop consisting of an error amplifier 111, a current sampling circuit 112, and a current comparator 113, combined with the set / reset logic of the turn-off time control module 114 and the RS flip-flop 115, while improving the dynamic response performance and stability of the system.

[0046] Figure 2 A schematic circuit diagram of a turn-off time control circuit according to the prior art is shown. The turn-off time control circuit 114 includes resistors R0 to R2, capacitor C0, and comparator 11.

[0047] Resistors R0 and C0 are connected in series between the switching node SW and ground, and the node between them is connected to the non-inverting input of comparator 11. Resistors R1 and R2 are connected in series between the input of power converter 100 and ground, and the node between them is connected to the inverting input of comparator 11. The output of comparator 11 provides the off-time end signal TOFF.

[0048] During the turn-on phase of power transistor M1, the switching node SW is grounded. Capacitor C0 discharges through resistor R0, and the voltage Vp across capacitor C0 decreases, causing the turn-off time end signal TOFF to flip from the active state to the inactive state, and subsequently remain in the inactive state.

[0049] During the turn-off phase of power transistor M1, switching node SW is connected to the input terminal of power converter 100 via inductor L. Capacitor C0 is charged through resistor R0, and the voltage Vp across capacitor C0 increases, causing the turn-off time end signal TOFF to flip from an invalid state to an active state, and subsequently remain active.

[0050] The turn-off time control circuit 114 starts timing after the power transistor M1 is turned off. When the set turn-off time Toff ends, the turn-off time end signal TOFF flips from the invalid state to the valid state, thereby generating a rising edge. The set turn-off time Toff corresponds to the moment when the voltage Vp across capacitor C0 rises to exceed the voltage division Vn of resistors R1 and R2.

[0051] During the turn-off phase of the power transistor M1, the voltage Vp across capacitor C0 changes with time t. Voltages Vp and Vn are shown in equations (1) and (2), respectively:

[0052] (1)

[0053] (2)

[0054] Where Vout represents the output voltage of the power converter 100, Vd represents the voltage drop of the freewheeling diode, C0 represents the capacitance value, R0, R1 and R2 represent the resistance values ​​of the corresponding resistors, and K represents the voltage division ratio of the voltage divider network composed of resistors R1 and R2.

[0055] Combining formulas (1) and (2) above, we can obtain that when Vp=Vn, the turn-off time Toff is as shown in formula (3):

[0056] (3)

[0057] Based on the relationship between the duty cycle D of the power converter 100 and the input voltage Vin and the output voltage Vout, the switching frequency Fsw of the power converter 100 can be obtained as shown in formula (4):

[0058] (4)

[0059] If we perform a Taylor expansion on the natural logarithm function ln in formula (4), and approximate... Furthermore, if the output diode voltage drop Vd is ignored, the switching frequency Fsw can be simplified to formula (5).

[0060] (5)

[0061] For the predetermined device parameters of the off-time control circuit 114, namely the capacitance value of capacitor C1 and the resistance values ​​of resistors R0 to R2, the switching frequency Fsw will be a fixed value, independent of the input voltage and output voltage, thus enabling fixed-frequency control with different outputs for different inputs.

[0062] However, the Taylor expansion of the natural logarithm function ln in the above formula (4) has a significant error near X=0. But if we accurately consider the Taylor expansion of ln(1-X) at X=0:

[0063] (6)

[0064] It can be seen that as x = Vin / (Vout + Vd) approaches 1, the proportion of polynomial terms in the Taylor expansion increases, leading to... The larger the error, the better.

[0065] Assuming the conversion ratio of power converter 100 Taking the derivative of formula (3) yields:

[0066] (7)

[0067] According to the above formula (7), the slope of the turn-off time Toff_init changes significantly with the change in conversion ratio M. In the power converter 100 with a wide conversion ratio range, the above-mentioned traditional constant turn-off time control circuit still has significant defects. The larger the conversion ratio M of the power converter 100, the greater the deviation between the actual switching frequency Fsw_real and the ideal switching frequency Fsw calculated above, making it impossible to maintain the constant frequency control of the power converter 100 in a wide conversion ratio range.

[0068] Figure 3 Showing the use of Figure 2 The waveform diagram of the power converter under the control of the turn-off time control circuit is shown. From top to bottom, the waveforms are the input voltage Vin, the inductor current iL, and the switching node voltage Vsw. The power transistor M1 goes through the conduction and turn-off phases in each switching cycle. The switching node voltage Vsw is a square waveform, and the inductor current iL is a periodic triangular waveform.

[0069] In the first stage before the input voltage Vin changes, the system operates in a state where the input voltage Vin is low, with a switching period of T1 and a turn-off time of Toff1.

[0070] In the second stage after the input voltage Vin jumps up, the system operates in a state with a higher input voltage Vin, and the switching cycle is T2, where the turn-off time is Toff2.

[0071] In the turn-off time control circuit, the turn-off time Toff is determined by the signal levels of the non-inverting and inverting inputs of comparator 11. At the non-inverting input, the voltage Vp across capacitor C0 is the charging voltage related to the charging speed. At the inverting input, the reference voltage Vn is a voltage divider of the input voltage Vin.

[0072] In the prior art, capacitor C0 is charged from the switching node of the power converter via a single charging path through resistor R0. When the input voltage Vin changes, the turn-off time varies from Toff1 to Toff2, and the switching period varies from T1 to T2. If the conversion ratio M of the power converter 100 is close to 1, the actual switching frequency Fsw_real of the power converter 100 deviates from the ideal switching frequency Fsw.

[0073] Figure 4 A schematic circuit diagram of a turn-off time control circuit 214 according to a first embodiment of the present disclosure is shown. The turn-off time control circuit 214 includes resistors R0 to R3, a capacitor C0, and a comparator 11.

[0074] Resistor R0 and capacitor C0 are connected in series between the switching node SW and ground, and the node between them is connected to the non-inverting input of comparator 11. Resistor R3 is connected between the input of power converter 100 and the node between resistor R0 and capacitor C0. Resistors R1 and R2 are connected in series between the input of power converter 100 and ground, and the node between them is connected to the inverting input of comparator 11. The output of comparator 11 provides the off-time end signal TOFF.

[0075] During the turn-on phase of power transistor M1, the switching node SW is grounded. Capacitor C0 discharges through resistor R0, and the voltage Vp across capacitor C0 decreases, causing the turn-off time end signal TOFF to flip from the active state to the inactive state, and subsequently remain in the inactive state.

[0076] During the turn-off phase of power transistor M1, switching node SW is connected to the input terminal of power converter 100 via inductor L. Capacitor C0 is charged from switching node SW via resistor R0 and simultaneously charged from the input terminal of power converter 100 via resistor R3. The voltage Vp across capacitor C0 increases, causing the turn-off time end signal TOFF to flip from an invalid state to an active state, and subsequently remain active.

[0077] The turn-off time control circuit 214 starts timing after the power transistor M1 is turned off. When the set turn-off time Toff ends, the turn-off time end signal TOFF flips from the invalid state to the valid state, thereby generating a rising edge. The set turn-off time Toff corresponds to the moment when the voltage Vp across capacitor C0 rises to exceed the voltage division Vn of resistors R1 and R2.

[0078] During the turn-off phase of the power transistor M1, due to the introduction of resistor R3, the charging path of capacitor C0 is formed by resistors R0 and R3, and its equivalent charging current Ichg is:

[0079] Ichg = (Vsw - Vp) / R0+(Vin-Vp) / R3(8)

[0080] Where Vsw represents the input voltage, Vsw represents the switching node voltage, Vp represents the voltage across capacitor C0, and R0 and R3 represent the resistance values ​​of the corresponding resistors.

[0081] During the charging process of capacitor C0, the voltage Vp across capacitor C0 changes with time t. Voltages Vp and Vn are shown in equations (9) and (10), respectively:

[0082] (9)

[0083] (10)

[0084] Where Vout represents the output voltage of the power converter 100, Vd represents the voltage drop of the freewheeling diode, C0 represents the capacitance value, R0, R1, R2 and R3 represent the resistance values ​​of the corresponding resistors, K represents the voltage division ratio of the voltage divider network composed of resistors R1 and R2, and Rc represents the equivalent parallel resistance value of resistors R0 and R3.

[0085] The equivalent parallel voltage Rc mentioned above = , can be represented as: ,or, And, u+v=1.

[0086] Combining formulas (9) and (10) above, we can obtain that when Vp=Vn, the turn-off time Toff is as shown in formula (11):

[0087] (11)

[0088] Assuming the conversion ratio of power converter 100 Differentiating formula (11) yields:

[0089] (12)

[0090] If design Then the turn-off time Toff changes the least with the conversion ratio M:

[0091] (13)

[0092] According to the above formula (13), the smaller the change in turn-off time Toff, the better the fixed-frequency control performance of power converter 100 over a wide conversion ratio range. Therefore, in engineering application design, the design value of u, v and K is generally close to 1, while the value of K is minimized as much as possible. However, due to the design limitations of the internal power domain, the value of K cannot infinitely approach 0.

[0093] Formula (7) above represents the switching frequency error of the prior art turn-off time control circuit. Formula (13) above represents the switching frequency error of the turn-off time control circuit of the first embodiment of this disclosure. Subtracting formulas (7) and (13) yields the degree of improvement in the frequency difference characteristic, as shown in formula (14):

[0094] (14)

[0095] According to the above formula (13), the entire conversion ratio range is greater than 0: 1 ≥ M ≥ 0. That is, the switching frequency error of the off-time control circuit in the prior art is always greater than the switching frequency error of the off-time control circuit in the first embodiment of this disclosure. Therefore, by using the off-time control circuit of the first embodiment of this disclosure, the power converter can obtain better fixed-frequency control performance over a wide conversion ratio range.

[0096] Figure 5 Showing the use of Figure 4 The waveform diagram of the power converter under the control of the turn-off time control circuit is shown. From top to bottom, the waveforms are the input voltage Vin, the inductor current iL, and the switching node voltage Vsw. The power transistor M1 goes through the conduction and turn-off phases in each switching cycle. The switching node voltage Vsw is a square waveform, and the inductor current iL is a periodic triangular waveform.

[0097] In the first stage before the input voltage Vin changes, the system operates in a state where the input voltage Vin is low, with a switching cycle of T3 and a turn-off time of Toff3.

[0098] In the second stage after the input voltage Vin jumps up, the system operates in a state with a higher input voltage Vin, and the switching cycle is T4, where the turn-off time is Toff4.

[0099] In the off-time control circuit, the off-time Toff is determined by the signal levels at the non-inverting input terminal and the inverting input terminal of the comparator 11. At the non-inverting input terminal, the voltage Vp across the capacitor C0 is a charging voltage related to the charging speed. At the inverting input terminal, the reference voltage Vn is a divided voltage of the input voltage Vin.

[0100] In the embodiments of the present disclosure, the capacitor C0 is charged via a first charging path through the resistor R0 from the switching node of the power converter, and via a second charging path through the resistor R3 from the input terminal of the power converter. When the input voltage Vin jumps, the off-time changes from Toff3 to Toff4, and the switching period changes from T3 to T4. Compared with Figure 3 the off-time fluctuation and switching period fluctuation shown in the drawing, Figure 5 the off-time fluctuation and switching period fluctuation shown in the drawing are reduced, that is, Toff4-Toff3<Toff2-Toff1, and T4-T3<T2-T1. Even if the conversion ratio M of the power converter 100 is close to 1, the actual switching frequency Fsw_real of the power converter 100 is closer to the ideal switching frequency Fsw.

[0101] Figure 5 shows the waveform diagram of the power converter when adopting Figure 4 the off-time control circuit 214 shown in the drawing. The waveforms from top to bottom are the input voltage Vin, the inductor current iL, and the switching node voltage Vsw in sequence.

[0102] In the first stage before the input voltage Vin jumps, the system operates in a state where the input voltage Vin is low, the inductor current iL presents a periodic triangular waveform, and the switching period is T1. In the second stage after the input voltage Vin jumps and rises, the switching period still remains T1 without significant change.

[0103] In the second stage after the input voltage Vin jumps and rises, the switching period still maintains T1.

[0104] In Figure 4 the off-time control circuit 214 shown in the drawing, the non-inverting input terminal of the comparator 11 is connected to the switching node SW and the input voltage Vin through the resistor R0 and the resistor R3 respectively at the same time. Therefore, when the input voltage Vin rises, the charging speed of the capacitor C0 is accelerated due to the additional charging path provided by the resistor R3, thereby compensating for the rise of the reference voltage Vn (obtained by dividing the input voltage Vin by the resistor R1 and the resistor R2). Compared with Figure 3 the off-time shown in the drawing, Figure 5The turn-off time Toff is further increased to effectively suppress fluctuations in the switching period T1. It can be seen that in the first embodiment of this disclosure, even if the conversion ratio M of the power converter 100 is close to 1, the switching frequency of the power converter 100 can remain constant, achieving constant-frequency control performance over a wide conversion ratio range.

[0105] Figure 6 A schematic circuit diagram of a turn-off time control circuit 314 according to a second embodiment of the present disclosure is shown. The turn-off time control circuit 314 includes resistors R0, R1, R2, capacitor C0, comparator 11, and voltage-controlled current source 12.

[0106] Resistor R0 and capacitor C0 are connected in series between the switching node SW and ground, and the node between them is connected to the non-inverting input of comparator 11. Voltage-controlled current source 12 is connected between the input terminal Vin of power converter 100 and the node between resistor R0 and capacitor C0. Its control terminal receives the signal of the input voltage Vin, thereby realizing voltage control of the current. Resistors R1 and R2 are connected in series between the input terminal Vin of power converter 100 and ground, and the node between them is connected to the inverting input of comparator 11. The output of comparator 11 provides the off-time end signal TOFF.

[0107] During the turn-on phase of power transistor M1, the switching node SW is grounded. Capacitor C0 discharges through resistor R0, and the voltage Vp across capacitor C0 decreases, causing the turn-off time end signal TOFF to flip from the active state to the inactive state, and subsequently remain in the inactive state.

[0108] During the turn-off phase of power transistor M1, switching node SW is connected to the input terminal of power converter 100 via inductor L. Capacitor C0 is charged from switching node SW via resistor R0 and simultaneously charged from the input terminal of power converter 100 via voltage-controlled current source 12. The voltage Vp across capacitor C0 increases, causing the turn-off time end signal TOFF to flip from an invalid state to an active state, and subsequently remain active.

[0109] The turn-off time control circuit 314 starts timing after the power transistor M1 is turned off. When the set turn-off time Toff ends, the turn-off time end signal TOFF flips from the invalid state to the valid state, thereby generating a rising edge. The set turn-off time Toff corresponds to the moment when the voltage Vp across capacitor C0 rises to exceed the voltage division Vn of resistors R1 and R2.

[0110] During the turn-off phase of the power transistor M1, due to the introduction of the voltage-controlled current source 12, the charging path of capacitor C0 is formed by resistor R0 and voltage-controlled current source 12, and its equivalent charging current Ichg is:

[0111] Ichg = (Vsw - Vp) / R0+ G*Vin (15)

[0112] Where Vsw represents the switching node voltage, Vp represents the voltage across capacitor C0, R0 represents the resistance value of the corresponding resistor, and G represents the gain coefficient of voltage-controlled current source 12.

[0113] Compared to the first embodiment, in the second embodiment, a voltage-controlled current source 12 is used to replace resistor R3, enabling dynamic adjustment of the charging current. When the input voltage Vin changes, the charging rate can be adaptively adjusted, thereby maintaining the stability of the off-time Toff over a wider conversion ratio range and significantly improving the accuracy of fixed-frequency control.

[0114] The above embodiments describe a turn-off time control circuit in a BOOST-type power converter. However, the constant turn-off time control circuit of this disclosure is not only applicable to boost circuits, but also to other power converter topologies, such as buck circuits, buck-boost circuits, flyback circuits, etc.

[0115] In various power converter topologies, the voltage waveform at the switching node SW reflects different combinations of input or output voltages, but the control circuit structure and operating principle of this disclosure are basically the same. Through a dual-path charging structure related to both the input voltage and the switching node voltage, the technical effect of minimizing the change in turn-off time Toff with the conversion ratio can still be achieved, ensuring the stability of the switching frequency.

[0116] In the above embodiments, it is described that during the turn-on phase of the power transistor in the power converter, capacitor C0 in the turn-off time control circuit is discharged via resistor R0. In an alternative embodiment, the capacitor may be discharged via transistors connected in parallel.

[0117] In the above embodiments, resistors R0 and C0 in the turn-off time control circuit are connected in series between the switching node SW and ground. In an alternative embodiment, resistors R0 and C0 are connected in series between the switching node SW and a predetermined potential.

[0118] Furthermore, according to embodiments of this disclosure, a method for controlling the turn-off time of a power converter is also provided, comprising: charging a capacitor from a switching node of the power converter via a first charging path and charging the capacitor from an input terminal of the power converter via a second charging path during the power transistor's turn-off period; comparing the charging voltage of the capacitor with a second reference voltage; and generating a turn-off time end signal when the charging voltage reaches the second reference voltage to turn on the power transistor.

[0119] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0120] As described above, these embodiments of the present disclosure do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present disclosure, thereby enabling those skilled in the art to make good use of the present disclosure and modifications based on it. This disclosure is limited only by the claims and their full scope and equivalents.

Claims

1. A turn-off time control circuit for a power converter, comprising: A comparator has a first input terminal, a second input terminal, and an output terminal; A capacitor, one end of which is coupled to the first input terminal of the comparator, and the other end of which is coupled to the first reference voltage; The first charging path is located between the switching node of the power converter and the first terminal of the capacitor; as well as The second charging path is located between the input terminal of the power converter and the first terminal of the capacitor. The comparator compares the charging voltage of the capacitor with a second reference voltage to generate a turn-off time end signal for the power converter, which is used to control the turn-off time of the power transistor in the power converter.

2. The turn-off time control circuit according to claim 1, wherein, The first reference voltage is a predetermined potential or ground potential.

3. The turn-off time control circuit according to claim 1, wherein, The first charging path includes a first resistor, which is coupled between the switching node of the power converter and the first terminal of the capacitor.

4. The turn-off time control circuit according to claim 1, wherein, The second charging path includes a second resistor coupled between the input terminal of the power converter and the first terminal of the capacitor.

5. The turn-off time control circuit according to claim 1, wherein, The second charging path includes a voltage-controlled current source coupled between the input terminal of the power converter and the first terminal of the capacitor, and its control terminal receives the input voltage of the power converter.

6. The turn-off time control circuit according to claim 1, wherein, The second reference voltage is generated by the input voltage of the power converter via a voltage divider network.

7. The turn-off time control circuit according to claim 6, wherein, The voltage divider network includes a third resistor and a fourth resistor connected in series between the input of the power converter and ground, and the node between the third resistor and the fourth resistor provides the second reference voltage to the second input of the comparator.

8. The turn-off time control circuit according to claim 1, wherein, During the conduction phase of the power transistor in the power converter, the capacitor discharges via the first charging path.

9. A power converter, comprising: Power stage circuitry, used to convert input voltage into output voltage; as well as The control circuit is used to control the on and off states of the power transistors in the power stage circuit. The control circuit includes a turn-off time control circuit according to any one of claims 1 to 8.

10. The power converter according to claim 9, wherein, The control circuit also includes: An error amplifier is used to compare the feedback signal of the output voltage with a reference signal to generate an error signal; A current sampling circuit is used to detect the current flowing through the power transistor to generate a current sampling signal; A current comparator is used to compare the current sampling signal with a control threshold corresponding to the error signal to generate a reset signal; and An RS flip-flop receives the reset signal at its reset terminal, receives the off-time end signal at its set terminal, and generates a control signal at its output terminal to drive the power transistor.

11. The power converter according to claim 9, wherein, The power stage circuit includes: An inductor is coupled between the input terminal and the switching node of the power converter; The power transistor is coupled between the switching node and ground; and A freewheeling element is coupled between the switching node and the output terminal.

12. The power converter according to claim 11, wherein, The freewheeling element is selected from either a diode or a transistor.

13. The power converter according to claim 9, wherein, The power converter is selected from any one of the following topologies: BUCK type, BOOST type, BUCK-BOOST type, and flyback topology.

14. A method for controlling the turn-off time of a power converter, comprising: During the power transistor's off period, the capacitor is charged from the switching node of the power converter via a first charging path, and the capacitor is charged from the input terminal of the power converter via a second charging path. The charging voltage of the capacitor is compared with the second reference voltage; as well as When the charging voltage reaches the second reference voltage, a shutdown time end signal is generated to turn on the power transistor.

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