Shut-off circuit and power converter

Abstract

The present disclosure provides a turn-off circuit and a power converter, and relates to the technical field of power converters. A specific implementation includes: circuitry arranged to change a voltage at a gate terminal of a transistor from an on voltage to an off voltage, the circuitry comprising: a first circuit arranged to change the voltage at the gate terminal from the on voltage to a first intermediate voltage at a first voltage rate with respect to time; and a second circuit arranged to change the voltage at the gate terminal from the first intermediate voltage to a second intermediate voltage at a second voltage rate with respect to time; wherein the first rate is faster than the second rate.

Description

[0001] This application is a divisional application of Chinese invention patent application filed on June 30, 2021, with application number 202110732707.1 and entitled "Shutdown Circuit and Power Converter". Technical Field

[0002] The described embodiments generally relate to power converters, and more specifically, this embodiment relates to a shutdown circuit for a power converter employing gallium nitride (GaN) transistors. Attached Figure Description

[0003] Figure 1 This is a simplified schematic diagram of a power converter with a shutdown circuit according to an embodiment of the present disclosure; Figure 2 According to embodiments of this disclosure Figure 1 A schematic diagram of the shutdown circuit shown; Figure 3 It shows Figure 1 The graph shown illustrates the gate voltage of a GaN power transistor as a function of time; and Figure 4 It shows Figure 1 The graph shows the gate voltage, drain voltage, and source voltage of a GaN power transistor as a function of time. Figure 5 A shutdown control circuit according to an embodiment of the present disclosure is shown; Figure 6 A timing diagram is shown, which illustrates... Figure 5 The gate and drain voltages of the power transistor in the turn-off control circuit are functions of time. Figure 7 The operation is shown Figure 5 The steps associated with the method for the transistor turn-off control circuit shown; Figure 8 A shutdown control circuit according to an embodiment of the present disclosure is shown; Figure 9 A timing diagram is shown, which illustrates... Figure 8 The gate and drain voltages of the power transistor in the turn-off control circuit are most time-dependent functions; and Figure 10 A shutdown control circuit according to an embodiment of the present disclosure is shown. Detailed Implementation

[0004] The circuits and related techniques disclosed herein generally relate to power conversion circuits employing one or more gallium nitride (GaN) devices. More specifically, the circuits, devices, and related techniques disclosed herein relate to power converter circuits employing GaN power switches, wherein a shutdown circuit can be used to control and optimize the shutdown of the GaN power switch, thereby improving the electromagnetic interference (EMI) performance of the power converter. In some embodiments, the shutdown circuit can control potentially present excessive ringing when an external silicon controller gate driver is used to drive the GaN power switch. In various embodiments, the shutdown circuit can reduce the high rate of change of the drain voltage of the GaN power switch as a function of time (dv / dt) and prevent the GaN power switch from turning on while remaining in the off state. Various embodiments of the invention are described herein, including methods, processes, systems, devices, etc.

[0005] Several illustrative embodiments will now be described with reference to the accompanying drawings, which form part of this specification. The following description provides examples only and is not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the subsequent description of the embodiments will provide those skilled in the art with an enabling description for implementing one or more embodiments. It should be understood that various changes can be made to the function and arrangement of elements without departing from the spirit and scope of this disclosure. In the following description, specific details are set forth for purposes of explanation in order to provide a thorough understanding of certain embodiments of the invention. However, it will be apparent, however, that various embodiments may be practiced without these specific details. The drawings and description are not limiting. The words “example” or “exemplary” are used herein to mean “serves as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” or “example” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0006] Figure 1 An illustrative representation of a power converter circuit according to some embodiments of the present disclosure is depicted, such as an AC-DC flyback power converter circuit 100. Figure 1As shown, the AC-DC flyback power converter circuit 100 may include a GaN power transistor 102. The AC-DC converter may further include an input circuit 108, a transformer 110, and an output circuit 112. The input circuit 108 may regulate a universal input voltage and feed it to the primary side of the transformer 110. The converter circuit 100 may also include a controller IC 114 that drives the GaN power transistor 102. The controller IC 114 may provide a gate drive voltage to the gate 106 of the GaN power transistor 102. In some embodiments, a turn-off circuit 104 may control the turn-off behavior of the GaN power transistor 102. When the GaN transistor 102 is turned off, the turn-off circuit 104 may be used to reduce excessive ringing in the drain-source current of the GaN power transistor 102, thereby improving the EMI performance of the power converter circuit 100. The turn-off speed of the GaN power transistor is much faster than that of the silicon power transistor; therefore, without proper control of the GaN power transistor, the rapid turn-off of the GaN power transistor can lead to excessive ringing due to the parasitic inductance inherent in the circuit board. The controller IC 114 can provide a pull-down (PD) voltage to the shutdown circuit 104 at node 118, which the shutdown circuit 104 can use to control the gate voltage of the GaN power transistor 102. In various embodiments, the shutdown circuit 104 can be formed in the same die as the GaN power transistor 102, while in other embodiments, the shutdown circuit can be formed as a portion of the same die as the controller IC 114. In some embodiments, the controller IC 114 can be formed in a silicon substrate.

[0007] To better understand the features and aspects of the shutdown circuit according to this disclosure, further text of this disclosure is provided in the following sections by discussing a particular implementation of the shutdown circuit according to embodiments of this disclosure. These embodiments are by way of example only, and other embodiments can be used in other power converter circuits, such as, but not limited to, DC-DC power converters employing GaN power devices.

[0008] Now refer to Figure 2A more detailed view of the shutdown circuit 104 of the power converter circuit 100 is shown. The shutdown circuit 104 may include three segments: a first segment 240, which includes a transistor 202 that can be connected between the gate 106 of the GaN power transistor 102 and ground; a second segment 208, which includes transistor 204 and a diode-connected transistor 206, wherein transistors 204 and 206 can be arranged in a cascode configuration; and a third segment 242, which may include a pull-down transistor 214 and its gate drive circuitry 210. This three-segment configuration of the shutdown circuit can mitigate EMI emissions during the shutdown of the GaN power transistor 102 without sacrificing performance or significantly increasing die size. In some embodiments, when the pull-down signal 118 (PD_GaN) goes high, the first segment transistor 202 can be turned on, providing a constant discharge of the gate 106 of the GaN power transistor 102. When the PD_GaN signal goes high, the second segment transistor 204 can also be turned on. Transistor 204 can be used for rapid discharge of the gate voltage of the GaN power transistor 102. Resistor 230 can be used to set the bias point for the operation of transistor 206. During the turn-off period of GaN power transistor 102, the voltage on its gate 106 can be pulled down by a second stage to within a threshold voltage above ground. When PD_GaN goes high, the third-stage transistor 214 can also turn on, but due to the presence of resistor 224 (R1) and capacitor 222 (C1), the turn-on of transistor 214 can be delayed by a time constant R1C1. For example, the R1C1 delay can be 10 to 20 ns. With the benefit of this disclosure, those skilled in the art will understand that the delay value can be set to any suitable value. The following... Figure 3 The voltage diagram of gate 106 during the turn-off period is further described below.

[0009] The transistor 214 can be sized such that when the gate 106 of the GaN power transistor 102 is pulled down, the gate 106 is prevented from going high again due to the high rate of change of voltage at the drain of the GaN power transistor 102 as a function of time (dv / dt) (i.e., the drain of the GaN power transistor 102 can rise rapidly and have overshoot). The gate-drain capacitance of the GaN power transistor 102 can couple the drain voltage (which overshoots to the high side) to its gate voltage, causing the gate voltage to go high (from the low state) and turning the GaN power transistor back on. Therefore, the transistor 214 is designed to overcome the gate-drain capacitance of the GaN power transistor 102; for example, the size of the transistor 214 can be designed to be 7% to 10% of the size of the GaN power transistor 102. Appropriate sizing of the transistor 214 allows it to keep the gate of the GaN power transistor 102 in a low state during turn-off. With the benefit of this disclosure, those skilled in the art will understand that any suitable size ratio of GaN power transistor 102 and transistor 214 can be used.

[0010] The R1C1 network (resistor 224 and capacitor 222) connected at the gate of transistor 214 increases the turn-off delay of transistor 214, which can lead to breakdown when the gate 106 of the GaN power transistor is turned on. To address this breakdown, diode-connected transistors 218 and 216 can be connected in parallel with resistor 224 (R1). Transistors 218 and 216 can be used to rapidly discharge the gate of transistor 214, allowing transistor 214 to turn off quickly and thus preventing breakdown. The gate of transistor 216 can be controlled by the signal PD_GaN and has a delay added by resistor 232 (R2) and capacitor 220 (C2). In this way, the R2C2 time delay keeps the voltage at the gate of transistor 216 at the value of the PD_GaN signal. For example, the value of the R2C2 delay can be 20 to 30 ns. With the benefit of this disclosure, those skilled in the art will understand that the delay value can be set to any suitable value.

[0011] Now refer to Figure 3 Figure 300 illustrates an example graph of the gate voltage of a GaN power transistor 102 as a function of time. More specifically, Figure 304 shows the gate voltage of a GaN power transistor 102 with a turn-off circuit connected to its gate, while Figure 302 shows the gate of a GaN power transistor 102 with a single pull-down transistor but no turn-off circuit. In Figure 300, the gate voltage drops from 6 V to 0 V to turn off the transistor 102. As shown in Figure 302, without a turn-off circuit, the gate of the GaN power transistor drops rapidly from a high state to a low state. This can cause ringing of the drain-source current and lead to EMI emissions.

[0012] Figure 304 illustrates three distinct phases when the turn-off circuit 104 is connected to the gate 106 of the GaN power transistor. During the first phase 310, the gate voltage drops rapidly from the on-state voltage 316 to a first intermediate voltage 318. This is caused by the turn-on of transistor 204. This rapid drop minimizes the delay time. During the second phase 312, the gate voltage drops at a slower rate from the first intermediate voltage 318 to a second intermediate voltage 320. By maintaining the gate voltage between the first and second intermediate voltages, this deceleration can lead to a significant reduction in EMI. The slower rate of gate voltage drop in the second phase slows down gate discharge, thereby reducing ripple in the drain-source current of the GaN power transistor. Transistor 202 can be configured to maintain the voltage on gate 106 in a low state between T1 and T2. During the second part 312, the voltage of gate 106 can drop to a threshold voltage value of transistor 206 because transistor 206 is in a diode-connected configuration; for example, the voltage of gate 106 can drop from 6 V to approximately 1.5 V. With the benefit of this disclosure, those skilled in the art will understand that the initial gate voltage and threshold voltage of transistor 206 can be adjusted to any suitable value. In the third part 314, after T2, the dv / dt event has passed, and the gate voltage drops rapidly to a low state and can be held low by pull-down transistor 214. Pull-down transistor 214 prevents the gate of GaN power transistor 102 from going high again, which could be caused by the capacitive coupling of gate 106 to the drain of transistor 102. As previously stated, the third part is controlled by the conduction of pull-down transistor 214 because transistor 214 conducts after the time delay caused by the R1C1 network. The three-stage drop in the gate voltage of the GaN power transistor during turn-off can reduce ringing and improve EMI while keeping switching power losses in power converter 100 low.

[0013] The shutdown circuit can effectively reduce EMI emissions without significantly increasing die size. For example, the size of transistors 206 and 204 can be 20% of the size of transistor 214, and the size of transistor 202 can be 20% of the size of transistor 204. With the benefit of this disclosure, those skilled in the art will understand that the ratio of transistor sizes can be any suitable size. Therefore, the die area of ​​the shutdown circuit can be minimized. Furthermore, the shutdown circuit does not require complex or additional control signals, thus saving die area. Additionally, the die area consumed by the R1C1 network can be minimized; for example, the delay of the R1C1 network can be 10 to 20 ns, which will use small values ​​for resistor R1 and capacitor C1. With the benefit of this disclosure, those skilled in the art will understand that the time delay value of the R1C1 network, as well as the values ​​of resistor R1 and capacitor C1, can be any suitable value. As those skilled in the art will further understand, the shutdown circuit can have fewer or more stages, a shutdown rate, a total shutdown time, and other characteristics that may differ from those described herein.

[0014] Now refer to Figure 4 Figure 400 shows an example graph 400 of the gate voltage and drain current of a GaN power transistor 102 as a function of time. In graph 400, the gate voltage drops from 6 V to 0 V. Figure 404 shows the gate voltage of the GaN power transistor 102 with the turn-off circuit connected to its gate 106, while Figure 402 shows the gate without the turn-off circuit connected. As shown in Figure 402, the gate voltage of the GaN power transistor drops rapidly from high to low. This can cause ringing of its drain current and lead to EMI emissions. With the turn-off circuit connected to the gate 106, Figure 404 shows three distinct segments, as previously shown in... Figure 3 As described in [the text].

[0015] Figure 408 shows the drain current of the GaN power transistor 102 with the shutdown circuit connected to its gate, while Figure 406 shows the drain current of the GaN power transistor 102 without the shutdown circuit connected. It can be seen that the shutdown circuit reduces ringing in the drain current of the GaN power transistor 102. This, in turn, reduces EMI emissions in the frequency range (electromagnetic spectrum) to be protected. After removing most of the ringing, the remaining ringing in the drain current could cause emissions in insignificant frequency ranges.

[0016] Although the power converter 100 (see Figure 1 While described and illustrated as a specific power converter, embodiments of this disclosure are applicable to a variety of power converters. For example, any power conversion device can be used with embodiments of this disclosure. In some cases, embodiments of this disclosure are particularly applicable to AC-DC power converters and / or DC-DC power converters.

[0017] For simplicity, various internal components, such as the control circuit system, bus, memory, storage device, and power converter 100 (see...) Figure 1 Other components are not shown in the figure.

[0018] In the foregoing description, numerous specific details have been described with reference to embodiments of this disclosure, which may vary depending on the implementation. Therefore, the description and drawings are to be considered illustrative rather than restrictive. The unique and exclusive indication of the scope of this disclosure, and the scope of this disclosure as desired by the applicant, is the literal and equivalent scope of the claims published in this application, in the specific form of such claims, including any subsequent corrections. Specific details of particular embodiments may be combined in any suitable manner without departing from the spirit and scope of the embodiments of this disclosure.

[0019] Additionally, spatially relative terms such as “bottom” or “top” may be used to describe the relationship between an element and / or feature and another element and / or feature, as illustrated in the figures, for example. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms are intended to cover different orientations of the device in use and / or operation. For example, if the device in the figures is flipped, then an element described as the “bottom” surface may be oriented “on” other elements or features. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein will be interpreted accordingly.

[0020] The terms “and,” “or,” and “one / or” as used herein can have a variety of meanings, which depend at least in part on the context in which such terms are used. Generally, “or,” when used in a list of associations such as A, B, or C, is intended to mean A, B, and C, used herein in an inclusive sense, and A, B, or C, used herein in an exclusive sense. Furthermore, the term “one or more” as used herein can be used to describe any feature, structure, or characteristic in the singular, or to describe some combination of features, structures, or characteristics. However, it should be noted that this is merely an illustrative example, and the claimed subject matter is not limited to this example. Additionally, the term “at least one,” when used in a list of associations such as A, B, or C, can be interpreted to mean any combination of A, B, and / or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

[0021] Throughout this specification, references to “an example,” “example,” “some examples,” or “exemplary implementation” mean that a particular feature, structure, or characteristic described in conjunction with a feature and / or example may be included in at least one feature and / or example of the claimed subject matter. Therefore, the appearance of the phrases “in one example,” “example,” “some examples,” “some implementations,” or other similar phrases throughout this specification does not necessarily refer to the same feature, example, and / or limitation. Furthermore, a particular feature, structure, or characteristic may be combined in one or more examples and / or features.

[0022] In the foregoing detailed description, numerous specific details have been set forth to provide a thorough understanding of the claimed subject matter. However, those skilled in the art will understand that the claimed subject matter can be practiced without these specific details. In other instances, methods and apparatus known to those of ordinary skill in the art have not been described in detail to avoid obscuring the claimed subject matter. Therefore, the claimed subject matter is not limited to the specific examples disclosed, but rather, such claimed subject matter may also include all aspects falling within the scope of the appended claims and their equivalents.

[0023] The circuits and related technologies disclosed herein generally relate to power conversion devices. More specifically, the circuits, devices, and related technologies disclosed herein relate to power transistor turn-off control circuits. In some embodiments, the turn-off control circuit can be used to control and optimize the turn-off rate of the power transistor, thereby reducing oscillations in the power conversion circuit. In various embodiments, the turn-off control circuit can reduce excessive ringing that may occur when an external gate driver integrated circuit (IC) is used to drive a gallium nitride (GaN) power switch. In some embodiments, the reduction of oscillations and ringing in the power conversion circuit can improve electromagnetic interference (EMI) performance. Various embodiments of the invention are described herein, including methods, processes, systems, devices, etc.

[0024] Several illustrative embodiments will now be described with reference to the accompanying drawings, which form part of this specification. The following description provides examples only and is not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the subsequent description of the embodiments will provide those skilled in the art with an enabling description for implementing one or more embodiments. It should be understood that various changes can be made to the function and arrangement of elements without departing from the spirit and scope of this disclosure. In the following description, specific details are set forth for purposes of explanation in order to provide a thorough understanding of certain embodiments of the invention. However, it will be apparent, however, that various embodiments may be practiced without these specific details. The drawings and description are not limiting. The words “example” or “exemplary” are used herein to mean “serves as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” or “example” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0025] Figure 5 A shutdown control circuit 500 according to an embodiment of the present disclosure is shown. For example... Figure 5 As shown, circuit 500 may include a GaN power transistor 526 having a drain terminal 522, a gate terminal 524, and a source terminal 512. When GaN power transistor 526 is turned off, the drain voltage of the GaN power transistor can rise relatively quickly. Since the drain voltage is coupled to the gate 524 through the parasitic Miller capacitance of GaN power transistor 526, the relatively high rate of change of the drain voltage as a function of time (dv / dt) can cause the GaN power transistor to turn back on. This secondary turn-on is generally undesirable because uncontrolled turn-on of GaN power transistor 526 can cause oscillations and ringing in the power conversion circuit and may damage the GaN power transistor. Furthermore, excessive oscillations and ringing may increase electromagnetic interference (EMI) generation in the power conversion circuit. In some embodiments, the turn-off dv / dt control circuitry can reduce the high dv / dt rate by sensing the voltage at the drain 522 of GaN power transistor 526 and adjusting the gate drive at the gate 524 of GaN power transistor based on the sensed voltage. However, turning off the dv / dt control circuit can improve EMI performance, as described in more detail below.

[0026] In various embodiments, circuit 500 can also be used to control the rate of change of the drain current of the GaN power transistor 526 as a function of time (dI / dt). When controlling dI / dt, circuit 500 controls the drain current switching rate of the GaN power transistor during turn-off. By reducing dI / dt, voltage spikes across the GaN power transistor can be reduced during turn-off, which allows the GaN power transistor to operate within its safe operating region.

[0027] Circuit 500 may include a sensing capacitor 502 connected to the drain 522 of GaN power transistor 526. Capacitor 502 may have a capacitance of C. During the dv / dt event, a current I = C x dv / dt can be generated through capacitor 502. This current can be fed into a current mirror circuit 540 formed by transistors 532 and 534. The current I can be mirrored into transistor 534 and can be drawn from V... ddA current 506 flows through resistor 550, causing the voltage at node 552 to drop. The voltage at node 552 can be fed into logic circuitry 516 at node 530. Logic circuitry 516 can use the signal from node 552 to drive the gate 515 of the first pull-down transistor 514 and the gate 511 of the second pull-down transistor 510. The first pull-down transistor 514 and the second pull-down transistor 510 can be used to turn off GaN power transistor 526. When transistors 514 and 510 are on, the gate 524 of GaN power transistor 526 can enter a low state. Transistor 510 can be 5 to 10 times larger than transistor 514, therefore transistor 510 can pull down its gate 524 at a faster rate than transistor 514. With the benefit of this disclosure, those skilled in the art will understand that the transistor size ratio can be set to any suitable value appropriate for a particular application.

[0028] Initially, both transistors 514 and 510 are turned on so that GaN power transistor 526 is turned off when the pulse width modulation (PWM) input signal goes low. The drain voltage of GaN power transistor 526 can then begin to rise. When sensing circuit 519 detects the voltage rise at drain 522, it can indicate that the voltage at gate 524 of GaN power transistor 526 has reached the Miller plateau. This... Figure 6 The timing diagram 600 further illustrates this.

[0029] Figure 6Timing diagram 600 shows the gate and drain voltages of GaN power transistor 526 as a function of time 602. Diagram 608 shows the voltage at the gate of GaN power transistor 526, and diagram 604 shows the voltage at the drain of GaN power transistor 526. Initially, the gate voltage starts high. When both transistors 510 and 514 are turned on, the gate voltage of GaN power transistor 526 decreases at a relatively fast rate, as shown in region 610. During region 610, the gate voltage drops rapidly from the on-state voltage 608 to a first intermediate voltage 620. This rapid decrease minimizes the delay time. During region 612, the gate voltage decreases at a slower rate from the first intermediate voltage 620 to a second intermediate voltage 622. By maintaining the gate voltage between the first and second intermediate voltages, this deceleration can lead to a significant reduction in EMI. The slower rate of gate voltage decrease in the second part slows down gate discharge, thereby reducing ripple in the drain-source current of GaN power transistor 526. In region 612, the gate voltage has reached the Miller plateau. In region 612, sensing circuit 519 detects the drain dv / dt and causes logic circuit 516 to turn off transistor 510 while keeping transistor 514 on. When the dv / dt event ends, the gate voltage of the GaN power transistor begins to drop again, as indicated by region 614. After region 614, logic circuit 516 can detect that the gate voltage has dropped below the threshold voltage, causing transistor 510 to turn on again. In this way, the rate of decrease of the gate voltage of the GaN power transistor can be slowed. Furthermore, logic circuit 516 can sense the gate voltage of the GaN power transistor at node 518. When logic circuit 516 detects that the gate voltage of GaN power transistor 526 has dropped below the threshold voltage, logic circuit 516 can turn on transistor 510. By keeping both transistors 514 and 510 in the ON state and simultaneously providing a pull-down to the gate of the GaN power transistor, circuit 500 can keep GaN power transistor 526 in the OFF state so that it will not turn on again if a dv / dt event occurs. When the GaN power transistor is off, keeping both transistors 514 and 510 in the ON state improves the circuit's dv / dt immunity.

[0030] Figure 7 An embodiment of the present disclosure is shown with reference to operation. Figure 5The steps associated with the method 700 for the transistor turn-off dv / dt control circuit 500 shown are as follows: In step 710, the pulse width modulation (PWM) input signal goes low, indicating that the GaN power transistor 526 can be turned off. In step 720, the fast pull-down transistor and the slow pull-down transistor can be turned on. As shown in circuit 500, the GaN power transistor 526 can be turned off by turning on transistor 510 (fast pull-down) and transistor 514 (slow pull-down). In step 730, the circuit can detect the start of the dv / dt transition. As shown in circuit 500, the sensing capacitor 502 detects the start of the dv / dt transition when the voltage at the drain 522 of the GaN power transistor begins to rise. In step 740, the circuit can detect that the gate of the power transistor transitions to a voltage below a threshold voltage. As shown in circuit 500, the fast pull-down transistor 510 can be turned off while the slow pull-down transistor 514 remains on. When the dv / dt event has completed and the gate voltage of the GaN power transistor has dropped below the threshold voltage, logic circuit 516 can detect the low state of the gate voltage. In step 760, the circuit can turn on the fast pull-down transistor and keep the slow pull-down transistor on. As shown in circuit 500, logic circuit 516 turns on the fast pull-down transistor 510 while keeping the slow pull-down transistor 514 on. It should be understood that process 700 is illustrative and variations and modifications are possible. Steps described as sequential can be executed in parallel, the order of steps can be changed, and steps can be modified, combined, added, or omitted.

[0031] Figure 8 A shutdown control circuit 800 according to an embodiment of the present disclosure is shown. Circuit 800 is similar to... Figure 5 The circuit 500 shown differs in that the current mirror 540 in circuit 500 has been replaced by a resistor 844 and a transistor 834. (As shown...) Figure 8 As shown, when the sensing capacitor 502, which can be connected to the drain 522 of the GaN power transistor 526, detects a dv / dt event at the drain 522, it generates a current I = C x dv / dt. This current can be fed into resistor 844, generating a voltage across resistor 844, causing a voltage rise at node 855. Node 855 is connected to the gate 854 of transistor 834. The voltage rise at the gate 854 of transistor 834 causes transistor 834 to turn on. Since the drain 851 of transistor 834 is connected to resistor 850, the current flowing through resistor 850 causes the voltage at node 857 to drop.

[0032] Node 857 can be connected to logic circuitry 516, which controls transistors 514 and 510. When node 857 goes low, indicating that a dv / dt event has occurred, logic circuitry 516 can turn off transistor 510 (fast pull-down) while simultaneously turning on transistor 514 (slow pull-down). Transistors 514 and 510 can be used to pull down the gate 524 of the GaN power transistor 526. When transistors 514 and 510 are on, the gate 524 of the GaN power transistor 526 can go low. Transistor 510 can be 5 to 10 times larger than transistor 514, so that transistor 510 can pull down its gate 524 at a faster rate than transistor 514. With the benefit of this disclosure, those skilled in the art will understand that the transistor size ratio can be set to any suitable value appropriate for a particular application.

[0033] Initially, both transistors 514 and 510 are turned on to turn off the GaN power transistor 526. Sensing circuit 519 can indicate that the voltage at gate 524 has reached the Miller plateau by detecting a voltage rise at drain 522. This... Figure 9 The timing diagram 900 further illustrates this. Figure 900 shows the gate and drain voltages of the GaN power transistor 526 as a function of time 902. Figure 908 shows the voltage at the gate of the GaN power transistor 526, and Figure 904 shows the voltage at the drain of the GaN power transistor. Initially, the gate voltage begins to be high. When both transistors 510 and 514 are turned on, the gate voltage of the GaN power transistor 526 decreases at a relatively rapid rate, as shown in region 910. In region 912, the gate voltage reaches the Miller plateau.

[0034] During region 910, the gate voltage drops rapidly from the on-state voltage 908 to the first intermediate voltage 920. This rapid drop minimizes the delay time. During region 912, the gate voltage drops at a slower rate from the first intermediate voltage 920 to the second intermediate voltage 922. By maintaining the gate voltage between the first and second intermediate voltages, this deceleration can lead to a significant reduction in EMI. The slower rate of gate voltage drop in the second part slows down gate discharge, thereby reducing ripple in the drain-source current of the GaN power transistor 526. In region 912, the sensing circuit 519 detects the drain dv / dt and causes the logic circuit 516 to turn off transistor 510 while keeping transistor 514 on. When the dv / dt event ends, the gate voltage of the GaN power transistor begins to drop again, as indicated by region 914. After region 914, the logic circuit 516 can detect that the gate voltage has dropped below a threshold, causing transistor 510 to turn on again. In this way, the rate of gate voltage drop of the GaN power transistor can be slowed down. Furthermore, logic circuit 516 can sense the gate voltage of the GaN power transistor at node 518. When logic circuit 516 detects that the gate voltage of GaN power transistor 526 has dropped below a threshold, logic circuit 516 can turn on transistor 510. By keeping both transistors 514 and 510 in the on state and providing a pull-down on the gate of the GaN power transistor, circuit 900 can keep GaN power transistor 526 in the off state even if subsequent dv / dt events occur. When the GaN power transistor is off, keeping both transistors 514 and 510 in the on state improves the circuit's dv / dt immunity.

[0035] Figure 10 A shutdown control circuit 1000 according to an embodiment of the present disclosure is shown. Circuit 1000 is similar to circuit 800, but with the addition of a capacitor 1017, which can be connected between the gate 524 and drain 522 of the GaN power transistor 526. Capacitor 1017 can further reduce the dv / dt conversion rate. More specifically, during the period when the fast pull-down transistor 510 is turned off and the slow pull-down transistor 514 is turned on (i.e., Figure 9 In region 912), capacitor 1017 can provide a boost to the gate-source voltage (Vgs) of the GaN power transistor 526. gs This boost can reduce the dv / dt conversion rate by increasing the drive voltage supplied to the gate of the GaN power transistor 526. Those skilled in the art will understand that the capacitor 1017 can be formed of various suitable materials and layers, for example, but not limited to, a transistor capacitor or a metal-dielectric-metal capacitor.

[0036] Although this document describes and illustrates a transistor turn-off dv / dt control circuit for a specific configuration of GaN power transistors, embodiments of this disclosure are applicable to other configurations of GaN and non-GaN transistors, such as silicon, silicon carbide, or other semiconductor devices. For example, any semiconductor transistor can be used in embodiments of this disclosure.

[0037] Some exemplary aspects of this disclosure are described below.

[0038] Aspect 1. A circuit comprising: A transistor, the transistor including a gate terminal for controlling the operation of the transistor; and A control circuit coupled to the gate terminal and arranged to change the voltage at the gate terminal from a first voltage to a first intermediate voltage at a first voltage rate relative to time, and to change the voltage at the gate terminal from the first intermediate voltage to a second intermediate voltage at a second voltage rate relative to time, wherein the first rate is different from the second rate.

[0039] Aspect 2. The circuit according to aspect 1, wherein the control circuit is further arranged to change the voltage at the gate terminal from the second intermediate voltage to the second voltage at a third voltage rate relative to time.

[0040] Aspect 3. The circuit according to aspect 2, wherein the first voltage is a turn-on voltage of the transistor that allows current to flow through the transistor, and the second voltage is a turn-off voltage of the transistor that prevents current from flowing through the transistor.

[0041] Aspect 4. A method for controlling the rate of change of voltage (dv / dt) as a function of time of a transistor, comprising: A circuit is provided having a first transistor and a second transistor, wherein the first transistor and the second transistor are arranged to control the gate voltage of a power transistor; The voltage at the drain and gate of the power transistor is sensed; When a rate of change of voltage as a function of time (dv / dt) is detected at the drain of the power transistor, the first transistor is turned off while the second transistor remains on; and When the voltage at the gate of the power transistor is lower than a threshold, the first transistor is turned on and the second transistor remains on.

[0042] Aspect 5. A power converter comprising: Gallium nitride (GaN) transistors; and Turn off the circuit; The shutdown circuit is configured to control the gate voltage of the GaN transistor during the GaN transistor's shutdown period.

[0043] In the foregoing description, numerous specific details have been described with reference to embodiments of this disclosure, which may vary depending on the implementation. Therefore, the description and drawings are to be considered illustrative rather than restrictive. The unique and exclusive indication of the scope of this disclosure, and the scope of this disclosure as desired by the applicant, is the literal and equivalent scope of the claims published in this application, in the specific form of such claims, including any subsequent corrections. Specific details of particular embodiments may be combined in any suitable manner without departing from the spirit and scope of the embodiments of this disclosure.

[0044] Additionally, spatially relative terms such as “bottom” or “top” may be used to describe the relationship between an element and / or feature and another element and / or feature, as illustrated in the figures, for example. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms are intended to cover different orientations of the device in use and / or operation. For example, if the device in the figures is flipped, then an element described as the “bottom” surface may be oriented “on” other elements or features. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein will be interpreted accordingly.

[0045] The terms “and,” “or,” and “one / or” as used herein can have a variety of meanings, which depend at least in part on the context in which such terms are used. Generally, “or,” when used in a list of associations such as A, B, or C, is intended to mean A, B, and C, used herein in an inclusive sense, and A, B, or C, used herein in an exclusive sense. Furthermore, the term “one or more” as used herein can be used to describe any feature, structure, or characteristic in the singular, or to describe some combination of features, structures, or characteristics. However, it should be noted that this is merely an illustrative example, and the claimed subject matter is not limited to this example. Additionally, the term “at least one,” when used in a list of associations such as A, B, or C, can be interpreted to mean any combination of A, B, and / or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

[0046] Throughout this specification, references to “an example,” “example,” “some examples,” or “exemplary implementation” mean that a particular feature, structure, or characteristic described in conjunction with a feature and / or example may be included in at least one feature and / or example of the claimed subject matter. Therefore, the appearance of the phrases “in one example,” “example,” “some examples,” “some implementations,” or other similar phrases throughout this specification does not necessarily refer to the same feature, example, and / or limitation. Furthermore, a particular feature, structure, or characteristic may be combined in one or more examples and / or features.

[0047] In the foregoing detailed description, numerous specific details have been set forth to provide a thorough understanding of the claimed subject matter. However, those skilled in the art will understand that the claimed subject matter can be practiced without these specific details. In other instances, methods and apparatus known to those of ordinary skill in the art have not been described in detail to avoid obscuring the claimed subject matter. Therefore, the claimed subject matter is not limited to the specific examples disclosed, but rather, such claimed subject matter may also include all aspects falling within the scope of the appended claims and their equivalents.

Claims

1. A circuit comprising: A transistor having a gate terminal, a source terminal, and a drain terminal; A control circuit coupled to the gate terminal and arranged to change the conduction state of the transistor; as well as The control circuit is configured to turn off the transistor by changing the voltage at the gate terminal from an on-state voltage to a first intermediate voltage at a first voltage rate relative to time, changing the voltage at the gate terminal from the first intermediate voltage to a second intermediate voltage at a second voltage rate relative to time, and changing the voltage at the second intermediate voltage to an off-state voltage at a third voltage rate relative to time.

2. The circuit according to claim 1, wherein the first rate is faster than the second rate.

3. The circuit according to claim 1, wherein the third rate is faster than the second rate.

4. The circuit of claim 1, wherein the transistor comprises gallium nitride (GaN).

5. The circuit according to claim 1, wherein the control circuit comprises: A first pull-down circuit is connected to the gate terminal; A second pull-down circuit is connected to the gate terminal; as well as A third pull-down circuit is connected to the gate terminal.

6. The circuit of claim 5, wherein the first pull-down circuit comprises a first pull-down transistor.

7. The circuit of claim 6, wherein the second pull-down circuit includes a second pull-down transistor coupled to a diode-connected transistor.

8. The circuit according to claim 7, wherein the third pull-down circuit comprises a third pull-down transistor and logic circuitry.

9. The circuit of claim 8, wherein the logic circuit is coupled to the gate terminal of the third pull-down transistor, and wherein the logic circuit is arranged to control the operation of the third pull-down transistor.

10. A method of operating a circuit, the method comprising: A power transistor is provided, the power transistor having a gate terminal, a source terminal and a drain terminal, the gate terminal being arranged to control the operation of the power transistor; A control circuit is provided, which is coupled to the gate terminal and arranged to change the on-state of the power transistor; as well as A shutdown signal is received at the control circuit, wherein in response to receiving the shutdown signal, the control circuit controls the voltage at the gate terminal such that the voltage at the gate terminal changes from a first voltage to a first intermediate voltage at a first voltage rate relative to time, from the first intermediate voltage to a second intermediate voltage at a second voltage rate relative to time, and from the second intermediate voltage to a second voltage at a third voltage rate relative to time.

11. The method of claim 10, wherein the first rate is faster than the second rate, and the third rate is faster than the second rate.

12. The method of claim 10, wherein the first voltage is an on-state voltage of the power transistor that allows current to flow through the power transistor, and the second voltage is an off-state voltage of the power transistor that prevents current from flowing through the power transistor.

13. The method according to claim 12, wherein the control circuit comprises a first pull-down circuit, a second pull-down circuit, and a third pull-down circuit.

14. The method of claim 13, wherein the first pull-down circuit comprises a first pull-down transistor.

15. The method of claim 14, wherein the second pull-down circuit comprises a second pull-down transistor.

16. The method of claim 15, wherein the second pull-down circuit further comprises a diode-connected transistor.

17. A power converter circuit, comprising: A power transistor having a gate terminal, a drain terminal and a source terminal, the gate terminal being arranged to control the operation of the power transistor, and the drain terminal being coupled to a first node of a first winding on the primary side of a transformer; A control circuit, the control circuit being coupled to a first node of the second winding on the primary side of the transformer and coupled to the gate terminal; as well as The control circuit is configured to change the voltage at the gate terminal from a first voltage to a first intermediate voltage at a first voltage rate relative to time, change the voltage at the gate terminal from the first intermediate voltage to a second intermediate voltage at a second voltage rate relative to time, and change the voltage at the gate terminal from the second intermediate voltage to a second voltage at a third voltage rate relative to time.

18. The power converter circuit of claim 17, wherein the first voltage is an on-state voltage of the power transistor that allows current to flow through the power transistor, and the second voltage is an off-state voltage of the power transistor that prevents current from flowing through the power transistor.

19. The power converter circuit of claim 18, wherein the first rate is faster than the second rate, and the third rate is faster than the second rate.

20. The power converter circuit according to claim 19, wherein the control circuit includes a first pull-down circuit, a second pull-down circuit, and a third pull-down circuit.

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