A driving circuit of a synchronous rectification buck circuit, a buck circuit and an aviation power supply

Abstract

The application discloses a driving circuit of a synchronous rectification Buck circuit, a Buck circuit and an aviation power supply. The driving circuit of the synchronous rectification Buck circuit comprises an error signal generation circuit, a first driving branch and a second driving branch. The error signal generation circuit is used for generating an error signal according to an output voltage sampling signal of the Buck circuit. The first driving branch is used for obtaining a first driving signal for driving a first switch tube according to the error signal and a triangular wave. The second driving branch is used for obtaining a second driving signal for driving a second switch tube according to the error signal, a reference voltage and the triangular wave. The first driving signal and the second driving signal have a time difference. The scheme can realize the synchronous rectification of the Buck circuit through a pure analog hardware circuit, and can improve the reliability of the system.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, specifically to a drive circuit for a synchronous rectification Buck circuit, a Buck circuit, and an aviation power supply. Background Technology

[0002] Buck circuits, as a fundamental DC / DC conversion topology, are widely used in voltage conversion applications. Improving conversion efficiency is one of the core objectives of Buck circuits. Synchronous rectification technology, by using metal-oxide-semiconductor field-effect transistors (MOSFETs) instead of traditional freewheeling diodes, significantly reduces conduction losses, thereby improving power conversion efficiency.

[0003] In related technologies, the driving circuit of synchronous rectification Buck circuits is usually implemented using a digital controller combined with software algorithms. This approach has weak anti-interference capabilities and relies on periodic signal sampling and software instruction execution. In environments with strong electromagnetic interference, such as aviation power supplies, the sampled signal is easily affected by noise, making it difficult to meet the requirements of high reliability scenarios. Summary of the Invention

[0004] In view of this, this application provides a driving circuit for a synchronous rectification Buck circuit, a Buck circuit, and an aviation power supply. The synchronous rectification of the Buck circuit is achieved through a purely analog hardware circuit, which can improve the reliability of the system.

[0005] To solve the above problems, the technical solution provided in this application is as follows: In a first aspect of this application, a driving circuit for a synchronous rectification Buck circuit is provided, comprising: an error signal generation circuit, a first driving branch, and a second driving branch; An error signal generation circuit is used to generate an error signal based on the output voltage sampling signal of the Buck circuit. The first drive branch is used to obtain the first drive signal for driving the first switch transistor based on the error signal and the triangular wave. The second drive branch is used to obtain a second drive signal for driving the second switch transistor based on the error signal, the reference voltage, and the triangular wave; there is a time difference between the first drive signal and the second drive signal.

[0006] One possible implementation is that the first driving branch includes: a follower circuit and a first wave transmitting circuit; The input terminal of the follower circuit is connected to the output terminal of the error signal generation circuit, the output terminal of the follower circuit is connected to the first input terminal of the first wave generation circuit, the second input terminal of the first wave generation circuit is connected to the triangular wave, and the output terminal of the first wave generation circuit outputs the first drive signal.

[0007] One possible implementation is that the follower circuit includes a first operational amplifier and a first resistor; The output of the error signal generation circuit is connected to the non-inverting input of the first operational amplifier through a first resistor, and the inverting input of the first operational amplifier is connected to the output of the first operational amplifier; the output of the first operational amplifier outputs the following error signal. The first waveform generating circuit includes a first comparator, a second resistor, and a third resistor; The output of the follower circuit is input to the non-inverting input of the first comparator via the second resistor, and the triangular wave is input to the inverting input of the first comparator via the third resistor; the output of the first comparator outputs the first drive signal.

[0008] One possible implementation is that the second driving branch includes: an in-phase adder circuit and a second wave generator circuit; The two non-inverting inputs of the non-inverting adder circuit are connected to the error signal and the reference voltage, respectively, and the output of the non-inverting adder circuit outputs the summed error signal. The second waveform circuit includes a second comparator, a fourth resistor, and a fifth resistor; The output of the non-inverting adder circuit is input to the inverting input of the second comparator via the fourth resistor, and the triangular wave is input to the non-inverting input of the second comparator via the fifth resistor. The second wave-generating circuit is used to compare the summed error signal with the triangular wave to obtain the second driving signal.

[0009] One possible implementation is that the non-inverting adder circuit includes a second operational amplifier, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor; The output of the error signal generation circuit is connected to the non-inverting input of the second operational amplifier through the sixth resistor, and the reference voltage is connected to the non-inverting input of the second operational amplifier through the seventh resistor. The inverting input terminal of the second operational amplifier is grounded through the eighth resistor, and the inverting input terminal of the second operational amplifier is connected to the output terminal of the second operational amplifier through the ninth resistor. The second operational amplifier outputs an error signal, which is the sum of the error signal and the reference voltage.

[0010] One possible implementation is that the error signal generation circuit includes: a third operational amplifier, a tenth resistor, and a first capacitor; The inverting input of the third operational amplifier is used to receive the output voltage sampling signal of the Buck circuit; the non-inverting input of the third operational amplifier is used to receive the given voltage signal. The inverting input of the third operational amplifier is connected to the output of the third operational amplifier via a series tenth resistor and a first capacitor; The output of the error signal generation circuit is connected to the first drive branch and the second drive branch.

[0011] One possible implementation also includes: a power drive circuit; The power drive circuit receives the first drive signal and the second drive signal, amplifies the power, and then drives the first switch and the second switch, respectively.

[0012] One possible implementation also includes: a triangular wave generating circuit; The triangular wave generator circuit is used to generate a triangular wave, and by adjusting the frequency of the triangular wave, the switching frequency of the synchronous rectifier Buck circuit can be adjusted.

[0013] In a second aspect of this application, a synchronous rectification Buck circuit is provided, comprising: a first switching transistor, a second switching transistor, an inductor, a capacitor, and a driving circuit for the synchronous rectification Buck circuit as described above; The first terminal of the first switching transistor is connected to the first terminal of the voltage source, the second terminal of the first switching transistor is connected to the first terminal of the second switching transistor, the second terminal of the second switching transistor is connected to the second terminal of the voltage source, and the second terminal of the first switching transistor is connected to the first terminal of the capacitor via an inductor, and the second terminal of the capacitor is connected to the second terminal of the voltage source. The driving circuit of the synchronous rectification Buck circuit is used to send a first driving signal and a second driving signal to the first switching transistor and the second switching transistor, respectively.

[0014] In a third aspect of this application, an aviation power supply is provided, comprising: the aforementioned synchronous rectification Buck circuit.

[0015] The synchronous rectification Buck circuit provided in this application includes an error signal generation circuit, a first drive branch, and a second drive branch. The error signal generation circuit generates an error signal based on the output voltage sampling signal of the Buck circuit. The first drive branch generates a first drive signal for driving the first switch transistor based on the error signal and a triangular wave. The second drive branch generates a second drive signal for driving the second switch transistor based on the error signal, a reference voltage, and a triangular wave, thereby achieving separate driving of the first and second switches. Because there is a time difference between the first and second drive signals, simultaneous conduction of the first and second switches can be avoided, preventing shoot-through short circuits and improving the operational reliability of the synchronous rectification Buck circuit. Simultaneously, the introduction of the reference voltage provides an adjustable reference for the generation of the second drive signal, facilitating the setting and adjustment of the time difference between the two drive signals. The drive circuit provided in this application is entirely composed of analog hardware circuits, without a digital controller, and can complete the synchronous rectification control of the Buck circuit without software intervention, thus improving the control reliability of the synchronous rectification Buck circuit. Attached Figure Description

[0016] Figure 1 A schematic diagram of the driving circuit for the first type of synchronous rectification Buck circuit provided in the embodiments of this application; Figure 2 A schematic diagram of the driving circuit for the second type of synchronous rectification Buck circuit provided in the embodiments of this application; Figure 3 A schematic diagram of the driving circuit for the third type of synchronous rectification Buck circuit provided in the embodiments of this application; Figure 4 A waveform diagram of a driving signal provided in an embodiment of this application; Figure 5 A schematic diagram of the driving circuit for the fourth synchronous rectification Buck circuit provided in the embodiments of this application; Figure 6 A schematic diagram of the driving circuit for the fifth synchronous rectification Buck circuit provided in the embodiments of this application; Figure 7 A schematic diagram of the driving circuit for the sixth type of synchronous rectification Buck circuit provided in the embodiments of this application; Figure 8 A schematic diagram of a synchronous rectification Buck circuit provided in an embodiment of this application; Figure 9 A schematic diagram illustrating the operation of the first synchronous rectification Buck circuit provided in the embodiments of this application; Figure 10 A schematic diagram illustrating the operation of the second synchronous rectification Buck circuit provided in the embodiments of this application; Figure 11 This is a schematic diagram of an aviation power supply provided in an embodiment of this application. Detailed Implementation

[0017] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the embodiments of this application will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0018] The embodiments of this application do not specifically limit the application field of the synchronous rectification Buck circuit drive circuit, and can be applied in various occasions where synchronous rectification Buck circuits are required for DC / DC buck conversion. For example, it can be applied in the field of aviation power supplies.

[0019] See Figure 1 The figure is a schematic diagram of the driving circuit of the first synchronous rectification Buck circuit provided in the embodiment of this application.

[0020] The synchronous rectification Buck circuit provided in this application includes an error signal generation circuit 100, a first driving branch 200, and a second driving branch 300.

[0021] Error signal generation circuit 100 is used to generate error signal Uerr based on the output voltage sampling signal Vf of Buck circuit; The first drive branch 200 is used to obtain the first drive signal P1 for driving the first switch transistor based on the error signal Uerr and the triangular wave Tri. The second drive branch 300 is used to obtain the second drive signal P2 for driving the second switch based on the error signal Uerr, the reference voltage Vref and the triangular wave Tri; there is a time difference between the first drive signal P1 and the second drive signal P2.

[0022] The output voltage sampling signal Vf is used to characterize the actual output voltage of the synchronous rectification Buck circuit, and the error signal generation circuit 100 generates an error signal Uerr that reflects the degree of output voltage deviation based on the output voltage sampling signal Vf.

[0023] The first drive branch 200 uses the error signal Uerr as the first comparison threshold and compares the signal with the triangular wave Tri to determine the flipping time of the first drive signal P1. The second drive branch 300 further introduces a reference voltage Vref based on the error signal Uerr, so that the second comparison threshold used by the second drive branch 300 forms a predetermined offset with the first comparison threshold used by the first drive branch 200, and compares the second comparison threshold with the same triangular wave Tri to determine the flipping time of the second drive signal P2.

[0024] Since the first drive branch 200 and the second drive branch 300 use different comparison thresholds, but can share the same triangular wave Tri, when the voltage of the triangular wave Tri rises or falls with time and crosses the two comparison thresholds successively, the state reversals of the first drive signal P1 and the second drive signal P2 occur at different times, thus creating a time difference between the first drive signal P1 and the second drive signal P2. This time difference can be used as the non-overlapping time between the first switch Q1 and the second switch Q2, i.e., the dead time, so that after one switch completes its turn-off, the other switch enters the turn-on state.

[0025] This application does not specifically limit the magnitude of the reference voltage Vref, which can be set according to different operating conditions. The reference voltage Vref is used to determine or adjust the interval between two comparison thresholds. Therefore, the time difference between the first drive signal P1 and the second drive signal P2 can be set by setting the reference voltage Vref and the parameters of the relevant devices in the second drive branch 300.

[0026] When the slope of the rising or falling segment of the triangular wave Tri is approximately constant, the greater the voltage difference between the two comparison thresholds, the longer the time required for the triangular wave Tri to successively cross the two comparison thresholds, and the longer the corresponding non-overlapping time; conversely, the smaller the voltage difference between the two comparison thresholds, the shorter the non-overlapping time. Therefore, the embodiments of this application can form a designable and adjustable dead time in the form of analog voltage quantities without relying on counters, timers, or software delay programs in a digital controller.

[0027] The time difference between the first drive signal P1 and the second drive signal P2 can reduce the possibility that the first and second switching transistors are simultaneously in the conducting state during the commutation process, thereby reducing the risk of the first and second switching transistors forming a direct current path, reducing the electrical and thermal stresses generated by the switching devices due to instantaneous large currents, and improving the operational reliability of the synchronous rectification Buck circuit.

[0028] The first drive branch 200 and the second drive branch 300 use the same triangular wave Tri as the comparison reference, which helps to reduce the frequency error or phase drift caused by the use of different carrier sources in the two drive branches. The relative timing of the two drive signals is mainly determined by the difference between the comparison thresholds, which makes it easier to design and calibrate the dead time.

[0029] In applications such as aviation power supplies where reliability and timing determinism are critical, the aforementioned pure analog hardware control method can also reduce dependence on the digital controller software state, sampling clock, and program execution state, which helps improve the predictability of the control link.

[0030] The synchronous rectification Buck circuit provided in this application includes an error signal generation circuit, a first drive branch, and a second drive branch. The error signal generation circuit generates an error signal based on the output voltage sampling signal of the Buck circuit. The first drive branch generates a first drive signal for driving the first switch transistor based on the error signal and a triangular wave. The second drive branch generates a second drive signal for driving the second switch transistor based on the error signal, a reference voltage, and a triangular wave, thereby achieving separate driving of the first and second switches. Because there is a time difference between the first and second drive signals, simultaneous conduction of the first and second switches can be avoided, preventing shoot-through short circuits and improving the operational reliability of the synchronous rectification Buck circuit. Simultaneously, the introduction of the reference voltage provides an adjustable reference for the generation of the second drive signal, facilitating the setting and adjustment of the time difference between the two drive signals. The drive circuit provided in this application is entirely composed of analog hardware circuits, without a digital controller, and can complete the synchronous rectification control of the Buck circuit without software intervention, thus improving the control reliability of the synchronous rectification Buck circuit.

[0031] To reduce signal interference in the first driving branch, the first driving branch provided in this application embodiment includes a follower circuit and a first wave transmitting circuit, which will be described in detail below with reference to the accompanying drawings.

[0032] See Figure 2 The figure is a schematic diagram of the driving circuit of the second synchronous rectification Buck circuit provided in the embodiment of this application.

[0033] The first driving branch 200 of the driving circuit provided in this application embodiment includes a follower circuit 201 and a first wave generation circuit 202; The input terminal of the follower circuit 201 is connected to the output terminal of the error signal generation circuit 100, the output terminal of the follower circuit is connected to the first input terminal of the first wave generation circuit 202, and the second input terminal of the first wave generation circuit 202 is connected to the triangular wave Tri; the output terminal of the first wave generation circuit 202 outputs the first driving signal.

[0034] The error signal generation circuit 100 generates an error signal Uerr based on the output voltage sampling signal Vf of the Buck circuit, and outputs the error signal Uerr to the first drive branch 200.

[0035] The follower circuit 201 in the first drive branch 200 receives the error signal Uerr, performs impedance transformation, and then sends it to the first wave transmitting circuit 202. The first wave transmitting circuit 202 compares the received signal with the triangular wave Tri, and outputs the first drive signal P1 according to the comparison result to drive the first switch Q1 to turn on or off.

[0036] The first driving branch of the driving circuit provided in this application embodiment adopts a two-stage structure of a follower circuit and a first wave generating circuit, which can isolate and impedance match the error signal generation circuit with the subsequent comparison circuit, avoid the subsequent circuit from affecting the output of the error signal generation circuit, and improve the stability and reliability of the driving circuit.

[0037] The following continues with the appendix. Figure 2 This paper introduces a specific possible implementation of the first driving branch.

[0038] The follower circuit 201 of the driving circuit provided in this application embodiment includes a first operational amplifier U1 and a first resistor R1; The output of the error signal generation circuit 100 is connected to the non-inverting input of the first operational amplifier U1 through the first resistor R1, and the inverting input of the first operational amplifier U1 is connected to the output of the first operational amplifier U1; the output of the first operational amplifier U1 outputs the following error signal Uerr1.

[0039] The first waveform generating circuit 202 includes a first comparator A1, a second resistor R2, and a third resistor R3; The output of the follower circuit 201 is input to the non-inverting input of the first comparator A1 via the second resistor R2, and the triangular wave Tri is input to the inverting input of the first comparator A1 via the third resistor R3; the output of the first comparator A1 outputs the first drive signal P1.

[0040] The first operational amplifier U1 and the direct connection between its inverting input and the output constitute a voltage follower, which is used to perform impedance transformation on the error signal Uerr to obtain the followed error signal Uerr1, making the followed error signal Uerr1 basically equal to the error signal Uerr. At the same time, it improves the load capacity and avoids the subsequent circuit from affecting the error signal generation circuit 100.

[0041] The first operational amplifier U1 buffers the error signal Uerr, reducing signal interference between the first drive branch 200 and the second drive branch 300 when the second drive branch 300 acquires the error signal Uerr.

[0042] The first comparator A1 compares the following error signal Uerr1 with the triangular wave Tri in real time. When the following error signal Uerr1 is higher than the triangular wave Tri, the first comparator A1 outputs a high level, and the first drive signal P1 is active, driving the first switch to turn on. When the triangular wave Tri is higher than the following error signal Uerr1, the first comparator A1 outputs a low level, the first drive signal P1 is inactive, and the first switch is off. Thus, as the triangular wave Tri changes periodically, a first drive signal P1 with a pulse width that varies with the following error signal Uerr1 is formed.

[0043] Therefore, the position of the error signal Uerr1 following the wave within the amplitude range of the triangular wave Tri can determine the intersection point of the triangular wave Tri and the error signal Uerr1 following the wave, and thus determine the pulse width of the first driving signal P1.

[0044] The first resistor R1 can provide a certain electrical isolation between the error signal generation circuit 100 and the first operational amplifier U1 and limit abnormal transient current; the second resistor R2 and the third resistor R3 are located in the two input paths of the first comparator A1, respectively, and can be used for input current limiting, impedance configuration and reducing transient impact at the input of the comparator.

[0045] The embodiments of this application do not specifically limit the values ​​of the first resistor R1, the second resistor R2, and the third resistor R3, nor do they specifically limit the model of the first operational amplifier U1 and the first comparator A1. They can be selected according to the input characteristics of the operational amplifier, the input characteristics of the comparator, and the control accuracy requirements.

[0046] The first driving branch of the driving circuit provided in this application embodiment only uses one operational amplifier, one comparator and three resistors to realize the tracking of the error signal and the generation of the first driving signal. It has a simple structure, low cost and high reliability, and is completely implemented by analog hardware circuit, which is beneficial to improving the response speed and control accuracy of the synchronous rectification Buck circuit.

[0047] The following is combined with Figure 3 ,exist Figure 2 Based on the first driving branch shown, we will further introduce the possible implementation methods of the second driving branch.

[0048] See Figure 3 The figure is a schematic diagram of the driving circuit of the third synchronous rectification Buck circuit provided in the embodiment of this application.

[0049] The second driving branch 300 of the driving circuit provided in this application embodiment includes an in-phase adder circuit 301 and a second wave generator circuit 302.

[0050] The two non-inverting input terminals of the non-inverting adder circuit 301 are connected to the error signal Uerr and the reference voltage Vref, respectively, and the output terminal of the non-inverting adder circuit 301 outputs the summed error signal Uerr2; The second wave transmitting circuit 302 includes a second comparator A2, a fourth resistor R4, and a fifth resistor R5; The output of the non-inverting adder circuit 301 is input to the inverting input of the second comparator A2 via the fourth resistor R4, and the triangular wave Tri is input to the non-inverting input of the second comparator A2 via the fifth resistor R5. The second wave transmitting circuit 302 is used to compare the summed error signal Uerr2 with the triangular wave Tri to obtain the second driving signal P2.

[0051] The error signal Uerr output by the error signal generation circuit 100 is input to one non-inverting input of the non-inverting adder circuit 301, and the reference voltage Vref is input to the other non-inverting input of the non-inverting adder circuit 301. The non-inverting adder circuit 301 performs a non-inverting addition operation on the error signal Uerr and the reference voltage Vref, and outputs the summed error signal Uerr2.

[0052] The summed error signal Uerr2 is input to the inverting input of the second comparator A2 via the fourth resistor R4, and the triangular wave Tri is input to the non-inverting input of the second comparator A2 via the fifth resistor R5. The second comparator A2 compares the triangular wave Tri with the summed error signal Uerr2: when the triangular wave Tri is greater than the summed error signal Uerr2, the second comparator A2 outputs a high level, the second drive signal P2 is active, and the second switch is turned on; when the triangular wave Tri is less than the summed error signal Uerr2, the second comparator A2 outputs a low level, the second drive signal P2 is inactive, and the second switch is turned off.

[0053] Since the summed error signal Uerr2 is greater than the following error signal Uerr1 generated by the first drive branch 200, there is a time difference between the effective level range of the second drive signal P2 and the effective level range of the first drive signal P1, i.e., the dead time.

[0054] The dead time is determined by the difference between the summed error signal Uerr2 and the following error signal Uerr1. By adjusting the reference voltage Vref and the parameters of the in-phase adder circuit 301, the difference between the summed error signal Uerr2 and the following error signal Uerr1 can be adjusted, thereby adjusting the dead time and preventing the first and second switches from being turned on simultaneously, which would cause a shoot-through short circuit.

[0055] The fourth resistor R4 and the fifth resistor R5 are used to limit the current and match the input impedance of the summed error signal Uerr2 and the triangular wave Tri, respectively, to improve the stability of the second comparator A2.

[0056] In the first wave generation circuit 202, the following error signal Uerr1 is input to the non-inverting input of the first comparator A1, and the triangular wave Tri is input to the inverting input of the first comparator A1; in the second wave generation circuit 302, the summed error signal Uerr2 is input to the inverting input of the second comparator A2, and the triangular wave Tri is input to the non-inverting input of the second comparator A2.

[0057] Thus, the two comparators, using opposite comparison polarities, can form essentially complementary driving logic. Meanwhile, since there is a predetermined threshold difference between the following error signal Uerr1 and the summed error signal Uerr2, the two comparators will not flip at exactly the same time in the same rising or falling segment of the triangular wave Tri, thereby forming a non-overlapping interval between the first driving signal P1 and the second driving signal P2.

[0058] The following is combined with Figure 4The relationship between the first driving signal P1 and the second driving signal P2 generated by the error signal Uerr1 after following, the summed error signal Uerr2, and the triangular wave Tri at the same time is introduced.

[0059] See Figure 4 The figure is a waveform diagram of a driving signal provided in an embodiment of this application.

[0060] The high-level range of the second driving signal P2 corresponds to the range where the triangular wave Tri is higher than the summed error signal Uerr2, and the low-level range of the second driving signal P2 corresponds to the range where the triangular wave Tri is lower than the summed error signal Uerr2.

[0061] At the same time, the first wave transmitting circuit compares the following error signal Uerr1 with the triangular wave Tri. When the following error signal Uerr1 is greater than the triangular wave Tri, the first drive signal P1 is at a high level and the first switch is turned on.

[0062] Since the error signal Uerr1 after following is less than the error signal Uerr2 after addition, the interval where the first driving signal P1 is high corresponds to the interval where the triangular wave Tri is less than the error signal Uerr1 after following, and this interval is included in the interval where the second driving signal P2 is low.

[0063] As the triangular wave Tri gradually rises from a low level, it first crosses the first threshold corresponding to the following error signal Uerr1, and then crosses the second threshold corresponding to the summed error signal Uerr2; the time interval between the two crossing moments forms a commutation dead zone. As the triangular wave Tri gradually falls from a high level, it will also cross two different thresholds in sequence, thus forming a corresponding dead zone in the other commutation direction.

[0064] As the following error signal Uerr1 and the summed error signal Uerr2 slowly rise, the pulse width of the first drive signal P1 and the low-level width of the second drive signal P2 will change accordingly, thereby adjusting the duty cycle of the synchronous rectification Buck circuit.

[0065] The second driving branch of the driving circuit provided in this application embodiment can generate the second driving signal by using only an in-phase adder circuit and a second comparator. It has a simple structure, low cost, high reliability, and is completely implemented by analog hardware circuit, which is beneficial to improving the response speed and control accuracy of the synchronous rectification Buck circuit.

[0066] The following will continue to combine Figure 3 This paper introduces one implementation of the in-phase adder circuit.

[0067] The non-inverting adder circuit 301 of the driving circuit provided in this application embodiment includes a second operational amplifier U2, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9.

[0068] The output of the error signal generation circuit 100 is connected to the non-inverting input of the second operational amplifier U2 through the sixth resistor R6, and the reference voltage Vref is connected to the non-inverting input of the second operational amplifier U2 through the seventh resistor R7. The inverting input terminal of the second operational amplifier U2 is grounded to GND via the eighth resistor R8, and the inverting input terminal of the second operational amplifier U2 is connected to the output terminal of the second operational amplifier U2 via the ninth resistor R9.

[0069] The error signal Uerr output by the error signal generation circuit 100 is input to the non-inverting input of the second operational amplifier U2 via the sixth resistor R6, and the reference voltage Vref is also input to the non-inverting input of the second operational amplifier U2 via the seventh resistor R7.

[0070] The sixth resistor R6 and the seventh resistor R7 form a non-inverting adder input network, which performs a weighted summation of the error signal Uerr and the reference voltage Vref, and obtains the summed voltage signal at the non-inverting input of the second operational amplifier U2.

[0071] The second operational amplifier U2, the eighth resistor R8, and the ninth resistor R9 constitute a non-inverting amplifier circuit. The eighth resistor R8 and the ninth resistor R9 form a feedback network that amplifies the summed signals at the non-inverting input terminals in a non-inverting manner. Finally, the summed error signal Uerr2 is obtained at the output of the second operational amplifier U2. This application does not specifically limit the resistance values ​​of the above resistors; they can be selected according to different operating conditions.

[0072] The reference voltage Vref can be a fixed reference voltage or a reference voltage set according to design requirements. The reference voltage Vref should be able to form the required difference between the comparison thresholds of the two drive branches.

[0073] By reasonably setting the values ​​of the reference voltage Vref, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, and the ninth resistor R9, the magnitude of the summed error signal Uerr2 and its proportional relationship with the error signal Uerr can be flexibly adjusted, so that the summed error signal Uerr2 is greater than the following error signal Uerr1 generated in the first drive branch 200.

[0074] The difference between the two determines the time difference between the first drive signal P1 and the second drive signal P2, which is the dead time between the first switch and the second switch.

[0075] When the local slope of the triangular wave Tri is approximately constant, the dead time is related to the threshold difference between the following error signal Uerr1 and the summed error signal Uerr2, as well as the slope of the triangular wave Tri.

[0076] Therefore, the threshold difference can be adjusted by changing the reference voltage Vref or the resistance ratio of the in-phase adder circuit 301, or the required dead time can be determined by combining the frequency and amplitude parameters of the triangular wave Tri.

[0077] When the dead time is too short, the first and second switching transistors may briefly overlap and conduct due to factors such as device turn-off delay or drive propagation delay. When the dead time is too long, in the implementation using MOSFET as synchronous rectifier switching transistor, the inductor current of the Buck circuit may flow through the body diode or other freewheeling paths for a longer period of time, thereby increasing conduction losses.

[0078] Therefore, by adjusting the dead time using the reference voltage Vref and the in-phase adder circuit 301, a design trade-off can be struck between reducing shoot-through risk and minimizing dead-time loss, which is beneficial for balancing the reliability and conversion efficiency of the synchronous rectification Buck circuit.

[0079] The in-phase adder circuit of the driving circuit provided in this application allows for convenient adjustment of the difference between the added error signal and the following error signal by adjusting the resistance values ​​of each resistor and the reference voltage. This, in turn, adjusts the dead time to adapt to the needs of different switching transistors and operating conditions. This in-phase adder circuit uses only one operational amplifier and several resistors to achieve the addition of the error signal and the reference voltage, as well as in-phase amplification. It features a simple structure, low cost, high reliability, and is entirely implemented using analog hardware circuitry, which is beneficial for improving the response speed and control accuracy of the synchronous rectification Buck circuit.

[0080] exist Figure 3 Based on the embodiments shown, this application further provides possible implementations of the error signal generation circuit, which are described below in conjunction with the appendix. Figure 5 A detailed introduction will be provided.

[0081] See Figure 5 The figure is a schematic diagram of the driving circuit of the fourth synchronous rectification Buck circuit provided in the embodiment of this application.

[0082] The error signal generation circuit 100 of the driving circuit provided in this application embodiment includes a third operational amplifier U3, a tenth resistor R10 and a first capacitor C1.

[0083] The inverting input of the third operational amplifier U3 is used to receive the output voltage sampling signal Vf of the synchronous rectifier Buck circuit, and the non-inverting input of the third operational amplifier U3 is used to receive the given voltage signal Vg. The inverting input of the third operational amplifier U3 is connected to the output of the third operational amplifier U3 via the tenth resistor R10 and the first capacitor C1 connected in series.

[0084] The output of the error signal generation circuit 100 is connected to the first drive branch 200 and the second drive branch 300.

[0085] A given voltage signal Vg is used to characterize the desired output voltage target, and an output voltage sampling signal Vf is used to characterize the actual output voltage of the synchronous rectification Buck circuit. The third operational amplifier U3 amplifies and adjusts the deviation between the given voltage signal Vg and the output voltage sampling signal Vf, and uses the feedback network formed by the tenth resistor R10 and the first capacitor C1 to form a proportional-integral regulation characteristic, thereby generating an error signal Uerr.

[0086] When the output voltage sampling signal Vf is lower than the given voltage signal Vg, the error signal generation circuit 100 can cause the error signal Uerr to change in the direction of increasing energy transfer in the synchronous rectification Buck circuit, thereby adjusting the effective conduction time of the first drive signal P1 formed by the first drive branch 200 to improve the energy obtained on the output side. When the output voltage sampling signal Vf is higher than the given voltage signal Vg, the error signal Uerr changes in the direction of decreasing energy transfer. Through the above closed-loop adjustment, the output voltage sampling signal Vf is made to approach the given voltage signal Vg, achieving stable control of the output voltage of the synchronous rectification Buck circuit.

[0087] The first capacitor C1 enables the error signal generation circuit 100 to have integral regulation capability under low-frequency and DC error conditions, which helps reduce steady-state output voltage deviation. The tenth resistor R10 provides the proportional regulation component and limits the gain of the feedback network at higher frequencies, which helps improve the dynamic response and damping characteristics of the control loop. By properly selecting the tenth resistor R10 and the first capacitor C1, a balance can be struck between steady-state accuracy, response speed, and loop stability.

[0088] The embodiments of this application do not specifically limit the values ​​of the tenth resistor R10 and the first capacitor C1, and can be set according to the input voltage range, output filtering parameters, switching frequency and load dynamic requirements of the synchronous rectification Buck circuit.

[0089] The error signal generation circuit of the drive circuit provided in this application embodiment adopts a continuous-time analog operation method. Once the output voltage deviation changes, it is continuously reflected in the error signal through the operational amplifier and feedback network. This reduces the control delay introduced by digital sampling and software calculation, which is beneficial to improving the timeliness of response to load changes or input voltage variations. At the same time, the proportional-integral feedback network shapes the frequency characteristics of the error signal, which can avoid unnecessarily amplifying high-frequency disturbances proportionally to the drive signal, thus improving the stability of closed-loop control.

[0090] exist Figure 5 Based on the embodiments shown, the embodiments of this application also include a power drive circuit, which will be described below in conjunction with the accompanying drawings. Figure 6 A detailed introduction will be provided.

[0091] See Figure 6 The figure is a schematic diagram of the driving circuit of the fifth synchronous rectification Buck circuit provided in the embodiment of this application.

[0092] The driving circuit provided in this application embodiment also includes a power driving circuit 400, which is used to receive the first driving signal P1 and the second driving signal P2, and after power amplification, drive the first switching transistor and the second switching transistor respectively.

[0093] The first driving signal P1 output by the first wave transmitting circuit 202 and the second driving signal P2 output by the second wave transmitting circuit 302 are respectively input into the power driving circuit 400. The power driving circuit 400 amplifies the power of the first driving signal P1 and the second driving signal P2, and outputs the amplified first driving signal PWM1 and the amplified second driving signal PWM2 respectively.

[0094] The first comparator A1 and the second comparator A2 are mainly used to perform voltage comparison and logic switching. Their output drive current capability is typically designed primarily for signal transmission. The control terminals of the first and second switches in the synchronous rectifier Buck circuit usually have a certain equivalent input capacitance or gate charge. By setting up the power drive circuit 400, the logic signal output by the comparators can be converted into a drive signal with strong charging and discharging capabilities, enabling the control terminals of the first and second switches to complete charging and discharging more quickly.

[0095] The power drive circuit 400 can adopt a dual-channel power drive structure, or it can be composed of two drive channels corresponding to the first switch and the second switch respectively. As long as it can receive the first drive signal P1 and the second drive signal P2, and output PWM1 and PWM2 for driving the corresponding switch.

[0096] The embodiments of this application do not specifically limit the model of the power drive circuit 400. Its specific device form, driving voltage and output current capability can be selected according to the type, gate charge and switching frequency of the first switch and the second switch. In one possible implementation, the power drive circuit 400 can be a half-bridge driver chip.

[0097] The power drive circuit 400 can make the two drive channels have similar propagation delays, so that the relative time difference between the first drive signal P1 and the second drive signal P2 before and after power amplification remains unchanged. As a result, the dead time formed by the reference voltage Vref in the front stage can be transmitted to the actual drive terminals of the first and second switching transistors more accurately, which helps to further reduce the risk of power stage shoot-through.

[0098] The driving circuit provided in this application embodiment also includes a power driving circuit. By increasing the charging and discharging speed of the control terminal of the switching transistor through the power driving circuit, the transition time of the first and second switching transistors in the linear region can be shortened, thereby reducing the voltage and current overlap loss during the switching process. At the same time, it can reduce the output edge slowing or level abnormality caused by excessive load when the comparator directly drives the switching transistor.

[0099] Based on the above embodiments, the driving circuit provided in this application also includes a triangular wave generating circuit, which is described below in conjunction with the appendix. Figure 7 A detailed introduction will be provided.

[0100] See Figure 7 The figure is a schematic diagram of the driving circuit of the sixth synchronous rectification Buck circuit provided in the embodiment of this application.

[0101] The driving circuit provided in this application embodiment also includes a triangular wave generating circuit 500. The triangular wave generating circuit 500 is used to generate a triangular wave Tri, and adjust the switching frequency of the synchronous rectification Buck circuit by adjusting the frequency of the triangular wave Tri.

[0102] The triangular wave generating circuit 500 generates a triangular wave Tri and provides the triangular wave Tri to the first comparator A1 in the first wave generating circuit 202 and the second comparator A2 in the second wave generating circuit 302, respectively. Thus, the first driving branch 200 and the second driving branch 300 use the same triangular wave Tri as the carrier reference.

[0103] The triangular wave generating circuit 500 can adjust the frequency of the first drive signal P1 and the second drive signal P2 by adjusting the frequency of the generated triangular wave Tri, thereby adjusting the switching frequency of the synchronous rectification Buck circuit.

[0104] During operation, each triangular wave cycle corresponds to one comparison and flip process completed by the first comparator A1 and the second comparator A2. Therefore, the frequency of the triangular wave Tri determines the basic switching rhythm of the drive signal.

[0105] When the frequency of the triangular wave Tri is increased, the switching cycle of the synchronous rectification Buck circuit is shortened; when the frequency of the triangular wave Tri is decreased, the switching cycle of the synchronous rectification Buck circuit is lengthened. Therefore, a suitable switching frequency can be selected based on design factors such as the power rating, output ripple, magnetic component size, switching losses, and electromagnetic compatibility of the synchronous rectification Buck circuit. This application does not impose specific limitations on this selection.

[0106] One possible implementation is that, in applications where the switching frequency needs to be changed while maintaining a predetermined dead time, the reference voltage Vref or the resistance parameters of the in-phase adder circuit 301 can be set accordingly based on the specific amplitude and slope of the triangular wave Tri.

[0107] The driving circuit provided in this application embodiment also includes a triangular wave generating circuit. Since the first comparator and the second comparator share the triangular wave generated by the triangular wave generating circuit, it can reduce the frequency deviation and long-term phase drift that may occur when the two drives use independent oscillation sources, which is beneficial to maintaining a stable relative timing between the first driving signal and the second driving signal.

[0108] Based on the synchronous rectification Buck circuit driving circuit provided in the above embodiments, this application also provides a synchronous rectification Buck circuit, which is described below in conjunction with the accompanying drawings. Figure 8 Please provide a detailed explanation.

[0109] See Figure 8 The figure is a schematic diagram of a synchronous rectification Buck circuit provided in an embodiment of this application.

[0110] The synchronous rectification Buck circuit 2000 provided in this application embodiment includes a first switch Q1, a second switch Q2, an inductor L, a capacitor C, and a driving circuit 1000 for the synchronous rectification Buck circuit described in any of the above embodiments.

[0111] The first terminal of the first switch Q1 is connected to the first terminal of the voltage source Vs, and the second terminal of the first switch Q1 is connected to the first terminal of the second switch Q2. The second terminal of the second switch Q2 is connected to the second terminal of the voltage source Vs. The second terminal of the first switch Q1 is connected to the first terminal of the capacitor C via the inductor L, and the second terminal of the capacitor C is connected to the second terminal of the voltage source Vs. The two ends of the capacitor C form the output terminal of the synchronous rectification Buck circuit 2000.

[0112] The synchronous rectification Buck circuit driver circuit 1000 is used to provide amplified first drive signal PWM1 and amplified second drive signal PWM2 to the first switch Q1 and the second switch Q2, respectively.

[0113] The embodiments of this application do not specifically limit the model of the first switch Q1 and the second switch Q2. For example, a fully controllable semiconductor device suitable for high-frequency switching, such as a MOSFET, can be used. When using a MOSFET, the inherent body diode of the device can provide a short-time continuous current path for the inductor current during the commutation dead zone.

[0114] The following is in conjunction with the appendix Figure 9 and attached Figure 10 This section introduces the operation of the synchronous rectification Buck circuit.

[0115] See Figure 9 The figure is a schematic diagram of the operation of the first synchronous rectification Buck circuit provided in the embodiment of this application.

[0116] like Figure 9 As shown, when the first switch Q1 is turned on and the second switch Q2 is turned off, the voltage source Vs transfers energy to the inductor L, capacitor C and load through the first switch Q1, and the current in the inductor L can rise and store energy.

[0117] See Figure 10 The figure is a schematic diagram of the operation of the second synchronous rectification Buck circuit provided in the embodiment of this application.

[0118] like Figure 10 As shown, when the first switch Q1 is turned off and the second switch Q2 is turned on, the current in the inductor L forms a synchronous freewheeling path through the second switch Q2, and the inductor L releases the stored energy and continues to supply power to the output side.

[0119] By having the first switch Q1 and the second switch Q2 work alternately in the manner described above, the input DC voltage can be stepped down.

[0120] The inductor L is used to suppress the voltage pulse of the switching node from directly acting on the load and to make the output current more continuous. The capacitor C is used to filter the output voltage and to provide or absorb some transient energy when the load changes.

[0121] The synchronous rectification Buck circuit driver circuit 1000 adjusts the error signal Uerr according to the voltage sampling signal at the output terminal where capacitor C is located, thereby forming the drive signal to drive the two switching transistors.

[0122] The embodiments of this application do not specifically limit the method of obtaining the voltage sampling signal. It can be selected according to different operating conditions. One possible implementation is to obtain the voltage sampling signal through a voltage sampling circuit.

[0123] The synchronous rectification Buck circuit provided in this application is composed entirely of analog hardware circuits and does not contain a digital controller. It can complete the synchronous rectification control of the Buck circuit without the need for software intervention, which can improve the control reliability of the synchronous rectification Buck circuit.

[0124] Based on the synchronous rectification Buck circuit provided in the above embodiments, this application also provides an aviation power supply, which is described below in conjunction with the appendix. Figure 11 A detailed introduction will be provided.

[0125] See Figure 11 The figure is a schematic diagram of an aviation power supply provided in an embodiment of this application.

[0126] The aviation power supply 3000 provided in this application embodiment includes the synchronous rectification Buck circuit 2000 described in the above embodiment.

[0127] The synchronous rectifier Buck circuit 2000 can be used as a first-stage DC-DC step-down converter unit in the aviation power supply 3000 to convert the DC bus voltage of the front stage to the DC voltage required by the load of the rear stage.

[0128] The aviation power supply provided in this application typically operates in environments that place high demands on the reliability, dynamic response, and electromagnetic compatibility of the power conversion device. This application employs analog error adjustment and analog comparison waveform generation to form two drive signals, eliminating the need for a digital controller to periodically execute synchronous rectification control algorithms, thus improving power supply reliability. Even in application environments with strong electromagnetic disturbances, the drive link continues to operate according to pre-set analog circuit relationships, which helps maintain the determinism of the control process.

[0129] The specific component models and parameters of the operational amplifier, comparator, resistor, capacitor, power drive circuit, and triangular wave generator circuit in the embodiments of this application can be selected according to the actual input voltage, output voltage, power level, and switching frequency, as long as they can achieve the above-mentioned functions of error adjustment, threshold offset, comparison wave generation, power amplification, and triangular wave generation. The functional circuits in different embodiments can be implemented using discrete components, or some functions can be integrated into the same analog chip or module; both are feasible forms of the technical concept of this application.

[0130] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0131] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A driving circuit for a synchronous rectified Buck circuit, characterized in that, include: Error signal generation circuit, first drive branch and second drive branch; The error signal generation circuit is used to generate an error signal based on the output voltage sampling signal of the Buck circuit. The first driving branch is used to obtain a first driving signal for driving the first switching transistor based on the error signal and the triangular wave. The second drive branch is used to obtain a second drive signal for driving the second switch transistor based on the error signal, the reference voltage, and the triangular wave. There is a time difference between the first drive signal and the second drive signal.

2. The driving circuit according to claim 1, characterized in that, The first driving branch includes: a follower circuit and a first wave transmitting circuit; The input terminal of the follower circuit is connected to the output terminal of the error signal generation circuit, the output terminal of the follower circuit is connected to the first input terminal of the first wave generating circuit, the second input terminal of the first wave generating circuit is connected to the triangular wave, and the output terminal of the first wave generating circuit outputs the first driving signal.

3. The driving circuit according to claim 2, characterized in that, The follower circuit includes a first operational amplifier and a first resistor; The output terminal of the error signal generation circuit is connected to the non-inverting input of the first operational amplifier through the first resistor, and the inverting input of the first operational amplifier is connected to the output terminal of the first operational amplifier; the output terminal of the first operational amplifier outputs the following error signal. The first waveform transmitting circuit includes a first comparator, a second resistor, and a third resistor; The output of the follower circuit is input to the non-inverting input of the first comparator via the second resistor, and the triangular wave is input to the inverting input of the first comparator via the third resistor; the output of the first comparator outputs the first driving signal.

4. The driving circuit according to claim 1, characterized in that, The second driving branch includes: an in-phase adder circuit and a second wave generation circuit; The two non-inverting input terminals of the non-inverting adder circuit are respectively connected to the error signal and the reference voltage, and the output terminal of the non-inverting adder circuit outputs the summed error signal; The second waveform transmission circuit includes a second comparator, a fourth resistor, and a fifth resistor; The output of the non-inverting adder circuit is input to the inverting input of the second comparator via the fourth resistor, and the triangular wave is input to the non-inverting input of the second comparator via the fifth resistor; The second wave transmitting circuit is used to compare the summed error signal with the triangular wave to obtain the second driving signal.

5. The driving circuit according to claim 4, characterized in that, The non-inverting adder circuit includes a second operational amplifier, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor; The output of the error signal generation circuit is connected to the non-inverting input of the second operational amplifier through the sixth resistor, and the reference voltage is connected to the non-inverting input of the second operational amplifier through the seventh resistor. The inverting input terminal of the second operational amplifier is grounded through the eighth resistor, and the inverting input terminal of the second operational amplifier is connected to the output terminal of the second operational amplifier through the ninth resistor; The second operational amplifier outputs the error signal obtained by adding the error signal to the reference voltage.

6. The driving circuit according to any one of claims 1 to 4, characterized in that, The error signal generation circuit includes: a third operational amplifier, a tenth resistor, and a first capacitor; The inverting input of the third operational amplifier is used to receive the output voltage sampling signal of the Buck circuit; the non-inverting input of the third operational amplifier is used to receive a given voltage signal. The inverting input terminal of the third operational amplifier is connected to the output terminal of the third operational amplifier via the tenth resistor and the first capacitor connected in series. The output of the error signal generation circuit is connected to the first drive branch and the second drive branch.

7. The driving circuit according to any one of claims 1 to 4, characterized in that, Also includes: Power drive circuit; The power drive circuit is used to receive the first drive signal and the second drive signal, and after power amplification, drive the first switch and the second switch respectively.

8. The driving circuit according to any one of claims 1 to 4, characterized in that, Also includes: Triangular wave generator circuit; The triangular wave generating circuit is used to generate the triangular wave and adjust the switching frequency of the synchronous rectification Buck circuit by adjusting the frequency of the triangular wave.

9. A synchronous rectification Buck circuit, characterized in that, include: The first switching transistor, the second switching transistor, the inductor, the capacitor, and the driving circuit of the synchronous rectification Buck circuit according to any one of claims 1 to 8; The first terminal of the first switching transistor is connected to the first terminal of the voltage source, the second terminal of the first switching transistor is connected to the first terminal of the second switching transistor, the second terminal of the second switching transistor is connected to the second terminal of the voltage source, the second terminal of the first switching transistor is connected to the first terminal of the capacitor via the inductor, and the second terminal of the capacitor is connected to the second terminal of the voltage source. The driving circuit of the synchronous rectification Buck circuit is used to send a first driving signal and a second driving signal to the first switch and the second switch, respectively.

10. An aviation power supply, characterized in that, include: The synchronous rectification Buck circuit as described in claim 9.

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