A half-bridge circuit combining e-gan and d-gan

Abstract

The application discloses a kind of E-GaN, D-GaN combined half-bridge circuit.The E-GaN, D-GaN combined half-bridge circuit includes upper and lower bridge drive separation circuit, E-GaN, D-GaN, upper and lower bridge drive separation circuit includes first integrated circuit, second integrated circuit, the output of first integrated circuit is connected with E-GaN, for controlling the working state of upper bridge arm E-GaN, the output of second integrated circuit is connected with D-GaN, for controlling the working state of lower bridge arm;Wherein, when first integrated circuit is connected with second integrated circuit, the input of second integrated circuit is connected with power supply, and second integrated circuit is connected with the input of first integrated circuit;When first integrated circuit is not connected with second integrated circuit, the input of first integrated circuit and second integrated circuit is respectively connected with power supply, and second integrated circuit is connected with negative voltage generation module.By using the mode of half-bridge driver cooperation high side cascade drive to drive, the driving capacity of upper bridge arm can be significantly improved, and the loss in driving process can be effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of half-bridge drive circuit technology, and more particularly to a half-bridge circuit combining E-GaN and D-GaN. Background Technology

[0002] The Buck converter is a simple, highly reliable non-isolated step-down topology widely used in secondary and tertiary power supplies. In practical applications, when the inductor current flows forward to the load, the upper transistor (high-side switch) performs hard switching, while the lower transistor (low-side switch) performs soft switching. In this operating mode, almost all switching losses occur through the upper transistor. Furthermore, in applications supplying final-stage loads, such as xPUs and main controllers, the supply voltage is often very low, such as below 1 volt. This causes the Buck circuit to operate with a low duty cycle during steady-state operation, meaning the lower transistor is on most of the time, while the upper transistor is off. In this case, conduction losses are primarily concentrated in the lower transistor.

[0003] To further improve the overall system efficiency, the switching losses of the upper transistor and the conduction losses of the lower transistor should be optimized. Gallium nitride (GaN) high electron mobility transistors are representative third-generation semiconductor wide-bandgap power devices. Compared with traditional silicon devices, GaN devices are more suitable for fabricating medium-voltage, high-voltage, and high-speed power devices. Applying GaN devices to Buck circuits can significantly increase the system's operating frequency, reduce the need for capacitance and inductance of magnetic components, thereby reducing the size and weight of related components. Therefore, using gallium nitride devices to replace silicon devices in Buck circuits can significantly improve the overall system performance.

[0004] In developing the existing technology, the inventors discovered that the half-bridge structure based on enhancement-mode gallium nitride (E-GaN) devices has gained widespread acceptance and application. Meanwhile, depletion-mode gallium nitride (D-GaN) devices also have two different application schemes: one is the D-GaN direct-drive scheme, which requires generating multiple negative voltages and is relatively complex to implement; the other is the Cascode GaN scheme, i.e., the common-source, common-gate cascaded gallium nitride scheme. Although the Cascode GaN scheme offers certain advantages, external adjustment of the switching speed is difficult, and oscillation problems may occur during application.

[0005] From a device perspective, D-GaN offers lower on-resistance, higher saturation current, superior impedance temperature characteristics, and smaller Coss capacitance compared to E-GaN under the same conditions. These characteristics make D-GaN significantly superior to E-GaN as the bottom-end transistor in Buck converter applications.

[0006] However, it's important to note that depletion-mode devices are essentially "normally on" devices, contrasting with the "normally off" characteristics of enhancement-mode devices. Therefore, when using D-GaN devices in a system, if the external power supply is interrupted or insufficient, the drive circuit will be unable to maintain the D-GaN device in its off state. This can lead to abnormal states such as shoot-through or short circuits in the system. In severe cases, these abnormal states may cause component failure, burnout, or even permanent damage to the system.

[0007] To address the reliability reset issue that may arise during power outages, power failures, or undervoltage conditions in the control section, both D-GaN direct-drive and Cascode GaN solutions typically introduce an enhancement-mode device (e.g., Si-NMOS) connected in series with the D-GaN device to form a composite transistor. This composite transistor combination transforms the overall device characteristics into "normal off-state." However, this approach inevitably leads to an increase in total on-resistance, directly resulting in a loss of operating efficiency. Summary of the Invention

[0008] The main objective of this invention is to provide a half-bridge circuit combining E-GaN and D-GaN, thereby overcoming the shortcomings of existing technologies. To achieve the aforementioned objective, the technical solution adopted by this invention includes:

[0009] This invention provides a half-bridge circuit combining E-GaN and D-GaN, including an upper and lower bridge drive separation circuit, an upper bridge arm E-GaN, and a lower bridge arm D-GaN. The upper and lower bridge drive separation circuit includes a first integrated circuit and a second integrated circuit. The output terminal of the first integrated circuit is connected to the upper bridge arm E-GaN and is used to control the working state of the upper bridge arm E-GaN. The output terminal of the second integrated circuit is connected to the lower bridge arm D-GaN and is used to control the working state of the lower bridge arm.

[0010] Specifically, when the first integrated circuit is connected to the second integrated circuit, the input terminal of the second integrated circuit is connected to a power supply, and the input terminal of the second integrated circuit is connected to the input terminal of the first integrated circuit; when the first integrated circuit and the second integrated circuit are not connected, the input terminals of the first integrated circuit and the second integrated circuit are respectively connected to a power supply, and the second integrated circuit is connected to the negative voltage generating module.

[0011] Generally, the upper and lower bridge arms can be HEMT devices, as well as similar MESFET and JFET devices; the materials are not limited to gallium arsenide (GaAs), indium phosphide (InP), and silicon carbide (SiC) devices. That is, in the Buck circuit, the upper transistor uses a corresponding enhancement-mode device, and the lower transistor uses a corresponding depletion-mode device. GaN devices are the most practical; preferably, the upper bridge arm uses E-GaN, and the lower bridge arm uses D-GaN.

[0012] In some more specific implementations, when the first integrated circuit and the second integrated circuit are connected, the first integrated circuit includes at least a first driving circuit, and the second integrated circuit includes at least a second driving circuit, a level shifting circuit, and a third driving circuit.

[0013] The input terminal of the level shifting circuit is a signal input terminal. The output terminal of the level shifting circuit is connected to the input terminals of the second driving circuit and the third driving circuit, respectively. The output terminal of the second driving circuit is connected to the input terminal of the first driving circuit. The output terminal of the first driving circuit is connected to the upper bridge arm. The output terminal of the third driving circuit is connected to the lower bridge arm. The negative pressure generating module is connected to the third driving circuit.

[0014] Furthermore, the first driving circuit includes a first transistor and a second transistor. The source of the first transistor is connected to HB, which supplies power to the first transistor. The gate of the first transistor and the gate of the second transistor are connected to a first connection point, which is the input terminal of the first driving circuit. The drain of the first transistor and the drain of the second transistor are connected to a second connection point, which is the output terminal of the first driving circuit. The source of the second transistor is connected to VS.

[0015] The second driving circuit includes a third transistor and a fourth transistor. The source of the third transistor is connected to HB, and the gate of the third transistor is connected to the gate of the fourth transistor to a third connection point, which is the input terminal of the second driving circuit. The drain of the third transistor is connected to the drain of the fourth transistor to a fourth connection point, which is the output terminal of the second driving circuit. The source of the fourth transistor is connected to VS.

[0016] The third driving circuit includes a fifth transistor and a sixth transistor. The source of the fifth transistor is connected to a power supply, and the gate of the fifth transistor is connected to the gate of the sixth transistor to a fifth connection point, which is the input terminal of the third driving circuit. The drain of the fifth transistor is connected to the drain of the sixth transistor to a sixth connection point, which is the output terminal of the third driving circuit. The source of the sixth transistor is connected to NEG.

[0017] The level shifting circuit includes at least a first level shifter, a second level shifter, and a third level shifter. The input terminal of the first level shifter is a signal input terminal. The output terminal of the first level shifter is connected to the input terminals of the second level shifter and the third level shifter, respectively. The output terminal of the second level shifter is connected to a third connection point, and the output terminal of the third level shifter is connected to a fifth connection point.

[0018] In some more specific implementation schemes, when the first integrated circuit and the second integrated circuit are not connected, an isolation module is provided in front of the input terminals of the first integrated circuit and the second integrated circuit.

[0019] In some more specific implementations, when the first integrated circuit and the second integrated circuit are not connected, the first integrated circuit includes a seventh transistor and an eighth transistor. The source of the seventh transistor is connected to HB, and HB supplies power to the seventh transistor. The gate of the seventh transistor is connected to the gate of the eighth transistor to a seventh connection point, which is the input terminal of the first integrated circuit. The drain of the seventh transistor is connected to the drain of the eighth transistor to an eighth connection point, which is the output terminal of the first integrated circuit. The source of the eighth transistor is connected to VS.

[0020] Furthermore, the second integrated circuit includes a ninth transistor and a tenth transistor. The source of the ninth transistor is connected to VSS, and the gate of the ninth transistor is connected to the gate of the tenth transistor to a ninth connection point, which is the input terminal of the second integrated circuit. The drain of the ninth transistor is connected to the drain of the tenth transistor to a tenth connection point, which is the output terminal of the second integrated circuit. The source of the tenth transistor is connected to the negative voltage generating module.

[0021] In some more specific implementations, the second integrated circuit includes an eleventh transistor and a twelfth transistor. The source of the eleventh transistor is connected to a power supply, the gate of the eleventh transistor is connected to an isolator, the gate of the twelfth transistor is connected to an isolator, and the drain of the eleventh transistor and the drain of the twelfth transistor are connected to an eleventh connection point, which is the output terminal of the second integrated circuit. The source of the twelfth transistor is connected to a negative voltage generating module.

[0022] In some more specific implementations, the negative pressure generating module includes a negative pressure charge pump circuit, a driving capacitor, a freewheeling capacitor, and a first decoupling capacitor. The negative pressure charge pump circuit includes a thirteenth transistor and a fourteenth transistor.

[0023] The source of the thirteenth transistor is connected to the power supply. The gate of the thirteenth transistor and the gate of the fourteenth transistor are connected to the CP controller. The source of the fourteenth transistor is grounded. The drain of the thirteenth transistor PM7 and the drain of the fourteenth transistor NM7 are connected to the driving capacitor. The driving capacitor is connected to the first anode of the freewheeling circuit. The second anode of the freewheeling circuit is connected to the source of the twelfth transistor. The common cathode is grounded. One end of the first decoupling capacitor is connected to the source of the twelfth transistor, and the other end is grounded.

[0024] In some more specific implementations, the negative pressure generating module includes a buck boost control circuit, a drive inductor, and a second decoupling capacitor. The buck boost control circuit includes a fifteenth transistor and a diode.

[0025] The source of the fifteenth transistor is connected to the power supply, the gate of the fifteenth transistor is connected to the Buck-Boost control circuit, the drain of the fifteenth transistor is connected to the diode, the other end of the diode is connected to the source of the twelfth transistor, the connection point between the drain of the fifteenth transistor and the diode is connected to the driving inductor, the other end of the driving inductor is grounded, one end of the second decoupling capacitor is connected to the source of the twelfth transistor, and the other end is grounded.

[0026] Furthermore, the E-GaN and D-GaN operate in the linear region when in the on state and in the off region when in the off state.

[0027] Compared with the prior art, the advantages of the present invention include at least the following:

[0028] First, in the upper and lower bridge drive separation circuit provided by this invention, the upper bridge arm uses E-GaN and the lower bridge arm uses D-GaN. Compared with E-GaN, D-GaN has lower on-resistance and higher saturation current, which can optimize system efficiency. Furthermore, by using a half-bridge driver in conjunction with a high-side cascaded drive, the driving capability of the upper bridge arm can be significantly improved, while effectively reducing losses during the driving process.

[0029] Secondly, the upper and lower bridge drive separation circuit provided by the present invention adopts the measure of separating the upper and lower drive circuits and configuring them with independent drive power supplies for driving, which can improve the stability, anti-interference ability and safety of the system, and is especially suitable for high voltage, high noise or scenarios with strict reliability requirements. Attached Figure Description

[0030] Figure 1 This is a circuit diagram of a half-bridge circuit provided in an embodiment of the present invention;

[0031] Figure 2 This is a circuit diagram of an upper and lower bridge drive separation circuit provided in Embodiment 1 of the present invention;

[0032] Figure 3 This is a circuit diagram of an upper and lower bridge drive separation circuit provided in Embodiment 2 of the present invention;

[0033] Figure 4 This is a circuit diagram of a lower bridge driving circuit provided in Embodiment 3 of the present invention;

[0034] Figure 5 This is a circuit diagram of a lower bridge driving circuit provided in Embodiment 4 of the present invention. Detailed Implementation

[0035] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate this technical solution, its implementation process, and its principles.

[0036] Please refer to Figure 1 This is a typical Buck circuit structure composed of a half-bridge structure combining E-GaN and D-GaN transistors. This half-bridge circuit includes: an E-GaN transistor in the upper arm, a D-GaN transistor in the lower arm, a controller module, a load module, and a filter circuit. The upper and lower bridge drive separation circuits are located in the controller module, and the E-GaN and D-GaN transistors are connected to these circuits. The load module consists of a resistor R. In the switching power supply circuit, the inductor L1 and capacitor C1, acting as energy storage elements, constitute the filter circuit to smooth the output voltage signal.

[0037] Between the input and output terminals of the circuit, the E-GaN transistor in the upper bridge arm is directly connected in series in the input power path. The E-GaN transistor has a "normally off" characteristic, remaining off under normal operating conditions. This characteristic allows it to cut off power to downstream circuits in the event of a power outage or undervoltage in the controller, completely preventing problems that could arise from input short circuits. Simultaneously, the D-GaN transistor in the lower bridge arm is in a naturally on state, providing a reliable discharge path for the load capacitor and ensuring the circuit remains stable and safe under various operating conditions.

[0038] For an example of a half-bridge circuit combining E-GaN and D-GaN, please refer to the following embodiment:

[0039] Example 1

[0040] Please refer to Figure 2A half-bridge circuit combining E-GaN and D-GaN is disclosed, comprising upper and lower bridge drive separation circuits, E-GaN, and D-GaN. The upper and lower bridge drive separation circuits include a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first drive circuit. The second integrated circuit includes a second drive circuit, a level shifting circuit, and a third drive circuit.

[0041] In the diagram, the upper dashed ellipse represents the first integrated circuit, and the lower dashed ellipse represents the second integrated circuit. Furthermore, the upper and lower solid boxes are the borders of the first and second integrated circuits, respectively, indicating that they are integrated. The intersections of circuit lines and borders are I / O (input / output) ports. The ports are labeled on the solid boxes. The first integrated circuit has four necessary ports: HSi, HB, HO, and VS. The second integrated circuit has seven necessary ports: IN, HB, HSo, VS, VSS, LO, and NEG. In this design, the first, second, and third driving circuits are all output-stage inverters. The output-stage inverter includes one PMOS transistor and one NMOS transistor, with their drains connected. The source of the PMOS transistor is connected to a floating power supply, and the source of the NMOS transistor is connected to a floating ground.

[0042] The first driving circuit includes a first transistor PM1 and a second transistor NM1. The second driving circuit includes a third transistor PM2 and a fourth transistor NM2. The third driving circuit includes a fifth transistor PM3 and a sixth transistor NM3. The level shifting circuit includes at least a first level shifter NOT1, a second level shifter NOT2, and a third level shifter NOT3.

[0043] Specifically, the source of PM1 is connected to HB, which is the power supply port, and the gates of PM1 and NM1 are connected to the first connection point. Figure 2 The "1" in the figure is used as the input terminal HSi, and the drain is connected to the second connection point ( Figure 2 The "2" in the figure is used as the output terminal HO, which is connected to the upper bridge arm to control the working state of the upper bridge arm. The source of NM1 is connected to VS. The source of PM2 is connected to HB for power supply, and the gate of PM2 and the gate of NM2 are connected to the third connection point ( Figure 2 The drain is connected to the fourth connection point (the "3" in the diagram). Figure 2 The "4" in the diagram serves as the output terminal HSo, with the source of NM2 connected to VS. The source of PM3 is connected to VSS, and the gates of PM3 and NM3 are connected to the fifth connection point (…). Figure 2 The drain is connected to the sixth connection point (5). Figure 2The "6" in the diagram is used as the output terminal LO, connected to the lower bridge arm to control the working state of the lower bridge arm. The source of NM3 is connected to a negative voltage NEG. The input terminal of NOT1 is the signal input terminal IN. The output terminal of NOT1 is connected to the input terminals of NOT2 and NOT3 respectively. The output terminal of NOT2 is connected to the third connection point, and the output terminal of NOT3 is connected to the fifth connection point.

[0044] In this design, the upper bridge arm uses E-GaN, and the lower bridge arm uses D-GaN. In the low-side IC, the second and third drive circuits after the level shifting circuit employ an isolated island structure. The low-side IC implements a complete half-bridge drive, while the high-side IC drives the upper bridge in a cascaded manner. The signals from the preceding stages are typically generated by a microcontroller unit (MCU) or a digital signal processor (DSP). These signals must be considered for the safety and stability of the entire system before being transmitted to subsequent drive circuits. Especially in high-voltage systems, strict isolation between high-voltage and low-voltage circuits is necessary for safety. Therefore, the low-voltage side (also known as the low-voltage side) and the high-voltage side (also known as the high-voltage side) are designed to be non-common grounded to prevent potential current backflow or short-circuit risks. The isolator ensures that the signal does not cause any direct electrical connection during transmission from the low-voltage side to the high-voltage side, thus guaranteeing system safety. The isolated signal is then sent to the driver IC and converted into an appropriate drive output. This conversion process includes increasing the voltage swing to adapt to the high-voltage side level requirements and enhancing the driving capability to ensure the drive circuit can effectively control subsequent power devices. By using a half-bridge driver in conjunction with a cascaded high-side driver, this cascaded driving method significantly improves the driving capability of the upper bridge arm while effectively reducing losses during the driving process. In the design of the low-side driver, this scheme adopts a dual design corresponding to the high-side driver, where the drive stage uses an independent isolation structure for isolation. Furthermore, this scheme specifically designs a negative voltage generation module, whose function is to provide the necessary negative voltage supply to the output stage of the lower bridge arm driver to ensure normal driver operation. In this embodiment, the high-side drive uses a floating ground reference and functionally requires level shifting or isolation for driving. In contrast, the low-side drive does not functionally require shifting or isolation, but isolation can be implemented from an electrical safety perspective.

[0045] Example 2

[0046] Please refer to Figure 3A half-bridge circuit combining E-GaN and D-GaN is disclosed, comprising an upper / lower bridge drive separation circuit, E-GaN, and D-GaN. The upper / lower bridge drive separation circuit includes a first integrated circuit and a second integrated circuit. When the first integrated circuit and the second integrated circuit are not connected, the input terminals of the first integrated circuit and the second integrated circuit are respectively connected to a power supply, and the second integrated circuit is connected to a negative voltage generating module.

[0047] In the diagram, the top and bottom solid-line boxes represent the borders of the first and second integrated circuits, respectively, indicating that they are integrated. The intersections of the circuit lines with the borders are the I / O (input / output) ports. The ports are labeled on the solid-line boxes. The first integrated circuit has four necessary ports: HSi, HB, HO, and VS. The second integrated circuit has four necessary ports: LSi, VSS, LO, and NEG. The first and second integrated circuits can be understood as an output-stage inverter, comprising a PMOS transistor and an NMOS transistor, with their drains connected. The source of the PMOS transistor is connected to a floating power supply, and the source of the NMOS transistor is connected to a floating ground.

[0048] The first integrated circuit includes a seventh transistor PM4 and an eighth transistor NM4, and the second integrated circuit includes a ninth transistor PM5 and a tenth transistor NM5. Specifically, the source of PM4 is connected to HB, which supplies power to PM4, and the gate of PM4 is connected to the gate of NM4 to a seventh connection point ( ). Figure 3 The seventh connection point ("7") is the input terminal HSi of the first integrated circuit; the drain of the seventh transistor PM4 is connected to the drain of the eighth transistor NM4 to the eighth connection point ( Figure 3 The eighth connection point ("8") is the output terminal HO of the first integrated circuit, connected to the upper bridge arm, and used to control the working state of the upper bridge arm; the source of the eighth transistor NM4 is connected to VS. The source of the ninth transistor PM5 is connected to VSS, and the gate of the ninth transistor PM5 is connected to the gate of the tenth transistor NM5 to the ninth connection point ( Figure 3 The ninth connection point is the input terminal LSi of the second integrated circuit; the drain of the ninth transistor PM5 is connected to the drain of the tenth transistor NM5 to the tenth connection point (indicated by "9"). Figure 3 The tenth connection point ("10") is the output terminal LO of the second integrated circuit, which is connected to the lower bridge arm and used to control the working state of the lower bridge arm; the source of the tenth transistor NM5 is connected to the negative voltage generation module NEG to provide negative voltage power supply.

[0049] In addition, digital isolators are each provided in front of the input terminals of the first integrated circuit and the second integrated circuit.

[0050] This proposed half-bridge, combining E-GaN and D-GaN technologies, separates the driving circuits for the upper and lower bridge arms, eliminating the need for connections between them. This design significantly reduces the number of transistors in the lower bridge driver circuit, thereby lowering overall area costs and improving wiring flexibility. Furthermore, the driver circuit can utilize isolated drivers or a combination of isolators and single-channel non-isolated drivers to meet diverse application requirements and design considerations. In this solution, the upper bridge arm is driven by inserting isolators or using isolated drivers, replacing the traditional level-shifting scheme in half-bridge integrated circuits. Since the secondary side of the isolator or isolated driver has no limitation on negative voltage, it can directly adapt to the negative voltage power supply requirements of the output stage.

[0051] Example 3

[0052] Please refer to Figure 4 A half-bridge circuit combining E-GaN and D-GaN is disclosed, comprising an upper / lower bridge drive separation circuit, E-GaN, and D-GaN. The upper / lower bridge drive separation circuit includes a first integrated circuit and a second integrated circuit. The input terminals of the first and second integrated circuits are respectively connected to a power supply, and the second integrated circuit is connected to a negative voltage generating module. Figure 4 In the diagram, the solid-line box represents the border of the second integrated circuit, indicating that it is integrated. The intersections of the circuit lines and the border are I / O (input / output) ports. These ports are labeled on the solid-line box. In this design, the first and second integrated circuits can be understood as a type of output-stage inverter. The output-stage inverter includes a PMOS transistor and an NMOS transistor, with their drains connected. The source of the PMOS transistor is connected to a floating power supply, and the source of the NMOS transistor is connected to a floating ground.

[0053] Specifically, the first integrated circuit can be the first integrated circuit in Embodiment 2 above. The second integrated circuit includes an eleventh transistor PM6 and a twelfth transistor NM6. Specifically, the source of PM6 is connected to VSS, the gate of PM6 is connected to an internal drive buffer (the triangle in the figure), and the drain of PM6 is connected to the drain of NM6 to the eleventh connection point (…). Figure 4 (11) The eleventh connection point is the output terminal LO of the second integrated circuit; the gate of the NM6 is connected to another internal drive buffer, and the source of the NM6 is connected to the negative voltage generation module.

[0054] The negative voltage generation module includes a negative voltage charge pump circuit, a driving capacitor C3, a freewheeling capacitor, and a first decoupling capacitor C2. The negative voltage charge pump circuit provides a negative voltage power supply. The driver output stage of the negative voltage charge pump circuit is a CMOS inverter, including a thirteenth transistor PM7 and a fourteenth transistor NM7. The source of PM7 is connected to the power supply, and the gates of both PM7 and NM7 are connected to the CP controller. The source of NM7 is grounded. The drains of PM7 and NM7 are connected to the twelfth connection point (…). Figure 4 The capacitor C2 ("12") is used to output the drive signal and is connected to the drive capacitor C3. The drive capacitor C3 is connected to the freewheeling device. The freewheeling device is a dual-diode integrated device, commonly model BAT54. The drive capacitor C3 is connected to the first anode of the freewheeling device, the second anode of the freewheeling device is connected to the source of NM6, the common cathode is grounded, and one end of the first decoupling capacitor C2 is connected to the source of NM6, and the other end is grounded.

[0055] This negative voltage generation module provides a negative voltage supply to the driver output stage of the lower bridge arm, which drives the D-GaN device. It can be packaged together with or integrated with the driver IC.

[0056] Example 4

[0057] Please refer to Figure 5 A half-bridge circuit combining E-GaN and D-GaN is disclosed, comprising an upper / lower bridge drive separation circuit, E-GaN, and D-GaN. The upper / lower bridge drive separation circuit includes a first integrated circuit and a second integrated circuit. The input terminals of the first and second integrated circuits are respectively connected to a power supply, and the second integrated circuit is connected to a negative voltage generating module. Figure 4 In the diagram, the solid-line box represents the border of the second integrated circuit, indicating that it is integrated. The intersections of the circuit lines and the border are I / O (input / output) ports. These ports are labeled on the solid-line box. In this scheme, the first and second integrated circuits can be understood as an output-stage inverter. The output-stage inverter includes a PMOS transistor and an NMOS transistor, with their drains connected. The source of the PMOS transistor is connected to a floating power supply, and the source of the NMOS transistor is connected to a floating ground. Specifically, the first integrated circuit can be the first and second integrated circuits described in Embodiment 3 above.

[0058] The negative pressure generating module includes a buck boost control circuit, a drive inductor L2, and a second decoupling capacitor C4. The buck boost control circuit includes a fifteenth transistor PM8 and a diode. The source of PM8 is connected to the power supply, the gate of PM8 is connected to the buck-boost control circuit, and the drain of PM8 and the diode are connected to the thirteenth connection point (…). Figure 5(13) The other end of the diode is connected to the source of NM6. The connection point between the drain of PM8 and the diode is connected to the driving inductor L2. The other end of the driving inductor L2 is grounded. One end of the second decoupling capacitor C4 is connected to the source of NM6, and the other end is grounded.

[0059] The charge pump circuit in Example 3 has the advantages of low cost and small size, but its output range and power are relatively limited. In contrast, the inductor-based switching power supply circuit has high output power and a wide output voltage range. The negative voltage generation module in this example is suitable for driving high-voltage, high-current, high-power devices, providing a negative supply voltage to the corresponding driver IC.

[0060] This negative voltage Buck-Boost provides a negative voltage to the driver output stage of the lower bridge arm, which drives the D-GaN device that serves as the lower bridge arm of the half-bridge. It can be packaged together with or integrated with the driver IC.

[0061] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A half-bridge circuit combining E-GaN and D-GaN, characterized in that, It includes an upper and lower bridge drive separation circuit, an upper bridge arm E-GaN, and a lower bridge arm D-GaN. The upper and lower bridge drive separation circuit includes a first integrated circuit and a second integrated circuit. The output terminal of the first integrated circuit is connected to the upper bridge arm E-GaN and is used to control the working state of the upper bridge arm E-GaN. The output terminal of the second integrated circuit is connected to the lower bridge arm D-GaN and is used to control the working state of the lower bridge arm D-GaN. Wherein, when the first integrated circuit is connected to the second integrated circuit, the input terminal of the second integrated circuit is connected to the power supply, and the input terminal of the second integrated circuit is connected to the input terminal of the first integrated circuit; When the first integrated circuit and the second integrated circuit are not connected, the input terminals of the first integrated circuit and the second integrated circuit are respectively connected to the power supply, and the second integrated circuit is connected to the negative voltage generating module.

2. The half-bridge circuit according to claim 1, characterized in that, When the first integrated circuit and the second integrated circuit are connected, the first integrated circuit includes at least a first driving circuit, and the second integrated circuit includes at least a second driving circuit, a level shifting circuit, and a third driving circuit. The input terminal of the level shifting circuit is a signal input terminal. The output terminal of the level shifting circuit is connected to the input terminals of the second driving circuit and the third driving circuit, respectively. The output terminal of the second driving circuit is connected to the input terminal of the first driving circuit. The output terminal of the first driving circuit is connected to the upper bridge arm. The output terminal of the third driving circuit is connected to the lower bridge arm. The negative pressure generating module is connected to the third driving circuit.

3. The half-bridge circuit according to claim 2, characterized in that, The first driving circuit includes a first transistor and a second transistor. The source of the first transistor is connected to HB, which supplies power to the first transistor. The gates of the first transistor and the second transistor are connected to a first connection point, which is the input terminal of the first driving circuit. The drains of the first transistor and the second transistor are connected to a second connection point, which is the output terminal of the first driving circuit. The source of the second transistor is connected to VS. And / or, the second driving circuit includes a third transistor and a fourth transistor, wherein the source of the third transistor is connected to HB, the gate of the third transistor is connected to the gate of the fourth transistor to a third connection point, the third connection point being the input terminal of the second driving circuit; the drain of the third transistor is connected to the drain of the fourth transistor to a fourth connection point, the fourth connection point being the output terminal of the second driving circuit; the source of the fourth transistor is connected to VS. And / or, the third driving circuit includes a fifth transistor and a sixth transistor. The source of the fifth transistor is connected to a power supply. The gate of the fifth transistor is connected to the gate of the sixth transistor to a fifth connection point, which is the input terminal of the third driving circuit. The drain of the fifth transistor is connected to the drain of the sixth transistor to a sixth connection point, which is the output terminal of the third driving circuit. The source of the sixth transistor is connected to NEG. And / or, the level shifting circuit includes at least a first level shifter, a second level shifter, and a third level shifter, wherein the input terminal of the first level shifter is a signal input terminal, the output terminal of the first level shifter is connected to the input terminals of the second level shifter and the third level shifter respectively, the output terminal of the second level shifter is connected to a third connection point, and the output terminal of the third level shifter is connected to a fifth connection point.

4. The half-bridge circuit according to claim 1, characterized in that, When the first integrated circuit and the second integrated circuit are not connected, an isolation module is provided in front of the input terminal of the first integrated circuit and / or the second integrated circuit.

5. The half-bridge circuit according to claim 1, characterized in that, When the first integrated circuit and the second integrated circuit are not connected, the first integrated circuit includes a seventh transistor and an eighth transistor. The source of the seventh transistor is connected to HB, and HB supplies power to the seventh transistor. The gate of the seventh transistor is connected to the gate of the eighth transistor to a seventh connection point, which is the input terminal of the first integrated circuit. The drain of the seventh transistor is connected to the drain of the eighth transistor to an eighth connection point, which is the output terminal of the first integrated circuit. The source of the eighth transistor is connected to VS.

6. The half-bridge circuit according to claim 5, characterized in that, The second integrated circuit includes a ninth transistor and a tenth transistor. The source of the ninth transistor is connected to VSS, and the gate of the ninth transistor is connected to the gate of the tenth transistor to a ninth connection point, which is the input terminal of the second integrated circuit. The drain of the ninth transistor is connected to the drain of the tenth transistor to a tenth connection point, which is the output terminal of the second integrated circuit. The source of the tenth transistor is connected to a negative voltage generating module.

7. The half-bridge circuit according to claim 5, characterized in that, The second integrated circuit includes an eleventh transistor and a twelfth transistor. The source of the eleventh transistor is connected to a power supply, the gate of the eleventh transistor is connected to an isolator, the gate of the twelfth transistor is connected to an isolator, and the drain of the eleventh transistor and the drain of the twelfth transistor are connected to an eleventh connection point, which is the output terminal of the second integrated circuit. The source of the twelfth transistor is connected to a negative voltage generating module.

8. The half-bridge circuit according to claim 7, characterized in that, The negative pressure generating module includes a negative pressure charge pump circuit, a driving capacitor, a freewheeling capacitor, and a first decoupling capacitor. The negative pressure charge pump circuit includes a thirteenth transistor and a fourteenth transistor. The source of the thirteenth transistor is connected to the power supply. The gate of the thirteenth transistor and the gate of the fourteenth transistor are connected to the CP controller. The source of the fourteenth transistor is grounded. The drain of the thirteenth transistor PM7 and the drain of the fourteenth transistor NM7 are connected to the driving capacitor. The driving capacitor is connected to the first anode of the freewheeling circuit. The second anode of the freewheeling circuit is connected to the source of the twelfth transistor. The common cathode is grounded. One end of the first decoupling capacitor is connected to the source of the twelfth transistor, and the other end is grounded.

9. The half-bridge circuit according to claim 7, characterized in that, The negative pressure generating module includes a buck boost control circuit, a drive inductor, and a second decoupling capacitor. The buck boost control circuit includes a fifteenth transistor and a diode. The source of the fifteenth transistor is connected to the power supply, the gate of the fifteenth transistor is connected to the Buck-Boost control circuit, the drain of the fifteenth transistor is connected to the diode, the other end of the diode is connected to the source of the twelfth transistor, the connection point between the drain of the fifteenth transistor and the diode is connected to the driving inductor, the other end of the driving inductor is grounded, one end of the second decoupling capacitor is connected to the source of the twelfth transistor, and the other end is grounded.

10. The half-bridge circuit according to claim 1, characterized in that, When E-GaN and D-GaN are in the on state, they operate in the linear region, and when they are in the off state, they operate in the cutoff region.

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