A drive half-bridge split circuit, half-bridge circuit

Abstract

The application discloses a kind of drive half-bridge separation circuit, half-bridge circuit.The drive half-bridge separation circuit includes first integrated circuit, second integrated circuit, the output of the first integrated circuit is connected with upper bridge arm, for controlling the working state of the upper bridge arm, the output of the second integrated circuit is connected with lower bridge arm, for controlling the working state of the lower bridge arm;Wherein, when the first integrated circuit is connected with second integrated circuit, the input of the second integrated circuit is connected with power supply, and the second integrated circuit is connected with the input of the first integrated circuit;When the first integrated circuit is not connected with second integrated circuit, the input of the first integrated circuit, second integrated circuit is respectively connected with power supply.The upper and lower bridge arm drive separation is independently controlled, ensures that driving path is shortest, promotes system performance and reliability.

Description

Technical Field

[0001] This invention relates to the field of half-bridge drive circuit technology, and in particular to a drive half-bridge separation circuit and a half-bridge circuit. Background Technology

[0002] Buck converters are among the simplest and most reliable non-isolated buck topologies currently available, finding widespread application in secondary and tertiary power supplies. In Buck converter applications, under most operating conditions, when inductor current flows to the load, the upper transistor (upper MOSFET) performs hard switching, while the lower transistor (lower MOSFET) performs soft switching. Since almost all switching losses originate from the upper MOSFET, maximizing the switching speed of the upper MOSFET while controlling switching stress and ensuring system reliability is crucial for improving overall system efficiency. In conventional solutions on the market, the Buck power stage and its drive circuit typically employ... Figure 1 The structure shown mainly consists of a half-bridge driver and power switching transistors for the upper and lower bridge arms. Depending on the system requirements, a digital isolator can be added to the front-end to achieve electrical isolation.

[0003] In the process of developing the existing technology, the inventors discovered that:

[0004] For most half-bridge drive solutions on the market, the high and low side drives are typically packaged together or integrated into a single package, and the drive capabilities of the high and low sides are the same. This approach has some problems:

[0005] 1) Because this half-bridge driver scheme cannot meet the optimization requirements of PCB routing, the driver IC must be placed close to the power transistor. During the layout and routing stage, the half-bridge driver IC can only be centered relative to the upper and lower bridge arms, or close to one of the two bridge arms, which limits the flexibility of routing.

[0006] 2) For the symmetrical half-bridge driver commonly found in the market (i.e., the driving capabilities of the upper and lower bridges are the same), when applied to the Buck structure and driving an asymmetrical half-bridge, insufficient driving capability of the upper bridge may be encountered. Specifically, the switching speed of the upper bridge is not fast enough, resulting in greater switching losses.

[0007] 3) Furthermore, in common half-bridge driver ICs, the pull-down drive strength of a single output is typically set to be 2-4 times that of the pull-up drive strength. For power devices with relatively small gate-drain junction capacitance (Cgd) and relatively large drain-source junction capacitance (Cds), such as gallium nitride (GaN) MOSFETs, under symmetrical drive conditions, their normal turn-on loss is much greater than their turn-off loss. Using a driver IC with such weak pull-up capability to drive a GaN MOSFET will further increase the device's turn-on loss, thus affecting overall performance. Summary of the Invention

[0008] The main objective of this invention is to provide a driving half-bridge separation circuit and a half-bridge circuit, thereby overcoming the shortcomings of the prior art.

[0009] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:

[0010] The first aspect of the present invention provides a driving half-bridge split circuit, including a first integrated circuit and a second integrated circuit, wherein the output terminal of the first integrated circuit is connected to the upper bridge arm and is used to control the working state of the upper bridge arm, and the output terminal of the second integrated circuit is connected to the lower bridge arm and is used to control the working state of the lower bridge arm.

[0011] Specifically, when the first integrated circuit is connected to the second integrated circuit, the input terminal of the second integrated circuit is connected to a power supply, and the input terminal of the second integrated circuit is connected to the input terminal of the first integrated circuit; when the first integrated circuit and the second integrated circuit are not connected, the input terminals of the first integrated circuit and the second integrated circuit are respectively connected to a power supply.

[0012] In some more specific implementations, when the first integrated circuit and the second integrated circuit are connected, the first integrated circuit includes at least a first driving circuit, and the second integrated circuit includes at least a second driving circuit, a first level shifting circuit, and a third driving circuit.

[0013] The input terminal of the first level shift circuit is connected to the input terminal of the third driving circuit, and the connection point is the signal input terminal; the output terminal of the third driving circuit is connected to the lower bridge arm; the output terminal of the first level shift circuit is connected to the input terminal of the second driving circuit, the output terminal of the second driving circuit is connected to the input terminal of the first driving circuit, and the output terminal of the first driving circuit is connected to the upper bridge arm. The first level shift circuit can be a level shifter.

[0014] In some more specific implementations, when the first integrated circuit and the second integrated circuit are not connected, the first integrated circuit includes at least a fourth driving circuit, and the second integrated circuit includes at least a fifth driving circuit. The input terminal of the fourth driving circuit is a signal input terminal, and the output terminal of the fourth driving circuit is connected to the upper bridge arm. The input terminal of the fifth driving circuit is a signal input terminal, and the output terminal of the fifth driving circuit is connected to the lower bridge arm.

[0015] In some more specific implementations, the first integrated circuit further includes a second level shift circuit, which is connected to the input terminal of the fourth driving circuit. The second level shift circuit can be a level shifter.

[0016] In some more specific implementations, the drive half-bridge separation circuit further includes an interlock logic or dead-time generation circuit, which is built into the first integrated circuit.

[0017] Preferably, the interlock logic or dead-time generation circuit is located externally and is connected to the input terminals of the first integrated circuit and the second integrated circuit, respectively.

[0018] In some more specific implementations, the driving half-bridge separation circuit further includes an isolation module, the input terminal of which is a signal input terminal, and the output terminal of which is connected to the input terminal of the fourth driving circuit.

[0019] Specifically, the isolation module can be a digital isolator.

[0020] In some more specific implementations, the isolation module is co-packaged with the fourth driving circuit.

[0021] A second aspect of the present invention provides a half-bridge circuit, comprising: an upper bridge arm, a lower bridge arm, and the aforementioned driving half-bridge separation circuit, wherein the upper bridge arm and the lower bridge arm are respectively connected to the driving half-bridge separation circuit. When the upper bridge arm and the lower bridge arm are in the on state, they operate in the linear region; when they are in the off state, they operate in the cutoff region.

[0022] Compared with the prior art, the advantages of the present invention include at least the following:

[0023] First, in the drive half-bridge split circuit provided by this invention, the second integrated circuit is compactly placed next to the lower bridge power device, while the first integrated circuit can be mounted close to the upper bridge power device. This layout optimizes circuit performance and helps reduce the overall board space occupied, while improving system stability and efficiency.

[0024] Secondly, the drive half-bridge separation circuit provided in this invention separates the upper and lower drive circuits and assigns them independent drive power supplies. This eliminates the need for connection between the upper and lower bridge drive circuits. Through this design, we can significantly reduce the number of transistors in the lower bridge drive circuit, thereby reducing the overall area cost. Attached Figure Description

[0025] Figure 1 This is a circuit diagram of a conventional half-bridge power stage and its driving circuit.

[0026] Figure 2 This is a circuit block diagram of an upper bridge single-channel isolated drive circuit provided in an embodiment of the present invention;

[0027] Figure 3This is a circuit diagram of a driving half-bridge split circuit provided in an embodiment of the present invention;

[0028] Figure 4 This is a circuit diagram of another driving half-bridge separation circuit provided in an embodiment of the present invention;

[0029] Figure 5 This is a circuit diagram of the external dead-time generation circuit provided in an embodiment of the present invention;

[0030] Figure 6 This is a circuit diagram of the built-in dead-time generation circuit provided in an embodiment of the present invention;

[0031] Figure 7 This is a circuit diagram of voltage level shifting provided in an embodiment of the present invention;

[0032] Figure 8 This is a circuit diagram of a built-in voltage level shifting method provided in an embodiment of the present invention;

[0033] Figure 9 This is a circuit diagram of a built-in voltage level shifting method provided in an embodiment of the present invention;

[0034] Figure 10 This is a circuit diagram of a driver half-bridge separation circuit based on a digital isolator provided in an embodiment of the present invention;

[0035] Figure 11 This is a circuit diagram of a single-channel isolated drive circuit for an upper bridge provided in an embodiment of the present invention. Detailed Implementation

[0036] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate this technical solution, its implementation process, and its principles.

[0037] Please refer to Figure 2 A half-bridge circuit includes: an upper bridge arm power transistor, a lower bridge arm power transistor, and upper and lower bridge arm drive separation circuits. The upper and lower bridge arm drive separation circuits include a first integrated circuit and a second integrated circuit. The first integrated circuit is a high-side drive IC, and the second integrated circuit is a low-side drive IC. The first integrated circuit can be packaged with the upper bridge arm power transistor or integrated on a single substrate. Similarly, the second integrated circuit can be packaged with the lower bridge arm power transistor or integrated on a single substrate.

[0038] Example 1

[0039] Please refer to Figure 3 A half-bridge circuit includes: an upper bridge arm, a lower bridge arm, and a drive separation circuit for the upper and lower bridge arms. The drive separation circuit for the upper and lower bridge arms includes a first integrated circuit and a second integrated circuit.

[0040] The first integrated circuit includes a first driving circuit, and the second integrated circuit includes a second driving circuit, a level shifting circuit, and a third driving circuit. The input terminal of the level shifting circuit is connected to the input terminal of the third driving circuit, and the output terminal LO of the third driving circuit controls the working state of the lower bridge arm. The output terminal HSo of the second driving circuit is connected to the input terminal HSi of the first driving circuit, and the output terminal HO of the first driving circuit controls the working state of the upper bridge arm.

[0041] In the diagram, the upper dashed ellipse represents the first integrated circuit, and the lower dashed ellipse represents the second integrated circuit. Furthermore, the upper and lower solid boxes are the borders of the first and second integrated circuits, respectively, indicating that they are integrated. The intersections of circuit lines and the borders are I / O (input / output) ports. The ports are labeled on the solid boxes. The first integrated circuit has four necessary ports: HSi, HB, HO, and VS. The second integrated circuit has seven necessary ports: IN, HB, HSo, VS, VDD, LO, and VSS. In this design, the first, second, and third driving circuits are all output-stage inverters. The output-stage inverter includes one PMOS transistor and one NMOS transistor, with their drains connected. The source of the PMOS transistor is connected to a floating power supply, and the source of the NMOS transistor is connected to a floating ground.

[0042] The first driving circuit includes a first transistor PM1 and a second transistor NM1. The second driving circuit includes a third transistor PM2 and a fourth transistor NM2. The first level shifting circuit includes a level shifter NOT1. The third driving circuit includes a fifth transistor PM3 and a sixth transistor NM3. Specifically, the source of PM1 is connected to HB, which is the power supply port, and the gates of PM1 and NM1 are connected to the first connection point (…). Figure 3 The "1" in the figure is used as the input terminal HSi, and the drain is connected to the second connection point ( Figure 3 The "2" in the diagram serves as the output terminal HO, with the source of NM1 connected to VS. The source of PM2 is connected to HB for power supply, and the gates of PM2 and NM2 are connected to the third connection point ( Figure 3 The "3" in the figure is used as the input terminal, and the drain is connected to the fourth connection point ( Figure 3 The "4" in the diagram serves as the output terminal HSo, with the source of NM2 connected to VS. The source of PM3 is connected to VDD, and the gates of PM3 and NM3 are connected to the fifth connection point (…). Figure 3 The "5" in the figure is used as the input terminal, and the drain is connected to the sixth connection point ( Figure 3 The "6" in the diagram serves as the output terminal LO, and the source of NM3 is connected to VSS. The NOT1 input terminal is connected to the signal input terminal IN, and the output terminal is connected to the third connection point. The NOT input terminal is also connected to the fifth connection point.

[0043] In this design, the upper and lower bridge drivers are separated, meaning independent integrated circuits are used to drive the upper and lower bridge arms respectively. The first integrated circuit includes a high-side driver and a high-side cascaded stage. The second integrated circuit includes a high-side cascaded pre-stage, a level shifter, and a low-side driver.

[0044] This design allows the second integrated circuit to be compactly placed next to the lower-bridge power device, while the first integrated circuit can be mounted close to the upper-bridge power device. This layout optimizes circuit performance and helps reduce overall board space footprint, while improving system stability and efficiency.

[0045] Example 2

[0046] Please refer to Figure 4 A half-bridge circuit includes an upper bridge arm, a lower bridge arm, and upper and lower bridge arm drive separation circuits. The upper and lower bridge arm drive separation circuits include a first integrated circuit and a second integrated circuit. The first integrated circuit has four necessary ports: HSi, HB, HO, and VS. The second integrated circuit has four necessary ports: LSi, VDD, LO, and VSS. The first integrated circuit includes at least a fourth drive circuit, and the second integrated circuit includes at least a fifth drive circuit. The input terminal HSi of the fourth drive circuit is a signal input terminal, and the output terminal HO of the fourth drive circuit is connected to the upper bridge arm. The input terminal LSi of the fifth drive circuit is a signal input terminal, and the output terminal LO of the fifth drive circuit is connected to the lower bridge arm.

[0047] In this design, both the fourth and fifth driving circuits are output-stage inverters. Each output-stage inverter includes a PMOS transistor and an NMOS transistor, with their drains connected. The source of the PMOS transistor is connected to a floating power supply, and the source of the NMOS transistor is connected to a floating ground. The fourth driving circuit includes a seventh transistor PM4 and an eighth transistor NM4. The fifth driving circuit includes a ninth transistor PM5 and a tenth transistor NM5. The second level shifting circuit includes a level shifter NOT2.

[0048] Specifically, the source of PM4 is connected to the power supply of HB, and the connection point between the gate of PM4 and the gate of NM4 is connected to the seventh connection point. Figure 4 The drain is connected to the eighth connection point (the "7" in the diagram). Figure 4 The "8" in the diagram serves as the output terminal HO. The source of NM4 is connected to VS. The source of PM5 is connected to VDD. The gates of PM5 and NM5 are connected to the ninth connection point ( ). Figure 4 The "9" in the figure is used as the input terminal LSi, and the drain is connected to the tenth connection point ( Figure 4 The "10" in the diagram is used as the output terminal LO, and the source of NM5 is connected to VSS. The input terminal of NOT2 is connected to HSi, and the output terminal is connected to the seventh connection point.

[0049] In a half-bridge circuit, there is a time interval when the upper and lower bridge arms switch, meaning that both arms may conduct simultaneously. This would cause a short circuit between the positive and negative terminals of the power supply through the two conducting devices. The half-bridge circuit also includes interlock logic or a dead-time generation circuit, which is built into the first integrated circuit. Alternatively, the interlock logic or dead-time generation circuit can be externally located and connected to the input terminal of NOT2 and the ninth connection point, respectively. The dead-time generation circuit prevents the power devices of the upper and lower bridge arms from conducting simultaneously. Its core function is to insert a brief "dead time" during the switching process of the upper and lower bridge arms, ensuring that the next bridge arm only begins to conduct after the previous bridge arm is completely turned off, thereby preventing damage to the power supply or load due to bridge arm shoot-through.

[0050] Please refer to Figure 5 The dead-time generation circuit includes two delay units (triangle symbols in the figure) and two AND gates. The delay units are preferably rising-edge (single-sided) delay units (Delay_Rising). One rising-edge (single-sided) delay unit is connected to the AND gate on one side and to the HI port on the other. The other input of the AND gate is also connected to the HI port, and the output of the AND gate is connected to the HSi port, thus completing further signal processing and transmission. The other rising-edge (single-sided) delay unit is connected to the other AND gate on one side and to the LI port on the other. The other input of the AND gate is also connected to the LI port, and the output of the AND gate is connected to the LSi port. When the dead-time generation circuit is external, the original NOT2 logic gate needs to be replaced with an inverter that does not have an inverting function. This replacement ensures that the circuit does not affect the logic state of the signal during level conversion, thus guaranteeing the normal operation of the circuit. Similarly, please refer to... Figure 6 If the dead-time generation circuit is built-in, the NOT2 logic gate also needs to be replaced with an inverter without inverting function.

[0051] When the signal reaches the upper bridge driver stage, it passes through the level shifter NOT2 and is then output via HO. When the signal reaches the lower bridge driver stage, it is output via LO; no level shifter is used in this process. To ensure consistent delay between the upper and lower bridges, a DUMMY circuit is built into the upper bridge driver stage. This DUMMY circuit has a similar structure to the level shifter circuit, but it does not actually perform level shifting. Please refer to [reference needed]. Figure 7 This can be a NOT gate in the same voltage domain. This NOT gate can be a differential structure, and VDD1 can be set to equal VDD2 to ensure circuit consistency and matching. Please refer to [reference needed]. Figure 8 The first method is to... Figure 4 Replace the NOT2 logic gate in the middle with Figure 7The DUMMY circuit is shown. The IN terminal of the DUMMY circuit is connected to the HSi port. Additionally, the OUTB port of the DUMMY circuit needs to be connected to the seventh connection point. The OUT port of the DUMMY circuit remains floating. Please refer to... Figure 9 The second method is to... Figure 5 The inverter that does not have a reversing function is replaced with Figure 7 The DUMMY circuit is shown below. Similarly, the IN terminal of the DUMMY circuit is connected to the HSi port. The OUTB port of the DUMMY circuit needs to be connected to the seventh connection point. The OUT port of the DUMMY circuit remains floating.

[0052] This embodiment 2 is a further solution to embodiment 1, which separates the upper and lower driving circuits and assigns them independent driving power supplies. This eliminates the need for connection between the upper and lower bridge driving circuits. This design significantly reduces the number of transistors in the lower bridge driving circuit, thereby reducing overall area cost. Simultaneously, this design also helps optimize overall performance. Furthermore, integrating the level shifting function into the high-side integrated circuit, while the low-side can use a general-purpose single-channel non-isolated driving IC, improves wiring flexibility. The delay matching circuit is a built-in delay module used to balance the transmission delays of the upper and lower signals, ensuring precise matching of the delays. The upper and lower bridge arm interlocking circuit logically prevents the upper and lower bridge arms from being turned on simultaneously; further, the addition of a dead-time generation circuit inserts a "dead-time" period during the upper and lower bridge switching process, where both bridges are simultaneously turned off, further preventing half-bridge shoot-through. Integrating delay matching, dead time generation, and upper / lower arm interlocking functions into the high-side IC can improve the integration level of the solution, simplify peripheral components, and theoretically achieve better matching accuracy (lower delay mismatch). Alternatively, these functions can be placed discretely at the end of the circuit board to provide greater design flexibility.

[0053] Example 3

[0054] Please refer to Figure 10 A half-bridge circuit includes an upper bridge arm, a lower bridge arm, and upper and lower bridge arm drive separation circuits. The upper and lower bridge arm drive separation circuits include a first integrated circuit and a second integrated circuit. The first integrated circuit includes at least a fourth drive circuit, and the second integrated circuit includes at least a fifth drive circuit. The input terminal HSi of the fourth drive circuit is a signal input terminal, and the output terminal HO of the fourth drive circuit is connected to the upper bridge arm. The input terminal LSi of the fifth drive circuit is a signal input terminal, and the output terminal LO of the fifth drive circuit is connected to the lower bridge arm. The fourth drive circuit includes a seventh transistor PM4 and an eighth transistor NM4. The fifth drive circuit includes a ninth transistor PM5 and a tenth transistor NM5.

[0055] Based on Embodiment 2, in this embodiment, the signals from the front end are typically generated by a microcontroller unit (MCU) or a digital signal processor (DSP). Before these signals are transmitted to the subsequent drive circuits, the safety and stability of the entire system must be considered. Especially in high-voltage systems, due to safety requirements, high-voltage and low-voltage circuits must be strictly isolated. Therefore, the low-voltage side (also known as the low-voltage side) and the high-voltage side (also known as the high-voltage side) are designed to be non-common grounded to prevent potential current backflow or short-circuit risks.

[0056] The half-bridge circuit also includes a digital isolator, located outside the first integrated circuit. The digital isolator ensures the safety and stability of the signal during transmission. All input signals first pass through the digital isolator, and the processed signals are then transmitted. The input terminal of the digital isolator is the signal input terminal, and the output terminal is connected to the gate connection point of the seventh and eighth transistors. This embodiment employs a structure of a lower-bridge single-channel non-isolated drive circuit and an upper-bridge isolator plus a single-channel non-isolated drive circuit. The digital isolator improves the safety and stability of the signal during transmission. The isolator ensures that the signal does not cause any direct electrical connection during transmission from the low-voltage side to the high-voltage side, thus guaranteeing system safety. The isolated signal is then sent to the driver integrated circuit and converted into an appropriate drive output. This conversion process includes increasing the voltage swing to adapt to the high-voltage side level requirements and enhancing the drive capability to ensure that the drive circuit can effectively control subsequent power devices. By using a half-bridge driver in conjunction with a high-side cascaded drive, this cascaded drive method significantly improves the drive capability of the upper bridge arm while effectively reducing losses during the drive process. In the design of the low-side driver, this scheme adopts a dual design corresponding to the high-side driver, where the driver stage uses an independent isolation structure to achieve isolation. Furthermore, this scheme specifically designs a negative voltage generation module, whose function is to provide the necessary negative voltage supply to the output stage of the lower bridge arm driver to ensure the normal operation of the driver. In this embodiment, the high-side driver uses a floating ground reference and, functionally, must employ level shifting or isolation for driving. In contrast, the low-side driver does not functionally require shifting or isolation, but isolation can be implemented from an electrical safety perspective.

[0057] Example 4

[0058] Please refer to Figure 11 A half-bridge circuit includes: an upper bridge arm, a lower bridge arm, and upper and lower bridge arm drive separation circuits. The upper and lower bridge arm drive separation circuits include a first integrated circuit and a second integrated circuit.

[0059] The first integrated circuit includes at least a fourth driving circuit, and the second integrated circuit includes at least a fifth driving circuit. The input terminal HSi of the fourth driving circuit is a signal input terminal, and the output terminal HO of the fourth driving circuit is connected to the upper bridge arm. The input terminal LSi of the fifth driving circuit is a signal input terminal, and the output terminal LO of the fifth driving circuit is connected to the lower bridge arm. The fourth driving circuit includes a seventh transistor PM4 and an eighth transistor NM4. The fifth driving circuit includes a ninth transistor PM5 and a tenth transistor NM5.

[0060] Based on Embodiment 2, in this embodiment, the half-bridge circuit further includes a digital isolator, which is co-packaged with the fourth driving circuit in the first integrated circuit. The input terminal of the digital isolator is the signal input terminal, and the output terminal of the digital isolator is connected to the connection point of the gates of PM4 and NM4. In the figure, the single-channel isolation driver can be considered as integrating a standard digital isolator and a single-channel non-isolated driver, which simplifies the circuit and reduces the number of components. This embodiment uses a single-channel non-isolated driver on the lower bridge and a single-channel isolated driver integrated circuit on the upper bridge to implement the half-bridge driving function. The digital isolator can improve the security and stability of signals during transmission.

[0061] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A driving half-bridge split circuit, characterized in that, It includes a first integrated circuit and a second integrated circuit. The output terminal of the first integrated circuit is connected to the upper bridge arm and is used to control the working state of the upper bridge arm. The output terminal of the second integrated circuit is connected to the lower bridge arm and is used to control the working state of the lower bridge arm. Specifically, when the first integrated circuit is connected to the second integrated circuit, the input terminal of the second integrated circuit is connected to a power supply, and the input terminal of the second integrated circuit is connected to the input terminal of the first integrated circuit; when the first integrated circuit and the second integrated circuit are not connected, the input terminals of the first integrated circuit and the second integrated circuit are respectively connected to a power supply.

2. The driving half-bridge separation circuit according to claim 1, characterized in that, When the first integrated circuit and the second integrated circuit are connected, the first integrated circuit includes at least a first driving circuit, and the second integrated circuit includes at least a second driving circuit, a first level shifting circuit, and a third driving circuit. The input terminal of the first level shift circuit is connected to the input terminal of the third driving circuit, and the connection point is the signal input terminal; the output terminal of the third driving circuit is connected to the lower bridge arm; the output terminal of the first level shift circuit is connected to the input terminal of the second driving circuit, the output terminal of the second driving circuit is connected to the input terminal of the first driving circuit, and the output terminal of the first driving circuit is connected to the upper bridge arm.

3. The driving half-bridge separation circuit according to claim 1, characterized in that, When the first integrated circuit and the second integrated circuit are not connected, the first integrated circuit includes at least a fourth driving circuit, and the second integrated circuit includes at least a fifth driving circuit. The input terminal of the fourth driving circuit is a signal input terminal, and the output terminal of the fourth driving circuit is connected to the upper bridge arm. The input terminal of the fifth driving circuit is a signal input terminal, and the output terminal of the fifth driving circuit is connected to the lower bridge arm.

4. The driving half-bridge separation circuit according to claim 3, characterized in that, The first integrated circuit further includes a second level shifting circuit, which is connected to the input terminal of the fourth driving circuit.

5. The driving half-bridge separation circuit according to claim 3, characterized in that, It also includes interlock logic or dead-time generation circuitry, which is built into the first integrated circuit.

6. The driving half-bridge separation circuit according to claim 5, characterized in that, The interlock logic or dead-time generation circuit is located externally and is connected to the input terminals of the first integrated circuit and the second integrated circuit, respectively.

7. The driving half-bridge separation circuit according to claim 3, characterized in that, It also includes an isolation module, the input of which is a signal input terminal, and the output of which is connected to the input of the fourth driving circuit.

8. The driving half-bridge separation circuit according to claim 5, characterized in that, The isolation module is co-packaged with the fourth driving circuit.

9. A half-bridge circuit, characterized in that, include: The upper bridge arm, the lower bridge arm, and the drive half-bridge separation circuit as described in claims 1-8, wherein the upper bridge arm and the lower bridge arm are respectively connected to the drive half-bridge separation circuit.

10. The half-bridge circuit according to claim 9, characterized in that, When the upper and lower bridge arms are in the conducting state, they operate in the linear region; when they are in the closed state, they operate in the cutoff region.

Images