An upper and lower bridge arm driving separation circuit and a half bridge circuit
Patent Information
- Application Number
- CN202510566617.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-30
- Publication Date
- 2026-10-30
AI Technical Summary
这样的布局导致驱动路径变长，进而使得驱动回路的直流阻抗升高，寄生电感和寄生电容增加，最终引起开关过程中的波形过冲、振荡现象，以及开关损耗的增加，从而影响整个电路的性能和效率
[0018]本发明提供的一种上下桥臂驱动分离电路，第一集成电路可与上桥臂功率器件紧密相邻，第二集成电路可与下桥臂功率器件紧密相邻。通过优化PCB布局和缩短器件间的距离，最大限度地减小了开关电源拓扑的环路面积，并且将板端走线的直流电阻和杂散电感降至最低，并且能够在多个方面提升系统的性能和可靠性，包括提高效率、降低功率级器件承受的应力，以及改善系统的电磁干扰(EMI)。
Smart Images
Figure CN123019391A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of half-bridge drive circuit technology, and in particular to an upper and lower bridge arm drive separation circuit and a half-bridge circuit. Background Technology
[0002] Buck converters are among the simplest and most reliable non-isolated buck topologies currently available. Their power stage design typically employs a half-bridge circuit structure. In conventional solutions on the market, the structure of the half-bridge power stage and its drive circuit is as follows: Figure 1 As shown, it mainly consists of a half-bridge driver and power switching transistors for the upper and lower bridge arms. Depending on the specific requirements of the system, it is possible to choose whether to insert a digital isolator in the front stage for electrical isolation.
[0003] In the process of developing the existing technology, the inventors discovered that:
[0004] For most half-bridge drivers on the market, the high-side and low-side drivers are typically packaged together or integrated into a single package. This design approach presents challenges for half-bridge driver solutions in addressing PCB routing optimization requirements. Specifically, such as... Figure 2 As shown, the driver IC must be placed close to the power transistor. During the circuit board layout and routing phase, the position of the half-bridge driver IC can usually only be centered relative to the upper and lower bridge arms, or close to one of the two bridge arms. This layout results in a longer drive path, which in turn increases the DC impedance of the drive circuit, increases parasitic inductance and parasitic capacitance, and ultimately causes waveform overshoot, oscillation, and increased switching losses during the switching process, thus affecting the performance and efficiency of the entire circuit. Summary of the Invention
[0005] The main objective of this invention is to provide an upper and lower bridge arm drive separation circuit and a half-bridge circuit, thereby overcoming the shortcomings of the prior art.
[0006] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:
[0007] A first aspect of the present invention provides an upper and lower bridge arm drive separation circuit, comprising: a first integrated circuit and a second integrated circuit, wherein the first integrated circuit includes at least a first drive circuit, and the second integrated circuit includes at least a second drive circuit, a level shifting circuit, and a third drive circuit.
[0008] The input terminal of the level shifting circuit is connected to the input terminal of the third driving circuit, and the connection point is a signal input terminal; the output terminal of the third driving circuit is connected to the lower bridge arm to control the working state of the lower bridge arm; the output terminal of the level shifting circuit is connected to the input terminal of the second driving circuit, the output terminal of the second driving circuit is connected to the input terminal of the first driving circuit, and the output terminal of the first driving circuit is connected to the upper bridge arm to control the working state of the upper bridge arm.
[0009] In some more specific implementations, the first driving circuit includes a first transistor and a second transistor, wherein the source of the first transistor is connected to HB, and HB supplies power to the first transistor.
[0010] The gate of the first transistor and the gate of the second transistor are connected to a first connection point, which is the input terminal of the first driving circuit; the drain of the first transistor and the drain of the second transistor are connected to a second connection point, which is the output terminal of the first driving circuit; the source of the second transistor is connected to VS.
[0011] In some more specific implementations, the second driving circuit includes a third transistor and a fourth transistor. The source of the third transistor is connected to HB, and the gate of the third transistor is connected to the gate of the fourth transistor to a third connection point, which is the input terminal of the second driving circuit. The drain of the third transistor is connected to the drain of the fourth transistor to a fourth connection point, which is the output terminal of the second driving circuit. The source of the fourth transistor is connected to VS.
[0012] Preferably, the level shifting circuit includes at least a level shifter, the input of which is connected to a signal input, and the output of which is connected to a third connection point.
[0013] In some more specific implementations, the third driving circuit includes a fifth transistor and a sixth transistor. The source of the fifth transistor is connected to VDD, and the gate of the fifth transistor is connected to the gate of the sixth transistor to a fifth connection point, which is the input terminal of the third driving circuit. The drain of the fifth transistor is connected to the drain of the sixth transistor to a sixth connection point, which is the output terminal of the third driving circuit. The source of the sixth transistor is connected to VSS.
[0014] In some more specific implementations, the first transistor is a first PMOS transistor, the second transistor is a first NMOS transistor; the third transistor is a second PMOS transistor, the fourth transistor is a second NMOS transistor; the fifth transistor is a third PMOS transistor, and the sixth transistor is a third NMOS transistor.
[0015] In some more specific implementations, the first and second transistors operate in the linear region when they are in the ON state and in the cutoff region when they are in the OFF state. The third and fourth transistors operate in the linear region when they are in the ON state and in the cutoff region when they are in the OFF state. The fifth and sixth transistors operate in the linear region when they are in the ON state and in the cutoff region when they are in the OFF state.
[0016] A second aspect of the present invention provides a half-bridge circuit, comprising: an upper bridge arm, a lower bridge arm, and a drive separation circuit for the upper and lower bridge arms, wherein the upper bridge arm and the lower bridge arm are respectively connected to the drive separation circuit for the upper and lower bridge arms. The upper bridge arm is a seventh transistor, and the lower bridge arm is an eighth transistor.
[0017] Compared with the prior art, the advantages of the present invention include at least the following:
[0018] This invention provides a separate drive circuit for upper and lower bridge arms. A first integrated circuit can be closely adjacent to the upper bridge arm power device, and a second integrated circuit can be closely adjacent to the lower bridge arm power device. By optimizing the PCB layout and shortening the distance between devices, the loop area of the switching power supply topology is minimized, and the DC resistance and stray inductance of the board traces are reduced to a minimum. Furthermore, it improves system performance and reliability in several ways, including increasing efficiency, reducing stress on power stage devices, and improving electromagnetic interference (EMI). Attached Figure Description
[0019] Figure 1 This is a circuit diagram of a conventional half-bridge power stage and its driving circuit.
[0020] Figure 2 This is a circuit block diagram of a conventional half-bridge power stage and its driving circuit.
[0021] Figure 3 This is a circuit diagram of an upper and lower bridge arm drive separation circuit provided in an embodiment of the present invention;
[0022] Figure 4 This is a circuit block diagram of an upper and lower bridge arm drive separation circuit provided in an embodiment of the present invention. Detailed Implementation
[0023] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate this technical solution, its implementation process, and its principles.
[0024] Please refer to Figure 3A half-bridge circuit includes: an upper bridge arm, a lower bridge arm, and a drive separation circuit for the upper and lower bridge arms. The drive separation circuit for the upper and lower bridge arms includes a first integrated circuit and a second integrated circuit.
[0025] The first integrated circuit includes a first driving circuit, and the second integrated circuit includes a second driving circuit, a level shifting circuit, and a third driving circuit. The input terminal of the level shifting circuit is connected to the input terminal of the third driving circuit, and the connection point is a signal input terminal. The output terminal LO of the third driving circuit is connected to the lower bridge arm to control the operating state of the lower bridge arm. The output terminal of the level shifting circuit is connected to the input terminal of the second driving circuit, the output terminal HSo of the second driving circuit is connected to the input terminal HSi of the first driving circuit, and the output terminal HO of the first driving circuit is connected to the upper bridge arm to control the operating state of the upper bridge arm.
[0026] In this design, the upper and lower bridge drivers are separated, meaning independent integrated circuits are used to drive the upper and lower bridge arms respectively. The first integrated circuit includes a high-side driver and a high-side cascaded stage. The second integrated circuit includes a high-side cascaded pre-stage, a level shifter, and a low-side driver. This design allows the second integrated circuit to be compactly placed next to the lower bridge power devices, while the first integrated circuit can be mounted close to the upper bridge power devices. This layout optimizes circuit performance, helps reduce overall board space, and improves system stability and efficiency.
[0027] Figure 3 In the diagram, the upper dashed ellipse represents the first integrated circuit, and the lower dashed ellipse represents the second integrated circuit. Furthermore, the upper and lower solid boxes are the borders of the first and second integrated circuits, respectively, indicating that they are integrated. The intersections of circuit lines and the borders are I / O (input / output) ports. The ports are labeled on the solid boxes.
[0028] The first integrated circuit has four necessary ports: HSi, HB, HO, and VS. The second integrated circuit has seven necessary ports: IN, HB, HSo, VS, VDD, LO, and VSS. In this design, the first, second, and third driving circuits are all output-stage inverters. The output-stage inverter includes one PMOS transistor and one NMOS transistor, with their drains connected. The source of the PMOS transistor is connected to a floating power supply, and the source of the NMOS transistor is connected to a floating ground.
[0029] Specifically, the first driving circuit includes a first transistor PM1 and a second transistor NM1. The source of the first transistor PM1 is connected to HB, which is a power supply port, and the gate of the first transistor PM1 is connected to the gate of the second transistor NM1 at a first connection point. Figure 3The first connection point is the input terminal HSi of the first driving circuit; the drain of the first transistor PM1 is connected to the drain of the second transistor NM1 to the second connection point (1). Figure 3 (2) The second connection point is the output terminal HO of the first driving circuit, which is connected to the lower bridge arm and used to control the working state of the lower bridge arm; the source of the second transistor NM1 is connected to the power supply VS. When the first transistor PM1 and the second transistor NM1 are in the on state, they operate in the linear region, and when they are in the off state, they operate in the cutoff region.
[0030] The second driving circuit includes a third transistor PM2 and a fourth transistor NM2. The source of the third transistor PM2 is connected to HB, and the gate of the third transistor PM2 is connected to the gate of the fourth transistor NM2 to a third connection point. Figure 3 The third connection point ("3") is the input terminal of the second driving circuit; the drain of the third transistor PM2 is connected to the drain of the fourth transistor NM2 to the fourth connection point ( Figure 3 (4) The fourth connection point is the output terminal HSo of the second driving circuit; the source of the fourth transistor NM2 is connected to the power supply VS. When the third transistor PM2 and the fourth transistor NM2 are in the on state, they operate in the linear region, and when they are in the off state, they operate in the cutoff region.
[0031] The third driving circuit includes a fifth transistor PM3 and a sixth transistor NM3. The source of the fifth transistor PM3 is connected to VSS, and the gate of the fifth transistor PM3 is connected to the gate of the sixth transistor NM3 to the fifth connection point. Figure 3 The fifth connection point ("5") is the input terminal of the third driving circuit; the drain of the fifth transistor PM3 is connected to the drain of the sixth transistor NM3 at the sixth connection point ( Figure 3 The sixth connection point ("6") is the output terminal LO of the third drive circuit, connected to the lower bridge arm, and used to control the working state of the lower bridge arm; the source of the sixth transistor NM3 is connected to a negative voltage NEG. When the fifth transistor PM3 and the sixth transistor NM3 are in the on state, they operate in the linear region; when they are in the off state, they operate in the cutoff region.
[0032] The level shifting circuit includes a level shifter NOT whose input terminal is the signal input terminal IN. The input terminal of the level shifter NOT is also connected to the fifth connection point. The output terminal of the level shifter NOT is connected to the third connection point.
[0033] In summary, this application proposes a half-bridge circuit with separate upper and lower bridge drivers. The overall driver circuit adopts a scheme of half-bridge driver IC plus bridge driver IC, where the high-side drive section of the half-bridge driver IC serves as the front stage, and the upper bridge driver IC is cascaded in the rear stage. The half-bridge driver IC can be placed adjacent to the lower bridge power device, and the upper bridge driver IC can be placed adjacent to the upper bridge power device. By optimizing the PCB layout and shortening the distance between components, the loop area of the switching power supply topology is minimized, and the DC resistance and stray inductance of the board traces are reduced to a minimum, thereby improving the system's performance and reliability in multiple aspects.
[0034] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.
Claims
1. A drive separation circuit for upper and lower bridge arms, characterized in that, It includes a first integrated circuit and a second integrated circuit, wherein the first integrated circuit includes at least a first driving circuit, and the second integrated circuit includes at least a second driving circuit, a level shifting circuit, and a third driving circuit. The input terminal of the level shifting circuit is connected to the input terminal of the third driving circuit, and the connection point is a signal input terminal; the output terminal of the third driving circuit is connected to the lower bridge arm to control the working state of the lower bridge arm; the output terminal of the level shifting circuit is connected to the input terminal of the second driving circuit, the output terminal of the second driving circuit is connected to the input terminal of the first driving circuit, and the output terminal of the first driving circuit is connected to the upper bridge arm to control the working state of the upper bridge arm.
2. The upper and lower bridge arm drive separation circuit according to claim 1, characterized in that, The first driving circuit includes a first transistor and a second transistor. The source of the first transistor is connected to HB, which supplies power to the first transistor. The gate of the first transistor and the gate of the second transistor are connected to a first connection point, which is the input terminal of the first driving circuit. The drain of the first transistor and the drain of the second transistor are connected to a second connection point, which is the output terminal of the first driving circuit. The source of the second transistor is connected to a power supply.
3. The upper and lower bridge arm drive separation circuit according to claim 1, characterized in that, The second driving circuit includes a third transistor and a fourth transistor. The source of the third transistor is connected to HB, and the gate of the third transistor is connected to the gate of the fourth transistor to a third connection point, which is the input terminal of the second driving circuit. The drain of the third transistor is connected to the drain of the fourth transistor to a fourth connection point, which is the output terminal of the second driving circuit. The source of the fourth transistor is connected to a power supply.
4. The upper and lower bridge arm drive separation circuit according to claim 3, characterized in that, The level shifting circuit includes at least a level shifter, the input of which is connected to a signal input, and the output of which is connected to a third connection point.
5. The upper and lower bridge arm drive separation circuit according to claim 1, characterized in that, The third driving circuit includes a fifth transistor and a sixth transistor. The source of the fifth transistor is connected to a power supply, and the gate of the fifth transistor is connected to the gate of the sixth transistor to a fifth connection point, which is the input terminal of the third driving circuit. The drain of the fifth transistor is connected to the drain of the sixth transistor to a sixth connection point, which is the output terminal of the third driving circuit. The source of the sixth transistor is grounded.
6. The upper and lower bridge arm drive separation circuit according to claim 1, characterized in that, The first transistor is a first PMOS transistor, and the second transistor is a first NMOS transistor; And / or, the third transistor is a second PMOS transistor and the fourth transistor is a second NMOS transistor; And / or, the fifth transistor is a third PMOS transistor and the sixth transistor is a third NMOS transistor.
7. The upper and lower bridge arm drive separation circuit according to claim 1, characterized in that, When the first transistor and the second transistor are in the on state, they operate in the linear region, and when they are in the off state, they operate in the cutoff region.
8. The upper and lower bridge arm drive separation circuit according to claim 1, characterized in that, When the third and fourth transistors are in the on state, they operate in the linear region; when they are in the off state, they operate in the cutoff region.
9. The upper and lower bridge arm drive separation circuit according to claim 1, characterized in that, When the fifth and sixth transistors are in the on state, they operate in the linear region, and when they are in the off state, they operate in the cutoff region.
10. A half-bridge circuit, characterized in that, include: The upper bridge arm, the lower bridge arm, and the upper and lower bridge arm drive separation circuits as described in claims 1-7, wherein the upper bridge arm and the lower bridge arm are respectively connected to the upper and lower bridge drive separation circuits.