Cascaded bidirectional gallium nitride device
Patent Information
- Application Number
- CN202611485893.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-09-23
- Publication Date
- 2026-10-30
AI Technical Summary
但Bi-GaN器件的衬底若在换流期间处于“浮置”或偏置错误，会引起动态电阻增加，在运行过程中会发生温升过高损坏的风险
[0007]可见，本发明实施例的级联型的双向氮化镓器件中，串联连接的第一场效应管的第一源极连接到第二开关管的栅极，以驱动第二开关管，而第二场效应管的第二源极连接到第一开关管的栅极，以驱动第一开关管，这样由于第一源极和第二源极的电压差值，可以分别自动地驱动第二开关管和第一开关管的关断或导通，从而实现了自适应地将电路结构切换为：第二开关管或第一开关管与连接的第二场效应管或第一场效应管形成导通通路，而无需隔离供电或外部检测，简化了级联型的双向氮化镓器件的实现。
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Figure CN123019394A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic circuit technology, and in particular to a cascaded bidirectional gallium nitride device. Background Technology
[0002] Gallium nitride (GaN) is a compound semiconductor material, belonging to the third generation of semiconductor materials. It possesses excellent physical and electrical properties, such as high electron mobility, high saturation electron velocity, high breakdown electric field strength, and high thermal conductivity. These characteristics make gallium nitride a promising candidate for applications in high-frequency, high-temperature, high-power, and optoelectronic fields.
[0003] In the structure of power cascaded bidirectional depletion mode (D-mode) gallium nitride devices, the potential of the substrate (backplane) electrodes needs to be switched and clamped in real time. This is suitable for high-voltage bidirectional power commutation scenarios, such as H-bridge PFC, bidirectional single-stage AC-DC DAB, Vienna PFC, photovoltaic micro-inverters, OBC, and other scenarios.
[0004] Bilateral GaN (Bi-GaN) devices offer advantages such as low output charge, high-speed switching, full control over forward and reverse conduction, small wafer area, and low cost in high-voltage bidirectional commutation. However, if the substrate of a Bi-GaN device is "floating" or incorrectly biased during commutation, it can cause an increase in dynamic resistance, leading to a risk of overheating and damage during operation. Summary of the Invention
[0005] This invention provides a cascaded bidirectional gallium nitride device that adaptively switches circuit structures.
[0006] One embodiment of the present invention provides a cascaded bidirectional gallium nitride device, comprising: A first field-effect transistor, a bidirectional gallium nitride (GaN) device, and a second field-effect transistor are connected in series. The first gate of the bidirectional GaN device is connected to the first source of the first field-effect transistor, the second gate of the bidirectional GaN device is connected to the second source of the second field-effect transistor, a first switch is connected between the substrate electrode of the bidirectional GaN device and the first source, and a second switch is connected between the substrate electrode of the bidirectional GaN device and the second source. The gate of the first switching transistor is connected to the second source of the second field-effect transistor, and the gate of the second switching transistor is connected to the first source of the first field-effect transistor.
[0007] As can be seen, in the cascaded bidirectional gallium nitride device of this embodiment, the first source of the first field-effect transistor connected in series is connected to the gate of the second switch to drive the second switch, and the second source of the second field-effect transistor is connected to the gate of the first switch to drive the first switch. In this way, due to the voltage difference between the first source and the second source, the second switch and the first switch can be automatically turned off or turned on respectively, thereby realizing the adaptive switching of the circuit structure to: the second switch or the first switch and the connected second field-effect transistor or the first field-effect transistor form a conduction path without the need for isolated power supply or external detection, which simplifies the implementation of the cascaded bidirectional gallium nitride device. Attached Figure Description
[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0009] Figure 1 This is a schematic diagram of the circuit structure of a cascaded bidirectional gallium nitride device provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a sub-chip packaged with any switching transistor in an embodiment of the present invention; Figure 3 This is a schematic diagram of a first switching transistor and a second switching transistor being packaged into a single chip in an embodiment of the present invention; Figure 4 This is another schematic diagram of packaging any switching transistor into a sub-chip in an embodiment of the present invention; Figure 5 This is another schematic diagram of packaging the first switching transistor and the second switching transistor into a single chip in an embodiment of the present invention. Detailed Implementation
[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0011] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0012] This invention provides a cascaded bidirectional gallium nitride device, the circuit structure of which is shown in the schematic diagram below. Figure 1 As shown, it includes: A first field-effect transistor T1, a bidirectional gallium nitride device 10, and a second field-effect transistor T2 are connected in series. The first gate G11 of the bidirectional gallium nitride device 10 is connected to the first source S1 of the first field-effect transistor T1, and the second gate G22 of the bidirectional gallium nitride device is connected to the second source S2 of the second field-effect transistor T2. A first switch M1 is connected between the substrate electrode Sub of the bidirectional gallium nitride device and the first source S1, and a second switch M2 is connected between the substrate electrode Sub of the bidirectional gallium nitride device and the second source S2. In addition, the drain D1 of the first field-effect transistor T1 is connected to one source of the bidirectional gallium nitride device 10, and the drain D2 of the second field-effect transistor T2 is connected to the other source of the bidirectional gallium nitride device 10.
[0013] The gate of the first switch M1 is connected to the second source S2 of the second field-effect transistor T2, the drain of the first switch M1 is connected to the first source S1 of the first field-effect transistor T1, and the source of the first switch M1 is connected to the substrate electrode Sub; the gate of the second switch M2 is connected to the first source S1 of the first field-effect transistor T1, the drain of the second switch M2 is connected to the second source S2 of the second field-effect transistor T2, and the source of the second switch M2 is connected to the substrate electrode Sub.
[0014] In the specific implementation process, the first voltage regulator Zg1 connected between the gate and source of the first switching transistor M1 can be a Zener diode to limit the voltage between the gate and source within a safe range; the second voltage regulator Zg2 connected between the gate and source of the second switching transistor M2 can also be a Zener diode to limit the voltage between the gate and source within a safe range.
[0015] In addition, the gate of the second switch M2 is connected to the drain of the first switch M1 through a parallel circuit of resistor Rg2 and diode MD2; the gate of the first switch M1 is connected to the drain of the second switch M2 through a parallel circuit of resistor Rg1 and diode MD1.
[0016] The drain of the first switching transistor M1 is connected to the first source S1 of the first field-effect transistor T1 through a resistor Rd1, and the source of the first switching transistor M1 is connected to the substrate electrode; the drain of the second switching transistor M2 is connected to the second source S2 of the second field-effect transistor T2 through a resistor Rd2, and the source of the second switching transistor M2 is connected to the substrate electrode.
[0017] Since the drain of the first switching transistor M1 is connected to the first source S1 of the first field-effect transistor T1 and the gate of the second switching transistor M2, the first source S1 of the first field-effect transistor T1 and the gate of the second switching transistor M2 can be connected; and since the drain of the second switching transistor M2 is connected to the second source S2 of the second field-effect transistor T2 and the gate of the first switching transistor M1, the second source S2 of the second field-effect transistor T2 and the gate of the first switching transistor M1 can be connected.
[0018] In practical implementation, any switch (such as the first or second switch) connected in a cascaded bidirectional gallium nitride device can be packaged as a sub-chip. In one case, such as... Figure 2 As shown, the sub-chip includes: a source interface S for the switching transistor, a gate resistor connection interface G, a drain interface Dd, and a drain resistor connection interface D. Specifically, in implementing this sub-chip, the gate of the switching transistor may be connected to a parallel circuit of a resistor and a diode, and the drain of the switching transistor may be connected to another resistor. The connection interface after the gate of the switching transistor is connected to the parallel circuit is the aforementioned gate resistor connection interface G, and the connection interface after the drain of the switching transistor is connected to the other resistor is the aforementioned drain resistor connection interface D.
[0019] Furthermore, the sub-chips of the first switching transistor M1 and the second switching transistor M2 are packaged into the same chip, such as... Figure 3As shown, the gate resistor connection interface G-1 of the first switch M1 is connected to the drain interface Dd-2 of the second switch M2, and the gate resistor connection interface G-2 of the second switch M2 is connected to the drain interface Dd-1 of the first switch M1. The source interface S-1 and drain resistor connection interface D-1 of the first switch M1, as well as the source interface S-2 and drain resistor connection interface D-2 of the first switch M1, serve as external interfaces for the packaged chip, thus the chip includes four external interfaces. The source interface S-1 of the first switch M1 and the source interface S-2 of the second switch M2 are then connected to the substrate electrode Sub. The drain resistor connection interface D-1 of the first switch M1 is connected to the first source S1 of the first field-effect transistor T1, and the drain resistor connection interface D-2 of the second switch M2 is connected to the second source S2 of the second field-effect transistor T2, thus forming the cascaded bidirectional gallium nitride device in this embodiment.
[0020] In another case, such as Figure 4 As shown, the sub-chip includes: a source interface S, a gate interface Gg, a drain circuit connection interface DL, and a drain resistor connection interface D for the switching transistor. Specifically, in implementing this sub-chip, the drain of the switching transistor may be connected to a parallel circuit of a resistor and a diode. The drain of the switching transistor may also be connected to another resistor. The connection interface after the drain of the switching transistor is connected to the parallel circuit is the aforementioned drain circuit connection interface DL, and the connection interface after the drain of the switching transistor is connected to the other resistor is the aforementioned drain resistor connection interface D.
[0021] In this case, the sub-chip of the first switch M1 and the sub-chip of the second switch M2 are packaged into the same chip, such as... Figure 5 As shown, the gate interface Gg-1 of the first switch M1 is connected to the drain circuit connection interface DL-2 of the second switch M2, and the gate interface Gg-2 of the second switch M2 is connected to the drain circuit connection interface DL-1 of the first switch M1. The source interface S-1 and drain resistor connection interface D-1 of the first switch M1, and the source interface S-2 and drain resistor connection interface D-2 of the first switch M1 serve as external interfaces for the packaged chip, thus the chip includes four external interfaces. The source interface S-1 of the first switch M1 and the source interface S-2 of the second switch M2 are then connected to the substrate electrode Sub. The drain resistor connection interface DL-1 of the first switch M1 is connected to the first source S1 of the first field-effect transistor T1, and the drain resistor connection interface DL-2 of the second switch M2 is connected to the second source S2 of the second field-effect transistor T2, thus forming the cascaded bidirectional gallium nitride device in this embodiment.
[0022] The first switch M1 and the second switch M2 can be packaged into the same chip using the two methods described above. In this way, the cascaded bidirectional gallium nitride device of the present invention can be realized simply by connecting the external interface of the chip to the first and second field-effect transistors, which can greatly simplify the fabrication process of the cascaded bidirectional gallium nitride device.
[0023] Thus, the cascaded bidirectional gallium nitride device of this embodiment can adaptively switch circuit structures, specifically: (1) In the zero current or equilibrium state, that is, the voltage of the first source S1 of the first field-effect transistor T1 is equal to or close to the voltage of the second source S2 of the second field-effect transistor T2. The gate-source voltages of both the first switch M1 and the second switch M2 are close to 0, indicating that they are either in the weak conduction or subthreshold region, or completely off.
[0024] (2) Forward voltage state, that is, the potential of the first source S1 of the first field-effect transistor T1 is higher than the potential of the second source S2 of the second field-effect transistor T2. The voltage at the first source S1 of the first field-effect transistor T1 is conducted to the gate of the second switch M2 through resistors Rd1 and Rg2. The gate-source voltage VgsM2 of the second switch M2 (the voltage value of the gate-source voltage VgsM2 is limited by the second regulator Zg2) is higher than the threshold voltage of the second switch M2, so the second switch M2 is turned on, and the substrate electrode Sub is equal to the low potential of the second source S2.
[0025] The voltage at the second source S2 of the second field-effect transistor T2 is conducted to the gate of the first switching transistor M1 through resistors Rd2 and Rg1. The gate-source voltage VgsM1 of the first switching transistor M1 is lower than the threshold voltage of the first switching transistor M1, so the first switching transistor M1 is turned off, and the substrate electrode Sub is disconnected from the first source S1.
[0026] (3) Reverse voltage state, that is, the potential of the first source S1 of the first field-effect transistor T1 is lower than the potential of the second source S2 of the second field-effect transistor T2. The voltage at the second source S2 of the second field-effect transistor T2 is conducted to the gate of the first switching transistor M1 through resistors Rd2 and Rg1. The gate-source voltage VgsM1 of the first switching transistor M1 (the voltage value of the gate-source voltage VgsM1 is limited by the first voltage regulator Zg1) is higher than the threshold voltage of the first switching transistor M1, so the first switching transistor M1 is turned on, and the substrate electrode Sub is equal to the low potential of the first source S1.
[0027] The voltage at the first source S1 of the first field-effect transistor T1 is conducted to the gate of the second switch M2 through resistors Rd1 and Rg2. When the gate-source voltage VgsM2 of the second switch M2 is lower than the threshold voltage of the second switch M2, the second switch M2 is turned off, and the substrate electrode Sub is disconnected from the second source S2.
[0028] (4) Dynamic commutation, i.e. zero-crossing reversal, i.e. the voltage difference between the first source S1 of the first field-effect transistor T1 and the second source S2 of the second field-effect transistor T2 crosses zero. The previously conducting switch exits saturation, and its drain is pulled up by the resistor to restore its potential. Once the differential voltage reverses, the other switch receives a positive voltage and begins to conduct, forming a strong positive feedback competition. The drains of the two switches complete complementary flipping, outputting a new direction logic.
[0029] As can be seen, in the cascaded bidirectional gallium nitride device of this embodiment, the first source of the first field-effect transistor connected in series is connected to the gate of the second switch to drive the second switch, and the second source of the second field-effect transistor is connected to the gate of the first switch to drive the first switch. In this way, due to the voltage difference between the first source and the second source, the second switch and the first switch can be automatically turned off or turned on respectively, thereby realizing the adaptive switching of the circuit structure to: the second switch or the first switch and the connected second field-effect transistor or the first field-effect transistor form a conduction path without the need for isolated power supply or external detection, which simplifies the implementation of the cascaded bidirectional gallium nitride device.
[0030] The foregoing has provided a detailed description of a cascaded bidirectional gallium nitride device provided by the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.
Claims
1. A cascaded bidirectional gallium nitride device, characterized in that, include: A first field-effect transistor, a bidirectional gallium nitride (GaN) device, and a second field-effect transistor are connected in series. The first gate of the bidirectional GaN device is connected to the first source of the first field-effect transistor, the second gate of the bidirectional GaN device is connected to the second source of the second field-effect transistor, a first switch is connected between the substrate electrode of the bidirectional GaN device and the first source, and a second switch is connected between the substrate electrode of the bidirectional GaN device and the second source. The gate of the first switching transistor is connected to the second source of the second field-effect transistor, and the gate of the second switching transistor is connected to the first source of the first field-effect transistor.
2. The cascaded bidirectional gallium nitride device as described in claim 1, characterized in that, A first Zener diode is connected between the gate and source of the first switching transistor, and a second Zener diode is connected between the gate and source of the second switching transistor.
3. The cascaded bidirectional gallium nitride device as described in claim 1, characterized in that, The gate of the second switching transistor is connected to the drain of the first switching transistor through a parallel circuit of a resistor and a diode; The gate of the first switching transistor is connected to the drain of the second switching transistor through a resistor and a diode in parallel circuit.
4. The cascaded bidirectional gallium nitride device as described in claim 3, characterized in that, The drain of the first switching transistor is connected to the first source through a resistor, and the source of the first switching transistor is connected to the substrate electrode. The drain of the second switch is connected to the second source through a resistor, and the source of the second switch is connected to the substrate electrode.
5. The cascaded bidirectional gallium nitride device as described in claim 4, characterized in that, The chip includes a first switch and a second switch, the chip comprising two sub-chips, each sub-chip including: a source interface, a gate resistor connection interface, a drain interface, and a drain resistor connection interface for each switch, wherein: The gate resistor connection interface of any sub-chip is connected to the drain interface of another sub-chip, and the source interface and drain resistor connection interface of any sub-chip are both used as external interfaces of the chip. The source interface of any switch in the chip is connected to the substrate electrode. The drain resistor connection interface of the first switch in the chip is connected to the first source of the first field-effect transistor, and the drain resistor connection interface of the second switch is connected to the second source of the second field-effect transistor.
6. The cascaded bidirectional gallium nitride device as described in claim 5, characterized in that, Each of the sub-chips includes: The gate of any of the aforementioned switching transistors is connected to a parallel circuit of a resistor and a diode, and the gate resistor connection interface in the sub-chip is the connection interface after the gate of the switching transistor is connected to the parallel circuit. Each of the sub-chips further includes a drain of any switching transistor connected to another resistor, and the drain resistor connection interface of the sub-chip is the connection interface after the drain of any switching transistor is connected to another resistor.
7. The cascaded bidirectional gallium nitride device as described in claim 4, characterized in that, The chip includes a first switch and a second switch, the chip comprising two sub-chips, each sub-chip including: a source interface, a gate interface, a drain circuit connection interface, and a drain resistor connection interface for each switch, wherein: The gate interface of any sub-chip is connected to the drain circuit connection interface of another sub-chip, and the source interface and drain resistor connection interface of any sub-chip are both used as external interfaces of the chip. The source interface of any switch in the chip is connected to the substrate electrode. The drain resistor connection interface of the first switch in the chip is connected to the first source of the first field-effect transistor, and the drain resistor connection interface of the second switch is connected to the second source of the second field-effect transistor.
8. The cascaded bidirectional gallium nitride device as described in claim 7, characterized in that, Each of the sub-chips includes: The drain of any of the aforementioned switching transistors is connected to a parallel circuit of a resistor and a diode, and the drain circuit connection interface in the sub-chip is the connection interface after the drain of the switching transistor is connected to the parallel circuit. Each sub-chip also includes a drain of any switching transistor connected to another resistor, and the drain resistor connection interface of the sub-chip is the connection interface after the drain of any switching transistor is connected to another resistor.
9. The cascaded bidirectional gallium nitride device according to any one of claims 1 to 8, characterized in that, When the voltage of the first source is higher than the voltage of the second source, the second switch is turned on and the first switch is turned off.
10. The cascaded bidirectional gallium nitride device according to any one of claims 1 to 8, characterized in that, When the voltage of the first source is lower than the voltage of the second source, the first switch is turned on and the second switch is turned off.