Power supply regulator circuit and method

Abstract

The application discloses a power supply voltage stabilizing circuit and method, and relates to the field of IC integrated circuit design. According to the technical scheme, a delay signal is generated by a driving circuit and combined with control logic to generate a compensation sharp feedback signal, which is coupled to the gate of a first LDMOS power tube through a first capacitor, and the gate potential is actively lifted by using the characteristic that the capacitor voltage cannot be suddenly changed, so that the power supply VDP transient drop caused by the charging of the input capacitor at the moment when the main power tube is turned on is compensated. The structure can maintain the dynamic stability of VDP without relying on a large-capacity energy storage capacitor, significantly reduces the chip layout area and manufacturing cost, effectively suppresses the VDP decay amplitude, avoids the main power tube from entering the saturation region to increase the conduction loss, improves the system conversion efficiency and reliability, and the compensation pulse width can be adaptively adjusted according to the load current, so that the voltage stabilizing precision and response speed under different working conditions are considered.

Description

Technical Field

[0001] This invention relates to the field of IC integrated circuit design technology, and in particular to a power supply voltage regulator circuit and method. Background Technology

[0002] With the rapid development of integrated circuits and wireless sensor networks, power management chips that supply power to interconnected nodes are widely used in consumer electronics, industrial control, automotive electronics, and other fields. The requirements for their operational stability, cost, and reliability are also increasing. In power management chips, the stability of the power supply VDP acting on the main power transistor is particularly critical. It not only affects whether the power transistor can turn on normally but also directly impacts the conversion efficiency of the entire system. In severe cases, abnormal voltage can even cause the device to burn out due to overstress, posing a significant safety hazard. Therefore, existing power supplies typically employ methods such as Zener diode breakdown clamping, linear regulators (LDOs), or built-in power clamping to generate and stabilize power. Figure 1 As shown, all of the above solutions require an additional, sufficiently large energy storage capacitor C11 to maintain a stable power supply voltage, which is a common practice in the industry.

[0003] However, the aforementioned existing technical solutions still have some shortcomings: on the one hand, the required large-capacity capacitor C11 occupies a large area of ​​the chip layout, directly increasing the chip manufacturing cost; on the other hand, such as Figure 2 As shown, under conditions requiring high drive capability and with large transient current during main power transistor switching, even with a large capacitor, the power supply VDP still experiences a significant voltage drop at the moment the power transistor turns on, resulting in limited voltage regulation and poor dynamic stability. To prevent the power transistor from entering the saturation region due to voltage drops and causing excessive heat generation, existing technologies often require additional auxiliary modules such as undervoltage protection circuits, further increasing circuit complexity and production costs. Therefore, how to achieve effective voltage regulation of the power supply VDP and suppress voltage drop during switching transients at a lower cost without relying on large-capacity capacitors has become a pressing technical problem to be solved in this field. Summary of the Invention

[0004] The purpose of this invention is to provide a power supply voltage regulation circuit and method to solve the problems existing in the prior art.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows: In a first aspect, the present invention provides a power supply voltage regulator circuit, comprising: a power supply clamping circuit B41, a driving circuit B42, a delay feedback circuit B43, a first capacitor C41, a first LDMOS power transistor N41, a first dummy load NMOS transistor N48, and a first anti-static resistor R46. The first terminal of the first anti-static resistor R46 is connected to the input power supply VIN, and the second terminal of the first anti-static resistor R46 is connected to the drain of the first LDMOS power transistor N41; the gate of the first LDMOS power transistor N41 is connected to the gate terminal of the first capacitor C41, and the source of the first LDMOS power transistor N41 is connected to the drain of the first dummy load NMOS transistor N48, so as to provide a power supply voltage VDP at the source of the first LDMOS power transistor N41; The input terminal of the driving circuit B42 is used to receive the driving control signal PWM, and the output terminal of the driving circuit B42 is used to output the driving signal LSG and is connected to the input terminal of the delay feedback circuit B43. The output terminal of the delay feedback circuit B43 outputs the compensation spike feedback signal LSGFB and is connected to the substrate terminal of the first capacitor C41. The compensation spike feedback signal LSGFB is coupled to the gate of the first LDMOS power transistor N41 through the first capacitor C41 to compensate for the instantaneous drop of the power supply voltage VDP. The power supply clamping circuit B41 is connected to the gate of the first LDMOS power transistor N41 and is used to clamp the gate potential of the first LDMOS power transistor N41 to indirectly stabilize the power supply voltage VDP; the source of the first dummy load NMOS transistor N48 is connected to analog ground AGND.

[0006] In some embodiments, the power supply clamping circuit B41 includes a first bias current source IBP41, a first NMOS transistor N40, a second NMOS transistor N42, a third NMOS transistor N43, a fourth NMOS transistor N44, a fifth NMOS transistor N49, a first PMOS transistor P41, a second PMOS transistor P42, a second discharge clamping transistor P47, a first resistor R41, a second resistor R42, a third resistor R43, and a fourth resistor R44. The first terminal of the first bias current source IBP41 is connected to the chip's built-in power supply VDD, and the second terminal of the first bias current source IBP41 is connected to the gate and drain of the first NMOS transistor N40, the gate of the fifth NMOS transistor N49, and the gate of the first dummy load NMOS transistor N48; the source of the first NMOS transistor N40, the source of the fifth NMOS transistor N49, and the source of the first dummy load NMOS transistor N48 are all connected to the analog ground AGND; The drain of the fifth NMOS transistor N49 is connected to the source of the fourth NMOS transistor N44 and the drain of the second discharge clamp transistor P47; the gate of the fourth NMOS transistor N44 and the source of the second discharge clamp transistor P47 are both connected to the chip's built-in power supply VDD; the drain of the fourth NMOS transistor N44 is connected to the first end of the third resistor R43, and the second end of the third resistor R43 is connected to the gate and drain of the first PMOS transistor P41 and the gate of the second PMOS transistor P42; The source of the first PMOS transistor P41 is connected to the first end of the first resistor R41, and the source of the second PMOS transistor P42 is connected to the first end of the second resistor R42. The second ends of both the first resistor R41 and the second resistor R42 are connected to the input power supply VIN. The drain of the second PMOS transistor P42 is connected to the first end of the fourth resistor R44. The second end of the fourth resistor R44 is connected to the gate and drain of the third NMOS transistor N43, the gate of the first capacitor C41, the gate of the first LDMOS power transistor N41, and the gate and drain of the first discharge clamp transistor N45. The source of the third NMOS transistor N43 is connected to the gate and drain of the second NMOS transistor N42, and the source of the second NMOS transistor N42 is connected to the chip's built-in power supply VDD.

[0007] In some embodiments, the source of the first discharge clamping transistor N45 is connected to the source of the first LDMOS power transistor N41 and the drain of the first dummy load NMOS transistor N48, so as to discharge the potential at the gate of the first capacitor C41 to the power supply voltage VDP when the power supply voltage VDP exceeds the clamping threshold.

[0008] In some embodiments, the drive circuit B42 includes a first inverter INV41, a seventh NMOS transistor N47, a sixth NMOS transistor N46, an eighth NMOS transistor N410, a ninth NMOS transistor N411, a tenth NMOS transistor N412, an eleventh NMOS transistor N413, a twelfth NMOS transistor N414, a thirteenth NMOS transistor N415, a fourth PMOS transistor P43, a fifth PMOS transistor P44, a sixth PMOS transistor P410, a seventh PMOS transistor P411, an eighth PMOS transistor P412, a ninth PMOS transistor P413, a tenth PMOS transistor P414, an eleventh PMOS transistor P415, a fifth resistor R45, a high-side LDMOS power transistor N416, and a low-side LDMOS power transistor N417. The drive control signal PWM is connected to the gate of the seventh NMOS transistor N47 and the input of the first inverter INV41. The drain of the seventh NMOS transistor N47 is connected to the drain of the fourth PMOS transistor P43 and the gate of the fifth PMOS transistor P44, and is output to the delay feedback circuit B43. The drain of the fifth PMOS transistor P44 is connected to the gate of the fourth PMOS transistor P43, the drain of the sixth NMOS transistor N46, the gate of the sixth PMOS transistor P410, and the gate of the eighth NMOS transistor N410. The drain of the sixth PMOS transistor P410 is connected to the drain of the eighth NMOS transistor N410, the gate of the seventh PMOS transistor P411, and the gate of the ninth NMOS transistor N411. The drain of the seventh PMOS transistor P411 is connected to the drain of the ninth NMOS transistor N411, the gate of the eighth PMOS transistor P412, and the gate of the tenth NMOS transistor N412. The drain of the eighth PMOS transistor P412 is connected to the drain of the tenth NMOS transistor N412, the gate of the ninth PMOS transistor P413, and the gate of the eleventh NMOS transistor N413. The drain of the ninth PMOS transistor P413 is connected to the drain of the eleventh NMOS transistor N413, the gate of the tenth PMOS transistor P414, and the gate of the twelfth NMOS transistor N414. The drain of the tenth PMOS transistor P414 is connected to the drain of the twelfth NMOS transistor N414, the gate of the eleventh PMOS transistor P415, and the gate of the thirteenth NMOS transistor N415. The drain of the eleventh PMOS transistor P415 is connected to the drain of the thirteenth NMOS transistor N415, the first terminal of the fifth resistor R45, and the gate of the low-side LDMOS power transistor N417 to output the drive signal LSG; the second terminal of the fifth resistor R45 is connected to power ground PGND. The sources of the sixth NMOS transistor N46, the seventh NMOS transistor N47, the eighth NMOS transistor N410, the ninth NMOS transistor N411, the tenth NMOS transistor N412, the eleventh NMOS transistor N413, the twelfth NMOS transistor N414, and the thirteenth NMOS transistor N415 are all connected to the power ground PGND, and the sources of the fourth PMOS transistor P43, the fifth PMOS transistor P44, the sixth PMOS transistor P410, the seventh PMOS transistor P411, the eighth PMOS transistor P412, the ninth PMOS transistor P413, the tenth PMOS transistor P414, and the eleventh PMOS transistor P415 are all connected to the power supply voltage VDP; The drain of the low-side LDMOS power transistor N417 is connected to the source of the high-side LDMOS power transistor N416, and the source of the low-side LDMOS power transistor N417 is connected to the power ground PGND; the gate of the high-side LDMOS power transistor N416 is connected to the high-side drive output signal HSG, and the drain of the high-side LDMOS power transistor N416 is connected to the input power supply VIN.

[0009] In some embodiments, the delay feedback circuit B43 includes a twelfth PMOS transistor P418, a thirteenth PMOS transistor P419, a fourteenth PMOS transistor P420, a fifteenth PMOS transistor P421, a sixteenth PMOS transistor P422, a seventeenth PMOS transistor P423, an eighteenth PMOS transistor P424, a nineteenth PMOS transistor P425, a fourteenth NMOS transistor N418, a fifteenth NMOS transistor N419, a sixteenth NMOS transistor N420, a seventeenth NMOS transistor N421, an eighteenth NMOS transistor N422, a nineteenth NMOS transistor N423, a twentieth NMOS transistor N424, a twenty-first NMOS transistor N425, a twenty-second NMOS transistor N426, a twenty-third NMOS transistor N427, a sixth resistor R47, and a second capacitor C42. The sixth resistor R47 and the second capacitor C42 constitute an RC delay circuit. The drive signal LSG is connected to the gate of the twelfth PMOS transistor P418, the gate of the fourteenth NMOS transistor N418, and the gate of the fifteenth NMOS transistor N419; the drain of the twelfth PMOS transistor P418 is connected to the drain of the fourteenth NMOS transistor N418, the drain of the fifteenth NMOS transistor N419, the gate of the thirteenth PMOS transistor P419, and the gate of the seventeenth NMOS transistor N421; the source of the fifteenth NMOS transistor N419 is connected to the gate of the thirteenth PMOS transistor P419. The drain of the sixteenth NMOS transistor N420 is connected; the drain of the thirteenth PMOS transistor P419 is connected to the first end of the sixth resistor R47, and the second end of the sixth resistor R47 is connected to the drain of the seventeenth NMOS transistor N421, the gate of the sixteenth NMOS transistor N420, the positive terminal of the second capacitor C42, the gate of the sixteenth PMOS transistor P422, and the gate of the twentieth NMOS transistor N424. After being delayed by the RC delay circuit, the delayed signal LSG_dly is obtained. The gate of the fourteenth PMOS transistor P420 is connected to the gate of the eighteenth NMOS transistor N422 and the drain of the seventh NMOS transistor N47 to receive the drive control signal PWM; the drain of the fourteenth PMOS transistor P420 is connected to the drain of the eighteenth NMOS transistor N422, the gate of the fifteenth PMOS transistor P421, and the gate of the nineteenth NMOS transistor N423; the drain of the fifteenth PMOS transistor P421 is connected to the drain of the nineteenth NMOS transistor N423, the drain of the twentieth NMOS transistor N424, the gate of the nineteenth PMOS transistor P425, and the gate of the twenty-first NMOS transistor N425; the sixteenth PMOS transistor P42... The drain of transistor 2 is connected to the source of the nineteenth PMOS transistor P425; the drain of the nineteenth PMOS transistor P425 is connected to the drain of the twenty-first NMOS transistor N425, the gate of the seventeenth PMOS transistor P423, and the gate of the twenty-second NMOS transistor N426; the drain of the seventeenth PMOS transistor P423 is connected to the drain of the twenty-second NMOS transistor N426, the gate of the eighteenth PMOS transistor P424, and the gate of the twenty-third NMOS transistor N427; the drain of the eighteenth PMOS transistor P424 is connected to the drain of the twenty-third NMOS transistor N427, and the compensation spike feedback signal LSGFB is output to the substrate of the first capacitor C41.

[0010] In some embodiments, the source terminals of the twelfth PMOS transistor P418, the thirteenth PMOS transistor P419, the fourteenth PMOS transistor P420, the fifteenth PMOS transistor P421, the sixteenth PMOS transistor P422, the seventeenth PMOS transistor P423, and the eighteenth PMOS transistor P424 are all connected to the power supply voltage VDP, and the source terminals of the fourteenth NMOS transistor N418, the sixteenth NMOS transistor N420, the seventeenth NMOS transistor N421, the eighteenth NMOS transistor N422, the nineteenth NMOS transistor N423, the twentieth NMOS transistor N424, the twenty-first NMOS transistor N425, the twenty-second NMOS transistor N426, and the twenty-third NMOS transistor N427 are all connected to the power ground PGND.

[0011] In some embodiments, when the drive signal LSG flips from low to high, the delay signal LSG_dly flips from low to high after a delay time determined by the RC delay circuit; during the delay time, the delay signal LSG_dly combines with the drive control signal PWM to generate the compensation spike feedback signal LSGFB. The compensation spike feedback signal LSGFB is coupled to the gate of the first LDMOS power transistor N41 through the first capacitor C41, causing the gate potential of the first capacitor C41 to rise, thereby compensating for the fading of the power supply voltage VDP at the moment the low-side LDMOS power transistor N417 is turned on.

[0012] In some implementations, the larger the instantaneous charging current of the input capacitor Ciss of the low-side LDMOS power transistor N417, the longer the delay time of the RC delay circuit becomes, in order to provide a larger compensation spike feedback voltage.

[0013] Secondly, the present invention provides a power supply voltage regulation method, applied to the power supply voltage regulation circuit described above, the method comprising: The driving circuit B42 receives the driving control signal PWM and outputs the driving signal LSG to the low-side LDMOS power transistor N417. When the drive control signal PWM flips from low level to high level, the power supply voltage VDP charges the input capacitor Ciss of the low-side LDMOS power transistor N417, causing the power supply voltage VDP to drop momentarily. The delay feedback circuit B43 delays the drive signal LSG to obtain the delay signal LSG_dly, and combines the delay signal LSG_dly with the drive control signal PWM to generate the compensation spike feedback signal LSGFB. The compensation spike feedback signal LSGFB is coupled to the gate of the first LDMOS power transistor N41 via the first capacitor C41, causing the gate terminal potential of the first capacitor C41 to rise, thereby compensating for the instantaneous drop in the power supply voltage VDP and keeping the power supply voltage VDP stable.

[0014] In some embodiments, the method further includes: The delay time of the RC delay circuit in the delay feedback circuit B43 is adjusted according to the input capacitance Ciss of the low-side LDMOS power transistor N417 to compensate for the instantaneous drop caused by the charging of the input capacitance Ciss. The larger the instantaneous charging current of the input capacitor Ciss, the longer the delay time of the RC delay circuit becomes, so as to provide a larger compensation spike feedback voltage.

[0015] The beneficial effects of the technical solution provided by this invention include at least the following: This technical solution generates a delayed signal through a driver circuit and combines it with control logic to generate a compensation spike feedback signal. This signal is coupled to the gate of the first LDMOS power transistor via a first capacitor. Utilizing the characteristic that capacitor voltage cannot change abruptly, the gate potential is actively raised to compensate for the instantaneous drop in power supply VDP caused by the charging of the input capacitor when the main power transistor is turned on. This structure can maintain dynamic VDP stability without relying on a large-capacity energy storage capacitor, significantly reducing chip layout area and manufacturing costs. Simultaneously, it effectively suppresses the VDP drop amplitude, preventing the main power transistor from entering the saturation region and increasing conduction losses, thus improving system conversion efficiency and reliability. Furthermore, the compensation pulse width can adaptively adjust with the load current, balancing voltage regulation accuracy and response speed under different operating conditions. Attached Figure Description

[0016] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof.

[0017] Figure 1 The schematic diagram of a traditional power supply voltage regulator circuit is shown.

[0018] Figure 2 A schematic diagram of the signal waveform of a traditional power supply voltage regulator circuit is shown.

[0019] Figure 3 The diagram shows a topology of a power supply voltage regulator circuit provided by an exemplary embodiment of the present invention.

[0020] Figure 4 A schematic diagram of a power supply voltage regulator circuit provided by an exemplary embodiment of the present invention is shown.

[0021] Figure 5 A flowchart of a power supply voltage regulation method provided by an exemplary embodiment of the present invention is shown.

[0022] Figure 6 The diagram illustrates a comparison of signal waveforms between a power supply voltage regulator circuit provided by an exemplary embodiment of the present invention and a conventional power supply voltage regulator circuit. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0025] Example 1 like Figure 3 and Figure 4 As shown, this embodiment provides a power supply voltage regulator circuit, which includes a power supply clamping circuit B41, a driving circuit B42, a delay feedback circuit B43, a first capacitor C41, a first LDMOS power transistor N41, a first dummy load NMOS transistor N48, and a first anti-static resistor R46.

[0026] The first terminal of the first anti-static resistor R46 is connected to the input power supply VIN (i.e., the external input power supply of the chip), and the second terminal of the first anti-static resistor R46 is connected to the drain of the first LDMOS power transistor N41. The first anti-static resistor R46 is connected in series between the input power supply VIN and the drain of the first LDMOS power transistor N41. During chip manufacturing, packaging, and testing, it provides electrostatic discharge protection to the gate and drain nodes of the first LDMOS power transistor N41, preventing the accumulation of electrostatic charge on the gate oxide layer of the first LDMOS power transistor N41 and thus avoiding device breakdown. This improves the circuit's anti-static capability and yield. Simultaneously, the first anti-static resistor R46 has a relatively large resistance value, resulting in a very small current flowing through it during normal circuit operation. This prevents significant static voltage drop and power consumption between the input power supply VIN and the drain of the first LDMOS power transistor N41, ensuring the circuit's high efficiency.

[0027] The gate of the first LDMOS power transistor N41 is connected to the gate of the first capacitor C41, and the source of the first LDMOS power transistor N41 is connected to the drain of the first dummy load NMOS transistor N48 to provide the power supply voltage VDP at the source of the first LDMOS power transistor N41. The first LDMOS power transistor N41 is a laterally diffused metal-oxide semiconductor device, which has strong voltage withstand capability and low on-resistance. It can withstand the high voltage of the input power supply VIN and transfer the voltage of the input power supply VIN to the source node, thereby achieving a high voltage withstand path with low device cost. The first LDMOS power transistor N41 and the first dummy load NMOS transistor N48 are connected in series to form a source follower structure. The first dummy load NMOS transistor N48 acts as the load device of the first LDMOS power transistor N41, providing a static bias current path for the power supply voltage VDP node, so that the power supply voltage VDP still has a definite potential under no-load or light-load conditions, avoiding the potential uncertainty caused by the node being floating.

[0028] The input of driver circuit B42 receives the drive control signal PWM, and the output of driver circuit B42 outputs the drive signal LSG, which is connected to the input of delay feedback circuit B43. Driver circuit B42 performs level conversion and amplifies the drive capability of the logic-level drive control signal PWM before outputting the drive signal LSG. This ensures that the drive signal LSG has sufficient voltage swing and current drive capability to drive the subsequent power switching transistor, thereby ensuring that the power switching transistor can be turned on and off quickly and completely, reducing switching losses.

[0029] The output terminal of the delay feedback circuit B43 outputs a compensation spike feedback signal LSGFB and is connected to the substrate terminal of the first capacitor C41. The compensation spike feedback signal LSGFB is coupled to the gate of the first LDMOS power transistor N41 through the first capacitor C41 to compensate for the instantaneous drop in the power supply voltage VDP. When the power switch in the subsequent stage draws a large instantaneous current from the power supply voltage VDP at the moment of turn-on, the power supply voltage VDP experiences a momentary drop. The delay feedback circuit B43 generates a compensation spike feedback signal LSGFB with a sharp peak shape. This signal is transmitted to the gate of the first LDMOS power transistor N41 through the AC coupling effect of the first capacitor C41, causing the gate potential of the first LDMOS power transistor N41 to rise accordingly. This, in turn, raises the source potential of the first LDMOS power transistor N41, i.e., the power supply voltage VDP, which precisely compensates for the aforementioned momentary drop and keeps the power supply voltage VDP stable. Since the compensation signal is transmitted by capacitive coupling, there is no need to add an additional voltage regulation loop and reference circuit. The circuit structure is simple and low in cost. Moreover, the compensation action is generated instantly at the same moment the drop occurs, resulting in fast response and timely compensation.

[0030] The power supply clamping circuit B41 is connected to the gate of the first LDMOS power transistor N41 and is used to clamp the gate potential of the first LDMOS power transistor N41 to indirectly stabilize the power supply voltage VDP. The power supply clamping circuit B41 provides a stable bias potential to the gate of the first LDMOS power transistor N41, limits the maximum value of the gate-source voltage of the first LDMOS power transistor N41, prevents the gate oxide layer of the first LDMOS power transistor N41 from being damaged due to overvoltage, and ensures that the power supply voltage VDP has a defined upper limit value, guaranteeing that the subsequent circuits operate within a safe voltage range.

[0031] The source of the first dummy load NMOS transistor N48 is connected to analog ground AGND. Together with the first LDMOS power transistor N41, the source of the first dummy load NMOS transistor N48 forms a complete current path from the input power supply VIN to analog ground AGND, enabling the first dummy load NMOS transistor N48 to provide a stable static bias current for the power supply voltage VDP node. Simultaneously, using analog ground AGND as the reference ground for this bias branch prevents the bias current from flowing through the power ground loop, avoiding power switch noise coupling into the bias branch and interfering with the potential accuracy of the power supply voltage VDP.

[0032] Example 2 like Figure 3 and Figure 4 As shown, this embodiment further defines the internal structure of the power supply clamping circuit B41 based on Embodiment 1: The power supply clamping circuit B41 includes a first bias current source IBP41, a first NMOS transistor N40, a second NMOS transistor N42, a third NMOS transistor N43, a fourth NMOS transistor N44, a fifth NMOS transistor N49, a first PMOS transistor P41, a second PMOS transistor P42, a second discharge clamping transistor P47, a first resistor R41, a second resistor R42, a third resistor R43, and a fourth resistor R44.

[0033] The first terminal of the first bias current source IBP41 is connected to the chip's built-in power supply VDD, and the second terminal of the first bias current source IBP41 is connected to the gate and drain of the first NMOS transistor N40, the gate of the fifth NMOS transistor N49, and the gate of the first dummy load NMOS transistor N48. The first bias current source IBP41 is powered by the chip's built-in power supply VDD, and its output current flows into the first NMOS transistor N40, which has its gate and drain shorted, generating a gate-source voltage on the first NMOS transistor N40. This gate-source voltage is simultaneously applied to the gates of the fifth NMOS transistor N49 and the first dummy load NMOS transistor N48, forming a current mirror structure. Since the fifth NMOS transistor N49 and the first dummy load NMOS transistor N48 replicate the current of the first NMOS transistor N40, the bias current of the clamping circuit and the quiescent current of the dummy load are both generated by mirroring the same reference current. The current value is precisely controllable and tracks changes in process and temperature consistently, thereby ensuring the stability of the static operating point of the power supply voltage VDP.

[0034] The sources of the first NMOS transistor N40, the fifth NMOS transistor N49, and the first dummy load NMOS transistor N48 are all connected to analog ground AGND. The common connection of the sources of these three devices to analog ground AGND provides a unified reference potential for the current mirror, eliminating the influence of ground potential differences on the mirror accuracy and ensuring the accuracy of the mirrored current.

[0035] The drain of the fifth NMOS transistor N49 is connected to the source of the fourth NMOS transistor N44 and the drain of the second discharge clamp transistor P47. The mirror current of the fifth NMOS transistor N49 flows through the fourth NMOS transistor N44, providing operating current for the fourth NMOS transistor N44. The drain of the second discharge clamp transistor P47 is connected to this node. When the chip's built-in power supply VDD is powered on or when the node potential rises abnormally, the second discharge clamp transistor P47 conducts to discharge the charge of the node, preventing node overvoltage.

[0036] The gate of the fourth NMOS transistor N44 and the source of the second bleeder clamp transistor P47 are both connected to the chip's internal power supply VDD. The connection of the gate of the fourth NMOS transistor N44 to the chip's internal power supply VDD ensures that N44 operates at a fixed gate voltage determined by VDD, acting as a common-gate device to isolate signal crosstalk between its drain and source nodes and improve the stability of the clamping circuit. The source of the second bleeder clamp transistor P47 is also connected to VDD, allowing it to conduct only when the drain node potential exceeds the turn-on threshold of VDD, thus achieving selective discharge in overvoltage situations.

[0037] The drain of the fourth NMOS transistor N44 is connected to the first terminal of the third resistor R43, and the second terminal of the third resistor R43 is connected to the gate and drain of the first PMOS transistor P41 and the gate of the second PMOS transistor P42. The drain current of the fourth NMOS transistor N44 flows through the third resistor R43 into the first PMOS transistor P41, which has its gate and drain shorted, generating a gate-source voltage on the first PMOS transistor P41. This gate-source voltage is simultaneously applied to the gate of the second PMOS transistor P42, forming a PMOS current mirror. The third resistor R43 generates a voltage drop in this branch and limits the branch current, so that the mirror relationship between the first PMOS transistor P41 and the second PMOS transistor P42 is established in the high voltage domain of the input power supply VIN, realizing the current transfer from the high voltage domain to the low voltage control domain.

[0038] The source of the first PMOS transistor P41 is connected to the first terminal of the first resistor R41, and the source of the second PMOS transistor P42 is connected to the first terminal of the second resistor R42. The second terminals of both resistors R41 and R42 are connected to the input power supply VIN. Resistors R41 and R42 are connected in series between the input power supply VIN and the sources of the first PMOS transistor P41 and the second PMOS transistor P42, respectively. This serves to bear the voltage difference between the high voltage of the input power supply VIN and the withstand voltage of the PMOS devices, ensuring that the first PMOS transistor P41 and the second PMOS transistor P42 operate within a safe source-drain voltage range and preventing high-voltage breakdown. Simultaneously, resistors R41 and P41, and R42 and P42, respectively, form mirror branches with source degradation resistors, improving the tolerance of the mirror current to device mismatch and enhancing the robustness of the clamping circuit.

[0039] The drain of the second PMOS transistor P42 is connected to the first end of the fourth resistor R44. The second end of the fourth resistor R44 is connected to the gate and drain of the third NMOS transistor N43, the gate of the first capacitor C41, the gate of the first LDMOS power transistor N41, and the gate and drain of the first discharge clamping transistor N45. The mirror current of the second PMOS transistor P42 flows into the gate-drain shorted third NMOS transistor N43 through the fourth resistor R44, establishing a clamping reference potential on the third NMOS transistor N43. This potential is simultaneously applied to the gate terminal of the first capacitor C41 and the gate of the first LDMOS power transistor N41, serving as the gate bias voltage of the first LDMOS power transistor N41. The fourth resistor R44 forms isolation between the drain and gate bias node of the second PMOS transistor P42. When the compensation spike feedback signal LSGFB is coupled through the first capacitor C41 to raise the gate bias node potential, the fourth resistor R44 restricts the transient current from flowing into the branch of the second PMOS transistor P42, preventing the compensation signal from being absorbed by the clamping branch and weakening the compensation effect, thus ensuring that the compensation spike feedback signal LSGFB can effectively act on the gate of the first LDMOS power transistor N41.

[0040] The source of the third NMOS transistor N43 is connected to the gate and drain of the second NMOS transistor N42, and the source of the second NMOS transistor N42 is connected to the chip's internal power supply VDD. The third NMOS transistor N43 and the second NMOS transistor N42 with its gate and drain shorted are connected in series and stacked. The two transistors share the voltage difference between the gate bias node and the chip's internal power supply VDD, so that the source-drain voltage and gate-source voltage of each device are within a safe range, improving the reliability of the clamping circuit under high-voltage processes. At the same time, the second NMOS transistor N42 provides a level shift for the third NMOS transistor N43, so that the clamping reference potential has a certain offset relative to the chip's internal power supply VDD, thereby accurately setting the clamping value of the power supply voltage VDP.

[0041] Example 3 like Figure 3 and Figure 4 As shown, this embodiment, based on embodiment two, further defines the connection relationship of the first discharge clamping tube N45: The source of the first discharge clamping transistor N45 is connected to the source of the first LDMOS power transistor N41 and the drain of the first dummy load NMOS transistor N48, so as to discharge the potential of the gate of the first capacitor C41 to the power supply voltage VDP when the power supply voltage VDP exceeds the clamping threshold. The gate and drain of the first discharge clamping transistor N45 are connected to the common node of the gate of the first capacitor C41 and the gate of the first LDMOS power transistor N41, and its source is connected to the power supply voltage VDP node, forming a gate-source voltage detection structure with the power supply voltage VDP as a reference. When the power supply voltage VDP exceeds the clamping threshold due to load change or overcompensation, the gate-source voltage of the first discharge clamping transistor N45 reaches the turn-on threshold and turns on, discharging the charge accumulated on the gate of the first capacitor C41 and the gate of the first LDMOS power transistor N41 to the power supply voltage VDP node, thereby limiting the further increase of the gate-source voltage of the first LDMOS power transistor N41, preventing the power supply voltage VDP from overshooting and damaging the subsequent circuit, and enabling the power supply voltage VDP to quickly fall back to the normal clamping value after the compensation operation is completed, shortening the overshoot duration.

[0042] Example 4 like Figure 3 and Figure 4 As shown, this embodiment further defines the internal structure of the driving circuit B42 based on embodiment three: The drive circuit B42 includes a first inverter INV41, a seventh NMOS transistor N47, a sixth NMOS transistor N46, an eighth NMOS transistor N410, a ninth NMOS transistor N411, a tenth NMOS transistor N412, an eleventh NMOS transistor N413, a twelfth NMOS transistor N414, a thirteenth NMOS transistor N415, a fourth PMOS transistor P43, a fifth PMOS transistor P44, a sixth PMOS transistor P410, a seventh PMOS transistor P411, an eighth PMOS transistor P412, a ninth PMOS transistor P413, a tenth PMOS transistor P414, an eleventh PMOS transistor P415, a fifth resistor R45, a high-side LDMOS power transistor N416, and a low-side LDMOS power transistor N417.

[0043] The drive control signal PWM is connected to the gate of the seventh NMOS transistor N47 and the input of the first inverter INV41. The drive control signal PWM simultaneously drives the seventh NMOS transistor N47 and the first inverter INV41, so that the inverted signals output by the seventh NMOS transistor N47 and the first inverter INV41 form a complementary drive pair. This provides a pair of control signals with opposite phases for the subsequent latch structure, ensuring that the latch structure has a definite flip direction at each level of the drive control signal PWM, and avoiding uncertain states during the change of the drive control signal PWM.

[0044] The drain of the seventh NMOS transistor N47 is connected to the drain of the fourth PMOS transistor P43 and the gate of the fifth PMOS transistor P44, and outputs to the delay feedback circuit B43. The fourth PMOS transistor P43 and the fifth PMOS transistor P44 are cross-coupled and together with the seventh NMOS transistor N47 and the sixth NMOS transistor N46, form a latching level shift stage, which converts the logic-ground referenced drive control signal PWM into a level signal referenced by the power supply voltage VDP. This node also serves as the signal node for the output from the drive circuit B42 to the delay feedback circuit B43, enabling the delay feedback circuit B43 to directly obtain the level shift signal synchronized with the drive control signal PWM, eliminating the need to set up a separate level shift circuit for the delay feedback circuit B43, simplifying the circuit structure and ensuring the timing consistency of the two signals.

[0045] The drain of the fifth PMOS transistor P44 is connected to the gate of the fourth PMOS transistor P43, the drain of the sixth NMOS transistor N46, the gate of the sixth PMOS transistor P410, and the gate of the eighth NMOS transistor N410. This node is the complementary output node of the latching level shift stage. Its potential is inversely proportional to the potential of the drain node of the seventh NMOS transistor N47, and it serves as the input of the first-stage buffer inverter, namely the inverter composed of the sixth PMOS transistor P410 and the eighth NMOS transistor N410, sending the level-shifted signal into the buffer amplifier chain.

[0046] The drain of the sixth PMOS transistor P410 is connected to the drain of the eighth NMOS transistor N410, the gate of the seventh PMOS transistor P411, and the gate of the ninth NMOS transistor N411; the drain of the seventh PMOS transistor P411 is connected to the drain of the ninth NMOS transistor N411, the gate of the eighth PMOS transistor P412, and the gate of the tenth NMOS transistor N412; the drain of the eighth PMOS transistor P412 is connected to the drain of the tenth NMOS transistor N412, the gate of the ninth PMOS transistor P413, and the gate of the eleventh NMOS transistor N413; the drain of the ninth PMOS transistor P413 is connected to the drain of the eleventh NMOS transistor N413, the gate of the tenth PMOS transistor P414, and the gate of the twelfth NMOS transistor N414; the drain of the tenth PMOS transistor P414 is connected to the drain of the twelfth NMOS transistor N414, the gate of the eleventh PMOS transistor P415, and the gate of the thirteenth NMOS transistor N415. The sixth PMOS transistor P410 to the eleventh PMOS transistor P415 are paired one-to-one with the eighth NMOS transistor N410 to the thirteenth NMOS transistor N415, forming a six-stage cascaded CMOS inverting buffer chain. The size of each stage of the device increases progressively. The progressively amplified buffer chain makes the driving capability of the signal edge increase exponentially. While amplifying the level-shifted signal to a level sufficient to drive the gate of the low-side LDMOS power transistor N417, it also matches the switching speed of each stage of the device, obtaining steep and symmetrical rising and falling edges, reducing overlap loss during the switching process, and suppressing edge ringing.

[0047] The drain of the eleventh PMOS transistor P415 is connected to the drain of the thirteenth NMOS transistor N415, the first terminal of the fifth resistor R45, and the gate of the low-side LDMOS power transistor N417 to output the drive signal LSG; the second terminal of the fifth resistor R45 is connected to the power ground PGND. The output of the last stage of the buffer chain directly drives the gate of the low-side LDMOS power transistor N417, outputting the drive signal LSG; the fifth resistor R45 is connected between the drive signal LSG node and the power ground PGND as a pull-down resistor, providing a defined low-potential path for the gate of the low-side LDMOS power transistor N417 when the drive circuit B42 is not powered on or has a high output impedance, preventing the low-side LDMOS power transistor N417 from being mis-conducted due to a floating gate, causing a bridge arm shoot-through short circuit, and improving the safety of the circuit at power-on and under abnormal operating conditions.

[0048] The sources of the sixth NMOS transistor N46, the seventh NMOS transistor N47, the eighth NMOS transistor N410, the ninth NMOS transistor N411, the tenth NMOS transistor N412, the eleventh NMOS transistor N413, the twelfth NMOS transistor N414, and the thirteenth NMOS transistor N415 are all connected to power ground PGND. The sources of the fourth PMOS transistor P43, the fifth PMOS transistor P44, the sixth PMOS transistor P410, the seventh PMOS transistor P411, the eighth PMOS transistor P412, the ninth PMOS transistor P413, the tenth PMOS transistor P414, and the eleventh PMOS transistor P415 are all connected to the power supply voltage VDP. In the drive circuit B42, the sources of all NMOS devices are connected to the power ground PGND, and the sources of all PMOS devices are connected to the power supply voltage VDP. This allows the level shift stage and the buffer chain to operate with the power supply voltage VDP as the high-level rail and the power ground PGND as the low-level rail. The high level of the output drive signal LSG is the power supply voltage VDP, which can fully turn on the low-side LDMOS power transistor N417 and make it operate in the low on-resistance region. At the same time, the power ground and analog ground are separated by power supply, which limits the ground bounce noise generated by the instantaneous switching of the buffer chain to the power ground PGND loop, without polluting the bias and clamping circuit on the analog ground AGND, thus ensuring the accuracy of the clamping potential.

[0049] The drain of the low-side LDMOS power transistor N417 is connected to the source of the high-side LDMOS power transistor N416, and the source of the low-side LDMOS power transistor N417 is connected to power ground PGND; the gate of the high-side LDMOS power transistor N416 is connected to the high-side drive output signal HSG, and the drain of the high-side LDMOS power transistor N416 is connected to the input power supply VIN. The high-side LDMOS power transistor N416 and the low-side LDMOS power transistor N417 are connected in series between the input power supply VIN and the power ground PGND, forming a half-bridge power stage. The low-side LDMOS power transistor N417 switches under the control of the drive signal LSG, and the high-side LDMOS power transistor N416 switches under the control of the high-side drive output signal HSG. The two alternately conduct to achieve power conversion. When the low-side LDMOS power transistor N417 turns on, its input capacitor Ciss is charged by the power supply voltage VDP, generating an instantaneous charging current. This current is the cause of the instantaneous drop in the power supply voltage VDP, which is the target of the delay feedback compensation of this invention. Thus, the drive circuit B42, the delay feedback circuit B43, and the power supply clamping circuit B41 cooperate with each other in function to jointly achieve the stability of the power supply voltage VDP.

[0050] Example 5 like Figure 3 and Figure 4As shown, this embodiment, based on embodiment four, further defines the internal structure of the delay feedback circuit B43, and explains the circuit's operation and the corresponding power supply voltage regulation method in conjunction with this structure: The delay feedback circuit B43 includes the twelfth PMOS transistor P418, the thirteenth PMOS transistor P419, the fourteenth PMOS transistor P420, the fifteenth PMOS transistor P421, the sixteenth PMOS transistor P422, the seventeenth PMOS transistor P423, the eighteenth PMOS transistor P424, the nineteenth PMOS transistor P425, the fourteenth NMOS transistor N418, the fifteenth NMOS transistor N419, the sixteenth NMOS transistor N420, the seventeenth NMOS transistor N421, the eighteenth NMOS transistor N422, the nineteenth NMOS transistor N423, the twentieth NMOS transistor N424, the twenty-first NMOS transistor N425, the twenty-second NMOS transistor N426, the twenty-third NMOS transistor N427, the sixth resistor R47, and the second capacitor C42. The sixth resistor R47 and the second capacitor C42 constitute an RC delay circuit.

[0051] The drive signal LSG is connected to the gates of the twelfth PMOS transistor P418, the fourteenth NMOS transistor N418, and the fifteenth NMOS transistor N419. The drive signal LSG simultaneously controls these three devices, ensuring that the charge / discharge switches of the delay branch are strictly synchronized with the drive signal LSG. This guarantees that the delay start point of the delay signal LSG_dly is always aligned with the transition edge of the drive signal LSG, thereby ensuring that the generation time of the compensation spike feedback signal LSGFB precisely corresponds to the turn-on time of the low-side LDMOS power transistor N417.

[0052] The drain of the twelfth PMOS transistor P418 is connected to the drain of the fourteenth NMOS transistor N418, the drain of the fifteenth NMOS transistor N419, the gate of the thirteenth PMOS transistor P419, and the gate of the seventeenth NMOS transistor N421. The twelfth PMOS transistor P418 and the fourteenth NMOS transistor N418 form the first-stage inverter controlled by the drive signal LSG, and its output node simultaneously drives the thirteenth PMOS transistor P419 and the seventeenth NMOS transistor N421. The fifteenth NMOS transistor N419 and the sixteenth NMOS transistor N420 are connected in series to form a pull-down branch, which, together with the thirteenth PMOS transistor P419 and the sixth resistor R47, determines the charging and discharging path of the RC delay circuit. This stage structure converts the drive signal LSG into a gate control signal that controls the charging and discharging of the RC delay circuit, so that the second capacitor C42 is charged or discharged only when the drive signal LSG is at a predetermined level, realizing single-edge delay.

[0053] The source of the fifteenth NMOS transistor N419 is connected to the drain of the sixteenth NMOS transistor N420. The fifteenth NMOS transistor N419 and the sixteenth NMOS transistor N420 are stacked in series to form a pull-down path for the delay branch. The conduction state of the sixteenth NMOS transistor N420 is controlled by the positive terminal potential of the second capacitor C42, i.e., the delay signal LSG_dly, forming a self-cutoff feedback. When the positive terminal potential of the second capacitor C42 is pulled down below the turn-on threshold of the sixteenth NMOS transistor N420, the pull-down path is automatically turned off to prevent the second capacitor C42 from being over-discharged, ensuring that the low level of the delay signal LSG_dly has a definite lower limit value, thereby ensuring that the initial conditions of each delay are consistent and the delay time repeatability is good.

[0054] The drain of the thirteenth PMOS transistor P419 is connected to the first end of the sixth resistor R47. The second end of the sixth resistor R47 is connected to the drain of the seventeenth NMOS transistor N421, the gate of the sixteenth NMOS transistor N420, the positive terminal of the second capacitor C42, the gate of the sixteenth PMOS transistor P422, and the gate of the twentieth NMOS transistor N424. After being delayed by the RC delay circuit, the delayed signal LSG_dly is obtained. The thirteenth PMOS transistor P419 acts as a charging switch. When it is turned on, it charges the second capacitor C42 through the sixth resistor R47. The potential at the positive terminal of the second capacitor C42 rises exponentially according to the RC time constant. The time required for it to rise to the flip threshold of the subsequent inverter is the delay time. The product of the sixth resistor R47 and the second capacitor C42 determines the length of the delay time. By selecting the resistance value of the sixth resistor R47 and the capacitance value of the second capacitor C42, the delay time can be precisely set so that the lag of the delay signal LSG_dly relative to the drive signal LSG matches the duration of the power supply voltage VDP drop when the low-side LDMOS power transistor N417 is turned on. The delay signal LSG_dly node simultaneously drives the subsequent inverter composed of the sixteenth PMOS transistor P422 and the twentieth NMOS transistor N424, shaping the analog RC charging potential into the digital level delay signal LSG_dly.

[0055] The gate of the fourteenth PMOS transistor P420 is connected to the gate of the eighteenth NMOS transistor N422 and the drain of the seventh NMOS transistor N47 to receive the drive control signal PWM. The fourteenth PMOS transistor P420 and the eighteenth NMOS transistor N422 form a second inverter controlled by the drive control signal PWM. Its input is taken from the drain node of the seventh NMOS transistor N47 in the drive circuit B42, that is, the level-shifted drive control signal PWM. This signal is introduced into the delay feedback circuit B43, so that the delay feedback circuit B43 can simultaneously know the two time bases, the drive control signal PWM and the delay signal LSG_dly, providing the conditions for the two to combine to generate the compensation spike feedback signal LSGFB.

[0056] The drain of the fourteenth PMOS transistor P420 is connected to the drain of the eighteenth NMOS transistor N422, the gate of the fifteenth PMOS transistor P421, and the gate of the nineteenth NMOS transistor N423; the drain of the fifteenth PMOS transistor P421 is connected to the drain of the nineteenth NMOS transistor N423, the drain of the twentieth NMOS transistor N424, the gate of the nineteenth PMOS transistor P425, and the gate of the twenty-first NMOS transistor N425. An inverter composed of the fourteenth PMOS transistor P420 and the eighteenth NMOS transistor N422, and an inverter composed of the fifteenth PMOS transistor P421 and the nineteenth NMOS transistor N423 are connected in series to perform two-stage buffering and shaping on the level-shifted drive control signal PWM, obtaining a PWM path signal with steep edges; the drain of the twentieth NMOS transistor N424 is connected to this node, so that when the delay signal LSG_dly is high, the twentieth NMOS transistor N424 forcibly pulls this node low, realizing the blocking of the PWM path signal by the delay signal LSG_dly; The source of the nineteenth PMOS transistor P425 is connected to the drain of the sixteenth PMOS transistor P422, and the gate is connected to the aforementioned node, forming a pull-up switch controlled by the PWM path signal. The nineteenth PMOS transistor P425 is turned on and pulled up only when the PWM path signal is low and the delay signal LSG_dly has not yet flipped to high. This generates a pulse of finite width within the time window after the drive signal LSG flips and before the delay signal LSG_dly flips. This time window is the pulse width of the compensation spike feedback signal LSGFB, which is also the duration of the compensation effect.

[0057] The drain of the sixteenth PMOS transistor P422 is connected to the source of the nineteenth PMOS transistor P425. The sixteenth PMOS transistor P422 is controlled by the node potential of the delay signal LSG_dly, and acts as a pull-up power switch for the nineteenth PMOS transistor P425. When the node of the delay signal LSG_dly is low, the sixteenth PMOS transistor P422 is turned on, providing a pull-up current path for the nineteenth PMOS transistor P425. When the node of the delay signal LSG_dly flips to high, the sixteenth PMOS transistor P422 is turned off, cutting off the pull-up path and ensuring that the compensation pulse ends in time, avoiding overshoot of the power supply voltage VDP caused by the continuous action of the compensation signal.

[0058] The drain of the nineteenth PMOS transistor P425 is connected to the drain of the twenty-first NMOS transistor N425, the gate of the seventeenth PMOS transistor P423, and the gate of the twenty-second NMOS transistor N426; the drain of the seventeenth PMOS transistor P423 is connected to the drain of the twenty-second NMOS transistor N426, the gate of the eighteenth PMOS transistor P424, and the gate of the twenty-third NMOS transistor N427; the drain of the eighteenth PMOS transistor P424 is connected to the drain of the twenty-third NMOS transistor N427, and outputs the compensation spike feedback signal LSGFB to the substrate of the first capacitor C41. An inverter consisting of the nineteenth PMOS transistor P425 and the twenty-first NMOS transistor N425, an inverter consisting of the seventeenth PMOS transistor P423 and the twenty-second NMOS transistor N426, and an inverter consisting of the eighteenth PMOS transistor P424 and the twenty-third NMOS transistor N427 are connected in series to form a three-stage buffer output stage. This stage shapes and amplifies the aforementioned finite-width pulses step by step and outputs them as the compensation spike feedback signal LSGFB. The three-stage inverting buffer gives the compensation spike feedback signal LSGFB a steep rising edge and sufficient driving capability, which can quickly couple out a sufficiently large spike voltage through the first capacitor C41, ensuring that the compensation effect takes effect immediately at the beginning of the drop in the power supply voltage VDP.

[0059] The sources of the twelfth PMOS transistor P418, the thirteenth PMOS transistor P419, the fourteenth PMOS transistor P420, the fifteenth PMOS transistor P421, the sixteenth PMOS transistor P422, the seventeenth PMOS transistor P423, and the eighteenth PMOS transistor P424 are all connected to the power supply voltage VDP. The sources of the fourteenth NMOS transistor N418, the sixteenth NMOS transistor N420, the seventeenth NMOS transistor N421, the eighteenth NMOS transistor N422, the nineteenth NMOS transistor N423, the twentieth NMOS transistor N424, the twenty-first NMOS transistor N425, the twenty-second NMOS transistor N426, and the twenty-third NMOS transistor N427 are all connected to the power ground PGND. In the delay feedback circuit B43, the source terminals of all PMOS devices are connected to the power supply voltage VDP, and the source terminals of all NMOS devices are connected to the power ground PGND. This allows the delay feedback circuit B43 to operate with the power supply voltage VDP as the high-level rail. The high level of its output compensation spike feedback signal LSGFB is the power supply voltage VDP. After being coupled through the first capacitor C41, it can obtain a sufficient boost amplitude on the gate of the first LDMOS power transistor N41. At the same time, the delay feedback circuit B43 and the drive circuit B42 share the same power rail and power ground rail. Their level references and timing references are completely consistent, avoiding level mismatch and timing deviation caused by signal transmission across power domains.

[0060] Based on the above circuit structure, such as Figure 5As shown, the working process of the power supply voltage regulator circuit and the power supply voltage regulation method in this embodiment are as follows: Step 501: The drive circuit B42 receives the drive control signal PWM and outputs the drive signal LSG to the low-side LDMOS power transistor N417.

[0061] In this embodiment, the drive circuit B42 converts the logic level drive control signal PWM into a drive signal LSG with sufficient drive capability, which is high at the power supply voltage VDP, through a latching level shift stage and a progressively amplified buffer chain. This enables the low-side LDMOS power transistor N417 to be turned on and off quickly and fully, reducing switching losses.

[0062] Step 502: When the drive control signal PWM flips from low level to high level, the drive signal LSG also flips from low level to high level, the low-side LDMOS power transistor N417 turns on, and the power supply voltage VDP charges the input capacitor Ciss of the low-side LDMOS power transistor N417, causing a momentary drop in the power supply voltage VDP.

[0063] In this embodiment, since the input capacitor Ciss presents a low impedance at the moment of turn-on, the charging current is a momentary spike current. This spike current draws charge from the power supply voltage VDP node, causing the power supply voltage VDP to experience a momentary drop at the moment the low-side LDMOS power transistor N417 turns on. If this drop is not compensated, it will affect the normal operation of the subsequent circuit and increase the output ripple.

[0064] Step 503: The delay feedback circuit B43 delays the drive signal LSG to obtain the delay signal LSG_dly, and combines the delay signal LSG_dly with the drive control signal PWM to generate the compensation spike feedback signal LSGFB.

[0065] In this embodiment, when the drive signal LSG flips from low to high, the delay signal LSG_dly flips from low to high after a delay time determined by the RC delay circuit. During the delay time, the delay signal LSG_dly remains low while the drive control signal PWM is high. The combination of these two causes the nineteenth PMOS transistor P425 to turn on and be pulled up, outputting a high-level compensation spike feedback signal LSGFB through a three-stage buffer inverter. When the delay time expires and the delay signal LSG_dly flips to high, the sixteenth PMOS transistor P422 turns off and the twentieth NMOS transistor N424 turns on and is pulled low, causing the compensation spike feedback signal LSGFB to fall back to low. Thus, the compensation spike feedback signal LSGFB presents as a spike pulse with a width equal to the delay time. Its pulse width is determined by the product of the sixth resistor R47 and the second capacitor C42, matching the duration of the power supply voltage VDP drop, so that the compensation energy just covers the drop period without being excessive.

[0066] Step 504: The compensation spike feedback signal LSGFB is coupled to the gate of the first LDMOS power transistor N41 through the first capacitor C41, so as to raise the potential of the gate terminal of the first capacitor C41 to compensate for the instantaneous drop of the power supply voltage VDP and keep the power supply voltage VDP stable.

[0067] In this embodiment, the rising edge of the compensation spike feedback signal LSGFB is transmitted to the gate terminal of the first capacitor C41, i.e., the gate of the first LDMOS power transistor N41, through the coupling effect of the first capacitor C41, causing the gate potential to rise instantaneously. The first LDMOS power transistor N41 then increases its conduction level, and its source, i.e., the power supply voltage VDP node, is synchronously raised, which exactly cancels the instantaneous drop when the low-side LDMOS power transistor N417 turns on. Since the transmission speed of the capacitor coupling is extremely fast, the compensation action and the drop occur almost simultaneously, without waiting for the feedback loop response. Therefore, the compensation is timely, the circuit structure is simple, and the cost is low. After the compensation pulse ends, the power supply clamping circuit B41 restores the gate potential of the first LDMOS power transistor N41 to the clamping reference value, and the power supply voltage VDP falls back to the normal regulated value, and the entire circuit enters a steady state.

[0068] Furthermore, the larger the instantaneous charging current of the input capacitor Ciss of the low-side LDMOS power transistor N417, the longer the delay time of the RC delay circuit becomes, thus providing a larger compensation spike feedback voltage. The larger the instantaneous charging current, the deeper and longer the drop in the power supply voltage VDP. Simultaneously, the charging current of the second capacitor C42 is affected by the corresponding node potential, extending the delay time of the RC delay circuit. The pulse width of the compensation spike feedback signal LSGFB widens accordingly, increasing the amount of compensation charge transmitted through the coupling of the first capacitor C41, and consequently increasing the compensation spike feedback voltage. This achieves adaptive adjustment of the compensation amount according to the drop depth, ensuring that the power supply voltage VDP receives appropriate compensation under different load current conditions, avoiding overcompensation under light loads and undercompensation under heavy loads.

[0069] In one specific implementation, such as Figure 6 As shown in the example, even with a large voltage regulator capacitor (e.g., a MOS capacitor with dimensions W=25um, L=10um, m=30), a voltage drop of approximately 3V still occurs when the low-side LDMOS power transistor N417 is turned on. In contrast, this invention uses a smaller first capacitor C41, which, compared to the traditional circuit which only requires a MOS capacitor with dimensions W=25um, L=10um, m=8, couples the 2.5V compensation spike feedback signal LSGFB generated by RC delay to the power supply at this moment of voltage drop, significantly reducing the instantaneous voltage drop to 0.5V and greatly enhancing the stability of the power supply. Specifically, the first capacitor C41 is implemented using a MOS capacitor, requiring no additional capacitor process layer and being fully compatible with standard CMOS processes. Compared to the traditional solution that requires a large-size MOS capacitor with m=30, this invention only requires a small-size MOS capacitor with m=8, reducing the capacitor area to less than a quarter of that of the traditional solution, significantly saving chip area and reducing manufacturing costs. At the same time, by utilizing the active compensation mechanism of the 2.5V compensation spike feedback signal LSGFB generated by the RC delay circuit and coupled through this small capacitor, the instantaneous drop of the power supply voltage from nearly 3V is suppressed to 0.5V. This achieves a better voltage regulation effect at a much smaller capacitor cost than the traditional solution, significantly improving the dynamic stability of the power supply voltage VDP and achieving a balance between low cost and high stability.

[0070] In another specific implementation, the delay time of the RC delay circuit in the delay feedback circuit B43 is adjusted according to the input capacitance Ciss of the low-side LDMOS power transistor N417 to compensate for the instantaneous drop caused by the charging of the input capacitor Ciss. Specifically, the larger the instantaneous charging current of the input capacitor Ciss, the longer the delay time of the RC delay circuit becomes, providing a larger compensation spike feedback voltage. By setting the resistance value of the sixth resistor R47 and the capacitance value of the second capacitor C42 according to the size of the input capacitor Ciss, the delay time is adapted to the charging time constant of the input capacitor Ciss, ensuring that the width of the compensation pulse always covers the charging period of the input capacitor Ciss, thus achieving sufficient compensation effect in applications with different power transistor specifications.

[0071] It is understood that the specific examples in this document are only intended to help those skilled in the art better understand this disclosure, and are not intended to limit the scope of the invention.

[0072] It is understood that the various implementation methods described in this specification can be implemented individually or in combination, and this disclosure does not limit them.

[0073] Unless otherwise stated, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this specification. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0074] The above description is merely a specific embodiment of this specification, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this specification should be included within the scope of protection of this specification. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A power supply voltage regulator circuit, characterized in that, include: Power supply clamping circuit B41, drive circuit B42, delay feedback circuit B43, first capacitor C41, first LDMOS power transistor N41, first dummy load NMOS transistor N48, and first anti-static resistor R46. The first terminal of the first anti-static resistor R46 is connected to the input power supply VIN, and the second terminal of the first anti-static resistor R46 is connected to the drain of the first LDMOS power transistor N41; the gate of the first LDMOS power transistor N41 is connected to the gate terminal of the first capacitor C41, and the source of the first LDMOS power transistor N41 is connected to the drain of the first dummy load NMOS transistor N48, so as to provide a power supply voltage VDP at the source of the first LDMOS power transistor N41; The input terminal of the drive circuit B42 is used to receive the drive control signal PWM, and the output terminal of the drive circuit B42 is used to output the drive signal LSG and is connected to the input terminal of the delay feedback circuit B43. The output terminal of the delay feedback circuit B43 outputs a compensation spike feedback signal LSGFB and is connected to the substrate terminal of the first capacitor C41. The compensation spike feedback signal LSGFB is coupled to the gate of the first LDMOS power transistor N41 through the first capacitor C41 to compensate for the instantaneous drop of the power supply voltage VDP. The power supply clamping circuit B41 is connected to the gate of the first LDMOS power transistor N41 and is used to clamp the gate potential of the first LDMOS power transistor N41 to indirectly stabilize the power supply voltage VDP; the source of the first dummy load NMOS transistor N48 is connected to analog ground AGND.

2. The power supply voltage regulator circuit according to claim 1, characterized in that, The power supply clamping circuit B41 includes a first bias current source IBP41, a first NMOS transistor N40, a second NMOS transistor N42, a third NMOS transistor N43, a fourth NMOS transistor N44, a fifth NMOS transistor N49, a first PMOS transistor P41, a second PMOS transistor P42, a second discharge clamping transistor P47, a first resistor R41, a second resistor R42, a third resistor R43, and a fourth resistor R44. The first terminal of the first bias current source IBP41 is connected to the chip's built-in power supply VDD, and the second terminal of the first bias current source IBP41 is connected to the gate and drain of the first NMOS transistor N40, the gate of the fifth NMOS transistor N49, and the gate of the first dummy load NMOS transistor N48; the source of the first NMOS transistor N40, the source of the fifth NMOS transistor N49, and the source of the first dummy load NMOS transistor N48 are all connected to the analog ground AGND; The drain of the fifth NMOS transistor N49 is connected to the source of the fourth NMOS transistor N44 and the drain of the second discharge clamp transistor P47; the gate of the fourth NMOS transistor N44 and the source of the second discharge clamp transistor P47 are both connected to the chip's built-in power supply VDD; the drain of the fourth NMOS transistor N44 is connected to the first end of the third resistor R43, and the second end of the third resistor R43 is connected to the gate and drain of the first PMOS transistor P41 and the gate of the second PMOS transistor P42; The source of the first PMOS transistor P41 is connected to the first end of the first resistor R41, and the source of the second PMOS transistor P42 is connected to the first end of the second resistor R42. The second ends of both the first resistor R41 and the second resistor R42 are connected to the input power supply VIN. The drain of the second PMOS transistor P42 is connected to the first end of the fourth resistor R44. The second end of the fourth resistor R44 is connected to the gate and drain of the third NMOS transistor N43, the gate of the first capacitor C41, the gate of the first LDMOS power transistor N41, and the gate and drain of the first discharge clamp transistor N45. The source of the third NMOS transistor N43 is connected to the gate and drain of the second NMOS transistor N42, and the source of the second NMOS transistor N42 is connected to the chip's built-in power supply VDD.

3. The power supply voltage regulator circuit according to claim 2, characterized in that, The source of the first discharge clamping transistor N45 is connected to the source of the first LDMOS power transistor N41 and the drain of the first dummy load NMOS transistor N48, so as to discharge the potential of the gate of the first capacitor C41 to the power supply voltage VDP when the power supply voltage VDP exceeds the clamping threshold.

4. The power supply voltage regulator circuit according to claim 3, characterized in that, The driving circuit B42 includes a first inverter INV41, a seventh NMOS transistor N47, a sixth NMOS transistor N46, an eighth NMOS transistor N410, a ninth NMOS transistor N411, a tenth NMOS transistor N412, an eleventh NMOS transistor N413, a twelfth NMOS transistor N414, a thirteenth NMOS transistor N415, a fourth PMOS transistor P43, a fifth PMOS transistor P44, a sixth PMOS transistor P410, a seventh PMOS transistor P411, an eighth PMOS transistor P412, a ninth PMOS transistor P413, a tenth PMOS transistor P414, an eleventh PMOS transistor P415, a fifth resistor R45, a high-side LDMOS power transistor N416, and a low-side LDMOS power transistor N417. The drive control signal PWM is connected to the gate of the seventh NMOS transistor N47 and the input of the first inverter INV41. The drain of the seventh NMOS transistor N47 is connected to the drain of the fourth PMOS transistor P43 and the gate of the fifth PMOS transistor P44, and is output to the delay feedback circuit B43. The drain of the fifth PMOS transistor P44 is connected to the gate of the fourth PMOS transistor P43, the drain of the sixth NMOS transistor N46, the gate of the sixth PMOS transistor P410, and the gate of the eighth NMOS transistor N410. The drain of the sixth PMOS transistor P410 is connected to the drain of the eighth NMOS transistor N410, the gate of the seventh PMOS transistor P411, and the gate of the ninth NMOS transistor N411. The drain of the seventh PMOS transistor P411 is connected to the drain of the ninth NMOS transistor N411, the gate of the eighth PMOS transistor P412, and the gate of the tenth NMOS transistor N412. The drain of the eighth PMOS transistor P412 is connected to the drain of the tenth NMOS transistor N412, the gate of the ninth PMOS transistor P413, and the gate of the eleventh NMOS transistor N413. The drain of the ninth PMOS transistor P413 is connected to the drain of the eleventh NMOS transistor N413, the gate of the tenth PMOS transistor P414, and the gate of the twelfth NMOS transistor N414. The drain of the tenth PMOS transistor P414 is connected to the drain of the twelfth NMOS transistor N414, the gate of the eleventh PMOS transistor P415, and the gate of the thirteenth NMOS transistor N415. The drain of the eleventh PMOS transistor P415 is connected to the drain of the thirteenth NMOS transistor N415, the first terminal of the fifth resistor R45, and the gate of the low-side LDMOS power transistor N417 to output the drive signal LSG; the second terminal of the fifth resistor R45 is connected to power ground PGND. The sources of the sixth NMOS transistor N46, the seventh NMOS transistor N47, the eighth NMOS transistor N410, the ninth NMOS transistor N411, the tenth NMOS transistor N412, the eleventh NMOS transistor N413, the twelfth NMOS transistor N414, and the thirteenth NMOS transistor N415 are all connected to the power ground PGND, and the sources of the fourth PMOS transistor P43, the fifth PMOS transistor P44, the sixth PMOS transistor P410, the seventh PMOS transistor P411, the eighth PMOS transistor P412, the ninth PMOS transistor P413, the tenth PMOS transistor P414, and the eleventh PMOS transistor P415 are all connected to the power supply voltage VDP; The drain of the low-side LDMOS power transistor N417 is connected to the source of the high-side LDMOS power transistor N416, and the source of the low-side LDMOS power transistor N417 is connected to the power ground PGND. The gate of the high-side LDMOS power transistor N416 is connected to the high-side drive output signal HSG, and the drain of the high-side LDMOS power transistor N416 is connected to the input power supply VIN.

5. The power supply voltage regulator circuit according to claim 4, characterized in that, The delay feedback circuit B43 includes a twelfth PMOS transistor P418, a thirteenth PMOS transistor P419, a fourteenth PMOS transistor P420, a fifteenth PMOS transistor P421, a sixteenth PMOS transistor P422, a seventeenth PMOS transistor P423, an eighteenth PMOS transistor P424, a nineteenth PMOS transistor P425, a fourteenth NMOS transistor N418, a fifteenth NMOS transistor N419, a sixteenth NMOS transistor N420, a seventeenth NMOS transistor N421, an eighteenth NMOS transistor N422, a nineteenth NMOS transistor N423, a twentieth NMOS transistor N424, a twenty-first NMOS transistor N425, a twenty-second NMOS transistor N426, a twenty-third NMOS transistor N427, a sixth resistor R47, and a second capacitor C42. The sixth resistor R47 and the second capacitor C42 constitute an RC delay circuit. The drive signal LSG is connected to the gate of the twelfth PMOS transistor P418, the gate of the fourteenth NMOS transistor N418, and the gate of the fifteenth NMOS transistor N419; the drain of the twelfth PMOS transistor P418 is connected to the drain of the fourteenth NMOS transistor N418, the drain of the fifteenth NMOS transistor N419, the gate of the thirteenth PMOS transistor P419, and the gate of the seventeenth NMOS transistor N421; the source of the fifteenth NMOS transistor N419 is connected to the gate of the thirteenth PMOS transistor P419. The drain of the sixteenth NMOS transistor N420 is connected; the drain of the thirteenth PMOS transistor P419 is connected to the first end of the sixth resistor R47, and the second end of the sixth resistor R47 is connected to the drain of the seventeenth NMOS transistor N421, the gate of the sixteenth NMOS transistor N420, the positive terminal of the second capacitor C42, the gate of the sixteenth PMOS transistor P422, and the gate of the twentieth NMOS transistor N424. After being delayed by the RC delay circuit, the delayed signal LSG_dly is obtained. The gate of the fourteenth PMOS transistor P420 is connected to the gate of the eighteenth NMOS transistor N422 and the drain of the seventh NMOS transistor N47 to receive the drive control signal PWM; the drain of the fourteenth PMOS transistor P420 is connected to the drain of the eighteenth NMOS transistor N422, the gate of the fifteenth PMOS transistor P421, and the gate of the nineteenth NMOS transistor N423; the drain of the fifteenth PMOS transistor P421 is connected to the drain of the nineteenth NMOS transistor N423, the drain of the twentieth NMOS transistor N424, the gate of the nineteenth PMOS transistor P425, and the gate of the twenty-first NMOS transistor N425; the sixteenth PMOS transistor P42... The drain of transistor 2 is connected to the source of the nineteenth PMOS transistor P425; the drain of the nineteenth PMOS transistor P425 is connected to the drain of the twenty-first NMOS transistor N425, the gate of the seventeenth PMOS transistor P423, and the gate of the twenty-second NMOS transistor N426; the drain of the seventeenth PMOS transistor P423 is connected to the drain of the twenty-second NMOS transistor N426, the gate of the eighteenth PMOS transistor P424, and the gate of the twenty-third NMOS transistor N427; the drain of the eighteenth PMOS transistor P424 is connected to the drain of the twenty-third NMOS transistor N427, and the compensation spike feedback signal LSGFB is output to the substrate of the first capacitor C41.

6. The power supply voltage regulator circuit according to claim 5, characterized in that, The source terminals of the twelfth PMOS transistor P418, the thirteenth PMOS transistor P419, the fourteenth PMOS transistor P420, the fifteenth PMOS transistor P421, the sixteenth PMOS transistor P422, the seventeenth PMOS transistor P423, and the eighteenth PMOS transistor P424 are all connected to the power supply voltage VDP. The source terminals of the fourteenth NMOS transistor N418, the sixteenth NMOS transistor N420, the seventeenth NMOS transistor N421, the eighteenth NMOS transistor N422, the nineteenth NMOS transistor N423, the twentieth NMOS transistor N424, the twenty-first NMOS transistor N425, the twenty-second NMOS transistor N426, and the twenty-third NMOS transistor N427 are all connected to the power ground PGND.

7. The power supply voltage regulator circuit according to claim 6, characterized in that, When the drive signal LSG flips from low to high, the delay signal LSG_dly flips from low to high after a delay time determined by the RC delay circuit. During the delay time, the delay signal LSG_dly combines with the drive control signal PWM to generate the compensation spike feedback signal LSGFB. The compensation spike feedback signal LSGFB is coupled to the gate of the first LDMOS power transistor N41 through the first capacitor C41, causing the gate potential of the first capacitor C41 to rise, thereby compensating for the drop in the power supply voltage VDP at the moment the low-side LDMOS power transistor N417 is turned on.

8. The power supply voltage regulator circuit according to claim 7, characterized in that, The larger the instantaneous charging current of the input capacitor Ciss of the low-side LDMOS power transistor N417, the longer the delay time of the RC delay circuit becomes, so as to provide a larger compensation spike feedback voltage.

9. A power supply voltage regulation method, applied to the power supply voltage regulation circuit as described in claim 6, characterized in that, The method includes: The driving circuit B42 receives the driving control signal PWM and outputs the driving signal LSG to the low-side LDMOS power transistor N417. When the drive control signal PWM flips from low level to high level, the power supply voltage VDP charges the input capacitor Ciss of the low-side LDMOS power transistor N417, causing the power supply voltage VDP to drop momentarily. The delay feedback circuit B43 delays the drive signal LSG to obtain the delay signal LSG_dly, and combines the delay signal LSG_dly with the drive control signal PWM to generate the compensation spike feedback signal LSGFB. The compensation spike feedback signal LSGFB is coupled to the gate of the first LDMOS power transistor N41 via the first capacitor C41, causing the gate terminal potential of the first capacitor C41 to rise, thereby compensating for the instantaneous drop in the power supply voltage VDP and keeping the power supply voltage VDP stable.

10. The power supply voltage regulation method according to claim 9, characterized in that, The method further includes: The delay time of the RC delay circuit in the delay feedback circuit B43 is adjusted according to the input capacitance Ciss of the low-side LDMOS power transistor N417 to compensate for the instantaneous drop caused by the charging of the input capacitance Ciss. The larger the instantaneous charging current of the input capacitor Ciss, the longer the delay time of the RC delay circuit becomes, so as to provide a larger compensation spike feedback voltage.

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