Power management circuit and home appliance

Abstract

The application relates to a power management circuit and a household appliance. The power management circuit comprises a power conversion chip and a detection control circuit. An input end of the power conversion chip is connected with an energy storage capacitor, and an output end of the power conversion chip is connected with a load. An input end of the detection control circuit is connected with the output end of the power conversion chip, and an output end of the detection control circuit is connected with the input end of the power conversion chip. The detection control circuit is used for detecting a voltage drop rate of the output end of the power conversion chip, and when the voltage drop rate is greater than a first preset drop rate, a capacitive load is connected with the energy storage capacitor, the energy storage capacitor is used for charging the capacitive load, the capacitive load is used for consuming the electric energy released by the energy storage capacitor, the input voltage of the power conversion chip is prevented from being pulled up by the electric energy released by the energy storage capacitor, and the input voltage of the power conversion chip is prevented from rising due to load power-off.

Description

Technical Field

[0001] This application relates to the field of home appliance technology, and more particularly to a power management circuit and a home appliance. Background Technology

[0002] Currently, home appliance controller motherboards typically have energy storage capacitors added at the power input front end due to their large loads. This is to reduce the impact of front-end power fluctuations on the back-end load, and vice versa. When the device loses power, the back-end load of the power conversion chip suddenly disconnects, causing the front-end energy storage capacitor to discharge and the input voltage to rebound momentarily. This allows the power conversion chip to restart, and the back-end load to regain power. However, the increased load accelerates the power loss at the front-end input voltage, causing the power conversion chip to stop working again, and the load to disconnect once more. The power conversion chip will experience a power-off-power-off process, which may occur multiple times in severe cases. This can affect the chip's lifespan and may also cause malfunctions in the air conditioning unit. Summary of the Invention

[0003] This application provides a power management circuit and a home appliance to solve the problem that when the controller loses power, the large energy storage capacitor at the power input front end discharges, causing the voltage to rise again and enabling the power conversion chip to start working again.

[0004] In a first aspect, this application provides a power management circuit, the power management circuit comprising: A power conversion chip, wherein the input terminal of the power conversion chip is connected to an energy storage capacitor, and the output terminal of the power conversion chip is connected to a load; A detection control circuit is provided, wherein the input terminal of the detection control circuit is connected to the output terminal of the power conversion chip, and the output terminal of the detection control circuit is connected to the input terminal of the power conversion chip. The detection control circuit is used to detect the voltage drop rate at the output terminal of the power conversion chip, and when the voltage drop rate is greater than a first preset drop rate, the capacitive load is connected to the energy storage capacitor, and the energy storage capacitor is used to charge the capacitive load, thereby preventing the input voltage of the power conversion chip from rising due to the load power loss.

[0005] Optionally, the detection control circuit includes: A filtering circuit, connected to the output terminal of the power conversion chip, is used to filter the output voltage of the power conversion chip and output a filtered voltage. A differential operation circuit is connected to the output terminal of the filter circuit and is used to output the voltage drop rate according to the filter voltage. A comparator circuit, connected to the output of the differential operation circuit, is used to output a conduction signal when the voltage drop rate is greater than a first preset drop rate. A switching circuit is connected to the output terminal of the comparator circuit, the energy storage capacitor, and the capacitive load, respectively, and is used to connect the capacitive load and the energy storage capacitor according to the conduction signal.

[0006] Optionally, the filter circuit includes a first resistor and a first capacitor. The first end of the first resistor is connected to the output terminal of the power conversion chip, the second end of the first resistor is connected to the differential operation circuit and the first end of the first capacitor, and the second end of the first capacitor is grounded.

[0007] Optionally, the differential operation circuit includes a second capacitor, a second resistor, a third resistor, and a first operational amplifier. The first end of the second capacitor is connected to the filter circuit, the second end of the second capacitor is connected to the second resistor and the inverting input terminal of the first operational amplifier, the second end of the second resistor is connected to the output terminal of the first operational amplifier, the non-inverting input terminal of the first operational amplifier is grounded through the third resistor, and the output terminal of the first operational amplifier is also connected to the comparator circuit. The first operational amplifier is used to output a first voltage signal representing the voltage drop rate based on the received filtered voltage.

[0008] Optionally, the comparison circuit includes a fourth resistor, a fifth resistor, and a first comparator. The inverting input of the first comparator is connected to the output of the first operational amplifier. The non-inverting input of the first comparator is connected to the first end of the fourth resistor and the first end of the fifth resistor, respectively. The output of the first comparator is connected to the switching circuit. The second end of the fourth resistor is grounded, and the second end of the fifth resistor is connected to the output of the power conversion chip. The first comparator is used to output a turn-on signal when the first voltage signal provided by the first operational amplifier is greater than the second voltage signal representing the first preset drop rate. The second voltage signal is the voltage signal obtained by dividing the output voltage of the power conversion chip through the fourth resistor and the fifth resistor.

[0009] Optionally, the switching circuit includes a seventh resistor and a first switching transistor. The first end of the seventh resistor is connected to the output terminal of the first comparator and the gate of the first switching transistor, respectively. The second end of the seventh resistor is connected to the energy storage capacitor and the drain of the first switching transistor, respectively. The source of the first switching transistor is connected to the capacitive load. When the first switching transistor receives the turn-on signal output by the first comparator, it connects the capacitive load and the energy storage capacitor.

[0010] Optionally, the differentiating operation circuit further includes a fourth capacitor, an eighth resistor, a ninth resistor, and a second operational amplifier. The first terminal of the fourth capacitor is connected to the filter circuit, the second terminal of the fourth capacitor is connected to the first terminal of the eighth resistor and the inverting input terminal of the second operational amplifier, the second terminal of the eighth resistor is connected to the output terminal of the second operational amplifier, the non-inverting input terminal of the second operational amplifier is grounded through the ninth resistor, and the output terminal of the second operational amplifier is also connected to the comparator circuit. The second operational amplifier is used to output a third voltage signal representing the voltage drop rate based on the received filtered voltage.

[0011] Optionally, the comparison circuit further includes a tenth resistor, an eleventh resistor, and a second comparator. The positive input terminal of the second comparator is connected to the output terminal of the second operational amplifier. The inverting input terminal of the second comparator is connected to the first terminal of the tenth resistor and the first terminal of the eleventh resistor, respectively. The output terminal of the second comparator is connected to the switching circuit. The second terminal of the tenth resistor is grounded, and the second terminal of the eleventh resistor is connected to the output terminal of the power conversion chip. The second comparator is used to output a turn-on signal when the third voltage signal provided by the second operational amplifier is less than the fourth voltage signal representing the second preset drop rate. The fourth voltage signal is the voltage signal obtained by dividing the output voltage of the power conversion chip through the tenth resistor and the eleventh resistor. The second preset drop rate is greater than the first preset drop rate.

[0012] Optionally, the switching circuit further includes a second switching transistor, the gate of which is connected to the output of the second comparator, the drain of which is connected to the source of the first switching transistor, and the source of which is connected to the capacitive load. When the first switch receives the turn-on signal output by the first comparator and the second switch receives the turn-on signal output by the second comparator, the capacitive load and the energy storage capacitor are connected.

[0013] Secondly, this application provides a home appliance that includes the power management circuit described in any of the above claims.

[0014] Compared with the prior art, the technical solution provided in this application has the following advantages: The power management circuit provided in this application includes a power conversion chip and a detection and control circuit. The input terminal of the power conversion chip is connected to an energy storage capacitor, and the output terminal of the power conversion chip is connected to a load. The input terminal of the detection and control circuit is connected to the output terminal of the power conversion chip, and the output terminal of the detection and control circuit is connected to the input terminal of the power conversion chip. This circuit detects the voltage drop rate at the output terminal of the power conversion chip, and when the voltage drop rate exceeds a first preset drop rate, it connects the capacitive load to the energy storage capacitor. The voltage drop rate is detected... This system detects whether the load is losing power. If the voltage drop rate exceeds a first preset drop rate, it predicts that the load is about to lose power. A capacitive load is connected to the power input of the power conversion chip, and the energy storage capacitor is used to charge the capacitive load. This is equivalent to using the capacitive load to consume the energy released by the energy storage capacitor. The capacitive load voltage cannot change abruptly, thus preventing the energy released by the energy storage capacitor from raising the input voltage of the power conversion chip. This prevents the input voltage of the power conversion chip from rising due to the load losing power, and avoids the power conversion chip restarting due to the input voltage rising when the load loses power. This solves the problem that when the controller loses power, the large energy storage capacitor at the power input front end discharges, causing the voltage to rise and the power conversion chip to restart. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0018] Figure 1 This is a schematic diagram of a power management circuit provided in an embodiment of this application; Figure 2 This is a schematic diagram of another power management circuit provided in an embodiment of this application; Figure 3 This is a schematic diagram of a detection control circuit provided in an embodiment of this application; Figure 4 This is a schematic diagram of another detection control circuit provided in an embodiment of this application; Figure 5 This is a schematic diagram of the internal structure of a household appliance provided in an embodiment of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of the invention. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0021] In one embodiment, Figure 1 This is a schematic diagram of a power management circuit in one embodiment, with reference to... Figure 1 This invention provides a power management circuit that can be applied to home appliances, such as air conditioners, refrigerators, fresh air systems, and air purifiers. The power management circuit specifically includes: A power conversion chip 110, the input terminal of which is connected to an energy storage capacitor 120, and the output terminal of which is connected to a load 130; A detection control circuit 140 is provided, the input terminal of which is connected to the output terminal of the power conversion chip 110, and the output terminal of the detection control circuit 140 is connected to the input terminal of the power conversion chip 110. The detection control circuit 140 is used to detect the voltage drop rate at the output terminal of the power conversion chip 110. When the voltage drop rate is greater than a first preset drop rate, the capacitive load 145 is connected to the energy storage capacitor 120, and the energy storage capacitor 120 is used to charge the capacitive load 145, thereby preventing the input voltage of the power conversion chip 110 from rising due to the power loss of the load 130.

[0022] Specifically, the power conversion chip 110 is a dedicated integrated circuit on the circuit board responsible for voltage and current conversion, voltage regulation, and power distribution management. The power conversion chip 110 is connected between the power supply and the load 130. When the voltage input from the mains / battery is unstable or the voltage specifications are mismatched, this chip converts the power to a voltage and current that is just usable by the load 130 (such as chips, motors, screens, CPUs, and other components), while also taking into account power saving and overvoltage and overcurrent protection.

[0023] A storage capacitor 120 is also provided at the input terminal (i.e., the power input front end) of the power conversion chip 110. The storage capacitor 120 is a large-capacity capacitor that quickly stores and discharges electrical energy in the form of an electric field, and releases it instantly when needed. Since the MOSFET inside the power conversion chip 110 conducts intermittently at high frequency, a large peak current is instantly drawn from the input terminal at the moment of conduction. Without the storage capacitor 120, the parasitic resistance and inductance of the power front-end cables and upstream power traces would cause the instantaneous large current to cause a sudden drop in the input bus voltage. If the voltage drop is too large, the power conversion chip 110 will lock up due to undervoltage protection, the whole machine will reset, and malfunction. By using the storage capacitor 120 at the power input terminal to pre-store charge, the peak current is provided by the nearby discharge of the storage capacitor 120 when the MOSFET inside the power conversion chip 110 conducts. The upstream power supply only needs to provide an average current, which greatly reduces the voltage drop of the traces and prevents the bus voltage from being pulled down instantly.

[0024] Furthermore, the high-speed switching of the power conversion chip 110's switching transistor generates high-frequency pulse interference and current spikes in the input circuit. The energy storage capacitor 120 absorbs this high-frequency pulsating current locally, preventing electromagnetic interference and voltage spikes generated by the switch from rising along the power supply line and interfering with the upstream power circuit. This achieves local suppression of switching noise at this stage. In other words, the energy storage capacitor 120 can absorb the backflow noise generated by the switch operation and isolate the noise from flowing back into the upstream power supply.

[0025] The upstream power supply itself experiences voltage fluctuations, such as the slow voltage drop during battery discharge; and the slight fluctuations in bus voltage caused by the simultaneous start and stop of multiple loads 130. The energy storage capacitor 120 uses charging and discharging to buffer these low-frequency voltage fluctuations, providing a relatively stable and clean input voltage to the power conversion chip 110. This ensures the stable operation of the chip's internal control loop and prevents output voltage regulation from becoming uncontrolled due to drastic input voltage fluctuations, thus smoothing out the fluctuations in the input voltage of the power conversion chip 110.

[0026] The detection control circuit 140 includes a capacitive load 145, which has a large-capacity capacitor connected in parallel internally. Upon power-up, the capacitor is charged first. The detection control circuit 140 is connected between the output and input terminals of the power conversion chip 110. It detects the trend of the output voltage change of the power conversion chip 110 to determine if the load 130 downstream of the power conversion chip 110 has experienced a power outage. Before the load 130 loses power, the capacitive load 145 is connected to the energy storage capacitor 120. When the load 130 loses power, the energy storage capacitor 120 charges and consumes the energy from the capacitive load 145. Furthermore, the voltage of the capacitive load 145 cannot change abruptly, ensuring that the input voltage at the front end of the power conversion chip 110 does not suddenly rise.

[0027] The detection control circuit 140 is specifically used to detect the voltage drop rate at the output terminal of the power conversion chip 110. If the voltage drop rate is less than or equal to the first preset drop rate, it indicates that the output voltage fluctuation of the power conversion chip 110 is normal, and it is determined that the load 130 is powered on normally and is not in a power-off state. Then, the connection between the capacitive load 145 and the energy storage capacitor 120 is disconnected.

[0028] The first preset voltage drop rate is used to indicate the voltage drop before the load 130 loses power. If the voltage drop rate is greater than the first preset voltage drop rate, it indicates that the output voltage of the power conversion chip 110 is dropping rapidly, and the load 130 is about to lose power. Then, the capacitive load 145 is connected to the energy storage capacitor 120, and the voltage drop rate is used to detect whether the load 130 is losing power. If the voltage drop rate is greater than the first preset voltage drop rate, it is predicted that the load 130 is about to lose power. The capacitive load 145 is then connected to the power supply front end of the power conversion chip 110, and the energy storage capacitor 120 is used to... The capacitive load 145 is charged, which is equivalent to using the capacitive load 145 to consume the electrical energy released by the energy storage capacitor 120. The voltage of the capacitive load 145 cannot change abruptly, thus preventing the electrical energy released by the energy storage capacitor 120 from raising the input voltage of the power conversion chip 110. This prevents the input voltage of the power conversion chip 110 from rising due to the power loss of the load 130, and prevents the power conversion chip 110 from restarting due to the rise in input voltage when the load 130 is powered off. This solves the problem that when the controller is powered off, the discharge of the large energy storage capacitor at the power input front end causes the voltage to rise, making the power conversion chip 110 restart.

[0029] In one embodiment, refer to Figure 2 The detection control circuit 140 includes: The filter circuit 141 is connected to the output terminal of the power conversion chip 110 and is used to filter the output voltage of the power conversion chip 110 and output a filtered voltage. Differentiation circuit 142 is connected to the output terminal of filter circuit 141 and is used to output voltage drop rate according to the filtered voltage. Comparison circuit 143 is connected to the output terminal of the differential operation circuit 142 and is used to output a conduction signal when the voltage drop rate is greater than the first preset drop rate. The switching circuit 144 is connected to the output terminal of the comparator circuit 143, the energy storage capacitor 120, and the capacitive load 145 respectively, and is used to connect the capacitive load 145 and the energy storage capacitor 120 according to the conduction signal.

[0030] Specifically, the filter circuit 141 can be implemented using a single capacitor, an LC filter structure composed of a capacitor and an inductor, an RC filter structure composed of a resistor and a capacitor, or a composite structure of a capacitor, an inductor, and a resistor. The filter circuit 141 is used to filter out AC components, retaining only stable DC, reducing voltage ripple, ensuring stable power supply to downstream circuits, and preventing false triggering due to small voltage fluctuations; it blocks high-frequency noise from the power supply from entering downstream circuits, avoiding interference with subsequent precision circuits; it absorbs instantaneous current fluctuations, buffering voltage spikes and drops caused by sudden changes in the load 130; and it suppresses high-voltage spikes generated by parasitic inductance in the traces, protecting downstream circuits.

[0031] The differential operation circuit 142 is used to perform differential operations on the input filtered voltage, that is, to calculate du / dt, and then output the voltage sag rate to the comparator circuit 143. When the output voltage of the power conversion chip 110 is in a stable high-level or low-level stage, the voltage sag rate is close to 0. Only when the output voltage is in a transition stage such as a rising edge or falling edge will it output a non-zero positive or negative pulse level. Based on the voltage sag rate, the voltage sag trend caused by the transient of the large load 130 can be identified tens of microseconds in advance, which greatly shortens the response delay of the capacitive load 145 and avoids connecting the capacitive load 145 only when the voltage drops to the point that the load 130 cannot work.

[0032] The comparator circuit 143 compares the voltage drop rate with a first preset drop rate to output a corresponding on / off signal. If the voltage drop rate is greater than the first preset drop rate, an on signal is output; if the voltage drop rate is less than or equal to the first preset drop rate, an off signal is output. By adjusting the threshold of the first preset drop rate, the power-off requirements of loads 130 with different sensitivities can be adapted. For precision core loads 130 with low tolerance for voltage drops, the threshold of the first preset drop rate can be lowered, allowing capacitive loads 145 to be connected for charging earlier. For ordinary loads 130 that are not sensitive to voltage fluctuations, the threshold of the first preset drop rate can be increased to avoid small normal voltage fluctuations triggering unnecessary switching actions, reduce the ineffective charging and discharging losses of the energy storage capacitor 120, and extend the service life of the energy storage capacitor 120.

[0033] The switching circuit 144 is located between the capacitive load 145 and the energy storage capacitor 120 to control the connection state between the capacitive load 145 and the energy storage capacitor 120. If a conduction signal is received from the comparator circuit 143, the capacitive load 145 and the energy storage capacitor 120 are connected; if a cut-off signal is received from the comparator circuit 143, the connection between the capacitive load 145 and the energy storage capacitor 120 is disconnected.

[0034] In one embodiment, refer to Figure 3 The filter circuit 141 includes a first resistor R1 and a first capacitor C1. The first end of the first resistor R1 is connected to the output end of the power conversion chip 110. The second end of the first resistor R1 is connected to the differential operation circuit 142 and the first end of the first capacitor C1, respectively. The second end of the first capacitor C1 is grounded.

[0035] Specifically, the first resistor R1 and the first capacitor C1 form an RC filter structure. This simple structure relies on the first resistor R1 to dissipate AC noise energy, thus filtering the output voltage of the power conversion chip 110. Compared to multi-stage complex filter structures, this RC filter structure can filter out high-frequency ripple noise in the output voltage while avoiding the introduction of excessive phase shifts. It does not disrupt the phase stability of the subsequent differential circuit 142. Furthermore, it can control the device delay in the filtering stage to the nanosecond level, matching the fast response output requirements of the power conversion chip 110 and preventing the filtering delay from slowing down the overall circuit's voltage signal processing speed. This RC filter structure can attenuate high-frequency noise above 10kHz by more than 40dB, effectively filtering out high-frequency switching noise generated by the switching action of the power conversion chip 110. This prevents noise coupling into the subsequent differential circuit 142, which could interfere with the differential calculation results, thus improving the signal-to-noise ratio of the entire circuit's output signal and ensuring the accuracy of signal processing.

[0036] In one embodiment, refer to Figure 3 The differentiating operation circuit 142 includes a second capacitor C2, a second resistor R2, a third resistor R3, and a first operational amplifier U1. The first end of the second capacitor C2 is connected to the filter circuit 141. The second end of the second capacitor C2 is connected to the second resistor R2 and the inverting input terminal of the first operational amplifier U1. The second end of the second resistor R2 is connected to the output terminal of the first operational amplifier U1. The non-inverting input terminal of the first operational amplifier U1 is grounded through the third resistor R3. The output terminal of the first operational amplifier U1 is also connected to the comparator circuit 143. The first operational amplifier U1 is used to output a first voltage signal representing the voltage drop rate based on the received filtered voltage.

[0037] Specifically, the filtered voltage is connected to the inverting input of the first operational amplifier U1 via the second capacitor C2. A feedback resistor, specifically the second resistor R2, is connected between the inverting input and output of the first operational amplifier U1. The non-inverting input of the first operational amplifier U1 is grounded via the third resistor R3. After differentiating the filtered voltage, the first operational amplifier U1 outputs a first voltage signal characterizing the voltage drop rate. , The first voltage signal represents the rate of change of the filtered voltage within a preset time period t. It is proportional to the first derivative of the filtered voltage with respect to time. The DC component is isolated by the first operational amplifier U1, and the DC component is blocked by the capacitor. This effectively removes the steady-state DC component from the filtered voltage, retaining only the characteristic component corresponding to the dynamic change of the voltage, thus avoiding interference from the DC component in the drop rate judgment. At the same time, the differential operation circuit 142 has a simple structure and flexible device parameter adjustment. By matching the resistance values ​​of the second capacitor C2 and the second resistor R2, it can adapt to the voltage drop detection requirements with different sensitivities. In different scenarios where the grid voltage experiences small and rapid drops or large and slow drops, it can output a first voltage signal with a clearly distinguishable amplitude, providing an accurate characteristic basis for the drop judgment of the subsequent comparison circuit 143, and improving the response speed and recognition accuracy of voltage drop detection.

[0038] In one embodiment, refer to Figure 3 The comparator circuit 143 includes a fourth resistor R4, a fifth resistor R5, and a first comparator U2. The inverting input of the first comparator U2 is connected to the output of the first operational amplifier U1. The non-inverting input of the first comparator U2 is connected to the first end of the fourth resistor R4 and the first end of the fifth resistor R5. The output of the first comparator U2 is connected to the switching circuit 144. The second end of the fourth resistor R4 is grounded. The second end of the fifth resistor R5 is connected to the output of the power conversion chip 110. The first comparator U2 is used to output a turn-on signal when the first voltage signal provided by the first operational amplifier U1 is greater than the second voltage signal representing the first preset drop rate. The second voltage signal is the voltage signal obtained by dividing the output voltage of the power conversion chip 110 through the fourth resistor R4 and the fifth resistor R5.

[0039] Specifically, the second voltage signal is obtained by dividing the output voltage of the power conversion chip 110 through the fourth resistor R4 and the fifth resistor R5. The second voltage signal is denoted as... ,in, The first comparator U2 is used to compare the first voltage signal with the output voltage of the power conversion chip 110. Second voltage signal ,like ,Right now , converted , , For voltage sag rate, Let the first preset drop rate be denoted as . When the voltage drop rate is greater than the first preset drop rate, the first comparator U2 outputs a low-level conduction signal. The first preset drop rate can be set by setting the values ​​of resistors R2, R4, R5 and capacitor C2, so that the first preset drop rate is less than the normal power-down voltage drop rate. Once the voltage drop rate of the output voltage of the power conversion chip 110 exceeds the first preset drop rate, the first comparator U2 immediately outputs a low-level conduction signal. The capacitive load 145 can be connected to the input terminal of the power conversion chip 110 in advance before the voltage starts to drop.

[0040] If the first voltage signal is less than or equal to the second voltage signal, that is That is When the voltage drop rate is less than or equal to the first preset drop rate, and the load 130 does not lose power, the first comparator U2 outputs a high-level shutdown signal to prevent the capacitive load 145 from being connected to the input of the power conversion chip 110.

[0041] This circuit structure directly correlates the second voltage signal obtained by voltage division with the current output voltage of the power conversion chip 110, avoiding the problem of the preset drop rate threshold shift caused by temperature drift and component aging of the independent reference source. It can maintain the accuracy of the first preset drop rate in the entire operating range, reducing the probability of false triggering or missed triggering. At the same time, the entire comparison process only relies on the passive resistor voltage division and the direct comparison of the first comparator U2, which reduces the signal transmission delay and improves the response speed. It can quickly output the conduction signal in the initial stage of the sudden drop of the load 130, leaving enough time for the capacitive load 145 to complete the connection. The capacitive load 145 consumes the power of the front-end energy storage capacitor 120, effectively avoiding the failure of subsequent circuits such as reset and shutdown due to voltage drop.

[0042] In one embodiment, refer to Figure 3 The switching circuit 144 includes a seventh resistor R7 and a first switching transistor Q1. The first end of the seventh resistor R7 is connected to the output terminal of the first comparator U2 and the gate of the first switching transistor Q1, respectively. The second end of the seventh resistor R7 is connected to the energy storage capacitor 120 and the drain of the first switching transistor Q1, respectively. The source of the first switching transistor Q1 is connected to the capacitive load 145. When the first switch Q1 receives the turn-on signal output by the first comparator U2, it connects the capacitive load 145 and the energy storage capacitor 120.

[0043] Specifically, the capacitive load 145 includes a third capacitor C3 and a sixth resistor R6. The first terminal of the third capacitor C3 is connected to the source of the first switching transistor Q1, and the second terminal of the third capacitor C3 is grounded. The sixth resistor R6 is connected between the two terminals of the third capacitor C3. The first switching transistor Q1 receives the on / off signal output by the first operational amplifier U1. If it receives a low-level on signal output by the first operational amplifier U1, it pulls down the gate voltage of the first switching transistor Q1, thereby turning on the first switching transistor Q1. The turned-on first switching transistor Q1 connects the energy storage capacitor 120 and the capacitive load 145, and the energy storage capacitor 120 charges the capacitive load 145 through the first switching transistor Q1. The charging time constant of the third capacitor C3 is T = R6. C3, this time is the time it takes for the voltage of the third capacitor C3 to charge to approximately the preset voltage, which is K. VIN, K is less than 1, for example K=0.63, VIN is the input voltage of power conversion chip 110. To ensure that the third capacitor C3 is not fully charged when VOUT drops to the point where the downstream load 130 loses power and cannot operate, VOUT is set to drop to the critical voltage for normal operation of the downstream load 130 after a charging time constant T. Assuming the critical voltage for normal operation of the downstream load 130 is V1, then (VOUT-V1) / =T, which is (VOUT-V1) / =R6 By adjusting the values ​​of the third capacitor C3 and the sixth resistor R6, VOUT can be made to drop below the normal operating threshold voltage of the back-end load 130. At this point, the front-end energy storage capacitor 120 will still charge the capacitive load 145 (the third capacitor C3 and the sixth resistor R6), ensuring that the input voltage of the power conversion chip 110 drops smoothly when the back-end load 130 is disconnected.

[0044] If a high-level turn-off signal is received from the first operational amplifier U1, the gate voltage of the first switching transistor Q1 is pulled up, thereby turning off the first switching transistor Q1 and disconnecting the connection between the capacitive load 145 and the energy storage capacitor 120.

[0045] This setting can accurately match the voltage drop process after power failure, avoiding false protection triggered by premature charging of the third capacitor C3, and also avoiding untimely power failure protection due to slow charging of the third capacitor C3. This ensures that the triggering timing of power failure detection is stable and reliable. At the same time, the sixth resistor R6 is connected in parallel across the third capacitor C3, which can provide a stable discharge circuit for the third capacitor C3 when the power supply is working normally, avoiding the accumulation of residual charge in the third capacitor C3 and causing the threshold deviation of the next power failure detection, further improving the power failure state recognition accuracy of the detection control circuit 140.

[0046] In one embodiment, refer to Figure 4 The differential operation circuit 142 further includes a fourth capacitor C4, an eighth resistor R8, a ninth resistor R9, and a second operational amplifier U3. The first end of the fourth capacitor C4 is connected to the filter circuit 141. The second end of the fourth capacitor C4 is connected to the first end of the eighth resistor R8 and the inverting input terminal of the second operational amplifier U3. The second end of the eighth resistor R8 is connected to the output terminal of the second operational amplifier U3. The non-inverting input terminal of the second operational amplifier U3 is grounded through the ninth resistor R9. The output terminal of the second operational amplifier U3 is also connected to the comparator circuit 143. The second operational amplifier U3 is used to output a third voltage signal representing the voltage drop rate based on the received filtered voltage.

[0047] Specifically, the differential operation circuit 142 also includes a second operational amplifier U3. That is, the differential operation circuit 142 includes two parallel operational amplifier branches. Each operational amplifier branch includes a capacitor, two resistors and an operational amplifier. The two operational amplifier branches simultaneously provide a voltage drop rate for the subsequent comparator circuit 143, which can improve the accuracy of the voltage drop rate.

[0048] The third voltage signal is , This represents the rate of change of the filtered voltage over a preset time period t. Under normal circumstances, the third voltage signal is equal to the first voltage signal, i.e. ,therefore The third voltage signal is proportional to the first derivative of the filtered voltage with respect to time. The DC component is isolated by the second operational amplifier U3, and the capacitor blocks the DC, which can effectively remove the steady-state DC component in the filtered voltage, retaining only the characteristic component corresponding to the dynamic change of voltage, and avoiding the interference of the DC component on the drop rate judgment. At the same time, the differential operation circuit 142 has a simple structure and flexible device parameter adjustment. By matching the resistance values ​​of the fourth capacitor C4 and the eighth resistor R8, it can be adapted to the voltage drop detection requirements with different sensitivities. In different scenarios where the grid voltage drops slightly and rapidly or drops significantly and slowly, it can output a first voltage signal with a clearly distinguishable amplitude, providing an accurate characteristic basis for the drop judgment of the subsequent comparison circuit 143, and improving the response speed and recognition accuracy of voltage drop detection.

[0049] In one embodiment, refer to Figure 4 The comparator circuit 143 further includes a tenth resistor R10, an eleventh resistor R11, and a second comparator U4. The positive input terminal of the second comparator U4 is connected to the output terminal of the second operational amplifier U3. The inverting input terminal of the second comparator U4 is connected to the first terminal of the tenth resistor R10 and the first terminal of the eleventh resistor R11, respectively. The output terminal of the second comparator U4 is connected to the switching circuit 144. The second terminal of the tenth resistor R10 is grounded, and the second terminal of the eleventh resistor R11 is connected to the output terminal of the power conversion chip 110. The second comparator U4 is used to output a turn-on signal when the third voltage signal provided by the second operational amplifier U3 is less than the fourth voltage signal representing the second preset drop rate. The fourth voltage signal is the voltage signal obtained by dividing the output voltage of the power conversion chip 110 through the tenth resistor R10 and the eleventh resistor R11. The second preset drop rate is greater than the first preset drop rate.

[0050] Specifically, a second comparator U4 is connected after the second operational amplifier U3. The second comparator U4 is used to compare the voltage drop rate with a second preset drop rate. The second preset drop rate is used to indicate the upper limit of the rate, while the first preset drop rate is used to indicate the lower limit of the rate. The upper limit of the rate is limited by comparing the voltage drop rate with the second preset drop rate.

[0051] The fourth voltage signal corresponding to the second preset drop rate is obtained by dividing the output voltage of the power conversion chip 110 through the tenth resistor R10 and the eleventh resistor R11. The fourth voltage signal is denoted as ,like ,Right now , converted , The second preset drop rate is denoted as . When the voltage drop rate is less than the second preset drop rate, the second comparator U4 outputs a low-level conduction signal. The second preset drop rate can be set by adjusting the values ​​of resistors R8, R10, R11 and capacitor C4. This parameter setting method eliminates the need for a dedicated adjustable voltage reference chip. The target threshold can be obtained simply by adjusting the parameters of general-purpose resistors and capacitors. This reduces the overall material cost and wiring complexity of the circuit while ensuring the matching accuracy of the second preset drop rate. It is suitable for power conversion chips 110 with different power levels and output voltage specifications. At the same time, the reference signal is obtained by directly dividing the output voltage of the power conversion chip 110 itself. When the output voltage of the power conversion chip 110 fluctuates slightly, the fourth voltage signal will change proportionally with the output voltage. This causes the threshold of the second preset drop rate to adjust synchronously with the output voltage, avoiding the threshold misjudgment problem that occurs when the fixed reference voltage deviates from the output voltage. This effectively improves the stability and accuracy of voltage drop detection. In scenarios such as abnormal power loss of the power system or large sudden changes in the load 130, it can ensure that the subsequent switching circuit 144 accurately triggers the corresponding action, reducing the probability of damage to core components due to abnormal power supply.

[0052] In one embodiment, refer to Figure 4 The switching circuit 144 further includes a second switching transistor Q2, the gate of the second switching transistor Q2 is connected to the output terminal of the second comparator U4, the drain of the second switching transistor Q2 is connected to the source of the first switching transistor Q1, and the source of the second switching transistor Q2 is connected to the capacitive load 145. When the first switch Q1 receives the turn-on signal output by the first comparator U2, and the second switch Q2 receives the turn-on signal output by the second comparator U4, the capacitive load 145 and the energy storage capacitor 120 are connected.

[0053] Specifically, the switching circuit 144 also includes a second switching transistor Q2 connected to the second comparator U4, used to switch on and off based on the on / off signal output by the second comparator U4. A first switching transistor Q1 and a second switching transistor Q2 are provided between the capacitive load 145 and the input terminal of the power conversion chip 110. The first switching transistor Q1 is turned on or off based on the comparison result of the voltage drop rate and the first preset drop rate, while the second switching transistor Q2 is turned on or off based on the comparison result of the voltage drop rate and the second preset drop rate. Only when the first switching transistor Q1 and the second switching transistor Q2 are turned on simultaneously can the capacitive load 145 and the energy storage capacitor 120 be connected.

[0054] That is, only when the voltage sag rate meets the requirement <Vdown< Only when the first comparator U2 and the second comparator U4 simultaneously output low-level conduction signals can the first switch Q1 and the second switch Q2 be turned on simultaneously, and the front-end power supply VIN will be connected to the capacitive load 145 composed of the third capacitor C3 and the sixth resistor R6.

[0055] This dual-threshold segmented verification conduction structure can significantly reduce the probability of erroneous connection of capacitive load 145. When the system experiences only a small voltage fluctuation and the voltage drop rate does not exceed the first preset drop rate, both switches remain off, preventing the connection of capacitive load 145 and avoiding unnecessary energy loss. It also prevents disruption of the original stable output state of the front-end power supply. When the voltage drops abnormally sharply and the voltage drop rate exceeds the first preset drop rate, only the first switch Q1 is turned on and the second switch Q2 is turned off. Similarly, capacitive load 145 will not be connected. In this case, if the front-end power supply experiences an irreversible hard fault such as a short circuit, connecting capacitive load 145 will not provide voltage support. This design can reduce invalid actions and prevent the fault range from expanding further. Only when the voltage drop rate falls between two drop rate thresholds, corresponding to scenarios requiring additional power replenishment such as normal plugging and unplugging of a high-power load 130 or instantaneous high-power startup, will the dual switching transistors be triggered to conduct simultaneously. At this time, the capacitive load 145 can quickly charge and consume the energy storage capacitor 120, providing stable input voltage support for the downstream power conversion chip 110, preventing the chip's input voltage from rising and restarting. At the same time, the dual-switch series structure can also achieve fault redundancy verification. When any comparator or switching transistor experiences a false turn-on fault, the capacitive load 145 will not be incorrectly connected, effectively improving the working reliability and anti-interference capability of the entire detection and control circuit 140.

[0056] It should be noted that the examples and application scenarios implemented by the above modules and corresponding steps are the same, but are not limited to the content disclosed in the above embodiments. It should also be noted that the above modules, as part of a device, can operate in environments such as... Figure 1 The hardware environment shown can be implemented either through software or through hardware.

[0057] like Figure 5 As shown in the figure, this application provides a home appliance device, including a processor 711, a communication interface 712, a memory 713, and a communication bus 714. The processor 711, the communication interface 712, and the memory 713 communicate with each other through the communication bus 714. The memory 713 is used to store computer programs. The processor 711 is used to execute the programs stored in the memory 713.

[0058] The memory and processor in the aforementioned electronic devices communicate with each other via a communication bus and a communication interface. The communication bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into an address bus, a data bus, a control bus, etc.

[0059] The memory may include random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0060] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0061] Those skilled in the art will understand that Figure 5 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the home appliances to which the present application is applied. Specific home appliances may include more or fewer components than those shown in the figure, or may combine certain components, or may have different component arrangements.

[0062] According to another aspect of the embodiments of this application, a computer program product or computer program is also provided, which includes computer instructions stored in a computer-readable storage medium. A processor of a home appliance reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the home appliance to perform the steps of any of the above embodiments.

[0063] Optionally, specific examples in this embodiment can refer to the examples described in the above embodiments, and will not be repeated here.

[0064] It is understood that the embodiments described herein can be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the processing unit can be implemented in one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers, microprocessors, other electronic units for performing the functions described herein, or combinations thereof.

[0065] For software implementation, the techniques described herein can be implemented by units that perform the functions described herein. The software code can be stored in memory and executed by a processor. The memory can be implemented in the processor or external to the processor.

[0066] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different power management circuits for each specific application to implement the described functions, but such implementation should not be considered beyond the scope of this application.

[0067] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned power management circuit embodiments, and will not be repeated here.

[0068] In the embodiments provided in this application, it should be understood that the disclosed devices and power management circuits can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0069] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0070] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0071] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a general-purpose hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as a USB flash drive, a portable hard drive, ROM, RAM, a magnetic disk, or an optical disk, or other media that can store program code, including several instructions to cause a home appliance (which may be a personal computer, a server, or a network device, etc.) to execute the power management circuit described in various embodiments or some parts of the embodiments.

[0072] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also mean including the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The power management circuit steps, processes, and operations described herein are not construed as requiring them to be performed in the specific order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that alternatives or substitutions may be used.

[0073] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A power management circuit, characterized in that, The power management circuit includes: A power conversion chip, wherein the input terminal of the power conversion chip is connected to an energy storage capacitor, and the output terminal of the power conversion chip is connected to a load; A detection control circuit is provided, wherein the input terminal of the detection control circuit is connected to the output terminal of the power conversion chip, and the output terminal of the detection control circuit is connected to the input terminal of the power conversion chip. The detection control circuit is used to detect the voltage drop rate at the output terminal of the power conversion chip, and when the voltage drop rate is greater than a first preset drop rate, the capacitive load is connected to the energy storage capacitor, and the energy storage capacitor is used to charge the capacitive load, thereby preventing the input voltage of the power conversion chip from rising due to the load power loss.

2. The power management circuit according to claim 1, characterized in that, The detection control circuit includes: A filtering circuit, connected to the output terminal of the power conversion chip, is used to filter the output voltage of the power conversion chip and output a filtered voltage. A differential operation circuit is connected to the output terminal of the filter circuit and is used to output the voltage drop rate according to the filter voltage. A comparator circuit, connected to the output of the differential operation circuit, is used to output a conduction signal when the voltage drop rate is greater than a first preset drop rate. A switching circuit is connected to the output terminal of the comparator circuit, the energy storage capacitor, and the capacitive load, respectively, and is used to connect the capacitive load and the energy storage capacitor according to the conduction signal.

3. The power management circuit according to claim 2, characterized in that, The filter circuit includes a first resistor and a first capacitor. The first end of the first resistor is connected to the output terminal of the power conversion chip, the second end of the first resistor is connected to the differential operation circuit and the first end of the first capacitor, and the second end of the first capacitor is grounded.

4. The power management circuit according to claim 2, characterized in that, The differential operation circuit includes a second capacitor, a second resistor, a third resistor, and a first operational amplifier. The first end of the second capacitor is connected to the filter circuit. The second end of the second capacitor is connected to the second resistor and the inverting input terminal of the first operational amplifier. The second end of the second resistor is connected to the output terminal of the first operational amplifier. The non-inverting input terminal of the first operational amplifier is grounded through the third resistor. The output terminal of the first operational amplifier is also connected to the comparator circuit. The first operational amplifier is used to output a first voltage signal representing the voltage drop rate based on the received filtered voltage.

5. The power management circuit according to claim 4, characterized in that, The comparison circuit includes a fourth resistor, a fifth resistor, and a first comparator. The inverting input of the first comparator is connected to the output of the first operational amplifier. The non-inverting input of the first comparator is connected to the first end of the fourth resistor and the first end of the fifth resistor, respectively. The output of the first comparator is connected to the switching circuit. The second end of the fourth resistor is grounded, and the second end of the fifth resistor is connected to the output of the power conversion chip. The first comparator is used to output a turn-on signal when the first voltage signal provided by the first operational amplifier is greater than the second voltage signal representing the first preset drop rate. The second voltage signal is the voltage signal obtained by dividing the output voltage of the power conversion chip through the fourth resistor and the fifth resistor.

6. The power management circuit according to claim 5, characterized in that, The switching circuit includes a seventh resistor and a first switching transistor. The first end of the seventh resistor is connected to the output of the first comparator and the gate of the first switching transistor, respectively. The second end of the seventh resistor is connected to the energy storage capacitor and the drain of the first switching transistor, respectively. The source of the first switching transistor is connected to the capacitive load. When the first switching transistor receives the turn-on signal output by the first comparator, it connects the capacitive load and the energy storage capacitor.

7. The power management circuit according to claim 6, characterized in that, The differential operation circuit further includes a fourth capacitor, an eighth resistor, a ninth resistor, and a second operational amplifier. The first end of the fourth capacitor is connected to the filter circuit. The second end of the fourth capacitor is connected to the first end of the eighth resistor and the inverting input terminal of the second operational amplifier. The second end of the eighth resistor is connected to the output terminal of the second operational amplifier. The non-inverting input terminal of the second operational amplifier is grounded through the ninth resistor. The output terminal of the second operational amplifier is also connected to the comparator circuit. The second operational amplifier is used to output a third voltage signal representing the voltage drop rate based on the received filtered voltage.

8. The power management circuit according to claim 7, characterized in that, The comparison circuit further includes a tenth resistor, an eleventh resistor, and a second comparator. The positive input terminal of the second comparator is connected to the output terminal of the second operational amplifier. The inverting input terminal of the second comparator is connected to the first terminal of the tenth resistor and the first terminal of the eleventh resistor, respectively. The output terminal of the second comparator is connected to the switching circuit. The second terminal of the tenth resistor is grounded, and the second terminal of the eleventh resistor is connected to the output terminal of the power conversion chip. The second comparator is used to output a turn-on signal when the third voltage signal provided by the second operational amplifier is less than the fourth voltage signal representing the second preset drop rate. The fourth voltage signal is the voltage signal obtained by dividing the output voltage of the power conversion chip through the tenth resistor and the eleventh resistor. The second preset drop rate is greater than the first preset drop rate.

9. The power management circuit according to claim 8, characterized in that, The switching circuit further includes a second switching transistor, the gate of which is connected to the output of the second comparator, the drain of which is connected to the source of the first switching transistor, and the source of which is connected to the capacitive load. When the first switch receives the turn-on signal output by the first comparator and the second switch receives the turn-on signal output by the second comparator, the capacitive load and the energy storage capacitor are connected.

10. A household appliance, characterized in that, The home appliance includes a power management circuit as described in any one of claims 1 to 9.

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