A negative voltage charge pump output discharge control circuit

Abstract

The application relates to the technical field of integrated circuits and discloses a negative voltage charge pump output discharge control circuit which comprises an enable control module, a voltage division module, a discharge module, a basic level module and a closed-loop feedback module. The enable control module uniformly controls the start and stop of each branch according to an external enable signal; the voltage division module collects a voltage difference between an input power supply and a negative voltage output and outputs a collected voltage; the basic level module is continuously turned on to realize potential clamping; the discharge module bleeds residual negative voltage according to the collected voltage and extracts a feedback voltage; and the closed-loop feedback module builds a feedback channel and dynamically adjusts a discharge impedance according to a difference between the negative voltage output and the ground. The greater the absolute value of the negative voltage is, the smaller the discharge impedance is. When the potential approaches the ground, the impedance is automatically increased to realize self-adaptive current limiting. The application does not need active devices, has high integration, can inhibit discharge surges, reduce standby power consumption, and is suitable for OLED, storage and vehicle-mounted low-voltage single power supply chips.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a negative pressure charge pump output discharge control circuit. Background Technology

[0002] Negative charge pumps are commonly used on-chip negative voltage generation power modules in integrated circuits. They rely on the time-sharing charging and discharging of charge transfer capacitors to convert positive input voltage to negative voltage, and are widely used in integrated circuit systems such as OLED display drivers, memory chips, RF analog front-ends, and automotive signal processing. This type of circuit requires no inductors, has high integration density, occupies a small chip layout area, and is compatible with low-voltage single-supply chip architectures. During normal operation, a large-capacity load capacitor is connected in parallel at the output to store negative charge, ensuring stable output voltage and sufficient load driving capability. When the chip system switches operating modes, goes into standby mode, or the negative voltage output channel is turned off, a large amount of residual negative charge remains in the load capacitor.

[0003] After the negative charge pump stops, the residual negative charge remaining on the load capacitor needs to be discharged in a controlled manner. Without a dedicated discharge control circuit, multiple device failure risks will arise. The residual negative voltage of the capacitor directly acts on the gate and source terminals of the subsequent low-voltage MOS devices, which can easily exceed the rated withstand voltage threshold of the devices, causing gate oxide layer breakdown and permanent transistor damage. Uncontrolled discharge of residual charge will create a sudden large current surge, which will cause drastic changes in the internal potential of the chip, interfering with the normal operation of other analog and digital modules on the same chip. In addition, uncontrolled continuous leakage will significantly increase the chip's standby static power consumption.

[0004] Existing negative pressure charge pump output discharge control schemes mainly adopt a fixed power resistor direct discharge architecture. The circuit structure is simple, but the current surge amplitude is large in the initial stage of discharge, there is no adaptive current limiting capability, and the gate has no reliable clamping protection under high voltage conditions, resulting in a high risk of device breakdown. Summary of the Invention

[0005] To achieve adaptive current limiting capability, this application provides a negative pressure charge pump output discharge control circuit, which adopts the following technical solution:

[0006] A negative pressure charge pump output discharge control circuit includes an enable control module, a voltage divider module, a discharge module, a base level module, and a closed-loop feedback module.

[0007] The enabling control module acquires an external enabling signal corresponding to the working state of the negative pressure charge pump; if the external enabling signal corresponds to the discharge condition of the negative pressure charge pump, the voltage divider module is activated, and the discharge module and the closed-loop feedback module are in an enabled working state; if the external enabling signal corresponds to the normal working condition of the negative pressure charge pump, the voltage divider module is deactivated, and the discharge module and the closed-loop feedback module are in a disabled shutdown state.

[0008] The voltage divider module is electrically connected to the positive terminal of the input power supply through the enable control module, and is electrically connected to the output terminal of the negative charge pump through the base level module. The base level module is kept in a normally conducting state to achieve voltage clamping. The voltage divider module is used to collect the voltage between the positive terminal of the input power supply and the output terminal of the negative charge pump and perform voltage division processing to generate the collected voltage and output it to the discharge module and the closed-loop feedback module.

[0009] The input terminal of the discharge module receives the collected voltage. When the collected voltage is greater than the preset start-up driving voltage, the discharge module opens the path between the output terminal of the negative pressure charge pump and the ground to realize the negative pressure charge discharge, and collects the intermediate voltage between the output terminal of the negative pressure charge pump and the ground as the feedback voltage, and outputs the feedback voltage to the closed-loop feedback module.

[0010] The closed-loop feedback module receives the feedback voltage and constructs a feedback channel based on the feedback voltage to connect the output terminal of the negative pressure charge pump to the input terminal of the discharge module. The feedback channel dynamically adjusts the on-resistance of the discharge module according to the output voltage of the negative pressure charge pump. The greater the difference between the output voltage of the negative pressure charge pump and ground, the smaller the on-resistance of the discharge module. The closer the output voltage of the negative pressure charge pump is to ground potential, the greater the on-resistance of the discharge module.

[0011] By adopting the above technical solution, a closed-loop adaptive discharge control mechanism is formed through the coordinated cooperation of various modules. Compared with the traditional fixed resistor discharge scheme, the discharge module's on-resistance can be dynamically adjusted according to the residual negative voltage at the output of the negative voltage charge pump, thereby achieving adaptive current limiting of the discharge current. This effectively suppresses the current surge in the initial stage of discharge, clamps the gate voltage of the device, eliminates the risk of MOS device breakdown and damage, and smoothly completes the discharge of residual negative voltage charge. This avoids the internal potential jump of the chip interfering with the operation of other modules and can also reduce the chip's standby leakage current and static power consumption.

[0012] Optionally, the enable control module includes a high-voltage PMOS transistor M1; the source of the high-voltage PMOS transistor M1 is connected to the input power supply VIN, the gate is connected to an external working enable signal, and the drain is electrically connected to the input terminal of the voltage divider module; when the external enable signal is low, the high-voltage PMOS transistor M1 is turned on, the input power supply VIN supplies power to the voltage divider module, and the discharge process is started; when the external enable signal is high, the high-voltage PMOS transistor M1 is turned off, cutting off the power supply path of the voltage divider module, so that the voltage divider module, the discharge module and the closed-loop feedback module are synchronously disabled.

[0013] By adopting the above technical solution, a high-voltage PMOS transistor is used as an enable switch to control the on / off state of the power supply path. The high voltage withstand characteristics of the high-voltage PMOS transistor are adapted to the high voltage input conditions of the chip. The power supply start and stop of the discharge branch can be completed synchronously with only a single enable signal. The number of circuit components is small, the layout area is small, the switching response speed is fast, and the working status of the voltage divider, discharge, and feedback modules can be accurately and synchronously controlled. This avoids the generation of additional static leakage current in the voltage divider branch when the negative voltage charge pump is working normally, and further reduces the chip's normal operating power consumption.

[0014] Optionally, the voltage divider module includes a voltage divider resistor R1 and a voltage divider resistor R2 connected in series; the upper end of the voltage divider resistor R1 is electrically connected to the drain of the high-voltage PMOS transistor M1, the lower end of the voltage divider resistor R1 is connected to the upper end of the voltage divider resistor R2 to form node A, the node A outputs the sampled voltage and is respectively connected to the discharge module and the closed-loop feedback module, and the lower end of the voltage divider resistor R2 is electrically connected to the basic level module.

[0015] By adopting the above technical solution, using R1 and R2 series resistors to form a voltage divider branch, the wide voltage difference between the positive terminal of the input power supply and the output terminal of the negative voltage charge pump can be converted into a sampling voltage that is compatible with the withstand voltage range of the subsequent discharge and feedback modules. The resistor voltage divider circuit has a simple structure, occupies a small chip layout area, has good voltage sampling linearity, and can restore the residual voltage change trend at the negative voltage output terminal.

[0016] Optionally, the discharge module includes a resistor R3, a discharge MOSFET M2, and a voltage divider resistor R4; one end of the resistor R3 is grounded, and the other end is connected to the drain of the discharge MOSFET M2; the gate of the discharge MOSFET M2 is connected to node A; the source of the discharge MOSFET M2 is connected to the upper end of the voltage divider resistor R4 to form node B; node B outputs a feedback voltage to the closed-loop feedback module; and the lower end of the voltage divider resistor R4 is connected to the output terminal of the negative voltage charge pump.

[0017] By adopting the above technical solution, the discharge module relies on R3, the discharge MOSFET M2 and the voltage divider resistor R4 to build a linkage path. The voltage divider level at node A controls the on / off state of M2. The negative voltage output by the charge pump is generated at node B via R4 and sent to the closed-loop feedback module. When powered on, M2 can be controlled to turn off, avoiding the loss of negative voltage charge pump output energy in the discharge branch and ensuring the accuracy of VOUT negative voltage output. When powered off / enabled, M2 is turned on, and R3 and R4 form a discharge circuit to quickly release the residual negative voltage of the load capacitor Cload. At the same time, M4 clamps the potential of node B to prevent negative voltage backflow from damaging the front-end voltage divider branch. It takes into account the triple advantages of low power consumption during normal operation, fast discharge during shutdown and accurate feedback sampling.

[0018] Optionally, the base level module includes an NMOS transistor M3; the gate of the NMOS transistor M3 is connected to a zero-level signal, the source is connected to the output terminal of the negative voltage charge pump, and the drain is electrically connected to the lower end of the voltage divider resistor R2. The NMOS transistor M3 remains in the conducting state throughout, providing a stable reference potential for the voltage divider module and realizing voltage clamping.

[0019] By adopting the above technical solution, the NMOS transistor M3, whose gate is connected to a zero-level signal, is continuously turned on, so that the output potential of the negative charge pump is stably supplied to the lower end of R2. On the one hand, it provides a constant and reliable reference potential for the voltage divider module composed of R1 and R2, ensuring that the voltage level of node A is not affected by the output fluctuation of the charge pump, and accurately controlling the switching logic of the discharge MOS transistor M2. On the other hand, M3 can form a voltage clamp on the lower end of the voltage divider branch, blocking the negative voltage output of the negative charge pump from flowing back into the previous stage voltage divider path, avoiding overvoltage damage to the voltage divider device. At the same time, the continuous conduction state does not require additional timing control, simplifying the circuit logic, reducing static control power consumption, and improving the overall working stability and device reliability of the negative charge pump system.

[0020] Optionally, the closed-loop feedback module includes a feedback PMOS transistor M4; the gate of the feedback PMOS transistor M4 is connected to the feedback voltage output by node B, the source of the feedback PMOS transistor M4 is connected to the output terminal of the negative voltage charge pump, and the drain of the feedback PMOS transistor M4 is connected to the gate of the discharge MOS transistor M2, thus forming a closed-loop feedback regulation path.

[0021] By adopting the above technical solution, a closed-loop feedback path is built using only a single PMOS transistor M4. The circuit structure is extremely simple, the chip layout occupies a small area, and the feedback branch conduction capability can be dynamically adjusted in real time according to the residual voltage output of the negative voltage charge pump. When the residual negative voltage is larger, the conduction degree of M4 is higher and the equivalent impedance of the discharge module is smaller. When the voltage approaches ground in the later stage of discharge, the conduction degree of M4 decreases and the discharge impedance increases, thereby achieving adaptive current limiting, suppressing discharge surge current, stabilizing and controlling the discharge rate, reducing potential change interference to other modules of the chip, and reducing standby leakage power consumption.

[0022] Optionally, when the external working enable signal is low, the high-voltage PMOS transistor M1 is turned on, and the input power supply VIN provides a voltage divider potential to node A through the high-voltage PMOS transistor M1 and the voltage divider resistor R1; the sampling voltage output by node A is connected to the gate of the discharge MOS transistor M2 through resistor R3, and the discharge main path composed of ground, resistor R3, discharge MOS transistor M2, voltage divider resistor R4, and the output terminal of the negative voltage charge pump is turned on, and node B outputs a feedback voltage; the sampling voltage output by node A is connected to the drain of the normally conducting NMOS transistor M3 through the voltage divider resistor R2, and the potential clamping of node A is achieved through the cooperation of voltage divider resistor R1, voltage divider resistor R2 and NMOS transistor M3; the feedback voltage output by node B is connected to the gate of the feedback PMOS transistor M4, and a closed-loop feedback adjustment channel is constructed through the feedback PMOS transistor M4.

[0023] By adopting the above technical solution, the gate drive voltage and high voltage clamping voltage are output synchronously through the same node A. The normally conducting NMOS transistor is used to achieve isolation and protection of high and low voltage devices. At the same time, a real-time feedback loop is built with M4. The on-resistance of the discharge branch can be dynamically adjusted according to the residual negative voltage VOUT. Under the premise of ensuring stable discharge of residual charge, the surge current in the early stage of discharge is suppressed, and the risk of overvoltage breakdown of the gate of the low voltage MOS at the back end is avoided. Moreover, the voltage divider, clamping and feedback branches are all micro-current branches, which will not increase the discharge loss and static power consumption.

[0024] Optionally, during the discharge process, when the output potential of the negative voltage charge pump rises to ground, the potential of node B changes synchronously, changing the gate-source voltage of the feedback PMOS transistor M4, adjusting the on-resistance of the feedback PMOS transistor M4, and thus finely adjusting the voltage divider potential at point A, changing the gate drive voltage of the discharge MOS transistor M2, and dynamically adjusting the on-resistance of the discharge MOS transistor M2; when the output potential of the negative voltage charge pump approaches ground potential at the end of the discharge, the on-resistance of the discharge MOS transistor M2 automatically increases to limit the discharge current; throughout the discharge process, the voltage divider resistors R1 and R2 maintain micro-current operation, the NMOS transistor M3 continues to conduct to achieve high-voltage clamping, and the resistors R3 and R4 carry the discharge main circuit current.

[0025] By adopting the above technical solution, adaptive dynamic current limiting of discharge current can be achieved solely by relying on the transmission characteristics of MOSFETs and passive voltage divider networks. No additional active devices such as reference sources and operational amplifiers are required. The circuit structure is simplified and has low static power consumption. At the end of the discharge, the discharge impedance can be automatically raised to suppress surge impact. At the same time, the voltage divider branch operates with microcurrent and the high voltage clamp is continuously effective, taking into account the discharge rate, device withstand voltage safety and low power consumption characteristics, and greatly improving the stability of the entire process of negative voltage residual charge discharge.

[0026] Optionally, when the external enable signal switches to a high level, the high-voltage PMOS transistor M1 is turned off, the input power supply VIN is electrically isolated from the back-end voltage divider, discharge, and feedback branches, and the potential of node A drops to a low level; the discharge MOS transistor M2 is cut off due to the loss of its gate drive voltage, and the main discharge path is disconnected; the feedback PMOS transistor M4 is turned off synchronously without an effective feedback voltage, and the closed-loop feedback channel stops working; the NMOS transistor M3 remains in the conducting state, but no current flows through the voltage divider resistors R1 and R2 branches, and the entire discharge circuit enters a standby state with zero static leakage current.

[0027] By adopting the above technical solution, the power supply, discharge, and feedback branches can be cut off simultaneously with a single enable signal. After being turned off, the voltage divider branch has no current and the circuit has almost zero static power consumption. This completely eliminates the load interference of the discharge branch on the boost operation of the negative voltage charge pump. All control paths are turned off synchronously and quickly, with thorough isolation and no leakage risks, which greatly reduces the power consumption during normal operation and standby of the chip.

[0028] In summary, this application includes at least one of the following beneficial technical effects: This application adopts a closed-loop adaptive discharge architecture built with pure MOSFETs and passive resistors, eliminating the need for active devices such as operational amplifiers and reference sources, resulting in a small chip layout area. The enable module uniformly controls the on / off state of all branches. During the discharge stage, the discharge impedance is dynamically adjusted in real time based on voltage divider sampling and single-tube feedback loop, adaptively suppressing discharge surges throughout the entire stage. Combined with the continuous high-voltage clamping protection of low-voltage MOSFETs by normally-on NMOS, each branch is synchronously isolated under the off-state condition, and the voltage divider branch has no current, achieving near-zero static power consumption. This not only reliably discharges the residual negative voltage charge of the load capacitor and avoids chip potential jumps interfering with other circuit modules, but also solves the defects of traditional fixed resistor discharge circuits, such as easy device breakdown, large current surge, and high standby leakage current, from multiple dimensions such as device withstand voltage, surge protection, low power consumption, and integration. Attached Figure Description

[0029] Figure 1 This is the overall circuit diagram of the negative pressure charge pump output discharge control circuit in this embodiment of the invention. Detailed Implementation

[0030] The embodiments of this application are described in detail below, and examples of the embodiments are shown in the accompanying drawings.

[0031] This embodiment is a preferred specific implementation of the present invention, and is only used to clearly and completely explain the technical principles, hardware connection relationships, and full-condition working logic of the present invention. It is not intended to limit the scope of protection of the present invention. Simple equivalent substitutions or parameter fine-tuning made by those skilled in the art to the MOS transistor type, resistor value ratio, and device voltage rating in this embodiment without creative effort are all within the scope of protection covered by the claims of the present invention.

[0032] In this embodiment, the circuit and the core circuit of the negative charge pump are integrated on the same semiconductor chip wafer, sharing a unified chip input power supply VIN and a common reference ground GND. The negative output port of the negative charge pump is defined as VOUT, and the VOUT pin is connected in parallel with the on-chip integrated load capacitor Cload to GND. The function of the load capacitor Cload is to store negative charge, smooth the VOUT output voltage, and improve the charge pump's load-driving capability. When the chip system switches to standby, channel-off, or shutdown modes, a large amount of residual negative charge will remain inside the load capacitor Cload. If no controllable discharge is performed, the residual negative voltage will exceed the gate-source withstand voltage of the downstream low-voltage MOS device, causing permanent breakdown of the gate oxide layer. Unconstrained discharge will generate a sudden large current surge, causing a violent jump in the global potential inside the chip, interfering with the normal operation of other functional modules such as on-chip digital logic, analog amplification, and reference. At the same time, continuous leakage will significantly increase the overall static power consumption of the chip. The negative charge pump output discharge control circuit disclosed in this embodiment is specifically designed to achieve safe, adaptive current limiting, and ultra-low static power consumption controllable discharge of the residual negative charge inside Cload.

[0033] The circuit in this embodiment includes an enable control module, a voltage divider module, a discharge module, a base level module, and a closed-loop feedback module. All functional units are built using only on-chip integrated MOS transistors and passive polysilicon resistors. No on-chip operational amplifiers, bandgap reference sources, off-chip inductors, capacitors, or other active or discrete components are required. The chip layout occupies a small area, has high integration, and lower manufacturing costs. It is compatible with various low-voltage single-supply integrated circuit architectures such as OLED display driver chips, memory chips, automotive analog front-ends, and RF signal processing chips.

[0034] The enable control module is the main switch control unit of the entire discharge circuit. Its function is to receive the external enable signal sent by the system and control the overall power supply of the downstream voltage divider module, discharge module and closed-loop feedback module in a unified manner according to the signal level logic. It can realize the enable / disable switching of all downstream branches synchronously with only a single control signal. The signal synchronization is strong and the control logic is simple.

[0035] In this embodiment, the enable control module is composed of a single high-voltage PMOS transistor M1. Considering that the chip input power supply VIN has a high-voltage input condition, ordinary low-voltage MOS transistors cannot withstand the high voltage difference of VIN. Therefore, M1 is selected as a high-voltage PMOS device with gate-source and drain-source withstand voltage specifications higher than the maximum rated voltage of VIN, thus avoiding the risk of high-voltage breakdown failure from the device selection level.

[0036] Complete electrical connection: The source metal pad of the high-voltage PMOS transistor M1 is directly electrically connected to the positive terminal VIN of the chip's input power supply; the gate of M1 is led out to the external control pin of the chip to receive the external working enable signal output by the system's main control unit; the drain of M1 serves as the power output terminal of the enable control module and is directly connected to the upper pad of the voltage divider resistor R1 inside the voltage divider module through the top metal interconnect.

[0037] This module has two stable operating conditions with clear level switching logic: In the first condition, the external enable signal outputs a low level. At this time, the gate potential of M1 is lower than the source potential VIN, and the gate-source voltage Vgs < 0, which meets the PMOS transistor conduction condition. The M1 channel is fully turned on, and the input power supply VIN can continuously supply a stable power supply voltage to the downstream voltage divider module. The voltage divider module, discharge module, and closed-loop feedback module simultaneously enter the enabled working state, and the entire discharge circuit starts the negative voltage charge discharge process. In the second condition, the external enable signal switches to a high level. The gate potential of M1 is completely equal to the source potential VIN, and the gate-source voltage Vgs = 0. No conductive channel is formed inside the PMOS transistor, and M1 is completely turned off. The input power supply VIN is completely electrically isolated from all branches of the downstream voltage divider, discharge, and feedback. The voltage divider module loses its power supply, and the discharge module and closed-loop feedback module simultaneously enter the disabled shutdown state, and the discharge process terminates.

[0038] Using a high-voltage PMOS transistor as the master enable switch, all discharge branches can be turned on and off synchronously with only a single control signal. The circuit requires fewer components and occupies less chip area. The MOS transistor has a fast switching response and no delay in level switching, which can accurately and synchronously control the working status of all downstream modules. During the normal voltage boosting phase of the negative voltage charge pump, M1 is continuously turned off, and there is no power input to the voltage divider branch. There is no additional static leakage current, which further reduces the overall power consumption of the chip under normal operation.

[0039] The voltage divider module is electrically connected in series between the output of the enable control module and the base level module, and is connected across the positive terminal VIN of the input power supply and the output terminal VOUT of the negative voltage charge pump. It has two core functions: first, it acquires the wide voltage difference between the high voltage VIN and the negative voltage VOUT to complete the voltage scaling and voltage division process; second, it outputs a voltage that matches the rated withstand voltage range of the low-voltage MOS device in the back end and sends it to the discharge module and the closed-loop feedback module as the control reference potential.

[0040] In this embodiment, the voltage divider module consists of two high-resistance polysilicon resistors R1 and R2 connected in series. R1 and R2 are selected as high-resistance resistors with a value of over kiloohms. The design intention is to ensure that only a microampere-level weak current flows through the entire voltage divider branch, so as not to generate a large power loss and avoid additional increase in the overall power consumption of the chip.

[0041] Complete electrical connection: The upper metal pad of voltage divider resistor R1 is directly connected to the drain output terminal of high-voltage PMOS transistor M1, receiving the VIN power supply voltage after M1 is turned on; the lower metal pad of R1 intersects with the upper metal pad of voltage divider resistor R2, and this intersection node is defined as node A, which is the core voltage output node of this voltage divider module; node A also leads out two independent metal connections, the first metal connection is connected to the gate of M2; the second metal connection is connected to the drain terminal of feedback PMOS transistor M4 of the closed-loop feedback module, providing a reference adjustment potential for the feedback adjustment path; the lower metal pad of voltage divider resistor R2 extends downward and is electrically connected to the drain pin of NMOS transistor M3 of the basic level module.

[0042] The overall working principle of the voltage divider module is as follows: VIN is a positive high voltage potential, and VOUT is a negative voltage potential. There is a huge voltage difference between the two. Directly applying this voltage difference to the gate of low-voltage MOSFETs such as M2 and M4 will directly cause gate oxide breakdown. The wide voltage difference is scaled and converted by fixing the voltage division ratio through resistors R1 and R2, so that the sampling voltage at node A is controlled and within the safe withstand voltage range of low-voltage devices. At the same time, R1, R2 and the normally conducting M3 cooperate to form a voltage divider clamping circuit, which stably constrains the potential of node A within the safe voltage range, eliminates the sampling voltage distortion caused by VOUT negative voltage drift and temperature drift, and has excellent voltage acquisition linearity. It can accurately reproduce the change trend of the residual voltage at the negative voltage output terminal in real time, and provide a stable and accurate sampling reference potential for subsequent discharge control and feedback regulation.

[0043] The basic level module is connected in series at the end of the voltage divider module. Its core functions are twofold: First, it provides a stable, temperature-drift-free, and negative voltage offset ground potential reference for the voltage divider branch formed by R1 and R2, ensuring that the sampling accuracy of the output voltage of node A is not affected by VOUT negative voltage fluctuations or chip temperature changes. Second, it continuously clamps the voltage at the lower end of the voltage divider branch and the VOUT negative voltage end, achieving electrical isolation protection between the front-end high-voltage area and the back-end low-voltage device area, blocking the direct conduction of VIN high voltage to the gate-source terminals of low-voltage MOS transistors such as M2 and M4, and avoiding the risk of gate oxide layer breakdown and permanent transistor failure of low-voltage devices from the hardware level.

[0044] In this embodiment, the basic level module is composed of a single general-purpose low-voltage NMOS transistor M3, which is a normally conducting clamping device. The complete electrical connection is as follows: the gate pin of M3 is constantly connected to a 0-level ground signal through a metal interconnect, maintaining a zero potential throughout; the source pin of M3 is directly connected to the negative voltage output port of the chip's negative voltage charge pump; the drain pin of M3 is electrically connected to the lower pad of the voltage divider resistor R2.

[0045] After the chip is powered on, the gate of M3 remains continuously grounded, and the source is synchronously grounded. The gate-source voltage Vgs is always greater than the NMOS turn-on threshold voltage. Therefore, M3 remains in the on state throughout the entire operating cycle of the chip, with no turn-off condition. No additional control signals are required, and the circuit control logic is extremely simple. M3 uses only a single NMOS transistor to achieve clamping and reference potential supply. The device structure is simple, the chip layout occupies a very small area, and it will not significantly increase the chip manufacturing cost and area overhead.

[0046] The discharge module has two core functions: First, when the sampling voltage reaches the threshold, it conducts the discharge path between the output terminal VOUT of the negative voltage charge pump and ground to release the residual negative voltage charge stored inside the load capacitor Cload; Second, it collects the intermediate voltage potential between the negative voltage of VOUT and the ground potential in real time, and continuously outputs the intermediate potential as the feedback voltage to the closed-loop feedback module to provide a real-time sampling signal for adaptive current limiting regulation.

[0047] The discharge module in this embodiment includes three types of passive and active devices: resistor R3, discharge NMOS transistor M2, and resistor R4.

[0048] Complete electrical connection: The upper metal wire of resistor R3 is grounded, and the lower metal wire of R3 is connected to the drain of MOSFET M2. Node A is connected to the gate pin of the discharge MOSFET M2. The drain pin of the discharge NMOS transistor M2 is grounded to GND through resistor R3. The source pin of M2 intersects with the upper pad of resistor R4, and this intersection node is defined as node B. The lower pin of resistor R4 is directly connected to the negative voltage output port of the chip's negative voltage charge pump.

[0049] Module Working Principle: When the amplitude of the sampling voltage output by node A is greater than the preset turn-on threshold voltage of M2, the gate-source voltage of M2 meets the conduction condition, the drain-source conductive channel is fully opened, forming a complete and continuous discharge main path. The complete path is as follows: chip ground GND → resistor R3 → gate-source conductive channel of discharge MOS transistor M2 → resistor R4 → negative voltage output terminal VOUT → load capacitor Cload. The residual negative voltage charge stored inside the load capacitor Cload will continuously flow back to ground along this path, completing the safe discharge of negative voltage. Node B, between the source of M2 and R4, can collect the intermediate voltage potential between the negative voltage VOUT and the ground potential in real time. The potential changes synchronously with VOUT in real time, and this potential is continuously output to the gate of the closed-loop feedback module M4 as a feedback voltage, providing a continuous real-time sampling signal for adaptive current limiting adjustment. Using only a single MOSFET and two resistors, negative voltage discharge and feedback voltage sampling can be achieved simultaneously. The circuit topology is simple and the chip integration is high. R3 and R4 are selected as power resistors with higher current ratings, which can stably carry the instantaneous large current of the discharge main circuit, taking into account both the charge discharge rate and the long-term endurance of the device.

[0050] The closed-loop feedback module is the core unit for achieving adaptive current limiting. It consists of a single feedback PMOS transistor M4 to build a negative feedback closed-loop regulation channel. Its core function is to dynamically adjust its own on-resistance according to the real-time feedback voltage output from node B, thereby indirectly changing the gate drive voltage of the discharge MOS transistor M2 and automatically adjusting the on-resistance of M2 to form an adaptive negative feedback regulation logic. This solves the defects of traditional fixed resistor discharge circuits, such as lack of adaptive current limiting and large discharge surge.

[0051] Complete electrical connection: The gate pin of M4 receives the real-time feedback voltage output from node B; the source pin of M4 is directly connected to the output terminal VOUT of the negative voltage charge pump; the drain pin of M4 is simultaneously connected in two ways, one to the output terminal of node A and the other to the gate pin of the discharge MOSFET M2, thereby establishing a closed-loop feedback regulation channel between the negative voltage terminal of VOUT and the gate drive terminal of M2.

[0052] Adaptive current limiting logic: The on-resistance of M4 is directly determined by the gate-source voltage Vgs, which dynamically changes synchronously with the feedback potential of node B. The larger the absolute value of the negative voltage VOUT at the output of the negative charge pump and the farther the potential is from ground, the larger the gate-source voltage difference of M4, and the smaller the on-resistance of M4. The drain of M4 pulls down the gate potential of M2 and raises the effective driving voltage of M2, causing the on-resistance of M2 to decrease synchronously, and the discharge current to increase accordingly, ensuring that a large amount of residual charge is quickly discharged in the early stage of discharge. As the discharge continues, the absolute value of the negative voltage VOUT continues to decrease and the potential slowly rises towards ground, the gate-source voltage difference of M4 continues to decrease, and the on-resistance of M4 gradually increases. The effect of the drain of M4 on the gate potential of M2 continues to weaken, the gate driving voltage of M2 decreases synchronously, and the on-resistance of M2 automatically increases, realizing adaptive current limiting of the discharge current and suppressing the surge current at the end of the discharge from the root. This module uses only a single PMOS transistor to complete all feedback regulation functions, resulting in a very simple circuit structure, small chip layout area, and no need for active devices such as operational amplifiers and reference sources to participate in the regulation. The circuit noise is low and the power consumption is even lower. It can dynamically adjust the conduction capability of the feedback branch in real time according to the residual negative voltage of VOUT, stably control the charge discharge rate, reduce the interference of potential changes to other modules of the chip, and reduce the overall standby leakage power consumption of the circuit.

[0053] Based on the hardware connections of all the modules and the operating characteristics of the devices, the complete circuit workflow of this embodiment is divided into three continuous operating phases: discharge enable, adaptive voltage regulation discharge, and discharge cutoff. The operating states of the devices, signal potential changes, and circuit regulation effects in each phase are described in detail below:

[0054] Phase 1: Discharge enable turn-on phase (external enable signal set to low level)

[0055] When the negative voltage charge pump completes its boost output and the system main control unit issues a shutdown command, requiring the discharge of residual negative voltage charge inside the load capacitor Cload, the external operating enable signal switches to a low level. At this time, the gate-source voltage Vgs of the high-voltage PMOS transistor M1 is less than 0, the conductive channel of M1 is fully turned on, and the input power supply VIN is stably delivered to the upper end of the voltage divider resistor R1 through the turned-on M1. R1 and R2 work together to generate a stable, amplitude-controlled acquisition voltage at node A.

[0056] The sampling voltage output from node A is divided into two independent control branches that work synchronously and in parallel: The first branch is the gate drive control branch of M2. The sampling voltage is applied to the gate of the discharge MOS transistor M2. When the sampling voltage amplitude exceeds the turn-on threshold voltage of M2, M2 is fully turned on, and the complete discharge main path is formally established. The negative voltage charge stored in the load capacitor Cload flows back to ground along the complete loop of GND-R3-M2-R4-VOUT, quickly releasing the residual charge. The potential of node B changes synchronously with the negative voltage of VOUT in real time. The second branch is the high voltage clamping branch. The sampling voltage of node A is connected to the drain of the normally conducting NMOS transistor M3 through R2. R1, R2 and M3 work together to form a voltage divider clamping loop, which strictly clamps the gate potential of node A and M2 within the safe withstand voltage range of the low voltage MOS device at the back end, realizing electrical isolation protection between high and low voltage devices, and completely avoiding the direct breakdown of low voltage transistors such as M2 and M4 by the high voltage of VIN.

[0057] Simultaneously, the real-time feedback voltage output from node B is connected to the gate of feedback PMOS transistor M4. M4 conducts synchronously according to the current gate-source voltage, and the closed-loop feedback regulation channel is officially started, continuously acquiring the real-time changes in VOUT potential to provide uninterrupted sampling signals for subsequent adaptive current limiting regulation. During this stage, the voltage divider branches of R1 and R2 are always micro-current branches, only undertaking voltage sampling and potential clamping functions, and do not carry the large current of the main discharge circuit, thus not generating additional high-power discharge losses.

[0058] Phase 2: Adaptive voltage regulation and discharge phase (VOUT potential continuously rises towards ground, closed-loop feedback dynamic current limiting)

[0059] As the discharge process continues, the residual negative voltage charge inside the load capacitor Cload is continuously consumed, the absolute value of the negative voltage at the VOUT terminal gradually decreases, and the output potential slowly rises back to ground potential. The circuit then enters the negative feedback adaptive voltage regulation discharge mode.

[0060] As the VOUT potential continues to rise, the node B potential changes synchronously in the same direction as VOUT, directly altering the gate-source voltage Vgs of the feedback PMOS transistor M4. The on-resistance of M4 increases synchronously with Vgs. The drain potential of M4 shifts synchronously, and the effective drive voltage applied to the gate of M2 at adjustment point A dynamically adjusts the conduction level and on-resistance of the discharge MOS transistor M2. At the end of the discharge, the VOUT potential is very close to ground, the on-resistance of M4 reaches its maximum value, the gate drive voltage of M2 drops significantly, and the on-resistance of M2 automatically increases significantly. This forcibly constrains the discharge current in the circuit, preventing a sudden surge and avoiding drastic changes in the global potential within the chip caused by a large instantaneous current, which could interfere with the normal operation of other functional modules on the same chip, such as analog amplifiers, digital logic, and reference sources.

[0061] During this phase, the voltage divider branches of R1 and R2 maintain a low current (microampere level) throughout operation, without generating additional static power consumption. NMOS transistor M3 remains continuously conducting, providing uninterrupted high-voltage clamping protection and ensuring the long-term safety of downstream low-voltage devices. Resistors R3 and R4 stably carry the entire current of the main discharge circuit, balancing charge discharge rate and long-term device tolerance. Furthermore, this phase relies solely on the inherent transfer characteristics of the MOS transistors and the passive voltage divider network to achieve adaptive current regulation, eliminating the need for active devices such as operational amplifiers or reference sources. This results in low circuit noise, small layout area, and significantly improved voltage and current stability throughout the entire negative voltage residual charge discharge process.

[0062] Phase 3: Discharge cutoff standby phase (external enable signal switches to high level, full circuit electrical isolation)

[0063] This operating condition is triggered in two scenarios: In the first scenario, the residual negative charge inside the load capacitor Cload is completely discharged, and the VOUT potential rises back to near ground potential. In the second scenario, the system's main control unit needs to restart the negative charge pump to boost voltage, prohibiting the downstream discharge operation. In both scenarios, the external operating enable signal switches to a high level.

[0064] At this point, the gate potential of the high-voltage PMOS transistor M1 is exactly equal to the source potential VIN, the gate-source voltage Vgs=0, the internal conductive channel of M1 completely disappears and is completely turned off, the input power supply VIN is completely electrically isolated from all branches of the downstream voltage divider, discharge, and feedback, node A loses its power supply, the potential drops rapidly to a low level, and all downstream control branches stop working synchronously. Each device switches to the off state synchronously: the gate of the discharge MOS transistor M2 loses its effective drive voltage and is quickly turned off, the main discharge path from GND to VOUT is completely disconnected, and the loop discharge current drops directly to zero; the gate of the feedback PMOS transistor M4 has no effective feedback sampling voltage and is turned off synchronously, the closed-loop feedback adjustment channel stops all dynamic adjustment work; although the NMOS transistor M3 of the basic level module remains in a normally conducting state, there is no voltage difference across the upstream R1 and R2 voltage divider branches, no current flows through the branches, and there is no static leakage loss.

[0065] At this point, the entire discharge control circuit enters a standby state with near-zero static leakage, which will not generate any additional load interference to the normal boost output of the negative pressure charge pump, significantly reducing the overall static power consumption of the chip under normal boost operation and long standby conditions. A single external enable signal can simultaneously cut off all branches of power supply, discharge, and feedback, ensuring thorough shutdown and isolation without any leakage risks, and the control logic is simple and efficient.

[0066] This embodiment uses an on-chip MOSFET and passive resistors to build a closed-loop adaptive discharge architecture, eliminating the need for external reference voltage sources, operational amplifiers, inductors, and other active or discrete components. The circuit topology is simple, the chip layout occupies a small area, the integration is high, and the fabrication cost is lower. All branches can be synchronously controlled using only a single external enable signal, resulting in fast MOSFET switch response and good synchronous control consistency. During the discharge phase, the discharge impedance is dynamically adjusted in real time using voltage divider sampling and a single-transistor feedback loop to adaptively suppress surge current throughout the discharge phase. Combined with a continuously high-voltage clamping function using a normally conducting NMOS transistor, the risk of low-voltage MOSFET gate overvoltage breakdown and permanent transistor failure is avoided at the hardware level. In standby mode, all branches are completely electrically isolated, and the voltage divider branches have no static current, achieving near-zero static power consumption. This effectively solves the inherent defects of traditional fixed-resistor discharge circuits, such as large surge impact, high standby leakage current, and easy device damage. It can be widely adapted to various low-voltage single-supply integrated circuit systems, including OLED display driver chips, memory chips, RF analog front-ends, and automotive signal processing.

[0067] Although preferred embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the scope of protection of this application. Those skilled in the art can make various changes, modifications, equivalent substitutions and variations to the above embodiments within the scope of the technical concept of this application, and all such variations should fall within the scope of protection defined by the claims of this application.

Claims

1. A negative pressure charge pump output discharge control circuit, characterized in that, This includes an enable control module, a voltage divider module, a discharge module, a base level module, and a closed-loop feedback module; The enabling control module acquires an external enabling signal corresponding to the working state of the negative pressure charge pump; if the external enabling signal corresponds to the discharge condition of the negative pressure charge pump, the voltage divider module is activated, and the discharge module and the closed-loop feedback module are in an enabled working state; if the external enabling signal corresponds to the normal working condition of the negative pressure charge pump, the voltage divider module is deactivated, and the discharge module and the closed-loop feedback module are in a disabled shutdown state. The voltage divider module is electrically connected to the positive terminal of the input power supply through the enable control module, and is electrically connected to the output terminal of the negative charge pump through the base level module. The base level module is kept in a normally conducting state to achieve voltage clamping. The voltage divider module is used to collect the voltage between the positive terminal of the input power supply and the output terminal of the negative charge pump and perform voltage division processing to generate the collected voltage and output it to the discharge module and the closed-loop feedback module. The input terminal of the discharge module receives the collected voltage. When the collected voltage is greater than the preset start-up driving voltage, the discharge module opens the path between the output terminal of the negative pressure charge pump and the ground to realize the negative pressure charge discharge, and collects the intermediate voltage between the output terminal of the negative pressure charge pump and the ground as the feedback voltage, and outputs the feedback voltage to the closed-loop feedback module. The closed-loop feedback module receives the feedback voltage and constructs a feedback channel based on the feedback voltage to connect the output of the negative pressure charge pump to the input of the discharge module. The feedback channel dynamically adjusts the on-resistance of the discharge module according to the output voltage of the negative pressure charge pump. The greater the difference between the output voltage of the negative pressure charge pump and ground, the smaller the on-resistance of the discharge module. The closer the output voltage of the negative pressure charge pump is to ground potential, the greater the on-resistance of the discharge module.

2. The negative pressure charge pump output discharge control circuit according to claim 1, characterized in that, The enable control module includes a high-voltage PMOS transistor M1. The source of the high-voltage PMOS transistor M1 is connected to the input power supply VIN, the gate is connected to an external enable signal, and the drain is electrically connected to the input terminal of the voltage divider module. When the external enable signal is low, the high-voltage PMOS transistor M1 is turned on, the input power supply VIN supplies power to the voltage divider module, and the discharge process is started. When the external enable signal is high, the high-voltage PMOS transistor M1 is turned off, cutting off the power supply path of the voltage divider module, so that the voltage divider module, the discharge module, and the closed-loop feedback module are simultaneously disabled.

3. The negative pressure charge pump output discharge control circuit according to claim 2, characterized in that, The voltage divider module includes voltage divider resistors R1 and R2 connected in series. The upper end of the voltage divider resistor R1 is electrically connected to the drain of the high-voltage PMOS transistor M1. The lower end of the voltage divider resistor R1 is connected to the upper end of the voltage divider resistor R2 to form node A. The node A outputs the sampled voltage and is connected to the discharge module and the closed-loop feedback module respectively. The lower end of the voltage divider resistor R2 is electrically connected to the basic level module.

4. The negative pressure charge pump output discharge control circuit according to claim 3, characterized in that, The discharge module includes a resistor R3, a discharge MOSFET M2, and a voltage divider resistor R4. One end of the resistor R3 is grounded, and the other end is connected to the drain of the discharge MOSFET M2. The gate of the discharge MOSFET M2 is connected to node A. The source of the discharge MOSFET M2 is connected to the upper end of the voltage divider resistor R4 to form node B. Node B outputs a feedback voltage to the closed-loop feedback module. The lower end of the voltage divider resistor R4 is connected to the output terminal of the negative voltage charge pump.

5. The negative pressure charge pump output discharge control circuit according to claim 4, characterized in that, The basic level module includes an NMOS transistor M3; the gate of the NMOS transistor M3 is connected to a zero-level signal, the source is connected to the output terminal of the negative voltage charge pump, and the drain is electrically connected to the lower end of the voltage divider resistor R2. The NMOS transistor M3 remains in the conducting state throughout, providing a stable reference potential for the voltage divider module and realizing voltage clamping.

6. The negative pressure charge pump output discharge control circuit according to claim 5, characterized in that, The closed-loop feedback module includes a feedback PMOS transistor M4; the gate of the feedback PMOS transistor M4 is connected to the feedback voltage output by node B, the source of the feedback PMOS transistor M4 is connected to the output terminal of the negative voltage charge pump, and the drain of the feedback PMOS transistor M4 is connected to the gate of the discharge MOS transistor M2, thus forming a closed-loop feedback regulation path.

7. The negative pressure charge pump output discharge control circuit according to claim 6, characterized in that, When the external enable signal is low, the high-voltage PMOS transistor M1 is turned on, and the input power supply VIN provides a voltage divider potential to node A through the high-voltage PMOS transistor M1 and the voltage divider resistor R1. The sampling voltage output from node A is connected to the gate of the discharge MOS transistor M2 through resistor R3, which turns on the main discharge path consisting of ground, resistor R3, discharge MOS transistor M2, voltage divider resistor R4, and the output terminal of the negative voltage charge pump. Node B outputs a feedback voltage. The sampling voltage output from node A is connected to the drain of the normally conducting NMOS transistor M3 through the voltage divider resistor R2. The voltage divider resistors R1 and R2 work together with the NMOS transistor M3 to clamp the potential of node A. The feedback voltage output from node B is connected to the gate of the feedback PMOS transistor M4, which forms a closed-loop feedback regulation channel.

8. The negative pressure charge pump output discharge control circuit according to claim 7, characterized in that, During discharge, as the output potential of the negative charge pump rises towards ground, the potential at node B changes synchronously, altering the gate-source voltage of the feedback PMOS transistor M4 and adjusting its on-resistance. This, in turn, fine-tunes the voltage divider potential at point A, changing the gate drive voltage of the discharge MOS transistor M2 and dynamically adjusting its on-resistance. Towards the end of discharge, when the output potential of the negative charge pump approaches ground, the on-resistance of the discharge MOS transistor M2 automatically increases to limit the discharge current. Throughout the discharge process, voltage divider resistors R1 and R2 maintain a small current, and NMOS transistor M3 remains continuously conducting to achieve high-voltage clamping. Resistors R3 and R4 carry the main discharge circuit current.

9. The negative pressure charge pump output discharge control circuit according to claim 8, characterized in that, When the external enable signal switches to a high level, the high-voltage PMOS transistor M1 is turned off, and the input power supply VIN is electrically isolated from the back-end voltage divider, discharge, and feedback branches. The potential of node A drops to a low level. The discharge MOS transistor M2 is cut off due to the loss of its gate drive voltage, and the main discharge path is disconnected. The feedback PMOS transistor M4 is turned off synchronously without an effective feedback voltage, and the closed-loop feedback channel stops working. The NMOS transistor M3 remains in the conducting state, but no current flows through the voltage divider resistors R1 and R2 branches, and the entire discharge circuit enters a standby state with zero static leakage current.

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