Cascade h-bridge zero sequence injection and carrier phase shift reconfiguration fault-tolerant method, system and device

Abstract

The application relates to the field of power electronics, and discloses a cascaded H-bridge zero sequence injection and carrier phase shift reconstruction fault-tolerant method, system and device. After a fault unit exits modulation and is bypassed, the upper limit of a phase voltage peak value is determined according to the remaining input units of each phase and the DC side voltage, and the feasibility of a target output is judged. When the feasibility is available, a three-phase shared zero sequence voltage is determined according to the target three-phase symmetrical voltage reference and the peak value constraint of each phase, a modulation reference is generated, the remaining input units are renumbered according to the phase, the carrier phase shift angle and the unit carrier phase are reconstructed, and the zero sequence parameters and the carrier phase parameters are coordinated and take effect at a unified synchronization event. When the feasibility is unavailable, the output voltage instruction is reduced or a preset shutdown process is executed. The application has the effects that after H-bridge power units are bypassed to cause asymmetry, the three-phase shared zero sequence voltage is coordinated according to the remaining output capacity of each phase, each phase modulation reference meets the corresponding phase voltage peak value constraint, and the target line voltage reference remains unchanged.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a fault-tolerant method, system, and apparatus for cascaded H-bridge zero-sequence injection and carrier phase-shift reconstruction. Background Technology

[0002] A cascaded H-bridge converter is a multi-level voltage source converter composed of multiple single-phase H-bridge power units connected in series. It is widely used in high-voltage power transmission and renewable energy systems. In actual use, each H-bridge power unit is equipped with a bypass branch. When an H-bridge power unit fails, the pulse width modulation output of that H-bridge power unit can be stopped, and the bypass branch can be used to remove it from the series output circuit of its phase. When the number of H-bridge power units in the three-phase bypass of the converter is different, the number of units that can be put into operation and the output capacity of each phase are also different, which makes the three-phase modulation and carrier configuration used before the fault no longer fully applicable.

[0003] For a topology where three-phase cascaded branches are connected to a floating neutral point and there is no zero-sequence current path on the load side, the existing fault-tolerant processing has the following shortcomings: First, if the output capabilities of the three phases of the converter are inconsistent, and the original target output is still used, the target voltage may exceed the output capability after bypass. If the zero-sequence components such as the fundamental zero-sequence and the third harmonic are set separately, it is difficult to unify the different phase voltage peak constraints of the three phases, and it is difficult to ensure that the synthesized three-phase modulation reference does not exceed the upper limit of the voltage peak of the corresponding phase. Second, after the H-bridge power unit is bypassed, the number of remaining power units in each phase changes, and the power unit number, adjacent carrier phase shift angle and unit carrier phase before the fault may no longer match the actual number of power units in operation. Third, the zero-sequence parameters and carrier parameters after bypass need to be recalculated and issued. If the two do not take effect at the same time, different H-bridge power units may confuse the use of new and old parameters during the switching period, resulting in inconsistency of parameters in a short period of time. Summary of the Invention

[0004] The purpose of this invention is to provide a fault-tolerant method, system, and apparatus for cascaded H-bridge zero-sequence injection and carrier phase shift reconstruction, which has the effect of coordinating the three phases to share the zero-sequence voltage according to the remaining output capacity of each phase after the H-bridge power unit exits the bypass and causes asymmetry, and ensuring that the modulation reference of each phase meets the peak voltage constraint of the corresponding phase, while keeping the target line voltage reference unchanged.

[0005] The above-mentioned technical objective of the present invention is achieved through the following technical solution:

[0006] In a first aspect, the present invention provides a cascaded H-bridge zero-sequence injection and carrier phase shift reconstruction fault-tolerant method, wherein the cascaded H-bridge includes multiple H-bridge power units connected in series in each phase of the converter, and each H-bridge power unit is configured with a bypass branch, comprising the following steps:

[0007] S1. Collect the operating status and DC side voltage of each H-bridge power unit. When a faulty H-bridge power unit is detected, control the faulty H-bridge power unit to exit modulation and close the corresponding bypass branch.

[0008] S2. Obtain the target three-phase symmetrical voltage reference, and determine the number of three-phase remaining operational power units of the converter based on the bypass branch status. , and and the upper limit of the peak output voltage of each phase. , and Determine whether the target output voltage corresponding to the target three-phase symmetrical voltage reference is feasible;

[0009] S3. When the target output voltage is feasible, calculate the three-phase common zero-sequence voltage based on the target three-phase symmetrical voltage reference and the upper limit of the peak output voltage of each phase. The three-phase shared zero-sequence voltage contains the third harmonic component. The three-phase shared zero-sequence voltage is superimposed on the target three-phase symmetrical voltage reference to obtain the three-phase modulation reference.

[0010] S4. Renumber the remaining H-bridge power units that can be put into operation in each phase according to their actual order in the corresponding branch, and configure the carrier phase of each H-bridge power unit put into operation according to the renumbering result.

[0011] S5. At the unified synchronization event, coordinate the updated zero-sequence parameters with the carrier phase parameters. If the target output voltage is not feasible, reduce the output voltage or perform a preset shutdown process.

[0012] A further configuration of the present invention is: the converter's first... The expression for the upper limit of the peak output voltage is:

[0013]

[0014] in For the first The set of H-bridge power units that are put into operation; For the first Xiangdi DC side voltage of each H-bridge power unit.

[0015] A further provision of the present invention is that the expression for the target three-phase symmetrical voltage reference is:

[0016]

[0017] in, The target phase voltage fundamental peak value, Given the fundamental angular frequency, the condition for determining whether the target output voltage is feasible is:

[0018] .

[0019] A further feature of the present invention is that the three phases share a zero-sequence voltage. The time-by-time lower and upper bounds are:

[0020]

[0021] From the interval The three-phase common zero-sequence voltage is selected and superimposed on the three-phase symmetrical voltage reference to generate a three-phase modulation reference.

[0022] A further provision of the present invention is that the three-phase shared zero-sequence voltage is taken as the midpoint of the time-sequential feasible interval:

[0023]

[0024] And generate the first Phase modulation reference:

[0025]

[0026] A further feature of this invention is that the three-phase shared zero-sequence voltage adopts a finite-order harmonic form.

[0027]

[0028] in To retain the highest harmonic order, For the first Peak value of the next zero-order component For the first The phase of the zero-sequence component, the finite-order harmonic form includes at least the third harmonic component.

[0029] A further feature of the present invention is that the three-phase shared zero-sequence voltage is configured according to... Transition is performed where 0 ≤ λ ≤ 1;

[0030] Peak constraints of each phase modulation reference are checked during the transition process.

[0031]

[0032] If the verification fails, adjust the change process of λ, reduce the output voltage command, or recalculate the zero-sequence voltage.

[0033] A further provision of the present invention is that, under a single-pole frequency-doubled carrier phase-shift modulation method, the first... The carrier phase shift angle of adjacent power units is:

[0034]

[0035] Renumber the remaining H-bridge power units according to the actual series sequence within each phase. The first phase after renumbering The carrier phase of each input power unit is:

[0036]

[0037] Secondly, the present invention also provides a cascaded H-bridge zero-sequence injection and carrier phase-shift reconstruction fault-tolerant system, comprising:

[0038] The status detection module is used to collect the operating status and DC side voltage of each power unit;

[0039] The bypass control module is used to control the faulty power unit to exit modulation and close the bypass branch;

[0040] The zero-sequence calculation module is used to calculate the three-phase common zero-sequence voltage containing the third harmonic component based on the number of three-phase remaining power units, the upper limit of the peak output voltage of each phase, and the target voltage reference.

[0041] The carrier reconfiguration module is used to calculate the carrier phase shift angle based on the number of remaining power units in each phase and to renumber the remaining power units.

[0042] The communication module is used to send zero-sequence parameters and carrier parameters to each power unit;

[0043] The synchronization switching module is used to make the zero-sequence parameters and carrier parameters effective at the unified synchronization event.

[0044] Thirdly, the present invention also provides a cascaded H-bridge zero-sequence injection and carrier phase shift reconstruction fault-tolerant device, including a three-phase cascaded H-bridge power unit, a bypass branch of each H-bridge power unit, a main controller and a power unit controller, and a computer program stored in a memory and executable on the main controller. When the computer program is executed by the main controller, it implements the steps of the cascaded H-bridge zero-sequence injection and carrier phase shift reconstruction fault-tolerant method as claimed in claim 1.

[0045] The beneficial effects of this invention are:

[0046] 1. Calculate the upper limit of the peak voltage of each phase based on the bypass status of each phase, the remaining power units and the DC side voltage, determine the feasibility of the target output, and determine the common zero-sequence voltage of the three phases within the feasible range of the three phases satisfying the peak constraints. This achieves coordination of the instantaneous peak values ​​of the three phase voltages after bypassing, and solves the problems that the target output may exceed the limit when the output capabilities of each phase are not equal and that it is difficult for each zero-sequence component to uniformly satisfy the peak constraints.

[0047] 2. By renumbering the remaining power units in each phase according to their actual sequence in the corresponding series branches, and determining the phase shift angle of adjacent carriers and the phase of unit carriers according to the number of remaining power units in each phase, the carrier phase shift relationship is reconfigured, which solves the problem of mismatch between the carrier configuration before the fault and the actual number of power units after bypass, so that the carrier configuration of each phase corresponds to the number of remaining power units in this phase.

[0048] 3. By verifying and preloading the updated zero-sequence parameters and carrier phase parameters, and triggering parameter switching through synchronization events, the two types of parameters can be coordinated and take effect at the agreed synchronization time, which solves the problem that different H-bridge power units may use different parameter versions for a short period of time and reduces the time of parameter inconsistency. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 The following is a flowchart of the fault-tolerant operation of the H-bridge unit provided by the present invention;

[0051] Figure 2 The topology diagram of the three-phase cascaded H-bridge converter and unit bypass branch provided by the present invention;

[0052] Figure 3 This is a table showing the correspondence of the remaining units in Embodiment 3 of the present invention, which are renumbered in series order.

[0053] Figure 4 This is an example field table provided in Embodiment 4 of the present invention;

[0054] Figure 5 This is the field configuration table of the parameter frame provided in Embodiment 5 of the present invention;

[0055] Figure 6 This is a comparison table of carrier phase shift angles under different unit numbers and bypass states provided in Embodiment Six of the present invention;

[0056] Figure 7 This is a schematic diagram of the feasible time interval of the zero-sequence voltage of the present invention;

[0057] Figure 8 This is a schematic diagram of the reconstructed phase shift angle of each carrier before and after bypass in this invention;

[0058] Figure 9 This is a schematic diagram of the generation of the three-phase unified third harmonic phase angle of the present invention;

[0059] Figure 10 This is a timing diagram of parameter distribution, preloading, and synchronous switching in this invention;

[0060] Figure 11 This is a schematic diagram of the output capability boundary under different bypass depths according to the present invention. Detailed Implementation

[0061] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0062] The technical solution of the present invention will now be clearly and completely described with reference to specific embodiments. Obviously, the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0063] Example 1: Two units of phase A bypassed in a 10kV system with 8 units per phase.

[0064] This embodiment provides a fault-tolerant method for zero-sequence injection and carrier phase-shift reconstruction of a cascaded H-bridge, used to illustrate the overall process. The cascaded H-bridge converter used in this embodiment includes a three-phase cascaded branch, each phase cascaded branch is composed of multiple H-bridge power units connected in series, and each H-bridge power unit is provided with a bypass branch; the three-phase cascaded branch is connected to the floating neutral point, and there is no zero-sequence current path on the load side. The fault-tolerant control process includes fault isolation and bypass confirmation, output and feasibility judgment, calculation of the three-phase shared zero-sequence voltage, phase-by-phase carrier phase-shift reconstruction and parameter synchronization.

[0065] The main controller collects the operating status, bypass status, and DC-side voltage of each H-bridge power unit; upon detecting a faulty H-bridge power unit, it stops the modulation of that power unit, closes the corresponding bypass branch, and confirms the bypass status. Based on the confirmed bypass status, it determines the next... Phase Remaining Power Unit Set Number of remaining power units and the upper limit of the peak phase voltage And determine whether the target output is feasible.

[0066] The target three-phase symmetrical voltage reference is based on the fundamental peak value of the target phase voltage. Fundamental angular frequency The initial phase angle of each phase is generated; the target output voltage refers to the target three-phase fundamental voltage characterized by the target three-phase symmetrical voltage reference.

[0067] When the target output is feasible, the three-phase common zero-sequence voltage is determined based on the target three-phase symmetrical voltage reference and the upper limit of the peak phase voltage of each phase, and the modulation reference of each phase is generated; the remaining power units of each phase are renumbered according to their actual order in the corresponding cascaded branches, and the phase shift angle of adjacent carriers and the carrier phase of each power unit are reconstructed based on the number of remaining power units of that phase, so that the updated zero-sequence parameters and carrier phase parameters are coordinated and effective at the unified synchronization event; when the target output is not feasible, the output voltage command is reduced or the preset shutdown process is executed.

[0068] The main controller collects the operating status, bypass status, and DC side voltage of each H-bridge power unit. When a fault is detected in an H-bridge power unit, the main controller first stops the pulse width modulation output of that power unit, and then closes the corresponding bypass branch. After confirming the bypass status, it updates the activation status of the power units within the phase. The upper limit of the phase-to-phase voltage peak value is determined by the following formula:

[0069]

[0070] In the formula, For the first Phase-to-phase voltage peak limit For the first Phase set The Middle The DC-side voltage of each remaining power input unit; when the DC-side voltages of all remaining power input units are equal, it can be simplified to:

[0071]

[0072] In the formula, For the DC-side voltage of the H-bridge power unit, considering DC voltage fluctuations, dead time, minimum pulse width, and device on-state voltage drop, it can be... Based on this, a control margin or derating factor is set. This embodiment does not limit the specific value of the control margin or derating factor.

[0073] The main controller uses the target phase voltage fundamental peak value U and fundamental angular frequency. The target three-phase symmetrical voltage reference is generated by the fundamental initial phase angle of each phase:

[0074]

[0075] The initial phase angles of the three phases are as follows:

[0076]

[0077] In the formula, Let U be the target three-phase symmetrical voltage reference for the i-th phase, and U be the fundamental peak value of the target phase voltage. The fundamental angular frequency, This is the fundamental frequency.

[0078] The target output voltage referred to in this embodiment refers to the target three-phase symmetrical voltage reference. The target three-phase fundamental voltage is characterized. When the three-phase shared zero-sequence voltage is not limited by a preset harmonic form, the theoretical feasibility condition for this target output voltage is:

[0079]

[0080] In the formula, i and j ∈ {a, b, c} and i ≠ j.

[0081] This formula represents a theoretical condition not limited by finite-order harmonic truncation. When using finite-order zero-sequence voltage, the truncation result needs to be checked again for peak constraints. , and Arranged in ascending order: The maximum line voltage fundamental peak value can be obtained. The corresponding maximum line voltage fundamental RMS value is:

[0082]

[0083] When the theoretical condition of not being restricted by finite order harmonic truncation is met, the main controller continues to calculate the zero-sequence voltage and carrier parameters; when it is not met, the main controller reduces the target output voltage command corresponding to the target three-phase symmetrical voltage reference until the condition is met, or executes a preset shutdown process according to the operating status.

[0084] For the already generated target three-phase symmetrical voltage reference and the upper limit of the peak value of each phase voltage, the time-by-time lower and upper bounds of the three-phase shared zero-sequence voltage are as follows:

[0085]

[0086] When the theoretical condition that is not limited by finite-order harmonic cutoff holds, the following condition is satisfied at any time. Therefore, it can be seen from the interval The three-phase common zero-sequence voltage is selected; as a specific selection method, the midpoint of the feasible interval is chosen:

[0087]

[0088] The above-mentioned midpoint zero-sequence voltage can also be written in the following equivalent form:

[0089]

[0090] In the formula, For a three-phase shared zero-sequence voltage, the above formula is one way to select a value that satisfies the peak constraint. The zero-sequence voltage can also be selected from the feasible range according to requirements such as neutral point potential, harmonic cutoff, or controller calculation.

[0091] The three-phase modulation reference is generated according to the following formula:

[0092]

[0093] The line voltage between any two phases satisfies:

[0094]

[0095] Since the three phases are superimposed with the same zero-sequence voltage, the three phases share the zero-sequence voltage to adjust the instantaneous peak distribution of the three-phase phase voltages without changing the target line voltage reference.

[0096] Depending on the controller's computing resources and communication method, the three-phase shared zero-sequence voltage can be calculated directly time-by-time, or it can be expanded using finite-order odd harmonics:

[0097]

[0098] In the formula, The highest retained harmonic order; For the first Peak value of the next zero-order component For the first Phase of the next zero-sequence component express The order cutoff approximation does not use the superscript K as a power; the finite-order zero-sequence voltage may include the fundamental, third, fifth, seventh, or ninth harmonic components. When using the third harmonic component, a uniform global fundamental angle is used for all three phases. generate:

[0099]

[0100] in:

[0101]

[0102] In the formula, The initial phase for a unified angular reference, Using radians, the three-phase controller uses the same , and This ensures that the three-phase third harmonic components have the same instantaneous value at the same time; after finite-order expansion, the peak constraint is rechecked according to the following formula:

[0103]

[0104] When the peak constraint check fails, the main controller increases the number of retained harmonics, reduces the target output voltage command, or directly issues the instantaneous value of zero-sequence voltage.

[0105] Under the single-pole frequency doubling carrier phase shift modulation method, the first The carrier phase shift angle of adjacent input power units is:

[0106]

[0107] After the bypass status is confirmed, the main controller renumbers the remaining power units according to their actual sequence in the corresponding series branches. Here, m represents the sequential number after bypassing; the carrier phase of the m-th power unit after renumbering is:

[0108]

[0109] The power input unit numbered 0 in each phase adopts a unified carrier phase reference, and the remaining power input units are configured with carrier phases sequentially. The equivalent switching frequency of the i-th phase is:

[0110]

[0111] In the formula, The carrier frequency of a single H-bridge power unit. The equivalent switching frequency of the cascaded output of the i-th phase is given. When the number of remaining power units in the three phases is different, the main controller calculates the carrier phase shift angle for each phase.

[0112] After the main controller completes the calculation of the zero-sequence parameters and carrier parameters, it forms a parameter data frame and sends it to each power unit controller. The parameter data frame includes at least one of the following parameters:

[0113] (1) Number of remaining three-phase input units; (2) Mapping relationship between physical unit number and renumbering; (3) Carrier frequency; (4) Carrier phase of each input unit; (5) Instantaneous reference of zero-sequence voltage; (6) Amplitude and phase of zero-sequence harmonics; (7) Sine coefficient and cosine coefficient of zero-sequence harmonics; (8) Parameter version number or synchronous effective sequence number; (9) Data verification field.

[0114] Each power unit controller performs integrity and verification field checks on the parameter data frame. After the verification is successful, the new parameters are written into the preload area. When a unified hardware synchronization event, a timer trigger event, or a conventional communication synchronization event arrives, the zero-sequence parameters and carrier parameters take effect simultaneously.

[0115] To reduce the change in neutral point potential caused by the switching between old and new zero-sequence voltages, a transition coefficient can be used. Switch to another device:

[0116]

[0117] in: In the formula, and These are the zero-sequence voltages before and after the switching, respectively. As a transition value, during the transition process, the main controller or power unit controller performs peak constraint verification according to the following formula:

[0118]

[0119] When the above formula does not hold true, reduce the target output voltage command and adjust. The process of change, or recalculation of the zero-sequence voltage.

[0120] Example 2: Distribution of Third Harmonic and Finite-Order Zero-Sequence Coefficients

[0121] To implement the above method, a cascaded H-bridge zero-sequence injection and carrier phase-shift reconstruction fault-tolerant system is also provided, comprising:

[0122] The status detection module is used to collect the operating status and DC side voltage of each power unit;

[0123] The bypass control module is used to control the faulty power unit to exit modulation and close the bypass branch;

[0124] The zero-sequence calculation module is used to calculate the three-phase common zero-sequence voltage containing the third harmonic component based on the number of three-phase remaining power units, the upper limit of the peak output voltage of each phase, and the target voltage reference.

[0125] The carrier reconfiguration module is used to calculate the carrier phase shift angle based on the number of remaining power units in each phase and to renumber the remaining power units.

[0126] The communication module is used to send zero-sequence parameters and carrier parameters to each power unit;

[0127] The synchronization switching module is used to make the zero-sequence parameter and carrier parameter effective at a unified synchronization event.

[0128] All of the above modules can be installed in a distributed control system consisting of a main controller, a power unit controller, or both.

[0129] To implement the above method, a cascaded H-bridge zero-sequence injection and carrier phase-shift reconstruction fault-tolerant device is also provided, including a three-phase cascaded H-bridge power unit, a bypass branch of each H-bridge power unit, a main controller and a power unit controller, and a computer program stored in a memory and executable on the main controller. When the computer program is executed by the main controller, it implements the steps of the cascaded H-bridge zero-sequence injection and carrier phase-shift reconstruction fault-tolerant method as described in claim 1.

[0130] Example 3: Parameter preloading and activation based on timer synchronization

[0131] This embodiment uses a 10kV scenario with 8 H-bridge power units per phase and 2 H-bridge power units bypassed in phase A to illustrate the complete fault-tolerant process of output capability judgment, zero-sequence voltage calculation, carrier phase shift reconstruction, and synchronization activation. The converter adopts a three-phase star connection with the three-phase neutral point floating. There is no zero-sequence current path on the load side. Each H-bridge power unit is equipped with a bypass branch, and the unit carrier frequency is 500Hz.

[0132] In this embodiment, the DC-side voltage of each input power unit is taken as... ,in This refers to the DC-side voltage of a single H-bridge power unit, in volts; during normal operation, the number of three-phase connected units... ,in , and These represent the number of power units connected to phases A, B, and C, respectively.

[0133] During operation, the main controller detects a fault in phase A physical units A2 and A6. The main controller first stops the pulse width modulation output of A2 and A6, then closes the corresponding bypass branches and confirms the bypass status. After bypassing is complete, phase A retains 6 power units in operation, while the power units in phases B and C remain unchanged. .

[0134] Under the condition that the DC side voltage of each input unit is equal, the upper limit of the peak voltage of each phase is calculated according to the following formula: The calculation yields:

[0135] The effective value of the fundamental frequency of the target line voltage in this embodiment is The corresponding target phase voltage fundamental peak value is:

[0136]

[0137] The corresponding target line voltage fundamental peak value is:

[0138] Arranging the three phase voltage peak upper limits in ascending order, we get:

[0139]

[0140] in , and These are the ascending order of the peak voltage upper limits of the three phases.

[0141] The sum of the upper limits of the two corresponding abilities with smaller abilities is ,therefore It can be seen that the target 10kV line voltage meets the output feasibility condition under the bypass state; furthermore, the effective value of the fundamental frequency of the maximum line voltage corresponding to this bypass state is:

[0142] The margin of the target line voltage peak relative to the theoretical boundary is:

[0143]

[0144] This margin is the result of the calculation under the pulse width modulation period average model. In actual operation, DC voltage fluctuation, dead zone, minimum pulse width and device on-state voltage drop also need to be taken into account.

[0145] The main controller generates a three-phase symmetrical reference based on the fundamental peak value of the target phase voltage. in In the formula, For the first The symmetrical voltage reference for the phase, in volts; Time, in seconds; The fundamental angular frequency is expressed in radians per second. The fundamental frequency is 50Hz in this embodiment; For the first The fundamental phase angle of a phase, expressed in radians.

[0146] At each modulation calculation moment, the main controller calculates the lower bound of the zero-sequence voltage according to the following formula:

[0147]

[0148] And calculate the upper bound of the zero-sequence voltage according to the following formula:

[0149]

[0150] At each calculation time, we have:

[0151] In this embodiment, the midpoint of the feasible interval is selected as the three-phase common zero-sequence voltage: In the formula, , and The units are all volts.

[0152] The three-phase modulation references are as follows: The main controller performs peak constraint verification on the calculation results. .

[0153] Since the three phases are superimposed with the same zero-sequence voltage, the line voltage reference between any two phases satisfies: Therefore, the peak distribution of the three-phase voltages after the zero-sequence voltage adjustment bypass does not change the target line voltage reference.

[0154] When using a finite-order harmonic transmission method, the main controller can decompose the zero-sequence voltage obtained from the above formula into the fundamental wave, the third harmonic, and other odd-order harmonic components. The third harmonic is generated according to a unified global angle reference. In the formula, The third harmonic zero-sequence voltage peak value is expressed in volts. The fundamental angle shared by the three-phase controller is expressed in radians. The first phase of the third harmonic is expressed in radians; phases A, B, and C use the same... , and The third harmonic is generated without relying on the local phase angle after the fundamental zero sequence adjustment of each phase.

[0155] This embodiment employs single-pole frequency-doubled carrier phase-shift modulation, and the carrier frequency of a single power unit is: After bypassing, phase A has 6 remaining input units, and the carrier phase shift angles of their adjacent units are:

[0156]

[0157] Phases B and C each retain 8 input units, and their carrier phase shift angles are:

[0158]

[0159] After physical units A2 and A6 of phase A are bypassed, the main controller renumbers the remaining power units according to the actual connection sequence in the series branch of phase A. The corresponding relationship is shown in [reference needed]. Figure 3 .

[0160] After renumbering The carrier phase of each input unit is calculated according to the following formula: .

[0161] Phases B and C did not experience unit bypassing and are still numbered according to their original series sequence. The corresponding carrier phases are 0°, 22.5°, 45°, 67.5°, 90°, 112.5°, 135° and 157.5° respectively.

[0162] The equivalent switching frequencies of the three phases after bypass are as follows:

[0163]

[0164]

[0165] After the main controller completes the calculation of zero-sequence voltage and carrier phase, it forms a parameter data frame. This parameter data frame includes at least the number of three-phase remaining power units, the mapping relationship between the physical units of phase A and the renumbering, the carrier frequency, the carrier phase of each power unit, the zero-sequence parameter, the parameter version number, and the synchronization activation sequence number.

[0166] After receiving the parameter data frame, each power unit controller checks the frame format, parameter range and check field in sequence. After the check passes, the new carrier phase and zero sequence parameters are written into the preload area. When the unified hardware synchronization event arrives, each power unit simultaneously makes the preload parameters effective.

[0167] If a smooth transition is required between the old and new zero-sequence voltages, the zero-sequence voltage during the transition process is generated according to the following formula:

[0168]

[0169] In the formula, and These are the zero-sequence voltages before and after bypass, respectively, in volts; This is a dimensionless transition coefficient, and it will be checked again during the transition period.

[0170]

[0171] After verification, proceed at the set rate. Adjust from 0 to 1; if the verification fails, the main controller reduces the target output voltage command or recalculates the transient process.

[0172] After the two faulty units in phase A were removed through processing, the main controller... The updated three-phase output capability calculates the shared zero-sequence voltage for all three phases, and adjusts the phase shift angle of the carrier within phase A from 22.5° to 30°, while keeping the carrier configurations of phases B and C unchanged. The zero-sequence parameters and carrier parameters take effect at the unified synchronization event.

[0173] Example 4: Carrier Phase Shift Reconstruction with Different Number of Units Per Phase

[0174] This embodiment illustrates a method for representing and issuing a three-phase shared zero-sequence voltage using finite-order harmonic coefficients under a distributed power unit control architecture. The main controller is responsible for calculating the zero-sequence voltage based on the upper limit of the peak voltage of each phase, extracting the harmonic coefficients, and verifying the phase voltage constraints after truncation. Each power unit controller generates the same instantaneous value of zero-sequence voltage based on the received harmonic coefficients and a unified angle reference.

[0175] After a faulty unit is bypassed, the main controller calculates the upper limit of the peak voltage of each phase based on the set of remaining connected units in each phase and the DC side voltage of each unit. ,in The target three-phase symmetrical voltage reference is... ,in .

[0176] At each modulation calculation moment, the master controller calculates the lower and upper bounds of the zero-sequence voltage:

[0177]

[0178]

[0179] And take the midpoint of the feasible interval as the complete zero-sequence voltage: .

[0180] In centralized real-time computing, the main controller can directly use the calculated instantaneous value of the zero-sequence voltage for generating the three-phase modulation reference. In distributed computing, the main controller... Perform a finite-order Fourier representation and send the corresponding coefficients to the controller of each power unit.

[0181] Let the global fundamental angle shared by the three-phase controller be . In the formula, The global fundamental electrical angle is expressed in radians. The initial phase is used to establish a unified angular reference, and the unit is radians.

[0182] This embodiment retains the fundamental, third, fifth, seventh, and ninth zero-sequence components, resulting in a cutoff zero-sequence voltage with the highest order of 9: .

[0183] In the formula, For the first The peak value of the second-zero sequence component, in volts; For the first The initial phase of the next zero-sequence component, in radians; This represents the harmonic order.

[0184] To facilitate calculations by the power unit controller, it can also be converted into sine and cosine coefficient forms.

[0185]

[0186] in The reverse conversion relationship is: .

[0187] The main controller can calculate the coefficients of each order according to the zero-sequence waveform within one fundamental period:

[0188]

[0189]

[0190] In the formula, The fundamental electrical angle is expressed in radians. In digital controllers, the above formula can be implemented through discrete Fourier transform, table lookup, or offline calibration.

[0191] The third harmonic component in the formula is: Equivalently, it can also be expressed as .

[0192] The power unit controllers for phases A, B, and C use the same global angle. and the same set of coefficients Thus, the same instantaneous value of the third harmonic is generated at the same time, and each phase controller does not generate the third harmonic according to the phase angle of the fundamental wave after the fundamental wave zero sequence adjustment.

[0193] Each phase modulation reference according to Generation, due to the same three-phase superposition The line voltage reference between any two phases is: Therefore, the finite-order zero-sequence voltage does not change the target line voltage reference.

[0194] After the main controller completes the finite-order coefficient calculation, it checks the cutoff zero-sequence voltage within one fundamental cycle:

[0195]

[0196] In digital implementation, a fundamental frequency period can be divided into: Individual verification points And judge point by point: .

[0197] In the formula, The number of checkpoints within one fundamental frequency cycle; This is a reserved voltage margin, measured in volts, used to account for DC voltage fluctuations, dead zone, minimum pulse width, coefficient quantization error, and discrete verification error.

[0198] When the above equation holds true, the main controller allows the issuance of finite-order zero-sequence coefficients; when it does not hold true, the main controller executes one or more of the following:

[0199] (1) Increase the number of the retained zero-sequence harmonics;

[0200] (2) Re-optimize the harmonic coefficients of each order;

[0201] (3) Command to reduce target output voltage;

[0202] (4) Reuse The zero-sequence voltage is calculated directly time-by-time.

[0203] (5) The zero-sequence voltage instantaneous reference is directly issued by the main controller.

[0204] The main controller generates a zero-sequence parameter data frame, which includes global angle synchronization information, harmonic orders, sine and cosine coefficients of each order, parameter version number, synchronization activation sequence number, and verification fields. Example fields are shown below. Figure 4 .

[0205] Each harmonic coefficient can be represented by a signed integer. With 0.01V as a counting unit, the conversion relationship between the coefficient and the data frame field is as follows:

[0206]

[0207]

[0208] After receiving the data frame, the power unit controller checks the parameter range, version number, and verification field. If the verification passes, it writes the harmonic coefficients of each order into the preload area; when the unified synchronization event arrives and the synchronization sequence number is consistent, it switches the preload coefficients to the running coefficients.

[0209] After the parameters take effect, each power unit controller operates according to a unified global perspective. calculate:

[0210]

[0211] Different power units use the same coefficients, angle references, and parameter versions, and each power unit selects the corresponding symmetrical phase reference according to its own phase. or Then, the same zero-sequence voltage is superimposed.

[0212] To reduce the amount of real-time trigonometric function calculations, each power unit can generate sine and cosine values ​​of various orders through table lookup, coordinate rotation digital calculation algorithm, or recursive oscillator; regardless of the calculation method used, the global angle reference and zero-sequence parameter version used by the three phases remain consistent.

[0213] This embodiment takes the highest retention up to the ninth harmonic as an example. Based on the controller's computational resources, communication frame length, and peak constraint verification results, other truncation orders can also be selected, such as... The cutoff order used does not change the principle of generating the three-phase shared zero sequence. After the cutoff is completed, the peak phase voltage constraint is rechecked.

[0214] Example 5: How Zero-Sequence Parameters and Carrier Phase Parameters Take Effect

[0215] This embodiment illustrates an implementation method in a distributed power unit control architecture where zero-sequence parameters and carrier phase parameters take effect at a predetermined time through parameter preloading and timer synchronization. The main controller is responsible for calculating the remaining number of input units for each phase, unit number mapping, zero-sequence harmonic coefficients, and carrier phases, and sending parameter frames to each power unit controller through the communication network. After each power unit completes data verification, it writes the new parameters into the preloading area and switches the parameters when the unified synchronization signal arrives and the parameter activation sequence number is consistent.

[0216] The main controller generates a parameter frame based on the power unit status after bypassing. One type of field configuration for the parameter frame is described in [link to parameter frame configuration]. Figure 5 .

[0217] Among them, Ni[3] and unit_map jointly determine the number of phase input units and the correspondence between physical units and carrier numbers. The conversion relationship between phase_x100 and carrier phase is as follows:

[0218] In the formula, For the first The first phase after renumbering The carrier phase of each input unit.

[0219] When it is necessary to transmit seventh, ninth or other zero-sequence components, the corresponding sine and cosine coefficient fields can be added to the parameter frame. The parameter frame can also set the global angle initial value or angle synchronization sequence number to determine the global fundamental angle when the unified synchronization signal arrives.

[0220] After receiving the parameter frame, the power unit controller performs the checks in the following order:

[0221] (1) Check the integrity of the data frame according to the CRC;

[0222] (2) Check whether Ni[3] is consistent with unit_map;

[0223] (3) Check whether fc_hz is within the carrier frequency range allowed by the timer;

[0224] (4) Check whether phase_x100 matches the number of remaining input units and renumbering of the corresponding phase;

[0225] (5) Check whether the zero-order coefficients of each order are within the preset data range;

[0226] (6) Check if effective_seq is the parameter number to be activated.

[0227] After the verification is successful, the power unit controller writes the carrier frequency, carrier phase, zero-sequence harmonic coefficient and parameter version number into the preload area and sets the parameter ready flag. Before the parameter switch, the run register continues to use the original parameters, and the preloaded new parameters do not participate in the PWM calculation.

[0228] If the verification fails, the power unit controller will not update the preload area, or will clear the parameter ready flag and continue to use the original operating parameters, while returning the corresponding parameter abnormality status to the main controller.

[0229] The unified synchronization signal can be a hardware pulse output by the main controller. Each power unit is equipped with an input capture timer and a single-pulse timer, which are used to record the arrival time of the synchronization signal and to implement delay compensation, respectively.

[0230] Input capture timer count clock

[0231] In one specific configuration, the PWM timer update event serves as a trigger output signal to reset the input capture timer. Upon arrival of the synchronization pulse, the input capture channel latches the current count value on the rising edge. The time position of the synchronization signal relative to the local pulse period reference point is:

[0232] In the formula, To input the capture count value, This represents the time offset of the synchronization signal relative to the local pulse reference point.

[0233] When the unit carrier frequency is 500Hz, the input capture count corresponding to one carrier cycle is:

[0234]

[0235] in This is the input capture timer count value corresponding to one carrier cycle.

[0236] To suppress short-term glitches at the synchronization input, digital filtering can be configured for the input capture channel. The digital filtering parameters are set according to the synchronization pulse width and the field interference conditions to capture effective synchronization pulses and filter out short-duration input changes.

[0237] There may be fixed time delays in the communication, synchronization signal transmission, and input conditioning paths of each power unit. These fixed delays can be measured during the equipment commissioning phase. And select common target delay ,in .

[0238] No. The delay time required to supplement each power unit is:

[0239] For the first The calibrated fixed delay of each power unit Delay for public purposes, This is the additional delay time for the power unit.

[0240] The delay count value of the single-pulse timer is:

[0241] In the formula, This is the counting clock frequency of the single-pulse timer. This indicates taking the nearest integer; in this embodiment, 17.5MHz is acceptable.

[0242] After the synchronization pulse arrives, the single-pulse timer proceeds according to... Counting. Upon completion of the count, the power unit controller checks the following conditions:

[0243]

[0244]

[0245] In the formula, parameter_ready indicates that the parameter preloading is complete; pending_seq is the local parameter sequence number to be effective; effective_seq is the parameter effective sequence number corresponding to the current synchronization event.

[0246] When the above conditions are met, the power unit controller will transfer the preloaded parameters to the operating parameters, initialize or adjust the PWM carrier according to the new carrier phase, and simultaneously make the new zero-sequence coefficient and parameter version effective; when the above conditions are not met, this synchronization event will not trigger parameter switching, and the power unit will continue to use the original parameters.

[0247] To ensure that the three-phase controllers generate the same instantaneous value of the third harmonic, the unified synchronization event is also used to calibrate the global fundamental angle of each power unit. Let the preset global fundamental angle corresponding to the synchronization event be... When the parameter takes effect, the following applies:

[0248]

[0249] In the formula, For the global fundamental electrical angle, This is the time when it takes effect simultaneously.

[0250] After the parameters take effect, each power unit updates the global angle according to the same fundamental frequency:

[0251]

[0252] This refers to the discrete calculation sequence number; The update cycle is calculated for the angle. This indicates that the angle is limited to to Within the range.

[0253] The zero-sequence component of the third harmonic is generated according to the following formula:

[0254]

[0255] For the first The third harmonic zero-sequence voltage at each calculation time. and These are the sine and cosine coefficients of the third zero-sequence component, respectively.

[0256] The fundamental electrical angle corresponding to a single timer count is

[0257] When the fundamental frequency ,and At that time, there were:

[0258]

[0259] In the formula, The fundamental electrical angle corresponding to a timer count, in degrees.

[0260] Since the third harmonic angle is three times the fundamental angle, the third harmonic electrical angle corresponding to a single count is:

[0261]

[0262] Actual synchronization error also includes synchronization signal transmission delay difference, input conditioning delay, digital filtering delay, clock frequency deviation, and fixed delay calibration error; the system synchronization index should be determined based on the combined result of the above error items, rather than replacing the total synchronization error with single counting resolution.

[0263] After the parameter switching is complete, the power unit controller generates PWM pulses using the new zero-sequence coefficients and carrier phase. The main controller then continues to verify whether the three-phase modulation reference is satisfied. .

[0264] The main controller also checks the parameter version number, carrier synchronization status and DC side voltage reported by each power unit. If it finds that some power units have not switched to the target parameter version or the synchronization error exceeds the set threshold, the main controller will not continue to increase the output command, and will resend the parameters, re-execute the synchronization process or enter derating operation according to the preset strategy.

[0265] According to the above process, the zero-sequence parameters and carrier phase parameters are written into the pre-load area during the communication phase, and then the switching is triggered by the unified synchronization signal; the input acquisition timer records the arrival time of the synchronization signal, and the single-pulse timer performs delay compensation, so that each power unit enters the fault-tolerant operation state after bypass according to the same parameter version and unified angle reference.

[0266] Example 6: Carrier phase shift parameter configuration methods for systems with different rated number of units

[0267] This embodiment illustrates the carrier phase shift parameter configuration method for systems with different rated number of units. Each power unit uses the same control program, and the unit carrier frequency is set to: .

[0268] Let the first Phase Rated Configuration One H-bridge power unit, this phase has If one power unit is bypassed, then the remaining number of power units is... .

[0269] Under the single-pole frequency doubling carrier phase shift modulation method, the first The carrier phase shift angle between adjacent input units is .

[0270] The equivalent switching frequency in Table S4-1 is... After the power unit is bypassed, the unit carrier frequency Maintaining 500Hz, the equivalent switching frequency increases with the number of remaining active units. change.

[0271] When the rated number of units per phase is 5, 8, and 12, respectively, the carrier phase shift angles corresponding to normal operation, bypassing one power unit, and bypassing two power units are shown in the figure. Figure 6 .

[0272] After the bypass status is confirmed, the main controller proceeds according to the power unit in the [number]th [phase]. The actual connection sequence in the series-connected branches is used to renumber the remaining input units. The renumbering range is... , No. The carrier phase of each input unit is Each input unit with phase number 0 adopts a unified 0° carrier reference.

[0273] Taking a rated capacity of 8 units per phase and a bypass of 1 unit for a certain phase as an example, the number of remaining units is: The corresponding carrier phases are as follows: ;

[0274] If the number of three-phase bypass units is different, the main controller will adjust the number of bypass units according to the phase. , and Calculate them separately, and each phase does not share the same intraphase carrier phase shift angle.

[0275] The phase_x100 field in the parameter frame uses 0.01° as a counting unit. Xiangdi The field values ​​for each input unit are calculated using the following formula: .

[0276] After receiving this field, the power unit controller recovers the carrier phase according to the following formula: .

[0277] To reduce the accumulation of phase quantization error among the various input power units, the phase_x100 field of each power unit does not use the method of repeatedly accumulating the phase shift angles of adjacent integer units.

[0278] by For example, the phase_x100 field of each input unit can be configured as follows:

[0279]

[0280] The parameter frame also includes the number of remaining power units Ni[3] for each phase, the mapping relationship between physical units and renumbering unit_map, the carrier frequency field fc_hz, the parameter effective synchronization number effective_seq, and the data verification field.

[0281] After receiving the parameter frame, the power unit controller verifies the following:

[0282] (1) Whether this unit is included in the input unit mapping table of the corresponding phase;

[0283] (2) Whether phase_x100 is within the allowed range of 0 to 18000;

[0284] (3) Whether fc_hz is within the configurable frequency range of the PWM timer;

[0285] (4) Whether the local parameter sequence number to be effective is consistent with effective_seq;

[0286] (5) Check if the data frame verification fields are correct.

[0287] After the verification is passed, the power unit controller writes the carrier frequency and carrier phase into the preload area. When the unified synchronization event arrives, each power unit initializes or adjusts its local PWM timer according to the new carrier phase, so that the bypassed carrier parameters take effect at the same synchronization boundary.

[0288] In this embodiment, each power unit is programmed with the same control program. The main controller dynamically calculates based on the actual bypass status. The units are renumbered and phase_x100 is used to complete the carrier phase shift reconstruction with 5, 8 or 12 rated units per phase and different bypass numbers.

[0289] This application is described with reference to flowchart illustrations and / or block diagrams of methods, systems, and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0290] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0291] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0292] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features, and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A fault-tolerant method for zero-sequence injection and carrier phase-shift reconstruction of a cascaded H-bridge, wherein the cascaded H-bridge comprises multiple H-bridge power units connected in series in each phase of a converter, and each H-bridge power unit is configured with a bypass branch, characterized in that, Includes the following steps: S1. Collect the operating status and DC side voltage of each H-bridge power unit. When a faulty H-bridge power unit is detected, control the faulty H-bridge power unit to exit modulation and close the corresponding bypass branch. S2. Obtain the target three-phase symmetrical voltage reference, and determine the number of three-phase remaining operational power units of the converter based on the bypass branch status. , and and the upper limit of the peak output voltage of each phase. , and Determine whether the target output voltage corresponding to the target three-phase symmetrical voltage reference is feasible. S3. When the target output voltage is feasible, calculate the three-phase common zero-sequence voltage based on the target three-phase symmetrical voltage reference and the upper limit of the peak value of each phase output voltage. The three-phase common zero-sequence voltage contains a third harmonic component. The three-phase common zero-sequence voltage is superimposed on the target three-phase symmetrical voltage reference to obtain a three-phase modulation reference. S4. Renumber the remaining H-bridge power units that can be put into operation in each phase according to their actual order in the corresponding branch, and configure the carrier phase of each H-bridge power unit that is put into operation according to the renumbering result. S5. At the unified synchronization event, coordinate the updated zero-sequence parameters with the carrier phase parameters. If the target output voltage is not feasible, reduce the output voltage or perform a preset shutdown process.

2. The cascaded H-bridge zero-sequence injection and carrier phase shift reconstruction fault-tolerant method according to claim 1, characterized in that: Converter The expression for the upper limit of the peak output voltage is: in For the first The set of H-bridge power units that are put into operation; For the first Xiangdi DC-side voltage of each H-bridge power unit.

3. The cascaded H-bridge zero-sequence injection and carrier phase shift reconstruction fault-tolerant method according to claim 1, characterized in that: The expression for the target three-phase symmetrical voltage reference is: in, The target phase voltage fundamental peak value, Given the fundamental angular frequency, the feasible condition for determining the target output voltage is: .

4. The cascaded H-bridge zero-sequence injection and carrier phase shift reconstruction fault-tolerant method according to claim 3, characterized in that: The three-phase common zero-sequence voltage The time-by-time lower and upper bounds are: From the interval The three-phase common zero-sequence voltage is selected and superimposed onto the three-phase symmetrical voltage reference to generate a three-phase modulation reference.

5. The cascaded H-bridge zero-sequence injection and carrier phase shift reconstruction fault-tolerant method according to claim 4, characterized in that: The three-phase shared zero-sequence voltage is taken as the midpoint of the time-by-time feasible interval: And generate the first Phase modulation reference: 。 6. The cascaded H-bridge zero-sequence injection and carrier phase shift reconstruction fault-tolerant method according to claim 1, characterized in that: The three-phase shared zero-sequence voltage adopts a finite-order harmonic form: in To retain the highest harmonic order, For the first Peak value of the next zero-order component For the first The phase of the zero-sequence component, wherein the finite-order harmonic form includes at least the third harmonic component.

7. The cascaded H-bridge zero-sequence injection and carrier phase shift reconstruction fault-tolerant method according to claim 1, characterized in that: Three-phase shared zero-sequence voltage according to Transition is performed where 0 ≤ λ ≤ 1; Peak constraints of each phase modulation reference are checked during the transition process. If the verification fails, adjust the change process of λ, reduce the output voltage command, or recalculate the zero-sequence voltage.

8. The cascaded H-bridge zero-sequence injection and carrier phase shift reconstruction fault-tolerant method according to claim 1, characterized in that: Under the single-pole frequency doubling carrier phase shift modulation method, the first The carrier phase shift angle of adjacent power units is: Renumber the remaining H-bridge power units according to the actual series sequence within each phase. The first phase after renumbering The carrier phase of each input power unit is: 。 9. A cascaded H-bridge zero-sequence injection and carrier phase-shift reconstruction fault-tolerant system, characterized in that, include: The status detection module is used to collect the operating status and DC side voltage of each power unit; The bypass control module is used to control the faulty power unit to exit modulation and close the bypass branch; The zero-sequence calculation module is used to calculate the three-phase common zero-sequence voltage containing the third harmonic component based on the number of three-phase remaining power units, the upper limit of the peak output voltage of each phase, and the target voltage reference. The carrier reconfiguration module is used to calculate the carrier phase shift angle based on the number of remaining power units in each phase and to renumber the remaining power units. The communication module is used to send zero-sequence parameters and carrier parameters to each power unit; The synchronization switching module is used to make the zero-sequence parameter and carrier parameter effective at a unified synchronization event.

10. A cascaded H-bridge zero-sequence injection and carrier phase-shift reconstruction fault-tolerant device, characterized in that: It includes a three-phase cascaded H-bridge power unit, a bypass branch of each H-bridge power unit, a main controller and a power unit controller, and a computer program stored in a memory and executable on the main controller. When the computer program is executed by the main controller, it implements the steps of the cascaded H-bridge zero-sequence injection and carrier phase shift reconstruction fault-tolerant method as described in claim 1.

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